Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.25
[linux-2.6] / arch / arm / mach-at91 / at91cap9_devices.c
1 /*
2  * arch/arm/mach-at91/at91cap9_devices.c
3  *
4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6  *  Copyright (C) 2007 Atmel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  */
14 #include <asm/mach/arch.h>
15 #include <asm/mach/map.h>
16
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/physmap.h>
20
21 #include <video/atmel_lcdc.h>
22
23 #include <asm/arch/board.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/at91cap9.h>
26 #include <asm/arch/at91sam926x_mc.h>
27 #include <asm/arch/at91cap9_matrix.h>
28
29 #include "generic.h"
30
31
32 /* --------------------------------------------------------------------
33  *  USB Host
34  * -------------------------------------------------------------------- */
35
36 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37 static u64 ohci_dmamask = DMA_BIT_MASK(32);
38 static struct at91_usbh_data usbh_data;
39
40 static struct resource usbh_resources[] = {
41         [0] = {
42                 .start  = AT91CAP9_UHP_BASE,
43                 .end    = AT91CAP9_UHP_BASE + SZ_1M - 1,
44                 .flags  = IORESOURCE_MEM,
45         },
46         [1] = {
47                 .start  = AT91CAP9_ID_UHP,
48                 .end    = AT91CAP9_ID_UHP,
49                 .flags  = IORESOURCE_IRQ,
50         },
51 };
52
53 static struct platform_device at91_usbh_device = {
54         .name           = "at91_ohci",
55         .id             = -1,
56         .dev            = {
57                                 .dma_mask               = &ohci_dmamask,
58                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
59                                 .platform_data          = &usbh_data,
60         },
61         .resource       = usbh_resources,
62         .num_resources  = ARRAY_SIZE(usbh_resources),
63 };
64
65 void __init at91_add_device_usbh(struct at91_usbh_data *data)
66 {
67         int i;
68
69         if (!data)
70                 return;
71
72         /* Enable VBus control for UHP ports */
73         for (i = 0; i < data->ports; i++) {
74                 if (data->vbus_pin[i])
75                         at91_set_gpio_output(data->vbus_pin[i], 0);
76         }
77
78         usbh_data = *data;
79         platform_device_register(&at91_usbh_device);
80 }
81 #else
82 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83 #endif
84
85
86 /* --------------------------------------------------------------------
87  *  Ethernet
88  * -------------------------------------------------------------------- */
89
90 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
91 static u64 eth_dmamask = DMA_BIT_MASK(32);
92 static struct at91_eth_data eth_data;
93
94 static struct resource eth_resources[] = {
95         [0] = {
96                 .start  = AT91CAP9_BASE_EMAC,
97                 .end    = AT91CAP9_BASE_EMAC + SZ_16K - 1,
98                 .flags  = IORESOURCE_MEM,
99         },
100         [1] = {
101                 .start  = AT91CAP9_ID_EMAC,
102                 .end    = AT91CAP9_ID_EMAC,
103                 .flags  = IORESOURCE_IRQ,
104         },
105 };
106
107 static struct platform_device at91cap9_eth_device = {
108         .name           = "macb",
109         .id             = -1,
110         .dev            = {
111                                 .dma_mask               = &eth_dmamask,
112                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
113                                 .platform_data          = &eth_data,
114         },
115         .resource       = eth_resources,
116         .num_resources  = ARRAY_SIZE(eth_resources),
117 };
118
119 void __init at91_add_device_eth(struct at91_eth_data *data)
120 {
121         if (!data)
122                 return;
123
124         if (data->phy_irq_pin) {
125                 at91_set_gpio_input(data->phy_irq_pin, 0);
126                 at91_set_deglitch(data->phy_irq_pin, 1);
127         }
128
129         /* Pins used for MII and RMII */
130         at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
131         at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
132         at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
133         at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
134         at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
135         at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
136         at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
137         at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
138         at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
139         at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
140
141         if (!data->is_rmii) {
142                 at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
143                 at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
144                 at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
145                 at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
146                 at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
147                 at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
148                 at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
149                 at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
150         }
151
152         eth_data = *data;
153         platform_device_register(&at91cap9_eth_device);
154 }
155 #else
156 void __init at91_add_device_eth(struct at91_eth_data *data) {}
157 #endif
158
159
160 /* --------------------------------------------------------------------
161  *  MMC / SD
162  * -------------------------------------------------------------------- */
163
164 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
165 static u64 mmc_dmamask = DMA_BIT_MASK(32);
166 static struct at91_mmc_data mmc0_data, mmc1_data;
167
168 static struct resource mmc0_resources[] = {
169         [0] = {
170                 .start  = AT91CAP9_BASE_MCI0,
171                 .end    = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
172                 .flags  = IORESOURCE_MEM,
173         },
174         [1] = {
175                 .start  = AT91CAP9_ID_MCI0,
176                 .end    = AT91CAP9_ID_MCI0,
177                 .flags  = IORESOURCE_IRQ,
178         },
179 };
180
181 static struct platform_device at91cap9_mmc0_device = {
182         .name           = "at91_mci",
183         .id             = 0,
184         .dev            = {
185                                 .dma_mask               = &mmc_dmamask,
186                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
187                                 .platform_data          = &mmc0_data,
188         },
189         .resource       = mmc0_resources,
190         .num_resources  = ARRAY_SIZE(mmc0_resources),
191 };
192
193 static struct resource mmc1_resources[] = {
194         [0] = {
195                 .start  = AT91CAP9_BASE_MCI1,
196                 .end    = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
197                 .flags  = IORESOURCE_MEM,
198         },
199         [1] = {
200                 .start  = AT91CAP9_ID_MCI1,
201                 .end    = AT91CAP9_ID_MCI1,
202                 .flags  = IORESOURCE_IRQ,
203         },
204 };
205
206 static struct platform_device at91cap9_mmc1_device = {
207         .name           = "at91_mci",
208         .id             = 1,
209         .dev            = {
210                                 .dma_mask               = &mmc_dmamask,
211                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
212                                 .platform_data          = &mmc1_data,
213         },
214         .resource       = mmc1_resources,
215         .num_resources  = ARRAY_SIZE(mmc1_resources),
216 };
217
218 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
219 {
220         if (!data)
221                 return;
222
223         /* input/irq */
224         if (data->det_pin) {
225                 at91_set_gpio_input(data->det_pin, 1);
226                 at91_set_deglitch(data->det_pin, 1);
227         }
228         if (data->wp_pin)
229                 at91_set_gpio_input(data->wp_pin, 1);
230         if (data->vcc_pin)
231                 at91_set_gpio_output(data->vcc_pin, 0);
232
233         if (mmc_id == 0) {              /* MCI0 */
234                 /* CLK */
235                 at91_set_A_periph(AT91_PIN_PA2, 0);
236
237                 /* CMD */
238                 at91_set_A_periph(AT91_PIN_PA1, 1);
239
240                 /* DAT0, maybe DAT1..DAT3 */
241                 at91_set_A_periph(AT91_PIN_PA0, 1);
242                 if (data->wire4) {
243                         at91_set_A_periph(AT91_PIN_PA3, 1);
244                         at91_set_A_periph(AT91_PIN_PA4, 1);
245                         at91_set_A_periph(AT91_PIN_PA5, 1);
246                 }
247
248                 mmc0_data = *data;
249                 at91_clock_associate("mci0_clk", &at91cap9_mmc1_device.dev, "mci_clk");
250                 platform_device_register(&at91cap9_mmc0_device);
251         } else {                        /* MCI1 */
252                 /* CLK */
253                 at91_set_A_periph(AT91_PIN_PA16, 0);
254
255                 /* CMD */
256                 at91_set_A_periph(AT91_PIN_PA17, 1);
257
258                 /* DAT0, maybe DAT1..DAT3 */
259                 at91_set_A_periph(AT91_PIN_PA18, 1);
260                 if (data->wire4) {
261                         at91_set_A_periph(AT91_PIN_PA19, 1);
262                         at91_set_A_periph(AT91_PIN_PA20, 1);
263                         at91_set_A_periph(AT91_PIN_PA21, 1);
264                 }
265
266                 mmc1_data = *data;
267                 at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk");
268                 platform_device_register(&at91cap9_mmc1_device);
269         }
270 }
271 #else
272 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
273 #endif
274
275
276 /* --------------------------------------------------------------------
277  *  NAND / SmartMedia
278  * -------------------------------------------------------------------- */
279
280 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
281 static struct at91_nand_data nand_data;
282
283 #define NAND_BASE       AT91_CHIPSELECT_3
284
285 static struct resource nand_resources[] = {
286         {
287                 .start  = NAND_BASE,
288                 .end    = NAND_BASE + SZ_256M - 1,
289                 .flags  = IORESOURCE_MEM,
290         }
291 };
292
293 static struct platform_device at91cap9_nand_device = {
294         .name           = "at91_nand",
295         .id             = -1,
296         .dev            = {
297                                 .platform_data  = &nand_data,
298         },
299         .resource       = nand_resources,
300         .num_resources  = ARRAY_SIZE(nand_resources),
301 };
302
303 void __init at91_add_device_nand(struct at91_nand_data *data)
304 {
305         unsigned long csa, mode;
306
307         if (!data)
308                 return;
309
310         csa = at91_sys_read(AT91_MATRIX_EBICSA);
311         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
312
313         /* set the bus interface characteristics */
314         at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1)
315                         | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
316
317         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6)
318                         | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
319
320         at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
321
322         if (data->bus_width_16)
323                 mode = AT91_SMC_DBW_16;
324         else
325                 mode = AT91_SMC_DBW_8;
326         at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
327
328         /* enable pin */
329         if (data->enable_pin)
330                 at91_set_gpio_output(data->enable_pin, 1);
331
332         /* ready/busy pin */
333         if (data->rdy_pin)
334                 at91_set_gpio_input(data->rdy_pin, 1);
335
336         /* card detect pin */
337         if (data->det_pin)
338                 at91_set_gpio_input(data->det_pin, 1);
339
340         nand_data = *data;
341         platform_device_register(&at91cap9_nand_device);
342 }
343 #else
344 void __init at91_add_device_nand(struct at91_nand_data *data) {}
345 #endif
346
347 /* --------------------------------------------------------------------
348  *  TWI (i2c)
349  * -------------------------------------------------------------------- */
350
351 /*
352  * Prefer the GPIO code since the TWI controller isn't robust
353  * (gets overruns and underruns under load) and can only issue
354  * repeated STARTs in one scenario (the driver doesn't yet handle them).
355  */
356 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
357
358 static struct i2c_gpio_platform_data pdata = {
359         .sda_pin                = AT91_PIN_PB4,
360         .sda_is_open_drain      = 1,
361         .scl_pin                = AT91_PIN_PB5,
362         .scl_is_open_drain      = 1,
363         .udelay                 = 2,            /* ~100 kHz */
364 };
365
366 static struct platform_device at91cap9_twi_device = {
367         .name                   = "i2c-gpio",
368         .id                     = -1,
369         .dev.platform_data      = &pdata,
370 };
371
372 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
373 {
374         at91_set_GPIO_periph(AT91_PIN_PB4, 1);          /* TWD (SDA) */
375         at91_set_multi_drive(AT91_PIN_PB4, 1);
376
377         at91_set_GPIO_periph(AT91_PIN_PB5, 1);          /* TWCK (SCL) */
378         at91_set_multi_drive(AT91_PIN_PB5, 1);
379
380         i2c_register_board_info(0, devices, nr_devices);
381         platform_device_register(&at91cap9_twi_device);
382 }
383
384 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
385
386 static struct resource twi_resources[] = {
387         [0] = {
388                 .start  = AT91CAP9_BASE_TWI,
389                 .end    = AT91CAP9_BASE_TWI + SZ_16K - 1,
390                 .flags  = IORESOURCE_MEM,
391         },
392         [1] = {
393                 .start  = AT91CAP9_ID_TWI,
394                 .end    = AT91CAP9_ID_TWI,
395                 .flags  = IORESOURCE_IRQ,
396         },
397 };
398
399 static struct platform_device at91cap9_twi_device = {
400         .name           = "at91_i2c",
401         .id             = -1,
402         .resource       = twi_resources,
403         .num_resources  = ARRAY_SIZE(twi_resources),
404 };
405
406 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
407 {
408         /* pins used for TWI interface */
409         at91_set_B_periph(AT91_PIN_PB4, 0);             /* TWD */
410         at91_set_multi_drive(AT91_PIN_PB4, 1);
411
412         at91_set_B_periph(AT91_PIN_PB5, 0);             /* TWCK */
413         at91_set_multi_drive(AT91_PIN_PB5, 1);
414
415         i2c_register_board_info(0, devices, nr_devices);
416         platform_device_register(&at91cap9_twi_device);
417 }
418 #else
419 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
420 #endif
421
422 /* --------------------------------------------------------------------
423  *  SPI
424  * -------------------------------------------------------------------- */
425
426 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
427 static u64 spi_dmamask = DMA_BIT_MASK(32);
428
429 static struct resource spi0_resources[] = {
430         [0] = {
431                 .start  = AT91CAP9_BASE_SPI0,
432                 .end    = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
433                 .flags  = IORESOURCE_MEM,
434         },
435         [1] = {
436                 .start  = AT91CAP9_ID_SPI0,
437                 .end    = AT91CAP9_ID_SPI0,
438                 .flags  = IORESOURCE_IRQ,
439         },
440 };
441
442 static struct platform_device at91cap9_spi0_device = {
443         .name           = "atmel_spi",
444         .id             = 0,
445         .dev            = {
446                                 .dma_mask               = &spi_dmamask,
447                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
448         },
449         .resource       = spi0_resources,
450         .num_resources  = ARRAY_SIZE(spi0_resources),
451 };
452
453 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
454
455 static struct resource spi1_resources[] = {
456         [0] = {
457                 .start  = AT91CAP9_BASE_SPI1,
458                 .end    = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
459                 .flags  = IORESOURCE_MEM,
460         },
461         [1] = {
462                 .start  = AT91CAP9_ID_SPI1,
463                 .end    = AT91CAP9_ID_SPI1,
464                 .flags  = IORESOURCE_IRQ,
465         },
466 };
467
468 static struct platform_device at91cap9_spi1_device = {
469         .name           = "atmel_spi",
470         .id             = 1,
471         .dev            = {
472                                 .dma_mask               = &spi_dmamask,
473                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
474         },
475         .resource       = spi1_resources,
476         .num_resources  = ARRAY_SIZE(spi1_resources),
477 };
478
479 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
480
481 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
482 {
483         int i;
484         unsigned long cs_pin;
485         short enable_spi0 = 0;
486         short enable_spi1 = 0;
487
488         /* Choose SPI chip-selects */
489         for (i = 0; i < nr_devices; i++) {
490                 if (devices[i].controller_data)
491                         cs_pin = (unsigned long) devices[i].controller_data;
492                 else if (devices[i].bus_num == 0)
493                         cs_pin = spi0_standard_cs[devices[i].chip_select];
494                 else
495                         cs_pin = spi1_standard_cs[devices[i].chip_select];
496
497                 if (devices[i].bus_num == 0)
498                         enable_spi0 = 1;
499                 else
500                         enable_spi1 = 1;
501
502                 /* enable chip-select pin */
503                 at91_set_gpio_output(cs_pin, 1);
504
505                 /* pass chip-select pin to driver */
506                 devices[i].controller_data = (void *) cs_pin;
507         }
508
509         spi_register_board_info(devices, nr_devices);
510
511         /* Configure SPI bus(es) */
512         if (enable_spi0) {
513                 at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
514                 at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
515                 at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
516
517                 at91_clock_associate("spi0_clk", &at91cap9_spi0_device.dev, "spi_clk");
518                 platform_device_register(&at91cap9_spi0_device);
519         }
520         if (enable_spi1) {
521                 at91_set_A_periph(AT91_PIN_PB12, 0);    /* SPI1_MISO */
522                 at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
523                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
524
525                 at91_clock_associate("spi1_clk", &at91cap9_spi1_device.dev, "spi_clk");
526                 platform_device_register(&at91cap9_spi1_device);
527         }
528 }
529 #else
530 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
531 #endif
532
533
534 /* --------------------------------------------------------------------
535  *  RTT
536  * -------------------------------------------------------------------- */
537
538 static struct platform_device at91cap9_rtt_device = {
539         .name           = "at91_rtt",
540         .id             = -1,
541         .num_resources  = 0,
542 };
543
544 static void __init at91_add_device_rtt(void)
545 {
546         platform_device_register(&at91cap9_rtt_device);
547 }
548
549
550 /* --------------------------------------------------------------------
551  *  Watchdog
552  * -------------------------------------------------------------------- */
553
554 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
555 static struct platform_device at91cap9_wdt_device = {
556         .name           = "at91_wdt",
557         .id             = -1,
558         .num_resources  = 0,
559 };
560
561 static void __init at91_add_device_watchdog(void)
562 {
563         platform_device_register(&at91cap9_wdt_device);
564 }
565 #else
566 static void __init at91_add_device_watchdog(void) {}
567 #endif
568
569
570 /* --------------------------------------------------------------------
571  *  AC97
572  * -------------------------------------------------------------------- */
573
574 #if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
575 static u64 ac97_dmamask = DMA_BIT_MASK(32);
576 static struct atmel_ac97_data ac97_data;
577
578 static struct resource ac97_resources[] = {
579         [0] = {
580                 .start  = AT91CAP9_BASE_AC97C,
581                 .end    = AT91CAP9_BASE_AC97C + SZ_16K - 1,
582                 .flags  = IORESOURCE_MEM,
583         },
584         [1] = {
585                 .start  = AT91CAP9_ID_AC97C,
586                 .end    = AT91CAP9_ID_AC97C,
587                 .flags  = IORESOURCE_IRQ,
588         },
589 };
590
591 static struct platform_device at91cap9_ac97_device = {
592         .name           = "ac97c",
593         .id             = 1,
594         .dev            = {
595                                 .dma_mask               = &ac97_dmamask,
596                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
597                                 .platform_data          = &ac97_data,
598         },
599         .resource       = ac97_resources,
600         .num_resources  = ARRAY_SIZE(ac97_resources),
601 };
602
603 void __init at91_add_device_ac97(struct atmel_ac97_data *data)
604 {
605         if (!data)
606                 return;
607
608         at91_set_A_periph(AT91_PIN_PA6, 0);     /* AC97FS */
609         at91_set_A_periph(AT91_PIN_PA7, 0);     /* AC97CK */
610         at91_set_A_periph(AT91_PIN_PA8, 0);     /* AC97TX */
611         at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
612
613         /* reset */
614         if (data->reset_pin)
615                 at91_set_gpio_output(data->reset_pin, 0);
616
617         ac97_data = *data;
618         platform_device_register(&at91cap9_ac97_device);
619 }
620 #else
621 void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
622 #endif
623
624
625 /* --------------------------------------------------------------------
626  *  LCD Controller
627  * -------------------------------------------------------------------- */
628
629 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
630 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
631 static struct atmel_lcdfb_info lcdc_data;
632
633 static struct resource lcdc_resources[] = {
634         [0] = {
635                 .start  = AT91CAP9_LCDC_BASE,
636                 .end    = AT91CAP9_LCDC_BASE + SZ_4K - 1,
637                 .flags  = IORESOURCE_MEM,
638         },
639         [1] = {
640                 .start  = AT91CAP9_ID_LCDC,
641                 .end    = AT91CAP9_ID_LCDC,
642                 .flags  = IORESOURCE_IRQ,
643         },
644 };
645
646 static struct platform_device at91_lcdc_device = {
647         .name           = "atmel_lcdfb",
648         .id             = 0,
649         .dev            = {
650                                 .dma_mask               = &lcdc_dmamask,
651                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
652                                 .platform_data          = &lcdc_data,
653         },
654         .resource       = lcdc_resources,
655         .num_resources  = ARRAY_SIZE(lcdc_resources),
656 };
657
658 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
659 {
660         if (!data)
661                 return;
662
663         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
664         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
665         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
666         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
667         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
668         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
669         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
670         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
671         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
672         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
673         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
674         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
675         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
676         at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
677         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
678         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
679         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
680         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
681         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
682         at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
683         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
684         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
685
686         lcdc_data = *data;
687         platform_device_register(&at91_lcdc_device);
688 }
689 #else
690 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
691 #endif
692
693
694 /* --------------------------------------------------------------------
695  *  SSC -- Synchronous Serial Controller
696  * -------------------------------------------------------------------- */
697
698 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
699 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
700
701 static struct resource ssc0_resources[] = {
702         [0] = {
703                 .start  = AT91CAP9_BASE_SSC0,
704                 .end    = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
705                 .flags  = IORESOURCE_MEM,
706         },
707         [1] = {
708                 .start  = AT91CAP9_ID_SSC0,
709                 .end    = AT91CAP9_ID_SSC0,
710                 .flags  = IORESOURCE_IRQ,
711         },
712 };
713
714 static struct platform_device at91cap9_ssc0_device = {
715         .name   = "ssc",
716         .id     = 0,
717         .dev    = {
718                 .dma_mask               = &ssc0_dmamask,
719                 .coherent_dma_mask      = DMA_BIT_MASK(32),
720         },
721         .resource       = ssc0_resources,
722         .num_resources  = ARRAY_SIZE(ssc0_resources),
723 };
724
725 static inline void configure_ssc0_pins(unsigned pins)
726 {
727         if (pins & ATMEL_SSC_TF)
728                 at91_set_A_periph(AT91_PIN_PB0, 1);
729         if (pins & ATMEL_SSC_TK)
730                 at91_set_A_periph(AT91_PIN_PB1, 1);
731         if (pins & ATMEL_SSC_TD)
732                 at91_set_A_periph(AT91_PIN_PB2, 1);
733         if (pins & ATMEL_SSC_RD)
734                 at91_set_A_periph(AT91_PIN_PB3, 1);
735         if (pins & ATMEL_SSC_RK)
736                 at91_set_A_periph(AT91_PIN_PB4, 1);
737         if (pins & ATMEL_SSC_RF)
738                 at91_set_A_periph(AT91_PIN_PB5, 1);
739 }
740
741 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
742
743 static struct resource ssc1_resources[] = {
744         [0] = {
745                 .start  = AT91CAP9_BASE_SSC1,
746                 .end    = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
747                 .flags  = IORESOURCE_MEM,
748         },
749         [1] = {
750                 .start  = AT91CAP9_ID_SSC1,
751                 .end    = AT91CAP9_ID_SSC1,
752                 .flags  = IORESOURCE_IRQ,
753         },
754 };
755
756 static struct platform_device at91cap9_ssc1_device = {
757         .name   = "ssc",
758         .id     = 1,
759         .dev    = {
760                 .dma_mask               = &ssc1_dmamask,
761                 .coherent_dma_mask      = DMA_BIT_MASK(32),
762         },
763         .resource       = ssc1_resources,
764         .num_resources  = ARRAY_SIZE(ssc1_resources),
765 };
766
767 static inline void configure_ssc1_pins(unsigned pins)
768 {
769         if (pins & ATMEL_SSC_TF)
770                 at91_set_A_periph(AT91_PIN_PB6, 1);
771         if (pins & ATMEL_SSC_TK)
772                 at91_set_A_periph(AT91_PIN_PB7, 1);
773         if (pins & ATMEL_SSC_TD)
774                 at91_set_A_periph(AT91_PIN_PB8, 1);
775         if (pins & ATMEL_SSC_RD)
776                 at91_set_A_periph(AT91_PIN_PB9, 1);
777         if (pins & ATMEL_SSC_RK)
778                 at91_set_A_periph(AT91_PIN_PB10, 1);
779         if (pins & ATMEL_SSC_RF)
780                 at91_set_A_periph(AT91_PIN_PB11, 1);
781 }
782
783 /*
784  * SSC controllers are accessed through library code, instead of any
785  * kind of all-singing/all-dancing driver.  For example one could be
786  * used by a particular I2S audio codec's driver, while another one
787  * on the same system might be used by a custom data capture driver.
788  */
789 void __init at91_add_device_ssc(unsigned id, unsigned pins)
790 {
791         struct platform_device *pdev;
792
793         /*
794          * NOTE: caller is responsible for passing information matching
795          * "pins" to whatever will be using each particular controller.
796          */
797         switch (id) {
798         case AT91CAP9_ID_SSC0:
799                 pdev = &at91cap9_ssc0_device;
800                 configure_ssc0_pins(pins);
801                 at91_clock_associate("ssc0_clk", &pdev->dev, "ssc");
802                 break;
803         case AT91CAP9_ID_SSC1:
804                 pdev = &at91cap9_ssc1_device;
805                 configure_ssc1_pins(pins);
806                 at91_clock_associate("ssc1_clk", &pdev->dev, "ssc");
807                 break;
808         default:
809                 return;
810         }
811
812         platform_device_register(pdev);
813 }
814
815 #else
816 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
817 #endif
818
819
820 /* --------------------------------------------------------------------
821  *  UART
822  * -------------------------------------------------------------------- */
823
824 #if defined(CONFIG_SERIAL_ATMEL)
825 static struct resource dbgu_resources[] = {
826         [0] = {
827                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
828                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
829                 .flags  = IORESOURCE_MEM,
830         },
831         [1] = {
832                 .start  = AT91_ID_SYS,
833                 .end    = AT91_ID_SYS,
834                 .flags  = IORESOURCE_IRQ,
835         },
836 };
837
838 static struct atmel_uart_data dbgu_data = {
839         .use_dma_tx     = 0,
840         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
841         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
842 };
843
844 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
845
846 static struct platform_device at91cap9_dbgu_device = {
847         .name           = "atmel_usart",
848         .id             = 0,
849         .dev            = {
850                                 .dma_mask               = &dbgu_dmamask,
851                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
852                                 .platform_data          = &dbgu_data,
853         },
854         .resource       = dbgu_resources,
855         .num_resources  = ARRAY_SIZE(dbgu_resources),
856 };
857
858 static inline void configure_dbgu_pins(void)
859 {
860         at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
861         at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
862 }
863
864 static struct resource uart0_resources[] = {
865         [0] = {
866                 .start  = AT91CAP9_BASE_US0,
867                 .end    = AT91CAP9_BASE_US0 + SZ_16K - 1,
868                 .flags  = IORESOURCE_MEM,
869         },
870         [1] = {
871                 .start  = AT91CAP9_ID_US0,
872                 .end    = AT91CAP9_ID_US0,
873                 .flags  = IORESOURCE_IRQ,
874         },
875 };
876
877 static struct atmel_uart_data uart0_data = {
878         .use_dma_tx     = 1,
879         .use_dma_rx     = 1,
880 };
881
882 static u64 uart0_dmamask = DMA_BIT_MASK(32);
883
884 static struct platform_device at91cap9_uart0_device = {
885         .name           = "atmel_usart",
886         .id             = 1,
887         .dev            = {
888                                 .dma_mask               = &uart0_dmamask,
889                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
890                                 .platform_data          = &uart0_data,
891         },
892         .resource       = uart0_resources,
893         .num_resources  = ARRAY_SIZE(uart0_resources),
894 };
895
896 static inline void configure_usart0_pins(unsigned pins)
897 {
898         at91_set_A_periph(AT91_PIN_PA22, 1);            /* TXD0 */
899         at91_set_A_periph(AT91_PIN_PA23, 0);            /* RXD0 */
900
901         if (pins & ATMEL_UART_RTS)
902                 at91_set_A_periph(AT91_PIN_PA24, 0);    /* RTS0 */
903         if (pins & ATMEL_UART_CTS)
904                 at91_set_A_periph(AT91_PIN_PA25, 0);    /* CTS0 */
905 }
906
907 static struct resource uart1_resources[] = {
908         [0] = {
909                 .start  = AT91CAP9_BASE_US1,
910                 .end    = AT91CAP9_BASE_US1 + SZ_16K - 1,
911                 .flags  = IORESOURCE_MEM,
912         },
913         [1] = {
914                 .start  = AT91CAP9_ID_US1,
915                 .end    = AT91CAP9_ID_US1,
916                 .flags  = IORESOURCE_IRQ,
917         },
918 };
919
920 static struct atmel_uart_data uart1_data = {
921         .use_dma_tx     = 1,
922         .use_dma_rx     = 1,
923 };
924
925 static u64 uart1_dmamask = DMA_BIT_MASK(32);
926
927 static struct platform_device at91cap9_uart1_device = {
928         .name           = "atmel_usart",
929         .id             = 2,
930         .dev            = {
931                                 .dma_mask               = &uart1_dmamask,
932                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
933                                 .platform_data          = &uart1_data,
934         },
935         .resource       = uart1_resources,
936         .num_resources  = ARRAY_SIZE(uart1_resources),
937 };
938
939 static inline void configure_usart1_pins(unsigned pins)
940 {
941         at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
942         at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
943
944         if (pins & ATMEL_UART_RTS)
945                 at91_set_B_periph(AT91_PIN_PD7, 0);     /* RTS1 */
946         if (pins & ATMEL_UART_CTS)
947                 at91_set_B_periph(AT91_PIN_PD8, 0);     /* CTS1 */
948 }
949
950 static struct resource uart2_resources[] = {
951         [0] = {
952                 .start  = AT91CAP9_BASE_US2,
953                 .end    = AT91CAP9_BASE_US2 + SZ_16K - 1,
954                 .flags  = IORESOURCE_MEM,
955         },
956         [1] = {
957                 .start  = AT91CAP9_ID_US2,
958                 .end    = AT91CAP9_ID_US2,
959                 .flags  = IORESOURCE_IRQ,
960         },
961 };
962
963 static struct atmel_uart_data uart2_data = {
964         .use_dma_tx     = 1,
965         .use_dma_rx     = 1,
966 };
967
968 static u64 uart2_dmamask = DMA_BIT_MASK(32);
969
970 static struct platform_device at91cap9_uart2_device = {
971         .name           = "atmel_usart",
972         .id             = 3,
973         .dev            = {
974                                 .dma_mask               = &uart2_dmamask,
975                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
976                                 .platform_data          = &uart2_data,
977         },
978         .resource       = uart2_resources,
979         .num_resources  = ARRAY_SIZE(uart2_resources),
980 };
981
982 static inline void configure_usart2_pins(unsigned pins)
983 {
984         at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
985         at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
986
987         if (pins & ATMEL_UART_RTS)
988                 at91_set_B_periph(AT91_PIN_PD5, 0);     /* RTS2 */
989         if (pins & ATMEL_UART_CTS)
990                 at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
991 }
992
993 static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
994 struct platform_device *atmel_default_console_device;   /* the serial console device */
995
996 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
997 {
998         struct platform_device *pdev;
999
1000         switch (id) {
1001                 case 0:         /* DBGU */
1002                         pdev = &at91cap9_dbgu_device;
1003                         configure_dbgu_pins();
1004                         at91_clock_associate("mck", &pdev->dev, "usart");
1005                         break;
1006                 case AT91CAP9_ID_US0:
1007                         pdev = &at91cap9_uart0_device;
1008                         configure_usart0_pins(pins);
1009                         at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1010                         break;
1011                 case AT91CAP9_ID_US1:
1012                         pdev = &at91cap9_uart1_device;
1013                         configure_usart1_pins(pins);
1014                         at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1015                         break;
1016                 case AT91CAP9_ID_US2:
1017                         pdev = &at91cap9_uart2_device;
1018                         configure_usart2_pins(pins);
1019                         at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1020                         break;
1021                 default:
1022                         return;
1023         }
1024         pdev->id = portnr;              /* update to mapped ID */
1025
1026         if (portnr < ATMEL_MAX_UART)
1027                 at91_uarts[portnr] = pdev;
1028 }
1029
1030 void __init at91_set_serial_console(unsigned portnr)
1031 {
1032         if (portnr < ATMEL_MAX_UART)
1033                 atmel_default_console_device = at91_uarts[portnr];
1034         if (!atmel_default_console_device)
1035                 printk(KERN_INFO "AT91: No default serial console defined.\n");
1036 }
1037
1038 void __init at91_add_device_serial(void)
1039 {
1040         int i;
1041
1042         for (i = 0; i < ATMEL_MAX_UART; i++) {
1043                 if (at91_uarts[i])
1044                         platform_device_register(at91_uarts[i]);
1045         }
1046 }
1047 #else
1048 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1049 void __init at91_set_serial_console(unsigned portnr) {}
1050 void __init at91_add_device_serial(void) {}
1051 #endif
1052
1053
1054 /* -------------------------------------------------------------------- */
1055 /*
1056  * These devices are always present and don't need any board-specific
1057  * setup.
1058  */
1059 static int __init at91_add_standard_devices(void)
1060 {
1061         at91_add_device_rtt();
1062         at91_add_device_watchdog();
1063         return 0;
1064 }
1065
1066 arch_initcall(at91_add_standard_devices);