2 * omap_uwire.c -- MicroWire interface driver for OMAP
4 * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
6 * Ported to 2.6 OMAP uwire interface.
7 * Copyright (C) 2004 Texas Instruments.
9 * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
11 * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
12 * Copyright (C) 2006 Nokia
14 * Many updates by Imre Deak <imre.deak@nokia.com>
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #include <linux/kernel.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/platform_device.h>
40 #include <linux/workqueue.h>
41 #include <linux/interrupt.h>
42 #include <linux/err.h>
43 #include <linux/clk.h>
45 #include <linux/spi/spi.h>
46 #include <linux/spi/spi_bitbang.h>
48 #include <asm/system.h>
50 #include <mach/hardware.h>
52 #include <asm/mach-types.h>
55 #include <mach/omap730.h> /* OMAP730_IO_CONF registers */
58 /* FIXME address is now a platform device resource,
59 * and irqs should show there too...
61 #define UWIRE_BASE_PHYS 0xFFFB3000
63 /* uWire Registers: */
64 #define UWIRE_IO_SIZE 0x20
65 #define UWIRE_TDR 0x00
66 #define UWIRE_RDR 0x00
67 #define UWIRE_CSR 0x01
68 #define UWIRE_SR1 0x02
69 #define UWIRE_SR2 0x03
70 #define UWIRE_SR3 0x04
71 #define UWIRE_SR4 0x05
72 #define UWIRE_SR5 0x06
75 #define RDRB (1 << 15)
76 #define CSRB (1 << 14)
77 #define START (1 << 13)
78 #define CS_CMD (1 << 12)
81 #define UWIRE_READ_FALLING_EDGE 0x0001
82 #define UWIRE_READ_RISING_EDGE 0x0000
83 #define UWIRE_WRITE_FALLING_EDGE 0x0000
84 #define UWIRE_WRITE_RISING_EDGE 0x0002
85 #define UWIRE_CS_ACTIVE_LOW 0x0000
86 #define UWIRE_CS_ACTIVE_HIGH 0x0004
87 #define UWIRE_FREQ_DIV_2 0x0000
88 #define UWIRE_FREQ_DIV_4 0x0008
89 #define UWIRE_FREQ_DIV_8 0x0010
90 #define UWIRE_CHK_READY 0x0020
91 #define UWIRE_CLK_INVERTED 0x0040
95 struct spi_bitbang bitbang;
100 unsigned bits_per_word;
104 /* REVISIT compile time constant for idx_shift? */
106 * Or, put it in a structure which is used throughout the driver;
107 * that avoids having to issue two loads for each bit of static data.
109 static unsigned int uwire_idx_shift;
110 static void __iomem *uwire_base;
112 static inline void uwire_write_reg(int idx, u16 val)
114 __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
117 static inline u16 uwire_read_reg(int idx)
119 return __raw_readw(uwire_base + (idx << uwire_idx_shift));
122 static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
127 if (flags & UWIRE_CLK_INVERTED)
139 w = uwire_read_reg(reg);
140 w &= ~(0x3f << shift);
142 uwire_write_reg(reg, w);
145 static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
149 unsigned long max_jiffies = jiffies + HZ;
152 w = uwire_read_reg(UWIRE_CSR);
153 if ((w & mask) == val)
155 if (time_after(jiffies, max_jiffies)) {
156 printk(KERN_ERR "%s: timeout. reg=%#06x "
157 "mask=%#06x val=%#06x\n",
158 __func__, w, mask, val);
162 if (might_not_catch && c > 64)
168 static void uwire_set_clk1_div(int div1_idx)
172 w = uwire_read_reg(UWIRE_SR3);
175 uwire_write_reg(UWIRE_SR3, w);
178 static void uwire_chipselect(struct spi_device *spi, int value)
180 struct uwire_state *ust = spi->controller_state;
185 BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
187 w = uwire_read_reg(UWIRE_CSR);
188 old_cs = (w >> 10) & 0x03;
189 if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
190 /* Deselect this CS, or the previous CS */
192 uwire_write_reg(UWIRE_CSR, w);
194 /* activate specfied chipselect */
195 if (value == BITBANG_CS_ACTIVE) {
196 uwire_set_clk1_div(ust->div1_idx);
198 if (spi->mode & SPI_CPOL)
199 uwire_write_reg(UWIRE_SR4, 1);
201 uwire_write_reg(UWIRE_SR4, 0);
203 w = spi->chip_select << 10;
205 uwire_write_reg(UWIRE_CSR, w);
209 static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
211 struct uwire_state *ust = spi->controller_state;
212 unsigned len = t->len;
213 unsigned bits = ust->bits_per_word;
218 if (!t->tx_buf && !t->rx_buf)
221 /* Microwire doesn't read and write concurrently */
222 if (t->tx_buf && t->rx_buf)
225 w = spi->chip_select << 10;
229 const u8 *buf = t->tx_buf;
231 /* NOTE: DMA could be used for TX transfers */
233 /* write one or two bytes at a time */
235 /* tx bit 15 is first sent; we byteswap multibyte words
236 * (msb-first) on the way out from memory.
247 pr_debug("%s: write-%d =%04x\n",
248 dev_name(&spi->dev), bits, val);
250 if (wait_uwire_csr_flag(CSRB, 0, 0))
253 uwire_write_reg(UWIRE_TDR, val);
256 val = START | w | (bits << 5);
258 uwire_write_reg(UWIRE_CSR, val);
261 /* Wait till write actually starts.
262 * This is needed with MPU clock 60+ MHz.
263 * REVISIT: we may not have time to catch it...
265 if (wait_uwire_csr_flag(CSRB, CSRB, 1))
271 /* REVISIT: save this for later to get more i/o overlap */
272 if (wait_uwire_csr_flag(CSRB, 0, 0))
275 } else if (t->rx_buf) {
278 /* read one or two bytes at a time */
286 val = START | w | (bits << 0);
287 uwire_write_reg(UWIRE_CSR, val);
290 /* Wait till read actually starts */
291 (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
293 if (wait_uwire_csr_flag(RDRB | CSRB,
297 /* rx bit 0 is last received; multibyte words will
298 * be properly byteswapped on the way to memory.
300 val = uwire_read_reg(UWIRE_RDR);
301 val &= (1 << bits) - 1;
307 pr_debug("%s: read-%d =%04x\n",
308 dev_name(&spi->dev), bits, val);
318 static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
320 struct uwire_state *ust = spi->controller_state;
321 struct uwire_spi *uwire;
331 uwire = spi_master_get_devdata(spi->master);
333 if (spi->chip_select > 3) {
334 pr_debug("%s: cs%d?\n", dev_name(&spi->dev), spi->chip_select);
339 bits = spi->bits_per_word;
340 if (t != NULL && t->bits_per_word)
341 bits = t->bits_per_word;
346 pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits);
350 ust->bits_per_word = bits;
352 /* mode 0..3, clock inverted separately;
353 * standard nCS signaling;
354 * don't treat DI=high as "not ready"
356 if (spi->mode & SPI_CS_HIGH)
357 flags |= UWIRE_CS_ACTIVE_HIGH;
359 if (spi->mode & SPI_CPOL)
360 flags |= UWIRE_CLK_INVERTED;
362 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
365 flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
369 flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
373 /* assume it's already enabled */
374 rate = clk_get_rate(uwire->ck);
376 hz = spi->max_speed_hz;
377 if (t != NULL && t->speed_hz)
381 pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
386 /* F_INT = mpu_xor_clk / DIV1 */
387 for (div1_idx = 0; div1_idx < 4; div1_idx++) {
403 div2 = (rate / div1 + hz - 1) / hz;
408 pr_debug("%s: lowest clock %ld, need %d\n",
409 dev_name(&spi->dev), rate / 10 / 8, hz);
414 /* we have to cache this and reset in uwire_chipselect as this is a
415 * global parameter and another uwire device can change it under
417 ust->div1_idx = div1_idx;
418 uwire_set_clk1_div(div1_idx);
426 flags |= UWIRE_FREQ_DIV_2;
431 flags |= UWIRE_FREQ_DIV_4;
438 flags |= UWIRE_FREQ_DIV_8;
442 omap_uwire_configure_mode(spi->chip_select, flags);
443 pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
445 clk_get_rate(uwire->ck) / 1000,
452 /* the spi->mode bits understood by this driver: */
453 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
455 static int uwire_setup(struct spi_device *spi)
457 struct uwire_state *ust = spi->controller_state;
459 if (spi->mode & ~MODEBITS) {
460 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
461 spi->mode & ~MODEBITS);
466 ust = kzalloc(sizeof(*ust), GFP_KERNEL);
469 spi->controller_state = ust;
472 return uwire_setup_transfer(spi, NULL);
475 static void uwire_cleanup(struct spi_device *spi)
477 kfree(spi->controller_state);
480 static void uwire_off(struct uwire_spi *uwire)
482 uwire_write_reg(UWIRE_SR3, 0);
483 clk_disable(uwire->ck);
485 spi_master_put(uwire->bitbang.master);
488 static int __init uwire_probe(struct platform_device *pdev)
490 struct spi_master *master;
491 struct uwire_spi *uwire;
494 master = spi_alloc_master(&pdev->dev, sizeof *uwire);
498 uwire = spi_master_get_devdata(master);
500 uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
502 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
503 spi_master_put(master);
507 dev_set_drvdata(&pdev->dev, uwire);
509 uwire->ck = clk_get(&pdev->dev, "armxor_ck");
510 if (!uwire->ck || IS_ERR(uwire->ck)) {
511 dev_dbg(&pdev->dev, "no mpu_xor_clk ?\n");
512 spi_master_put(master);
515 clk_enable(uwire->ck);
517 if (cpu_is_omap730())
522 uwire_write_reg(UWIRE_SR3, 1);
524 master->bus_num = 2; /* "official" */
525 master->num_chipselect = 4;
526 master->setup = uwire_setup;
527 master->cleanup = uwire_cleanup;
529 uwire->bitbang.master = master;
530 uwire->bitbang.chipselect = uwire_chipselect;
531 uwire->bitbang.setup_transfer = uwire_setup_transfer;
532 uwire->bitbang.txrx_bufs = uwire_txrx;
534 status = spi_bitbang_start(&uwire->bitbang);
542 static int __exit uwire_remove(struct platform_device *pdev)
544 struct uwire_spi *uwire = dev_get_drvdata(&pdev->dev);
547 // FIXME remove all child devices, somewhere ...
549 status = spi_bitbang_stop(&uwire->bitbang);
555 /* work with hotplug and coldplug */
556 MODULE_ALIAS("platform:omap_uwire");
558 static struct platform_driver uwire_driver = {
560 .name = "omap_uwire",
561 .owner = THIS_MODULE,
563 .remove = __exit_p(uwire_remove),
564 // suspend ... unuse ck
568 static int __init omap_uwire_init(void)
570 /* FIXME move these into the relevant board init code. also, include
571 * H3 support; it uses tsc2101 like H2 (on a different chipselect).
574 if (machine_is_omap_h2()) {
575 /* defaults: W21 SDO, U18 SDI, V19 SCL */
576 omap_cfg_reg(N14_1610_UWIRE_CS0);
577 omap_cfg_reg(N15_1610_UWIRE_CS1);
579 if (machine_is_omap_perseus2()) {
580 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
581 int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000;
582 omap_writel(val | 0x00AAA000, OMAP730_IO_CONF_9);
585 return platform_driver_probe(&uwire_driver, uwire_probe);
588 static void __exit omap_uwire_exit(void)
590 platform_driver_unregister(&uwire_driver);
593 subsys_initcall(omap_uwire_init);
594 module_exit(omap_uwire_exit);
596 MODULE_LICENSE("GPL");