git.oblomov.eu Git - linux-2.6/blob - drivers/net/ixgbe/ixgbe_82599.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82599_MAX_TX_QUEUES 128
  36 #define IXGBE_82599_MAX_RX_QUEUES 128
  37 #define IXGBE_82599_RAR_ENTRIES   128
  38 #define IXGBE_82599_MC_TBL_SIZE   128
  39 #define IXGBE_82599_VFT_TBL_SIZE  128
  40
  41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
  42                                       ixgbe_link_speed *speed,
  43                                       bool *autoneg);
  44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
  45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
  46 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
  47                                      ixgbe_link_speed speed, bool autoneg,
  48                                      bool autoneg_wait_to_complete);
  49 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
  50 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
  51                                ixgbe_link_speed *speed,
  52                                bool *link_up, bool link_up_wait_to_complete);
  53 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
  54                                      ixgbe_link_speed speed,
  55                                      bool autoneg,
  56                                      bool autoneg_wait_to_complete);
  57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
  58                                              ixgbe_link_speed *speed,
  59                                              bool *autoneg);
  60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
  61 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
  62                                                ixgbe_link_speed speed,
  63                                                bool autoneg,
  64                                                bool autoneg_wait_to_complete);
  65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
  66 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  67 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  68 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
  69                          u32 vind, bool vlan_on);
  70 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
  71 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
  72 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
  73 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
  74 s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
  75 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
  76 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
  77 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
  78
  79 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
  80 {
  81         struct ixgbe_mac_info *mac = &hw->mac;
  82         if (hw->phy.multispeed_fiber) {
  83                 /* Set up dual speed SFP+ support */
  84                 mac->ops.setup_link =
  85                           &ixgbe_setup_mac_link_multispeed_fiber;
  86                 mac->ops.setup_link_speed =
  87                           &ixgbe_setup_mac_link_speed_multispeed_fiber;
  88         } else {
  89                 mac->ops.setup_link =
  90                           &ixgbe_setup_mac_link_82599;
  91                 mac->ops.setup_link_speed =
  92                           &ixgbe_setup_mac_link_speed_82599;
  93         }
  94 }
  95
  96 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
  97 {
  98         s32 ret_val = 0;
  99         u16 list_offset, data_offset, data_value;
 100
 101         if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
 102                 ixgbe_init_mac_link_ops_82599(hw);
 103
 104                 hw->phy.ops.reset = NULL;
 105
 106                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 107                                                               &data_offset);
 108
 109                 if (ret_val != 0)
 110                         goto setup_sfp_out;
 111
 112                 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 113                 while (data_value != 0xffff) {
 114                         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
 115                         IXGBE_WRITE_FLUSH(hw);
 116                         hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 117                 }
 118                 /* Now restart DSP */
 119                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
 120                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
 121                 IXGBE_WRITE_FLUSH(hw);
 122         }
 123
 124 setup_sfp_out:
 125         return ret_val;
 126 }
 127
 128 /**
 129  *  ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
 130  *  @hw: pointer to hardware structure
 131  *
 132  *  Read PCIe configuration space, and get the MSI-X vector count from
 133  *  the capabilities table.
 134  **/
 135 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
 136 {
 137         struct ixgbe_adapter *adapter = hw->back;
 138         u16 msix_count;
 139         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
 140                              &msix_count);
 141         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
 142
 143         /* MSI-X count is zero-based in HW, so increment to give proper value */
 144         msix_count++;
 145
 146         return msix_count;
 147 }
 148
 149 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
 150 {
 151         struct ixgbe_mac_info *mac = &hw->mac;
 152
 153         ixgbe_init_mac_link_ops_82599(hw);
 154
 155         mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
 156         mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
 157         mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
 158         mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
 159         mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
 160         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
 161
 162         return 0;
 163 }
 164
 165 /**
 166  *  ixgbe_init_phy_ops_82599 - PHY/SFP specific init
 167  *  @hw: pointer to hardware structure
 168  *
 169  *  Initialize any function pointers that were not able to be
 170  *  set during get_invariants because the PHY/SFP type was
 171  *  not known.  Perform the SFP init if necessary.
 172  *
 173  **/
 174 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
 175 {
 176         struct ixgbe_mac_info *mac = &hw->mac;
 177         struct ixgbe_phy_info *phy = &hw->phy;
 178         s32 ret_val = 0;
 179
 180         /* Identify the PHY or SFP module */
 181         ret_val = phy->ops.identify(hw);
 182
 183         /* Setup function pointers based on detected SFP module and speeds */
 184         ixgbe_init_mac_link_ops_82599(hw);
 185
 186         /* If copper media, overwrite with copper function pointers */
 187         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 188                 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
 189                 mac->ops.setup_link_speed =
 190                                      &ixgbe_setup_copper_link_speed_82599;
 191                 mac->ops.get_link_capabilities =
 192                                   &ixgbe_get_copper_link_capabilities_82599;
 193         }
 194
 195         /* Set necessary function pointers based on phy type */
 196         switch (hw->phy.type) {
 197         case ixgbe_phy_tn:
 198                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 199                 phy->ops.get_firmware_version =
 200                              &ixgbe_get_phy_firmware_version_tnx;
 201                 break;
 202         default:
 203                 break;
 204         }
 205
 206         return ret_val;
 207 }
 208
 209 /**
 210  *  ixgbe_get_link_capabilities_82599 - Determines link capabilities
 211  *  @hw: pointer to hardware structure
 212  *  @speed: pointer to link speed
 213  *  @negotiation: true when autoneg or autotry is enabled
 214  *
 215  *  Determines the link capabilities by reading the AUTOC register.
 216  **/
 217 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
 218                                       ixgbe_link_speed *speed,
 219                                       bool *negotiation)
 220 {
 221         s32 status = 0;
 222         u32 autoc = 0;
 223
 224         /*
 225          * Determine link capabilities based on the stored value of AUTOC,
 226          * which represents EEPROM defaults.  If AUTOC value has not been
 227          * stored, use the current register value.
 228          */
 229         if (hw->mac.orig_link_settings_stored)
 230                 autoc = hw->mac.orig_autoc;
 231         else
 232                 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 233
 234         switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 235         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 236                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 237                 *negotiation = false;
 238                 break;
 239
 240         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 241                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 242                 *negotiation = false;
 243                 break;
 244
 245         case IXGBE_AUTOC_LMS_1G_AN:
 246                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 247                 *negotiation = true;
 248                 break;
 249
 250         case IXGBE_AUTOC_LMS_10G_SERIAL:
 251                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 252                 *negotiation = false;
 253                 break;
 254
 255         case IXGBE_AUTOC_LMS_KX4_KX_KR:
 256         case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
 257                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 258                 if (autoc & IXGBE_AUTOC_KR_SUPP)
 259                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 260                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
 261                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 262                 if (autoc & IXGBE_AUTOC_KX_SUPP)
 263                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 264                 *negotiation = true;
 265                 break;
 266
 267         case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
 268                 *speed = IXGBE_LINK_SPEED_100_FULL;
 269                 if (autoc & IXGBE_AUTOC_KR_SUPP)
 270                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 271                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
 272                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 273                 if (autoc & IXGBE_AUTOC_KX_SUPP)
 274                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 275                 *negotiation = true;
 276                 break;
 277
 278         case IXGBE_AUTOC_LMS_SGMII_1G_100M:
 279                 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
 280                 *negotiation = false;
 281                 break;
 282
 283         default:
 284                 status = IXGBE_ERR_LINK_SETUP;
 285                 goto out;
 286                 break;
 287         }
 288
 289         if (hw->phy.multispeed_fiber) {
 290                 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
 291                           IXGBE_LINK_SPEED_1GB_FULL;
 292                 *negotiation = true;
 293         }
 294
 295 out:
 296         return status;
 297 }
 298
 299 /**
 300  *  ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
 301  *  @hw: pointer to hardware structure
 302  *  @speed: pointer to link speed
 303  *  @autoneg: boolean auto-negotiation value
 304  *
 305  *  Determines the link capabilities by reading the AUTOC register.
 306  **/
 307 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
 308                                                     ixgbe_link_speed *speed,
 309                                                     bool *autoneg)
 310 {
 311         s32 status = IXGBE_ERR_LINK_SETUP;
 312         u16 speed_ability;
 313
 314         *speed = 0;
 315         *autoneg = true;
 316
 317         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 318                                       &speed_ability);
 319
 320         if (status == 0) {
 321                 if (speed_ability & MDIO_SPEED_10G)
 322                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 323                 if (speed_ability & MDIO_PMA_SPEED_1000)
 324                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 325         }
 326
 327         return status;
 328 }
 329
 330 /**
 331  *  ixgbe_get_media_type_82599 - Get media type
 332  *  @hw: pointer to hardware structure
 333  *
 334  *  Returns the media type (fiber, copper, backplane)
 335  **/
 336 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
 337 {
 338         enum ixgbe_media_type media_type;
 339
 340         /* Detect if there is a copper PHY attached. */
 341         if (hw->phy.type == ixgbe_phy_cu_unknown ||
 342             hw->phy.type == ixgbe_phy_tn) {
 343                 media_type = ixgbe_media_type_copper;
 344                 goto out;
 345         }
 346
 347         switch (hw->device_id) {
 348         case IXGBE_DEV_ID_82599:
 349         case IXGBE_DEV_ID_82599_KX4:
 350                 /* Default device ID is mezzanine card KX/KX4 */
 351                 media_type = ixgbe_media_type_backplane;
 352                 break;
 353         case IXGBE_DEV_ID_82599_SFP:
 354                 media_type = ixgbe_media_type_fiber;
 355                 break;
 356         default:
 357                 media_type = ixgbe_media_type_unknown;
 358                 break;
 359         }
 360 out:
 361         return media_type;
 362 }
 363
 364 /**
 365  *  ixgbe_setup_mac_link_82599 - Setup MAC link settings
 366  *  @hw: pointer to hardware structure
 367  *
 368  *  Configures link settings based on values in the ixgbe_hw struct.
 369  *  Restarts the link.  Performs autonegotiation if needed.
 370  **/
 371 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
 372 {
 373         u32 autoc_reg;
 374         u32 links_reg;
 375         u32 i;
 376         s32 status = 0;
 377
 378         /* Restart link */
 379         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 380         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 381         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 382
 383         /* Only poll for autoneg to complete if specified to do so */
 384         if (hw->phy.autoneg_wait_to_complete) {
 385                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 386                      IXGBE_AUTOC_LMS_KX4_KX_KR ||
 387                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 388                      IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 389                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 390                      IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 391                         links_reg = 0; /* Just in case Autoneg time = 0 */
 392                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 393                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 394                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 395                                         break;
 396                                 msleep(100);
 397                         }
 398                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 399                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 400                                 hw_dbg(hw, "Autoneg did not complete.\n");
 401                         }
 402                 }
 403         }
 404
 405         /* Set up flow control */
 406         status = ixgbe_setup_fc_generic(hw, 0);
 407
 408         /* Add delay to filter out noises during initial link setup */
 409         msleep(50);
 410
 411         return status;
 412 }
 413
 414 /**
 415  *  ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
 416  *  @hw: pointer to hardware structure
 417  *
 418  *  Configures link settings based on values in the ixgbe_hw struct.
 419  *  Restarts the link for multi-speed fiber at 1G speed, if link
 420  *  fails at 10G.
 421  *  Performs autonegotiation if needed.
 422  **/
 423 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
 424 {
 425         s32 status = 0;
 426         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
 427         status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
 428                                                              true, true);
 429         return status;
 430 }
 431
 432 /**
 433  *  ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
 434  *  @hw: pointer to hardware structure
 435  *  @speed: new link speed
 436  *  @autoneg: true if autonegotiation enabled
 437  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 438  *
 439  *  Set the link speed in the AUTOC register and restarts link.
 440  **/
 441 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
 442                                                 ixgbe_link_speed speed,
 443                                                 bool autoneg,
 444                                                 bool autoneg_wait_to_complete)
 445 {
 446         s32 status = 0;
 447         ixgbe_link_speed phy_link_speed;
 448         ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 449         u32 speedcnt = 0;
 450         u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 451         bool link_up = false;
 452         bool negotiation;
 453
 454         /* Mask off requested but non-supported speeds */
 455         hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
 456         speed &= phy_link_speed;
 457
 458         /*
 459          * Try each speed one by one, highest priority first.  We do this in
 460          * software because 10gb fiber doesn't support speed autonegotiation.
 461          */
 462         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 463                 speedcnt++;
 464                 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
 465
 466                 /* Set hardware SDP's */
 467                 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
 468                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 469
 470                 ixgbe_setup_mac_link_speed_82599(hw,
 471                                                  IXGBE_LINK_SPEED_10GB_FULL,
 472                                                  autoneg,
 473                                                  autoneg_wait_to_complete);
 474
 475                 msleep(50);
 476
 477                 /* If we have link, just jump out */
 478                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
 479                 if (link_up)
 480                         goto out;
 481         }
 482
 483         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 484                 speedcnt++;
 485                 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
 486                         highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
 487
 488                 /* Set hardware SDP's */
 489                 esdp_reg &= ~IXGBE_ESDP_SDP5;
 490                 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
 491                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 492
 493                 ixgbe_setup_mac_link_speed_82599(
 494                         hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
 495                         autoneg_wait_to_complete);
 496
 497                 msleep(50);
 498
 499                 /* If we have link, just jump out */
 500                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
 501                 if (link_up)
 502                         goto out;
 503         }
 504
 505         /*
 506          * We didn't get link.  Configure back to the highest speed we tried,
 507          * (if there was more than one).  We call ourselves back with just the
 508          * single highest speed that the user requested.
 509          */
 510         if (speedcnt > 1)
 511                 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
 512                                                      highest_link_speed,
 513                                                      autoneg,
 514                                                      autoneg_wait_to_complete);
 515
 516 out:
 517         return status;
 518 }
 519
 520 /**
 521  *  ixgbe_check_mac_link_82599 - Determine link and speed status
 522  *  @hw: pointer to hardware structure
 523  *  @speed: pointer to link speed
 524  *  @link_up: true when link is up
 525  *  @link_up_wait_to_complete: bool used to wait for link up or not
 526  *
 527  *  Reads the links register to determine if link is up and the current speed
 528  **/
 529 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 530                                bool *link_up, bool link_up_wait_to_complete)
 531 {
 532         u32 links_reg;
 533         u32 i;
 534
 535         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 536         if (link_up_wait_to_complete) {
 537                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 538                         if (links_reg & IXGBE_LINKS_UP) {
 539                                 *link_up = true;
 540                                 break;
 541                         } else {
 542                                 *link_up = false;
 543                         }
 544                         msleep(100);
 545                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 546                 }
 547         } else {
 548                 if (links_reg & IXGBE_LINKS_UP)
 549                         *link_up = true;
 550                 else
 551                         *link_up = false;
 552         }
 553
 554         if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 555             IXGBE_LINKS_SPEED_10G_82599)
 556                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 557         else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 558                  IXGBE_LINKS_SPEED_1G_82599)
 559                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 560         else
 561                 *speed = IXGBE_LINK_SPEED_100_FULL;
 562
 563
 564         return 0;
 565 }
 566
 567 /**
 568  *  ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
 569  *  @hw: pointer to hardware structure
 570  *  @speed: new link speed
 571  *  @autoneg: true if autonegotiation enabled
 572  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 573  *
 574  *  Set the link speed in the AUTOC register and restarts link.
 575  **/
 576 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
 577                                      ixgbe_link_speed speed, bool autoneg,
 578                                      bool autoneg_wait_to_complete)
 579 {
 580         s32 status = 0;
 581         u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 582         u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 583         u32 orig_autoc = 0;
 584         u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
 585         u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
 586         u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
 587         u32 links_reg;
 588         u32 i;
 589         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 590
 591         /* Check to see if speed passed in is supported. */
 592         hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
 593         speed &= link_capabilities;
 594
 595         /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
 596         if (hw->mac.orig_link_settings_stored)
 597                 orig_autoc = hw->mac.orig_autoc;
 598         else
 599                 orig_autoc = autoc;
 600
 601
 602         if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
 603                 status = IXGBE_ERR_LINK_SETUP;
 604         } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 605                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 606                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 607                 /* Set KX4/KX/KR support according to speed requested */
 608                 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
 609                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 610                         if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 611                                 autoc |= IXGBE_AUTOC_KX4_SUPP;
 612                         if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
 613                                 autoc |= IXGBE_AUTOC_KR_SUPP;
 614                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 615                         autoc |= IXGBE_AUTOC_KX_SUPP;
 616         } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
 617                    (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
 618                     link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
 619                 /* Switch from 1G SFI to 10G SFI if requested */
 620                 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
 621                     (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
 622                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
 623                         autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
 624                 }
 625         } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
 626                    (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
 627                 /* Switch from 10G SFI to 1G SFI if requested */
 628                 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
 629                     (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
 630                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
 631                         if (autoneg)
 632                                 autoc |= IXGBE_AUTOC_LMS_1G_AN;
 633                         else
 634                                 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
 635                 }
 636         }
 637
 638         if (status == 0) {
 639                 /* Restart link */
 640                 autoc |= IXGBE_AUTOC_AN_RESTART;
 641                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 642
 643                 /* Only poll for autoneg to complete if specified to do so */
 644                 if (autoneg_wait_to_complete) {
 645                         if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 646                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 647                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 648                                 links_reg = 0; /*Just in case Autoneg time=0*/
 649                                 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 650                                         links_reg =
 651                                                IXGBE_READ_REG(hw, IXGBE_LINKS);
 652                                         if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 653                                                 break;
 654                                         msleep(100);
 655                                 }
 656                                 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 657                                         status =
 658                                                 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 659                                         hw_dbg(hw, "Autoneg did not "
 660                                                "complete.\n");
 661                                 }
 662                         }
 663                 }
 664
 665                 /* Set up flow control */
 666                 status = ixgbe_setup_fc_generic(hw, 0);
 667
 668                 /* Add delay to filter out noises during initial link setup */
 669                 msleep(50);
 670         }
 671
 672         return status;
 673 }
 674
 675 /**
 676  *  ixgbe_setup_copper_link_82599 - Setup copper link settings
 677  *  @hw: pointer to hardware structure
 678  *
 679  *  Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
 680  **/
 681 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
 682 {
 683         s32 status;
 684
 685         /* Restart autonegotiation on PHY */
 686         status = hw->phy.ops.setup_link(hw);
 687
 688         /* Set up MAC */
 689         ixgbe_setup_mac_link_82599(hw);
 690
 691         return status;
 692 }
 693
 694 /**
 695  *  ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
 696  *  @hw: pointer to hardware structure
 697  *  @speed: new link speed
 698  *  @autoneg: true if autonegotiation enabled
 699  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 700  *
 701  *  Restarts link on PHY and MAC based on settings passed in.
 702  **/
 703 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
 704                                                ixgbe_link_speed speed,
 705                                                bool autoneg,
 706                                                bool autoneg_wait_to_complete)
 707 {
 708         s32 status;
 709
 710         /* Setup the PHY according to input speed */
 711         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 712                                               autoneg_wait_to_complete);
 713         /* Set up MAC */
 714         ixgbe_setup_mac_link_82599(hw);
 715
 716         return status;
 717 }
 718
 719 /**
 720  *  ixgbe_reset_hw_82599 - Perform hardware reset
 721  *  @hw: pointer to hardware structure
 722  *
 723  *  Resets the hardware by resetting the transmit and receive units, masks
 724  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 725  *  reset.
 726  **/
 727 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
 728 {
 729         s32 status = 0;
 730         u32 ctrl, ctrl_ext;
 731         u32 i;
 732         u32 autoc;
 733         u32 autoc2;
 734
 735         /* Call adapter stop to disable tx/rx and clear interrupts */
 736         hw->mac.ops.stop_adapter(hw);
 737
 738         /* PHY ops must be identified and initialized prior to reset */
 739
 740         /* Init PHY and function pointers, perform SFP setup */
 741         status = hw->phy.ops.init(hw);
 742
 743         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 744                 goto reset_hw_out;
 745
 746         /* Setup SFP module if there is one present. */
 747         if (hw->phy.sfp_setup_needed) {
 748                 status = hw->mac.ops.setup_sfp(hw);
 749                 hw->phy.sfp_setup_needed = false;
 750         }
 751
 752         /* Reset PHY */
 753         if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
 754                 hw->phy.ops.reset(hw);
 755
 756         /*
 757          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 758          * access and verify no pending requests before reset
 759          */
 760         status = ixgbe_disable_pcie_master(hw);
 761         if (status != 0) {
 762                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 763                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 764         }
 765
 766         /*
 767          * Issue global reset to the MAC.  This needs to be a SW reset.
 768          * If link reset is used, it might reset the MAC when mng is using it
 769          */
 770         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 771         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 772         IXGBE_WRITE_FLUSH(hw);
 773
 774         /* Poll for reset bit to self-clear indicating reset is complete */
 775         for (i = 0; i < 10; i++) {
 776                 udelay(1);
 777                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 778                 if (!(ctrl & IXGBE_CTRL_RST))
 779                         break;
 780         }
 781         if (ctrl & IXGBE_CTRL_RST) {
 782                 status = IXGBE_ERR_RESET_FAILED;
 783                 hw_dbg(hw, "Reset polling failed to complete.\n");
 784         }
 785         /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
 786         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 787         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 788         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 789
 790         msleep(50);
 791
 792
 793
 794         /*
 795          * Store the original AUTOC/AUTOC2 values if they have not been
 796          * stored off yet.  Otherwise restore the stored original
 797          * values since the reset operation sets back to defaults.
 798          */
 799         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 800         autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 801         if (hw->mac.orig_link_settings_stored == false) {
 802                 hw->mac.orig_autoc = autoc;
 803                 hw->mac.orig_autoc2 = autoc2;
 804                 hw->mac.orig_link_settings_stored = true;
 805         } else {
 806                 if (autoc != hw->mac.orig_autoc)
 807                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
 808                                         IXGBE_AUTOC_AN_RESTART));
 809
 810                 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
 811                     (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
 812                         autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
 813                         autoc2 |= (hw->mac.orig_autoc2 &
 814                                    IXGBE_AUTOC2_UPPER_MASK);
 815                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 816                 }
 817         }
 818
 819         /* Store the permanent mac address */
 820         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 821
 822 reset_hw_out:
 823         return status;
 824 }
 825
 826 /**
 827  *  ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
 828  *  @hw: pointer to hardware struct
 829  *  @rar: receive address register index to disassociate
 830  *  @vmdq: VMDq pool index to remove from the rar
 831  **/
 832 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 833 {
 834         u32 mpsar_lo, mpsar_hi;
 835         u32 rar_entries = hw->mac.num_rar_entries;
 836
 837         if (rar < rar_entries) {
 838                 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 839                 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 840
 841                 if (!mpsar_lo && !mpsar_hi)
 842                         goto done;
 843
 844                 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
 845                         if (mpsar_lo) {
 846                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
 847                                 mpsar_lo = 0;
 848                         }
 849                         if (mpsar_hi) {
 850                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
 851                                 mpsar_hi = 0;
 852                         }
 853                 } else if (vmdq < 32) {
 854                         mpsar_lo &= ~(1 << vmdq);
 855                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
 856                 } else {
 857                         mpsar_hi &= ~(1 << (vmdq - 32));
 858                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
 859                 }
 860
 861                 /* was that the last pool using this rar? */
 862                 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
 863                         hw->mac.ops.clear_rar(hw, rar);
 864         } else {
 865                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 866         }
 867
 868 done:
 869         return 0;
 870 }
 871
 872 /**
 873  *  ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
 874  *  @hw: pointer to hardware struct
 875  *  @rar: receive address register index to associate with a VMDq index
 876  *  @vmdq: VMDq pool index
 877  **/
 878 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 879 {
 880         u32 mpsar;
 881         u32 rar_entries = hw->mac.num_rar_entries;
 882
 883         if (rar < rar_entries) {
 884                 if (vmdq < 32) {
 885                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 886                         mpsar |= 1 << vmdq;
 887                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
 888                 } else {
 889                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 890                         mpsar |= 1 << (vmdq - 32);
 891                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
 892                 }
 893         } else {
 894                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 895         }
 896         return 0;
 897 }
 898
 899 /**
 900  *  ixgbe_set_vfta_82599 - Set VLAN filter table
 901  *  @hw: pointer to hardware structure
 902  *  @vlan: VLAN id to write to VLAN filter
 903  *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
 904  *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
 905  *
 906  *  Turn on/off specified VLAN in the VLAN filter table.
 907  **/
 908 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 909                          bool vlan_on)
 910 {
 911         u32 regindex;
 912         u32 bitindex;
 913         u32 bits;
 914         u32 first_empty_slot;
 915
 916         if (vlan > 4095)
 917                 return IXGBE_ERR_PARAM;
 918
 919         /*
 920          * this is a 2 part operation - first the VFTA, then the
 921          * VLVF and VLVFB if vind is set
 922          */
 923
 924         /* Part 1
 925          * The VFTA is a bitstring made up of 128 32-bit registers
 926          * that enable the particular VLAN id, much like the MTA:
 927          *    bits[11-5]: which register
 928          *    bits[4-0]:  which bit in the register
 929          */
 930         regindex = (vlan >> 5) & 0x7F;
 931         bitindex = vlan & 0x1F;
 932         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 933         if (vlan_on)
 934                 bits |= (1 << bitindex);
 935         else
 936                 bits &= ~(1 << bitindex);
 937         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 938
 939
 940         /* Part 2
 941          * If the vind is set
 942          *   Either vlan_on
 943          *     make sure the vlan is in VLVF
 944          *     set the vind bit in the matching VLVFB
 945          *   Or !vlan_on
 946          *     clear the pool bit and possibly the vind
 947          */
 948         if (vind) {
 949                 /* find the vlanid or the first empty slot */
 950                 first_empty_slot = 0;
 951
 952                 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
 953                         bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
 954                         if (!bits && !first_empty_slot)
 955                                 first_empty_slot = regindex;
 956                         else if ((bits & 0x0FFF) == vlan)
 957                                 break;
 958                 }
 959
 960                 if (regindex >= IXGBE_VLVF_ENTRIES) {
 961                         if (first_empty_slot)
 962                                 regindex = first_empty_slot;
 963                         else {
 964                                 hw_dbg(hw, "No space in VLVF.\n");
 965                                 goto out;
 966                         }
 967                 }
 968
 969                 if (vlan_on) {
 970                         /* set the pool bit */
 971                         if (vind < 32) {
 972                                 bits = IXGBE_READ_REG(hw,
 973                                                     IXGBE_VLVFB(regindex * 2));
 974                                 bits |= (1 << vind);
 975                                 IXGBE_WRITE_REG(hw,
 976                                               IXGBE_VLVFB(regindex * 2), bits);
 977                         } else {
 978                                 bits = IXGBE_READ_REG(hw,
 979                                               IXGBE_VLVFB((regindex * 2) + 1));
 980                                 bits |= (1 << vind);
 981                                 IXGBE_WRITE_REG(hw,
 982                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
 983                         }
 984                 } else {
 985                         /* clear the pool bit */
 986                         if (vind < 32) {
 987                                 bits = IXGBE_READ_REG(hw,
 988                                      IXGBE_VLVFB(regindex * 2));
 989                         bits &= ~(1 << vind);
 990                                 IXGBE_WRITE_REG(hw,
 991                                               IXGBE_VLVFB(regindex * 2), bits);
 992                                 bits |= IXGBE_READ_REG(hw,
 993                                               IXGBE_VLVFB((regindex * 2) + 1));
 994                         } else {
 995                                 bits = IXGBE_READ_REG(hw,
 996                                               IXGBE_VLVFB((regindex * 2) + 1));
 997                                 bits &= ~(1 << vind);
 998                                 IXGBE_WRITE_REG(hw,
 999                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
1000                                 bits |= IXGBE_READ_REG(hw,
1001                                                     IXGBE_VLVFB(regindex * 2));
1002                         }
1003                 }
1004
1005                 if (bits)
1006                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1007                                         (IXGBE_VLVF_VIEN | vlan));
1008                 else
1009                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1010         }
1011
1012 out:
1013         return 0;
1014 }
1015
1016 /**
1017  *  ixgbe_clear_vfta_82599 - Clear VLAN filter table
1018  *  @hw: pointer to hardware structure
1019  *
1020  *  Clears the VLAN filer table, and the VMDq index associated with the filter
1021  **/
1022 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1023 {
1024         u32 offset;
1025
1026         for (offset = 0; offset < hw->mac.vft_size; offset++)
1027                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1028
1029         for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1030                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1031                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1032                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1033         }
1034
1035         return 0;
1036 }
1037
1038 /**
1039  *  ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1040  *  @hw: pointer to hardware structure
1041  **/
1042 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1043 {
1044         int i;
1045         hw_dbg(hw, " Clearing UTA\n");
1046
1047         for (i = 0; i < 128; i++)
1048                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1049
1050         return 0;
1051 }
1052
1053 /**
1054  *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1055  *  @hw: pointer to hardware structure
1056  *  @reg: analog register to read
1057  *  @val: read value
1058  *
1059  *  Performs read operation to Omer analog register specified.
1060  **/
1061 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1062 {
1063         u32  core_ctl;
1064
1065         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1066                         (reg << 8));
1067         IXGBE_WRITE_FLUSH(hw);
1068         udelay(10);
1069         core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1070         *val = (u8)core_ctl;
1071
1072         return 0;
1073 }
1074
1075 /**
1076  *  ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1077  *  @hw: pointer to hardware structure
1078  *  @reg: atlas register to write
1079  *  @val: value to write
1080  *
1081  *  Performs write operation to Omer analog register specified.
1082  **/
1083 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1084 {
1085         u32  core_ctl;
1086
1087         core_ctl = (reg << 8) | val;
1088         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1089         IXGBE_WRITE_FLUSH(hw);
1090         udelay(10);
1091
1092         return 0;
1093 }
1094
1095 /**
1096  *  ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1097  *  @hw: pointer to hardware structure
1098  *
1099  *  Starts the hardware using the generic start_hw function.
1100  *  Then performs device-specific:
1101  *  Clears the rate limiter registers.
1102  **/
1103 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1104 {
1105         u32 q_num;
1106
1107         ixgbe_start_hw_generic(hw);
1108
1109         /* Clear the rate limiters */
1110         for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1111                 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1112                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1113         }
1114         IXGBE_WRITE_FLUSH(hw);
1115
1116         return 0;
1117 }
1118
1119 /**
1120  *  ixgbe_identify_phy_82599 - Get physical layer module
1121  *  @hw: pointer to hardware structure
1122  *
1123  *  Determines the physical layer module found on the current adapter.
1124  **/
1125 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1126 {
1127         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1128         status = ixgbe_identify_phy_generic(hw);
1129         if (status != 0)
1130                 status = ixgbe_identify_sfp_module_generic(hw);
1131         return status;
1132 }
1133
1134 /**
1135  *  ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1136  *  @hw: pointer to hardware structure
1137  *
1138  *  Determines physical layer capabilities of the current configuration.
1139  **/
1140 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1141 {
1142         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1143         u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1144         u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1145         u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1146         u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1147         u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1148         u16 ext_ability = 0;
1149         u8 comp_codes_10g = 0;
1150
1151         hw->phy.ops.identify(hw);
1152
1153         if (hw->phy.type == ixgbe_phy_tn ||
1154             hw->phy.type == ixgbe_phy_cu_unknown) {
1155                 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1156                                      &ext_ability);
1157                 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1158                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1159                 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1160                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1161                 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1162                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1163                 goto out;
1164         }
1165
1166         switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1167         case IXGBE_AUTOC_LMS_1G_AN:
1168         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1169                 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1170                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1171                             IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1172                         goto out;
1173                 } else
1174                         /* SFI mode so read SFP module */
1175                         goto sfp_check;
1176                 break;
1177         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1178                 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1179                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1180                 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1181                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1182                 goto out;
1183                 break;
1184         case IXGBE_AUTOC_LMS_10G_SERIAL:
1185                 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1186                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1187                         goto out;
1188                 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1189                         goto sfp_check;
1190                 break;
1191         case IXGBE_AUTOC_LMS_KX4_KX_KR:
1192         case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1193                 if (autoc & IXGBE_AUTOC_KX_SUPP)
1194                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1195                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1196                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1197                 if (autoc & IXGBE_AUTOC_KR_SUPP)
1198                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1199                 goto out;
1200                 break;
1201         default:
1202                 goto out;
1203                 break;
1204         }
1205
1206 sfp_check:
1207         /* SFP check must be done last since DA modules are sometimes used to
1208          * test KR mode -  we need to id KR mode correctly before SFP module.
1209          * Call identify_sfp because the pluggable module may have changed */
1210         hw->phy.ops.identify_sfp(hw);
1211         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1212                 goto out;
1213
1214         switch (hw->phy.type) {
1215         case ixgbe_phy_tw_tyco:
1216         case ixgbe_phy_tw_unknown:
1217                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1218                 break;
1219         case ixgbe_phy_sfp_avago:
1220         case ixgbe_phy_sfp_ftl:
1221         case ixgbe_phy_sfp_intel:
1222         case ixgbe_phy_sfp_unknown:
1223                 hw->phy.ops.read_i2c_eeprom(hw,
1224                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1225                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1226                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1227                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1228                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1229                 break;
1230         default:
1231                 break;
1232         }
1233
1234 out:
1235         return physical_layer;
1236 }
1237
1238 /**
1239  *  ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1240  *  @hw: pointer to hardware structure
1241  *  @regval: register value to write to RXCTRL
1242  *
1243  *  Enables the Rx DMA unit for 82599
1244  **/
1245 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1246 {
1247 #define IXGBE_MAX_SECRX_POLL 30
1248         int i;
1249         int secrxreg;
1250
1251         /*
1252          * Workaround for 82599 silicon errata when enabling the Rx datapath.
1253          * If traffic is incoming before we enable the Rx unit, it could hang
1254          * the Rx DMA unit.  Therefore, make sure the security engine is
1255          * completely disabled prior to enabling the Rx unit.
1256          */
1257         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1258         secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1259         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1260         for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1261                 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1262                 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1263                         break;
1264                 else
1265                         udelay(10);
1266         }
1267
1268         /* For informational purposes only */
1269         if (i >= IXGBE_MAX_SECRX_POLL)
1270                 hw_dbg(hw, "Rx unit being enabled before security "
1271                        "path fully disabled.  Continuing with init.\n");
1272
1273         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1274         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1275         secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1276         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1277         IXGBE_WRITE_FLUSH(hw);
1278
1279         return 0;
1280 }
1281
1282 /**
1283  *  ixgbe_get_device_caps_82599 - Get additional device capabilities
1284  *  @hw: pointer to hardware structure
1285  *  @device_caps: the EEPROM word with the extra device capabilities
1286  *
1287  *  This function will read the EEPROM location for the device capabilities,
1288  *  and return the word through device_caps.
1289  **/
1290 s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1291 {
1292         hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1293
1294         return 0;
1295 }
1296
1297
1298 static struct ixgbe_mac_operations mac_ops_82599 = {
1299         .init_hw                = &ixgbe_init_hw_generic,
1300         .reset_hw               = &ixgbe_reset_hw_82599,
1301         .start_hw               = &ixgbe_start_hw_82599,
1302         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1303         .get_media_type         = &ixgbe_get_media_type_82599,
1304         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1305         .enable_rx_dma          = &ixgbe_enable_rx_dma_82599,
1306         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1307         .get_device_caps        = &ixgbe_get_device_caps_82599,
1308         .stop_adapter           = &ixgbe_stop_adapter_generic,
1309         .get_bus_info           = &ixgbe_get_bus_info_generic,
1310         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1311         .read_analog_reg8       = &ixgbe_read_analog_reg8_82599,
1312         .write_analog_reg8      = &ixgbe_write_analog_reg8_82599,
1313         .setup_link             = &ixgbe_setup_mac_link_82599,
1314         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82599,
1315         .check_link             = &ixgbe_check_mac_link_82599,
1316         .get_link_capabilities  = &ixgbe_get_link_capabilities_82599,
1317         .led_on                 = &ixgbe_led_on_generic,
1318         .led_off                = &ixgbe_led_off_generic,
1319         .blink_led_start        = &ixgbe_blink_led_start_generic,
1320         .blink_led_stop         = &ixgbe_blink_led_stop_generic,
1321         .set_rar                = &ixgbe_set_rar_generic,
1322         .clear_rar              = &ixgbe_clear_rar_generic,
1323         .set_vmdq               = &ixgbe_set_vmdq_82599,
1324         .clear_vmdq             = &ixgbe_clear_vmdq_82599,
1325         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1326         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1327         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1328         .enable_mc              = &ixgbe_enable_mc_generic,
1329         .disable_mc             = &ixgbe_disable_mc_generic,
1330         .clear_vfta             = &ixgbe_clear_vfta_82599,
1331         .set_vfta               = &ixgbe_set_vfta_82599,
1332         .setup_fc               = &ixgbe_setup_fc_generic,
1333         .init_uta_tables        = &ixgbe_init_uta_tables_82599,
1334         .setup_sfp              = &ixgbe_setup_sfp_modules_82599,
1335 };
1336
1337 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1338         .init_params            = &ixgbe_init_eeprom_params_generic,
1339         .read                   = &ixgbe_read_eeprom_generic,
1340         .write                  = &ixgbe_write_eeprom_generic,
1341         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1342         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1343 };
1344
1345 static struct ixgbe_phy_operations phy_ops_82599 = {
1346         .identify               = &ixgbe_identify_phy_82599,
1347         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1348         .init                   = &ixgbe_init_phy_ops_82599,
1349         .reset                  = &ixgbe_reset_phy_generic,
1350         .read_reg               = &ixgbe_read_phy_reg_generic,
1351         .write_reg              = &ixgbe_write_phy_reg_generic,
1352         .setup_link             = &ixgbe_setup_phy_link_generic,
1353         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1354         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
1355         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
1356         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
1357         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
1358 };
1359
1360 struct ixgbe_info ixgbe_82599_info = {
1361         .mac                    = ixgbe_mac_82599EB,
1362         .get_invariants         = &ixgbe_get_invariants_82599,
1363         .mac_ops                = &mac_ops_82599,
1364         .eeprom_ops             = &eeprom_ops_82599,
1365         .phy_ops                = &phy_ops_82599,
1366 };