git.oblomov.eu Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39
  40 #include <net/checksum.h>
  41
  42 #include <asm/system.h>
  43 #include <asm/io.h>
  44 #include <asm/byteorder.h>
  45 #include <asm/uaccess.h>
  46
  47 #ifdef CONFIG_SPARC64
  48 #include <asm/idprom.h>
  49 #include <asm/oplib.h>
  50 #include <asm/pbm.h>
  51 #endif
  52
  53 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  54 #define TG3_VLAN_TAG_USED 1
  55 #else
  56 #define TG3_VLAN_TAG_USED 0
  57 #endif
  58
  59 #ifdef NETIF_F_TSO
  60 #define TG3_TSO_SUPPORT 1
  61 #else
  62 #define TG3_TSO_SUPPORT 0
  63 #endif
  64
  65 #include "tg3.h"
  66
  67 #define DRV_MODULE_NAME         "tg3"
  68 #define PFX DRV_MODULE_NAME     ": "
  69 #define DRV_MODULE_VERSION      "3.32"
  70 #define DRV_MODULE_RELDATE      "June 24, 2005"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_RING_SIZE                512
 100 #define TG3_DEF_RX_RING_PENDING         200
 101 #define TG3_RX_JUMBO_RING_SIZE          256
 102 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 103
 104 /* Do not place this n-ring entries value into the tp struct itself,
 105  * we really want to expose these constants to GCC so that modulo et
 106  * al.  operations are done with shifts and masks instead of with
 107  * hw multiply/modulo instructions.  Another solution would be to
 108  * replace things like '% foo' with '& (foo - 1)'.
 109  */
 110 #define TG3_RX_RCB_RING_SIZE(tp)        \
 111         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 112
 113 #define TG3_TX_RING_SIZE                512
 114 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 115
 116 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_RING_SIZE)
 118 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_JUMBO_RING_SIZE)
 120 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 121                                    TG3_RX_RCB_RING_SIZE(tp))
 122 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 123                                  TG3_TX_RING_SIZE)
 124 #define TX_RING_GAP(TP) \
 125         (TG3_TX_RING_SIZE - (TP)->tx_pending)
 126 #define TX_BUFFS_AVAIL(TP)                                              \
 127         (((TP)->tx_cons <= (TP)->tx_prod) ?                             \
 128           (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod :            \
 129           (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
 130 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 131
 132 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 133 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 134
 135 /* minimum number of free TX descriptors required to wake up TX process */
 136 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 137
 138 /* number of ETHTOOL_GSTATS u64's */
 139 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 140
 141 #define TG3_NUM_TEST            6
 142
 143 static char version[] __devinitdata =
 144         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 145
 146 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 147 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 148 MODULE_LICENSE("GPL");
 149 MODULE_VERSION(DRV_MODULE_VERSION);
 150
 151 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 152 module_param(tg3_debug, int, 0);
 153 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 154
 155 static struct pci_device_id tg3_pci_tbl[] = {
 156         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 157           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 158         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 160         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 161           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 162         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 163           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 164         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 165           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 166         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 167           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 168         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 169           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 170         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 171           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 172         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 173           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 174         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 175           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 176         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 177           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 178         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 179           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 180         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 181           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 182         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 183           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 184         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 185           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 186         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 187           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 188         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 189           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 190         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 191           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 192         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 193           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 194         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 195           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 196         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 197           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 198         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 199           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 200         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 201           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 202         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 203           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 204         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 205           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 206         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 207           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 208         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 209           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 210         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 211           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 212         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 213           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 214         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 215           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 216         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 217           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 218         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 220         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 222         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 223           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 224         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 225           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 226         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 227           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 228         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 229           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 230         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 231           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 232         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 233           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 234         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 235           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 236         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 238         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 240         { 0, }
 241 };
 242
 243 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 244
 245 static struct {
 246         const char string[ETH_GSTRING_LEN];
 247 } ethtool_stats_keys[TG3_NUM_STATS] = {
 248         { "rx_octets" },
 249         { "rx_fragments" },
 250         { "rx_ucast_packets" },
 251         { "rx_mcast_packets" },
 252         { "rx_bcast_packets" },
 253         { "rx_fcs_errors" },
 254         { "rx_align_errors" },
 255         { "rx_xon_pause_rcvd" },
 256         { "rx_xoff_pause_rcvd" },
 257         { "rx_mac_ctrl_rcvd" },
 258         { "rx_xoff_entered" },
 259         { "rx_frame_too_long_errors" },
 260         { "rx_jabbers" },
 261         { "rx_undersize_packets" },
 262         { "rx_in_length_errors" },
 263         { "rx_out_length_errors" },
 264         { "rx_64_or_less_octet_packets" },
 265         { "rx_65_to_127_octet_packets" },
 266         { "rx_128_to_255_octet_packets" },
 267         { "rx_256_to_511_octet_packets" },
 268         { "rx_512_to_1023_octet_packets" },
 269         { "rx_1024_to_1522_octet_packets" },
 270         { "rx_1523_to_2047_octet_packets" },
 271         { "rx_2048_to_4095_octet_packets" },
 272         { "rx_4096_to_8191_octet_packets" },
 273         { "rx_8192_to_9022_octet_packets" },
 274
 275         { "tx_octets" },
 276         { "tx_collisions" },
 277
 278         { "tx_xon_sent" },
 279         { "tx_xoff_sent" },
 280         { "tx_flow_control" },
 281         { "tx_mac_errors" },
 282         { "tx_single_collisions" },
 283         { "tx_mult_collisions" },
 284         { "tx_deferred" },
 285         { "tx_excessive_collisions" },
 286         { "tx_late_collisions" },
 287         { "tx_collide_2times" },
 288         { "tx_collide_3times" },
 289         { "tx_collide_4times" },
 290         { "tx_collide_5times" },
 291         { "tx_collide_6times" },
 292         { "tx_collide_7times" },
 293         { "tx_collide_8times" },
 294         { "tx_collide_9times" },
 295         { "tx_collide_10times" },
 296         { "tx_collide_11times" },
 297         { "tx_collide_12times" },
 298         { "tx_collide_13times" },
 299         { "tx_collide_14times" },
 300         { "tx_collide_15times" },
 301         { "tx_ucast_packets" },
 302         { "tx_mcast_packets" },
 303         { "tx_bcast_packets" },
 304         { "tx_carrier_sense_errors" },
 305         { "tx_discards" },
 306         { "tx_errors" },
 307
 308         { "dma_writeq_full" },
 309         { "dma_write_prioq_full" },
 310         { "rxbds_empty" },
 311         { "rx_discards" },
 312         { "rx_errors" },
 313         { "rx_threshold_hit" },
 314
 315         { "dma_readq_full" },
 316         { "dma_read_prioq_full" },
 317         { "tx_comp_queue_full" },
 318
 319         { "ring_set_send_prod_index" },
 320         { "ring_status_update" },
 321         { "nic_irqs" },
 322         { "nic_avoided_irqs" },
 323         { "nic_tx_threshold_hit" }
 324 };
 325
 326 static struct {
 327         const char string[ETH_GSTRING_LEN];
 328 } ethtool_test_keys[TG3_NUM_TEST] = {
 329         { "nvram test     (online) " },
 330         { "link test      (online) " },
 331         { "register test  (offline)" },
 332         { "memory test    (offline)" },
 333         { "loopback test  (offline)" },
 334         { "interrupt test (offline)" },
 335 };
 336
 337 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 338 {
 339         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 340                 spin_lock_bh(&tp->indirect_lock);
 341                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 342                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 343                 spin_unlock_bh(&tp->indirect_lock);
 344         } else {
 345                 writel(val, tp->regs + off);
 346                 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
 347                         readl(tp->regs + off);
 348         }
 349 }
 350
 351 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 354                 spin_lock_bh(&tp->indirect_lock);
 355                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 356                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 357                 spin_unlock_bh(&tp->indirect_lock);
 358         } else {
 359                 void __iomem *dest = tp->regs + off;
 360                 writel(val, dest);
 361                 readl(dest);    /* always flush PCI write */
 362         }
 363 }
 364
 365 static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
 366 {
 367         void __iomem *mbox = tp->regs + off;
 368         writel(val, mbox);
 369         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 370                 readl(mbox);
 371 }
 372
 373 static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 374 {
 375         void __iomem *mbox = tp->regs + off;
 376         writel(val, mbox);
 377         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 378                 writel(val, mbox);
 379         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 380                 readl(mbox);
 381 }
 382
 383 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tp->regs + (reg))
 384 #define tw32_rx_mbox(reg, val)  _tw32_rx_mbox(tp, reg, val)
 385 #define tw32_tx_mbox(reg, val)  _tw32_tx_mbox(tp, reg, val)
 386
 387 #define tw32(reg,val)           tg3_write_indirect_reg32(tp,(reg),(val))
 388 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val))
 389 #define tw16(reg,val)           writew(((val) & 0xffff), tp->regs + (reg))
 390 #define tw8(reg,val)            writeb(((val) & 0xff), tp->regs + (reg))
 391 #define tr32(reg)               readl(tp->regs + (reg))
 392 #define tr16(reg)               readw(tp->regs + (reg))
 393 #define tr8(reg)                readb(tp->regs + (reg))
 394
 395 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 396 {
 397         spin_lock_bh(&tp->indirect_lock);
 398         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 399         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 400
 401         /* Always leave this as zero. */
 402         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 403         spin_unlock_bh(&tp->indirect_lock);
 404 }
 405
 406 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 407 {
 408         spin_lock_bh(&tp->indirect_lock);
 409         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 410         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 411
 412         /* Always leave this as zero. */
 413         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 414         spin_unlock_bh(&tp->indirect_lock);
 415 }
 416
 417 static void tg3_disable_ints(struct tg3 *tp)
 418 {
 419         tw32(TG3PCI_MISC_HOST_CTRL,
 420              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 421         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 422         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 423 }
 424
 425 static inline void tg3_cond_int(struct tg3 *tp)
 426 {
 427         if (tp->hw_status->status & SD_STATUS_UPDATED)
 428                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 429 }
 430
 431 static void tg3_enable_ints(struct tg3 *tp)
 432 {
 433         tp->irq_sync = 0;
 434         wmb();
 435
 436         tw32(TG3PCI_MISC_HOST_CTRL,
 437              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 438         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 439                      (tp->last_tag << 24));
 440         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 441         tg3_cond_int(tp);
 442 }
 443
 444 static inline unsigned int tg3_has_work(struct tg3 *tp)
 445 {
 446         struct tg3_hw_status *sblk = tp->hw_status;
 447         unsigned int work_exists = 0;
 448
 449         /* check for phy events */
 450         if (!(tp->tg3_flags &
 451               (TG3_FLAG_USE_LINKCHG_REG |
 452                TG3_FLAG_POLL_SERDES))) {
 453                 if (sblk->status & SD_STATUS_LINK_CHG)
 454                         work_exists = 1;
 455         }
 456         /* check for RX/TX work to do */
 457         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 458             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 459                 work_exists = 1;
 460
 461         return work_exists;
 462 }
 463
 464 /* tg3_restart_ints
 465  *  similar to tg3_enable_ints, but it accurately determines whether there
 466  *  is new work pending and can return without flushing the PIO write
 467  *  which reenables interrupts
 468  */
 469 static void tg3_restart_ints(struct tg3 *tp)
 470 {
 471         tw32(TG3PCI_MISC_HOST_CTRL,
 472                 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 473         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 474                      tp->last_tag << 24);
 475         mmiowb();
 476
 477         /* When doing tagged status, this work check is unnecessary.
 478          * The last_tag we write above tells the chip which piece of
 479          * work we've completed.
 480          */
 481         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 482             tg3_has_work(tp))
 483                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 484                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 485 }
 486
 487 static inline void tg3_netif_stop(struct tg3 *tp)
 488 {
 489         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 490         netif_poll_disable(tp->dev);
 491         netif_tx_disable(tp->dev);
 492 }
 493
 494 static inline void tg3_netif_start(struct tg3 *tp)
 495 {
 496         netif_wake_queue(tp->dev);
 497         /* NOTE: unconditional netif_wake_queue is only appropriate
 498          * so long as all callers are assured to have free tx slots
 499          * (such as after tg3_init_hw)
 500          */
 501         netif_poll_enable(tp->dev);
 502         tp->hw_status->status |= SD_STATUS_UPDATED;
 503         tg3_enable_ints(tp);
 504 }
 505
 506 static void tg3_switch_clocks(struct tg3 *tp)
 507 {
 508         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 509         u32 orig_clock_ctrl;
 510
 511         orig_clock_ctrl = clock_ctrl;
 512         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 513                        CLOCK_CTRL_CLKRUN_OENABLE |
 514                        0x1f);
 515         tp->pci_clock_ctrl = clock_ctrl;
 516
 517         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 518                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 519                         tw32_f(TG3PCI_CLOCK_CTRL,
 520                                clock_ctrl | CLOCK_CTRL_625_CORE);
 521                         udelay(40);
 522                 }
 523         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 524                 tw32_f(TG3PCI_CLOCK_CTRL,
 525                      clock_ctrl |
 526                      (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
 527                 udelay(40);
 528                 tw32_f(TG3PCI_CLOCK_CTRL,
 529                      clock_ctrl | (CLOCK_CTRL_ALTCLK));
 530                 udelay(40);
 531         }
 532         tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
 533         udelay(40);
 534 }
 535
 536 #define PHY_BUSY_LOOPS  5000
 537
 538 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 539 {
 540         u32 frame_val;
 541         unsigned int loops;
 542         int ret;
 543
 544         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 545                 tw32_f(MAC_MI_MODE,
 546                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 547                 udelay(80);
 548         }
 549
 550         *val = 0x0;
 551
 552         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 553                       MI_COM_PHY_ADDR_MASK);
 554         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 555                       MI_COM_REG_ADDR_MASK);
 556         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 557
 558         tw32_f(MAC_MI_COM, frame_val);
 559
 560         loops = PHY_BUSY_LOOPS;
 561         while (loops != 0) {
 562                 udelay(10);
 563                 frame_val = tr32(MAC_MI_COM);
 564
 565                 if ((frame_val & MI_COM_BUSY) == 0) {
 566                         udelay(5);
 567                         frame_val = tr32(MAC_MI_COM);
 568                         break;
 569                 }
 570                 loops -= 1;
 571         }
 572
 573         ret = -EBUSY;
 574         if (loops != 0) {
 575                 *val = frame_val & MI_COM_DATA_MASK;
 576                 ret = 0;
 577         }
 578
 579         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 580                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 581                 udelay(80);
 582         }
 583
 584         return ret;
 585 }
 586
 587 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 588 {
 589         u32 frame_val;
 590         unsigned int loops;
 591         int ret;
 592
 593         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 594                 tw32_f(MAC_MI_MODE,
 595                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 596                 udelay(80);
 597         }
 598
 599         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 600                       MI_COM_PHY_ADDR_MASK);
 601         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 602                       MI_COM_REG_ADDR_MASK);
 603         frame_val |= (val & MI_COM_DATA_MASK);
 604         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 605
 606         tw32_f(MAC_MI_COM, frame_val);
 607
 608         loops = PHY_BUSY_LOOPS;
 609         while (loops != 0) {
 610                 udelay(10);
 611                 frame_val = tr32(MAC_MI_COM);
 612                 if ((frame_val & MI_COM_BUSY) == 0) {
 613                         udelay(5);
 614                         frame_val = tr32(MAC_MI_COM);
 615                         break;
 616                 }
 617                 loops -= 1;
 618         }
 619
 620         ret = -EBUSY;
 621         if (loops != 0)
 622                 ret = 0;
 623
 624         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 625                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 626                 udelay(80);
 627         }
 628
 629         return ret;
 630 }
 631
 632 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 633 {
 634         u32 val;
 635
 636         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 637                 return;
 638
 639         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 640             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 641                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 642                              (val | (1 << 15) | (1 << 4)));
 643 }
 644
 645 static int tg3_bmcr_reset(struct tg3 *tp)
 646 {
 647         u32 phy_control;
 648         int limit, err;
 649
 650         /* OK, reset it, and poll the BMCR_RESET bit until it
 651          * clears or we time out.
 652          */
 653         phy_control = BMCR_RESET;
 654         err = tg3_writephy(tp, MII_BMCR, phy_control);
 655         if (err != 0)
 656                 return -EBUSY;
 657
 658         limit = 5000;
 659         while (limit--) {
 660                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 661                 if (err != 0)
 662                         return -EBUSY;
 663
 664                 if ((phy_control & BMCR_RESET) == 0) {
 665                         udelay(40);
 666                         break;
 667                 }
 668                 udelay(10);
 669         }
 670         if (limit <= 0)
 671                 return -EBUSY;
 672
 673         return 0;
 674 }
 675
 676 static int tg3_wait_macro_done(struct tg3 *tp)
 677 {
 678         int limit = 100;
 679
 680         while (limit--) {
 681                 u32 tmp32;
 682
 683                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 684                         if ((tmp32 & 0x1000) == 0)
 685                                 break;
 686                 }
 687         }
 688         if (limit <= 0)
 689                 return -EBUSY;
 690
 691         return 0;
 692 }
 693
 694 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 695 {
 696         static const u32 test_pat[4][6] = {
 697         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 698         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 699         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 700         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 701         };
 702         int chan;
 703
 704         for (chan = 0; chan < 4; chan++) {
 705                 int i;
 706
 707                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 708                              (chan * 0x2000) | 0x0200);
 709                 tg3_writephy(tp, 0x16, 0x0002);
 710
 711                 for (i = 0; i < 6; i++)
 712                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 713                                      test_pat[chan][i]);
 714
 715                 tg3_writephy(tp, 0x16, 0x0202);
 716                 if (tg3_wait_macro_done(tp)) {
 717                         *resetp = 1;
 718                         return -EBUSY;
 719                 }
 720
 721                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 722                              (chan * 0x2000) | 0x0200);
 723                 tg3_writephy(tp, 0x16, 0x0082);
 724                 if (tg3_wait_macro_done(tp)) {
 725                         *resetp = 1;
 726                         return -EBUSY;
 727                 }
 728
 729                 tg3_writephy(tp, 0x16, 0x0802);
 730                 if (tg3_wait_macro_done(tp)) {
 731                         *resetp = 1;
 732                         return -EBUSY;
 733                 }
 734
 735                 for (i = 0; i < 6; i += 2) {
 736                         u32 low, high;
 737
 738                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 739                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 740                             tg3_wait_macro_done(tp)) {
 741                                 *resetp = 1;
 742                                 return -EBUSY;
 743                         }
 744                         low &= 0x7fff;
 745                         high &= 0x000f;
 746                         if (low != test_pat[chan][i] ||
 747                             high != test_pat[chan][i+1]) {
 748                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 749                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 750                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 751
 752                                 return -EBUSY;
 753                         }
 754                 }
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 761 {
 762         int chan;
 763
 764         for (chan = 0; chan < 4; chan++) {
 765                 int i;
 766
 767                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 768                              (chan * 0x2000) | 0x0200);
 769                 tg3_writephy(tp, 0x16, 0x0002);
 770                 for (i = 0; i < 6; i++)
 771                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 772                 tg3_writephy(tp, 0x16, 0x0202);
 773                 if (tg3_wait_macro_done(tp))
 774                         return -EBUSY;
 775         }
 776
 777         return 0;
 778 }
 779
 780 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 781 {
 782         u32 reg32, phy9_orig;
 783         int retries, do_phy_reset, err;
 784
 785         retries = 10;
 786         do_phy_reset = 1;
 787         do {
 788                 if (do_phy_reset) {
 789                         err = tg3_bmcr_reset(tp);
 790                         if (err)
 791                                 return err;
 792                         do_phy_reset = 0;
 793                 }
 794
 795                 /* Disable transmitter and interrupt.  */
 796                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 797                         continue;
 798
 799                 reg32 |= 0x3000;
 800                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 801
 802                 /* Set full-duplex, 1000 mbps.  */
 803                 tg3_writephy(tp, MII_BMCR,
 804                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 805
 806                 /* Set to master mode.  */
 807                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 808                         continue;
 809
 810                 tg3_writephy(tp, MII_TG3_CTRL,
 811                              (MII_TG3_CTRL_AS_MASTER |
 812                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 813
 814                 /* Enable SM_DSP_CLOCK and 6dB.  */
 815                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 816
 817                 /* Block the PHY control access.  */
 818                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 819                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 820
 821                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 822                 if (!err)
 823                         break;
 824         } while (--retries);
 825
 826         err = tg3_phy_reset_chanpat(tp);
 827         if (err)
 828                 return err;
 829
 830         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 831         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 832
 833         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 834         tg3_writephy(tp, 0x16, 0x0000);
 835
 836         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 837             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 838                 /* Set Extended packet length bit for jumbo frames */
 839                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 840         }
 841         else {
 842                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 843         }
 844
 845         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 846
 847         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 848                 reg32 &= ~0x3000;
 849                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 850         } else if (!err)
 851                 err = -EBUSY;
 852
 853         return err;
 854 }
 855
 856 /* This will reset the tigon3 PHY if there is no valid
 857  * link unless the FORCE argument is non-zero.
 858  */
 859 static int tg3_phy_reset(struct tg3 *tp)
 860 {
 861         u32 phy_status;
 862         int err;
 863
 864         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 865         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 866         if (err != 0)
 867                 return -EBUSY;
 868
 869         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 870             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 871             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 872                 err = tg3_phy_reset_5703_4_5(tp);
 873                 if (err)
 874                         return err;
 875                 goto out;
 876         }
 877
 878         err = tg3_bmcr_reset(tp);
 879         if (err)
 880                 return err;
 881
 882 out:
 883         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 884                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 885                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 886                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 887                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 888                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 889                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 890         }
 891         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 892                 tg3_writephy(tp, 0x1c, 0x8d68);
 893                 tg3_writephy(tp, 0x1c, 0x8d68);
 894         }
 895         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 896                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 897                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 898                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
 899                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 900                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
 901                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
 902                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
 903                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 904         }
 905         /* Set Extended packet length bit (bit 14) on all chips that */
 906         /* support jumbo frames */
 907         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 908                 /* Cannot do read-modify-write on 5401 */
 909                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 910         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
 911                 u32 phy_reg;
 912
 913                 /* Set bit 14 with read-modify-write to preserve other bits */
 914                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
 915                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
 916                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
 917         }
 918
 919         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
 920          * jumbo frames transmission.
 921          */
 922         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
 923                 u32 phy_reg;
 924
 925                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
 926                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
 927                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
 928         }
 929
 930         tg3_phy_set_wirespeed(tp);
 931         return 0;
 932 }
 933
 934 static void tg3_frob_aux_power(struct tg3 *tp)
 935 {
 936         struct tg3 *tp_peer = tp;
 937
 938         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
 939                 return;
 940
 941         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 942                 tp_peer = pci_get_drvdata(tp->pdev_peer);
 943                 if (!tp_peer)
 944                         BUG();
 945         }
 946
 947
 948         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
 949             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
 950                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
 951                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
 952                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 953                              (GRC_LCLCTRL_GPIO_OE0 |
 954                               GRC_LCLCTRL_GPIO_OE1 |
 955                               GRC_LCLCTRL_GPIO_OE2 |
 956                               GRC_LCLCTRL_GPIO_OUTPUT0 |
 957                               GRC_LCLCTRL_GPIO_OUTPUT1));
 958                         udelay(100);
 959                 } else {
 960                         u32 no_gpio2;
 961                         u32 grc_local_ctrl;
 962
 963                         if (tp_peer != tp &&
 964                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
 965                                 return;
 966
 967                         /* On 5753 and variants, GPIO2 cannot be used. */
 968                         no_gpio2 = tp->nic_sram_data_cfg &
 969                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
 970
 971                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
 972                                          GRC_LCLCTRL_GPIO_OE1 |
 973                                          GRC_LCLCTRL_GPIO_OE2 |
 974                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
 975                                          GRC_LCLCTRL_GPIO_OUTPUT2;
 976                         if (no_gpio2) {
 977                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
 978                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
 979                         }
 980                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 981                                                 grc_local_ctrl);
 982                         udelay(100);
 983
 984                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
 985
 986                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 987                                                 grc_local_ctrl);
 988                         udelay(100);
 989
 990                         if (!no_gpio2) {
 991                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
 992                                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 993                                        grc_local_ctrl);
 994                                 udelay(100);
 995                         }
 996                 }
 997         } else {
 998                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
 999                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1000                         if (tp_peer != tp &&
1001                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1002                                 return;
1003
1004                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1005                              (GRC_LCLCTRL_GPIO_OE1 |
1006                               GRC_LCLCTRL_GPIO_OUTPUT1));
1007                         udelay(100);
1008
1009                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1010                              (GRC_LCLCTRL_GPIO_OE1));
1011                         udelay(100);
1012
1013                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1014                              (GRC_LCLCTRL_GPIO_OE1 |
1015                               GRC_LCLCTRL_GPIO_OUTPUT1));
1016                         udelay(100);
1017                 }
1018         }
1019 }
1020
1021 static int tg3_setup_phy(struct tg3 *, int);
1022
1023 #define RESET_KIND_SHUTDOWN     0
1024 #define RESET_KIND_INIT         1
1025 #define RESET_KIND_SUSPEND      2
1026
1027 static void tg3_write_sig_post_reset(struct tg3 *, int);
1028 static int tg3_halt_cpu(struct tg3 *, u32);
1029
1030 static int tg3_set_power_state(struct tg3 *tp, int state)
1031 {
1032         u32 misc_host_ctrl;
1033         u16 power_control, power_caps;
1034         int pm = tp->pm_cap;
1035
1036         /* Make sure register accesses (indirect or otherwise)
1037          * will function correctly.
1038          */
1039         pci_write_config_dword(tp->pdev,
1040                                TG3PCI_MISC_HOST_CTRL,
1041                                tp->misc_host_ctrl);
1042
1043         pci_read_config_word(tp->pdev,
1044                              pm + PCI_PM_CTRL,
1045                              &power_control);
1046         power_control |= PCI_PM_CTRL_PME_STATUS;
1047         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1048         switch (state) {
1049         case 0:
1050                 power_control |= 0;
1051                 pci_write_config_word(tp->pdev,
1052                                       pm + PCI_PM_CTRL,
1053                                       power_control);
1054                 udelay(100);    /* Delay after power state change */
1055
1056                 /* Switch out of Vaux if it is not a LOM */
1057                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1058                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1059                         udelay(100);
1060                 }
1061
1062                 return 0;
1063
1064         case 1:
1065                 power_control |= 1;
1066                 break;
1067
1068         case 2:
1069                 power_control |= 2;
1070                 break;
1071
1072         case 3:
1073                 power_control |= 3;
1074                 break;
1075
1076         default:
1077                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1078                        "requested.\n",
1079                        tp->dev->name, state);
1080                 return -EINVAL;
1081         };
1082
1083         power_control |= PCI_PM_CTRL_PME_ENABLE;
1084
1085         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1086         tw32(TG3PCI_MISC_HOST_CTRL,
1087              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1088
1089         if (tp->link_config.phy_is_low_power == 0) {
1090                 tp->link_config.phy_is_low_power = 1;
1091                 tp->link_config.orig_speed = tp->link_config.speed;
1092                 tp->link_config.orig_duplex = tp->link_config.duplex;
1093                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1094         }
1095
1096         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1097                 tp->link_config.speed = SPEED_10;
1098                 tp->link_config.duplex = DUPLEX_HALF;
1099                 tp->link_config.autoneg = AUTONEG_ENABLE;
1100                 tg3_setup_phy(tp, 0);
1101         }
1102
1103         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1104
1105         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1106                 u32 mac_mode;
1107
1108                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1109                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1110                         udelay(40);
1111
1112                         mac_mode = MAC_MODE_PORT_MODE_MII;
1113
1114                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1115                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1116                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1117                 } else {
1118                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1119                 }
1120
1121                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1122                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1123
1124                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1125                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1126                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1127
1128                 tw32_f(MAC_MODE, mac_mode);
1129                 udelay(100);
1130
1131                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1132                 udelay(10);
1133         }
1134
1135         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1136             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1137              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1138                 u32 base_val;
1139
1140                 base_val = tp->pci_clock_ctrl;
1141                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1142                              CLOCK_CTRL_TXCLK_DISABLE);
1143
1144                 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1145                      CLOCK_CTRL_ALTCLK |
1146                      CLOCK_CTRL_PWRDOWN_PLL133);
1147                 udelay(40);
1148         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1149                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1150                 u32 newbits1, newbits2;
1151
1152                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1153                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1154                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1155                                     CLOCK_CTRL_TXCLK_DISABLE |
1156                                     CLOCK_CTRL_ALTCLK);
1157                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1158                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1159                         newbits1 = CLOCK_CTRL_625_CORE;
1160                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1161                 } else {
1162                         newbits1 = CLOCK_CTRL_ALTCLK;
1163                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1164                 }
1165
1166                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1167                 udelay(40);
1168
1169                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1170                 udelay(40);
1171
1172                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1173                         u32 newbits3;
1174
1175                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1176                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1177                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1178                                             CLOCK_CTRL_TXCLK_DISABLE |
1179                                             CLOCK_CTRL_44MHZ_CORE);
1180                         } else {
1181                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1182                         }
1183
1184                         tw32_f(TG3PCI_CLOCK_CTRL,
1185                                          tp->pci_clock_ctrl | newbits3);
1186                         udelay(40);
1187                 }
1188         }
1189
1190         tg3_frob_aux_power(tp);
1191
1192         /* Workaround for unstable PLL clock */
1193         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1194             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1195                 u32 val = tr32(0x7d00);
1196
1197                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1198                 tw32(0x7d00, val);
1199                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1200                         tg3_halt_cpu(tp, RX_CPU_BASE);
1201         }
1202
1203         /* Finally, set the new power state. */
1204         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1205         udelay(100);    /* Delay after power state change */
1206
1207         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1208
1209         return 0;
1210 }
1211
1212 static void tg3_link_report(struct tg3 *tp)
1213 {
1214         if (!netif_carrier_ok(tp->dev)) {
1215                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1216         } else {
1217                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1218                        tp->dev->name,
1219                        (tp->link_config.active_speed == SPEED_1000 ?
1220                         1000 :
1221                         (tp->link_config.active_speed == SPEED_100 ?
1222                          100 : 10)),
1223                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1224                         "full" : "half"));
1225
1226                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1227                        "%s for RX.\n",
1228                        tp->dev->name,
1229                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1230                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1231         }
1232 }
1233
1234 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1235 {
1236         u32 new_tg3_flags = 0;
1237         u32 old_rx_mode = tp->rx_mode;
1238         u32 old_tx_mode = tp->tx_mode;
1239
1240         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1241                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1242                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1243                                 if (remote_adv & LPA_PAUSE_CAP)
1244                                         new_tg3_flags |=
1245                                                 (TG3_FLAG_RX_PAUSE |
1246                                                 TG3_FLAG_TX_PAUSE);
1247                                 else if (remote_adv & LPA_PAUSE_ASYM)
1248                                         new_tg3_flags |=
1249                                                 (TG3_FLAG_RX_PAUSE);
1250                         } else {
1251                                 if (remote_adv & LPA_PAUSE_CAP)
1252                                         new_tg3_flags |=
1253                                                 (TG3_FLAG_RX_PAUSE |
1254                                                 TG3_FLAG_TX_PAUSE);
1255                         }
1256                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1257                         if ((remote_adv & LPA_PAUSE_CAP) &&
1258                         (remote_adv & LPA_PAUSE_ASYM))
1259                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1260                 }
1261
1262                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1263                 tp->tg3_flags |= new_tg3_flags;
1264         } else {
1265                 new_tg3_flags = tp->tg3_flags;
1266         }
1267
1268         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1269                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1270         else
1271                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1272
1273         if (old_rx_mode != tp->rx_mode) {
1274                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1275         }
1276
1277         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1278                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1279         else
1280                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1281
1282         if (old_tx_mode != tp->tx_mode) {
1283                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1284         }
1285 }
1286
1287 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1288 {
1289         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1290         case MII_TG3_AUX_STAT_10HALF:
1291                 *speed = SPEED_10;
1292                 *duplex = DUPLEX_HALF;
1293                 break;
1294
1295         case MII_TG3_AUX_STAT_10FULL:
1296                 *speed = SPEED_10;
1297                 *duplex = DUPLEX_FULL;
1298                 break;
1299
1300         case MII_TG3_AUX_STAT_100HALF:
1301                 *speed = SPEED_100;
1302                 *duplex = DUPLEX_HALF;
1303                 break;
1304
1305         case MII_TG3_AUX_STAT_100FULL:
1306                 *speed = SPEED_100;
1307                 *duplex = DUPLEX_FULL;
1308                 break;
1309
1310         case MII_TG3_AUX_STAT_1000HALF:
1311                 *speed = SPEED_1000;
1312                 *duplex = DUPLEX_HALF;
1313                 break;
1314
1315         case MII_TG3_AUX_STAT_1000FULL:
1316                 *speed = SPEED_1000;
1317                 *duplex = DUPLEX_FULL;
1318                 break;
1319
1320         default:
1321                 *speed = SPEED_INVALID;
1322                 *duplex = DUPLEX_INVALID;
1323                 break;
1324         };
1325 }
1326
1327 static void tg3_phy_copper_begin(struct tg3 *tp)
1328 {
1329         u32 new_adv;
1330         int i;
1331
1332         if (tp->link_config.phy_is_low_power) {
1333                 /* Entering low power mode.  Disable gigabit and
1334                  * 100baseT advertisements.
1335                  */
1336                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1337
1338                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1339                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1340                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1341                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1342
1343                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1344         } else if (tp->link_config.speed == SPEED_INVALID) {
1345                 tp->link_config.advertising =
1346                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1347                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1348                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1349                          ADVERTISED_Autoneg | ADVERTISED_MII);
1350
1351                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1352                         tp->link_config.advertising &=
1353                                 ~(ADVERTISED_1000baseT_Half |
1354                                   ADVERTISED_1000baseT_Full);
1355
1356                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1357                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1358                         new_adv |= ADVERTISE_10HALF;
1359                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1360                         new_adv |= ADVERTISE_10FULL;
1361                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1362                         new_adv |= ADVERTISE_100HALF;
1363                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1364                         new_adv |= ADVERTISE_100FULL;
1365                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1366
1367                 if (tp->link_config.advertising &
1368                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1369                         new_adv = 0;
1370                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1371                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1372                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1373                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1374                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1375                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1376                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1377                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1378                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1379                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1380                 } else {
1381                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1382                 }
1383         } else {
1384                 /* Asking for a specific link mode. */
1385                 if (tp->link_config.speed == SPEED_1000) {
1386                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1387                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1388
1389                         if (tp->link_config.duplex == DUPLEX_FULL)
1390                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1391                         else
1392                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1393                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1394                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1395                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1396                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1397                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1398                 } else {
1399                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1400
1401                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1402                         if (tp->link_config.speed == SPEED_100) {
1403                                 if (tp->link_config.duplex == DUPLEX_FULL)
1404                                         new_adv |= ADVERTISE_100FULL;
1405                                 else
1406                                         new_adv |= ADVERTISE_100HALF;
1407                         } else {
1408                                 if (tp->link_config.duplex == DUPLEX_FULL)
1409                                         new_adv |= ADVERTISE_10FULL;
1410                                 else
1411                                         new_adv |= ADVERTISE_10HALF;
1412                         }
1413                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1414                 }
1415         }
1416
1417         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1418             tp->link_config.speed != SPEED_INVALID) {
1419                 u32 bmcr, orig_bmcr;
1420
1421                 tp->link_config.active_speed = tp->link_config.speed;
1422                 tp->link_config.active_duplex = tp->link_config.duplex;
1423
1424                 bmcr = 0;
1425                 switch (tp->link_config.speed) {
1426                 default:
1427                 case SPEED_10:
1428                         break;
1429
1430                 case SPEED_100:
1431                         bmcr |= BMCR_SPEED100;
1432                         break;
1433
1434                 case SPEED_1000:
1435                         bmcr |= TG3_BMCR_SPEED1000;
1436                         break;
1437                 };
1438
1439                 if (tp->link_config.duplex == DUPLEX_FULL)
1440                         bmcr |= BMCR_FULLDPLX;
1441
1442                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1443                     (bmcr != orig_bmcr)) {
1444                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1445                         for (i = 0; i < 1500; i++) {
1446                                 u32 tmp;
1447
1448                                 udelay(10);
1449                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1450                                     tg3_readphy(tp, MII_BMSR, &tmp))
1451                                         continue;
1452                                 if (!(tmp & BMSR_LSTATUS)) {
1453                                         udelay(40);
1454                                         break;
1455                                 }
1456                         }
1457                         tg3_writephy(tp, MII_BMCR, bmcr);
1458                         udelay(40);
1459                 }
1460         } else {
1461                 tg3_writephy(tp, MII_BMCR,
1462                              BMCR_ANENABLE | BMCR_ANRESTART);
1463         }
1464 }
1465
1466 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1467 {
1468         int err;
1469
1470         /* Turn off tap power management. */
1471         /* Set Extended packet length bit */
1472         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1473
1474         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1475         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1476
1477         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1478         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1479
1480         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1481         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1482
1483         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1484         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1485
1486         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1487         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1488
1489         udelay(40);
1490
1491         return err;
1492 }
1493
1494 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1495 {
1496         u32 adv_reg, all_mask;
1497
1498         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1499                 return 0;
1500
1501         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1502                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1503         if ((adv_reg & all_mask) != all_mask)
1504                 return 0;
1505         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1506                 u32 tg3_ctrl;
1507
1508                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1509                         return 0;
1510
1511                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1512                             MII_TG3_CTRL_ADV_1000_FULL);
1513                 if ((tg3_ctrl & all_mask) != all_mask)
1514                         return 0;
1515         }
1516         return 1;
1517 }
1518
1519 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1520 {
1521         int current_link_up;
1522         u32 bmsr, dummy;
1523         u16 current_speed;
1524         u8 current_duplex;
1525         int i, err;
1526
1527         tw32(MAC_EVENT, 0);
1528
1529         tw32_f(MAC_STATUS,
1530              (MAC_STATUS_SYNC_CHANGED |
1531               MAC_STATUS_CFG_CHANGED |
1532               MAC_STATUS_MI_COMPLETION |
1533               MAC_STATUS_LNKSTATE_CHANGED));
1534         udelay(40);
1535
1536         tp->mi_mode = MAC_MI_MODE_BASE;
1537         tw32_f(MAC_MI_MODE, tp->mi_mode);
1538         udelay(80);
1539
1540         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1541
1542         /* Some third-party PHYs need to be reset on link going
1543          * down.
1544          */
1545         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1546              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1547              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1548             netif_carrier_ok(tp->dev)) {
1549                 tg3_readphy(tp, MII_BMSR, &bmsr);
1550                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1551                     !(bmsr & BMSR_LSTATUS))
1552                         force_reset = 1;
1553         }
1554         if (force_reset)
1555                 tg3_phy_reset(tp);
1556
1557         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1558                 tg3_readphy(tp, MII_BMSR, &bmsr);
1559                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1560                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1561                         bmsr = 0;
1562
1563                 if (!(bmsr & BMSR_LSTATUS)) {
1564                         err = tg3_init_5401phy_dsp(tp);
1565                         if (err)
1566                                 return err;
1567
1568                         tg3_readphy(tp, MII_BMSR, &bmsr);
1569                         for (i = 0; i < 1000; i++) {
1570                                 udelay(10);
1571                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1572                                     (bmsr & BMSR_LSTATUS)) {
1573                                         udelay(40);
1574                                         break;
1575                                 }
1576                         }
1577
1578                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1579                             !(bmsr & BMSR_LSTATUS) &&
1580                             tp->link_config.active_speed == SPEED_1000) {
1581                                 err = tg3_phy_reset(tp);
1582                                 if (!err)
1583                                         err = tg3_init_5401phy_dsp(tp);
1584                                 if (err)
1585                                         return err;
1586                         }
1587                 }
1588         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1589                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1590                 /* 5701 {A0,B0} CRC bug workaround */
1591                 tg3_writephy(tp, 0x15, 0x0a75);
1592                 tg3_writephy(tp, 0x1c, 0x8c68);
1593                 tg3_writephy(tp, 0x1c, 0x8d68);
1594                 tg3_writephy(tp, 0x1c, 0x8c68);
1595         }
1596
1597         /* Clear pending interrupts... */
1598         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1599         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1600
1601         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1602                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1603         else
1604                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1605
1606         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1607             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1608                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1609                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1610                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1611                 else
1612                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1613         }
1614
1615         current_link_up = 0;
1616         current_speed = SPEED_INVALID;
1617         current_duplex = DUPLEX_INVALID;
1618
1619         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1620                 u32 val;
1621
1622                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1623                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1624                 if (!(val & (1 << 10))) {
1625                         val |= (1 << 10);
1626                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1627                         goto relink;
1628                 }
1629         }
1630
1631         bmsr = 0;
1632         for (i = 0; i < 100; i++) {
1633                 tg3_readphy(tp, MII_BMSR, &bmsr);
1634                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1635                     (bmsr & BMSR_LSTATUS))
1636                         break;
1637                 udelay(40);
1638         }
1639
1640         if (bmsr & BMSR_LSTATUS) {
1641                 u32 aux_stat, bmcr;
1642
1643                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1644                 for (i = 0; i < 2000; i++) {
1645                         udelay(10);
1646                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1647                             aux_stat)
1648                                 break;
1649                 }
1650
1651                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1652                                              &current_speed,
1653                                              &current_duplex);
1654
1655                 bmcr = 0;
1656                 for (i = 0; i < 200; i++) {
1657                         tg3_readphy(tp, MII_BMCR, &bmcr);
1658                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1659                                 continue;
1660                         if (bmcr && bmcr != 0x7fff)
1661                                 break;
1662                         udelay(10);
1663                 }
1664
1665                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1666                         if (bmcr & BMCR_ANENABLE) {
1667                                 current_link_up = 1;
1668
1669                                 /* Force autoneg restart if we are exiting
1670                                  * low power mode.
1671                                  */
1672                                 if (!tg3_copper_is_advertising_all(tp))
1673                                         current_link_up = 0;
1674                         } else {
1675                                 current_link_up = 0;
1676                         }
1677                 } else {
1678                         if (!(bmcr & BMCR_ANENABLE) &&
1679                             tp->link_config.speed == current_speed &&
1680                             tp->link_config.duplex == current_duplex) {
1681                                 current_link_up = 1;
1682                         } else {
1683                                 current_link_up = 0;
1684                         }
1685                 }
1686
1687                 tp->link_config.active_speed = current_speed;
1688                 tp->link_config.active_duplex = current_duplex;
1689         }
1690
1691         if (current_link_up == 1 &&
1692             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1693             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1694                 u32 local_adv, remote_adv;
1695
1696                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1697                         local_adv = 0;
1698                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1699
1700                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1701                         remote_adv = 0;
1702
1703                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1704
1705                 /* If we are not advertising full pause capability,
1706                  * something is wrong.  Bring the link down and reconfigure.
1707                  */
1708                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1709                         current_link_up = 0;
1710                 } else {
1711                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1712                 }
1713         }
1714 relink:
1715         if (current_link_up == 0) {
1716                 u32 tmp;
1717
1718                 tg3_phy_copper_begin(tp);
1719
1720                 tg3_readphy(tp, MII_BMSR, &tmp);
1721                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1722                     (tmp & BMSR_LSTATUS))
1723                         current_link_up = 1;
1724         }
1725
1726         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1727         if (current_link_up == 1) {
1728                 if (tp->link_config.active_speed == SPEED_100 ||
1729                     tp->link_config.active_speed == SPEED_10)
1730                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1731                 else
1732                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1733         } else
1734                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1735
1736         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1737         if (tp->link_config.active_duplex == DUPLEX_HALF)
1738                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1739
1740         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1741         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1742                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1743                     (current_link_up == 1 &&
1744                      tp->link_config.active_speed == SPEED_10))
1745                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1746         } else {
1747                 if (current_link_up == 1)
1748                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1749         }
1750
1751         /* ??? Without this setting Netgear GA302T PHY does not
1752          * ??? send/receive packets...
1753          */
1754         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1755             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1756                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1757                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1758                 udelay(80);
1759         }
1760
1761         tw32_f(MAC_MODE, tp->mac_mode);
1762         udelay(40);
1763
1764         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1765                 /* Polled via timer. */
1766                 tw32_f(MAC_EVENT, 0);
1767         } else {
1768                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1769         }
1770         udelay(40);
1771
1772         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1773             current_link_up == 1 &&
1774             tp->link_config.active_speed == SPEED_1000 &&
1775             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1776              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1777                 udelay(120);
1778                 tw32_f(MAC_STATUS,
1779                      (MAC_STATUS_SYNC_CHANGED |
1780                       MAC_STATUS_CFG_CHANGED));
1781                 udelay(40);
1782                 tg3_write_mem(tp,
1783                               NIC_SRAM_FIRMWARE_MBOX,
1784                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1785         }
1786
1787         if (current_link_up != netif_carrier_ok(tp->dev)) {
1788                 if (current_link_up)
1789                         netif_carrier_on(tp->dev);
1790                 else
1791                         netif_carrier_off(tp->dev);
1792                 tg3_link_report(tp);
1793         }
1794
1795         return 0;
1796 }
1797
1798 struct tg3_fiber_aneginfo {
1799         int state;
1800 #define ANEG_STATE_UNKNOWN              0
1801 #define ANEG_STATE_AN_ENABLE            1
1802 #define ANEG_STATE_RESTART_INIT         2
1803 #define ANEG_STATE_RESTART              3
1804 #define ANEG_STATE_DISABLE_LINK_OK      4
1805 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1806 #define ANEG_STATE_ABILITY_DETECT       6
1807 #define ANEG_STATE_ACK_DETECT_INIT      7
1808 #define ANEG_STATE_ACK_DETECT           8
1809 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1810 #define ANEG_STATE_COMPLETE_ACK         10
1811 #define ANEG_STATE_IDLE_DETECT_INIT     11
1812 #define ANEG_STATE_IDLE_DETECT          12
1813 #define ANEG_STATE_LINK_OK              13
1814 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
1815 #define ANEG_STATE_NEXT_PAGE_WAIT       15
1816
1817         u32 flags;
1818 #define MR_AN_ENABLE            0x00000001
1819 #define MR_RESTART_AN           0x00000002
1820 #define MR_AN_COMPLETE          0x00000004
1821 #define MR_PAGE_RX              0x00000008
1822 #define MR_NP_LOADED            0x00000010
1823 #define MR_TOGGLE_TX            0x00000020
1824 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
1825 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
1826 #define MR_LP_ADV_SYM_PAUSE     0x00000100
1827 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
1828 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1829 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1830 #define MR_LP_ADV_NEXT_PAGE     0x00001000
1831 #define MR_TOGGLE_RX            0x00002000
1832 #define MR_NP_RX                0x00004000
1833
1834 #define MR_LINK_OK              0x80000000
1835
1836         unsigned long link_time, cur_time;
1837
1838         u32 ability_match_cfg;
1839         int ability_match_count;
1840
1841         char ability_match, idle_match, ack_match;
1842
1843         u32 txconfig, rxconfig;
1844 #define ANEG_CFG_NP             0x00000080
1845 #define ANEG_CFG_ACK            0x00000040
1846 #define ANEG_CFG_RF2            0x00000020
1847 #define ANEG_CFG_RF1            0x00000010
1848 #define ANEG_CFG_PS2            0x00000001
1849 #define ANEG_CFG_PS1            0x00008000
1850 #define ANEG_CFG_HD             0x00004000
1851 #define ANEG_CFG_FD             0x00002000
1852 #define ANEG_CFG_INVAL          0x00001f06
1853
1854 };
1855 #define ANEG_OK         0
1856 #define ANEG_DONE       1
1857 #define ANEG_TIMER_ENAB 2
1858 #define ANEG_FAILED     -1
1859
1860 #define ANEG_STATE_SETTLE_TIME  10000
1861
1862 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1863                                    struct tg3_fiber_aneginfo *ap)
1864 {
1865         unsigned long delta;
1866         u32 rx_cfg_reg;
1867         int ret;
1868
1869         if (ap->state == ANEG_STATE_UNKNOWN) {
1870                 ap->rxconfig = 0;
1871                 ap->link_time = 0;
1872                 ap->cur_time = 0;
1873                 ap->ability_match_cfg = 0;
1874                 ap->ability_match_count = 0;
1875                 ap->ability_match = 0;
1876                 ap->idle_match = 0;
1877                 ap->ack_match = 0;
1878         }
1879         ap->cur_time++;
1880
1881         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1882                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1883
1884                 if (rx_cfg_reg != ap->ability_match_cfg) {
1885                         ap->ability_match_cfg = rx_cfg_reg;
1886                         ap->ability_match = 0;
1887                         ap->ability_match_count = 0;
1888                 } else {
1889                         if (++ap->ability_match_count > 1) {
1890                                 ap->ability_match = 1;
1891                                 ap->ability_match_cfg = rx_cfg_reg;
1892                         }
1893                 }
1894                 if (rx_cfg_reg & ANEG_CFG_ACK)
1895                         ap->ack_match = 1;
1896                 else
1897                         ap->ack_match = 0;
1898
1899                 ap->idle_match = 0;
1900         } else {
1901                 ap->idle_match = 1;
1902                 ap->ability_match_cfg = 0;
1903                 ap->ability_match_count = 0;
1904                 ap->ability_match = 0;
1905                 ap->ack_match = 0;
1906
1907                 rx_cfg_reg = 0;
1908         }
1909
1910         ap->rxconfig = rx_cfg_reg;
1911         ret = ANEG_OK;
1912
1913         switch(ap->state) {
1914         case ANEG_STATE_UNKNOWN:
1915                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1916                         ap->state = ANEG_STATE_AN_ENABLE;
1917
1918                 /* fallthru */
1919         case ANEG_STATE_AN_ENABLE:
1920                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1921                 if (ap->flags & MR_AN_ENABLE) {
1922                         ap->link_time = 0;
1923                         ap->cur_time = 0;
1924                         ap->ability_match_cfg = 0;
1925                         ap->ability_match_count = 0;
1926                         ap->ability_match = 0;
1927                         ap->idle_match = 0;
1928                         ap->ack_match = 0;
1929
1930                         ap->state = ANEG_STATE_RESTART_INIT;
1931                 } else {
1932                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1933                 }
1934                 break;
1935
1936         case ANEG_STATE_RESTART_INIT:
1937                 ap->link_time = ap->cur_time;
1938                 ap->flags &= ~(MR_NP_LOADED);
1939                 ap->txconfig = 0;
1940                 tw32(MAC_TX_AUTO_NEG, 0);
1941                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1942                 tw32_f(MAC_MODE, tp->mac_mode);
1943                 udelay(40);
1944
1945                 ret = ANEG_TIMER_ENAB;
1946                 ap->state = ANEG_STATE_RESTART;
1947
1948                 /* fallthru */
1949         case ANEG_STATE_RESTART:
1950                 delta = ap->cur_time - ap->link_time;
1951                 if (delta > ANEG_STATE_SETTLE_TIME) {
1952                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1953                 } else {
1954                         ret = ANEG_TIMER_ENAB;
1955                 }
1956                 break;
1957
1958         case ANEG_STATE_DISABLE_LINK_OK:
1959                 ret = ANEG_DONE;
1960                 break;
1961
1962         case ANEG_STATE_ABILITY_DETECT_INIT:
1963                 ap->flags &= ~(MR_TOGGLE_TX);
1964                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1965                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1966                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1967                 tw32_f(MAC_MODE, tp->mac_mode);
1968                 udelay(40);
1969
1970                 ap->state = ANEG_STATE_ABILITY_DETECT;
1971                 break;
1972
1973         case ANEG_STATE_ABILITY_DETECT:
1974                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1975                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1976                 }
1977                 break;
1978
1979         case ANEG_STATE_ACK_DETECT_INIT:
1980                 ap->txconfig |= ANEG_CFG_ACK;
1981                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1982                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1983                 tw32_f(MAC_MODE, tp->mac_mode);
1984                 udelay(40);
1985
1986                 ap->state = ANEG_STATE_ACK_DETECT;
1987
1988                 /* fallthru */
1989         case ANEG_STATE_ACK_DETECT:
1990                 if (ap->ack_match != 0) {
1991                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1992                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1993                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1994                         } else {
1995                                 ap->state = ANEG_STATE_AN_ENABLE;
1996                         }
1997                 } else if (ap->ability_match != 0 &&
1998                            ap->rxconfig == 0) {
1999                         ap->state = ANEG_STATE_AN_ENABLE;
2000                 }
2001                 break;
2002
2003         case ANEG_STATE_COMPLETE_ACK_INIT:
2004                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2005                         ret = ANEG_FAILED;
2006                         break;
2007                 }
2008                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2009                                MR_LP_ADV_HALF_DUPLEX |
2010                                MR_LP_ADV_SYM_PAUSE |
2011                                MR_LP_ADV_ASYM_PAUSE |
2012                                MR_LP_ADV_REMOTE_FAULT1 |
2013                                MR_LP_ADV_REMOTE_FAULT2 |
2014                                MR_LP_ADV_NEXT_PAGE |
2015                                MR_TOGGLE_RX |
2016                                MR_NP_RX);
2017                 if (ap->rxconfig & ANEG_CFG_FD)
2018                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2019                 if (ap->rxconfig & ANEG_CFG_HD)
2020                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2021                 if (ap->rxconfig & ANEG_CFG_PS1)
2022                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2023                 if (ap->rxconfig & ANEG_CFG_PS2)
2024                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2025                 if (ap->rxconfig & ANEG_CFG_RF1)
2026                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2027                 if (ap->rxconfig & ANEG_CFG_RF2)
2028                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2029                 if (ap->rxconfig & ANEG_CFG_NP)
2030                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2031
2032                 ap->link_time = ap->cur_time;
2033
2034                 ap->flags ^= (MR_TOGGLE_TX);
2035                 if (ap->rxconfig & 0x0008)
2036                         ap->flags |= MR_TOGGLE_RX;
2037                 if (ap->rxconfig & ANEG_CFG_NP)
2038                         ap->flags |= MR_NP_RX;
2039                 ap->flags |= MR_PAGE_RX;
2040
2041                 ap->state = ANEG_STATE_COMPLETE_ACK;
2042                 ret = ANEG_TIMER_ENAB;
2043                 break;
2044
2045         case ANEG_STATE_COMPLETE_ACK:
2046                 if (ap->ability_match != 0 &&
2047                     ap->rxconfig == 0) {
2048                         ap->state = ANEG_STATE_AN_ENABLE;
2049                         break;
2050                 }
2051                 delta = ap->cur_time - ap->link_time;
2052                 if (delta > ANEG_STATE_SETTLE_TIME) {
2053                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2054                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2055                         } else {
2056                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2057                                     !(ap->flags & MR_NP_RX)) {
2058                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2059                                 } else {
2060                                         ret = ANEG_FAILED;
2061                                 }
2062                         }
2063                 }
2064                 break;
2065
2066         case ANEG_STATE_IDLE_DETECT_INIT:
2067                 ap->link_time = ap->cur_time;
2068                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2069                 tw32_f(MAC_MODE, tp->mac_mode);
2070                 udelay(40);
2071
2072                 ap->state = ANEG_STATE_IDLE_DETECT;
2073                 ret = ANEG_TIMER_ENAB;
2074                 break;
2075
2076         case ANEG_STATE_IDLE_DETECT:
2077                 if (ap->ability_match != 0 &&
2078                     ap->rxconfig == 0) {
2079                         ap->state = ANEG_STATE_AN_ENABLE;
2080                         break;
2081                 }
2082                 delta = ap->cur_time - ap->link_time;
2083                 if (delta > ANEG_STATE_SETTLE_TIME) {
2084                         /* XXX another gem from the Broadcom driver :( */
2085                         ap->state = ANEG_STATE_LINK_OK;
2086                 }
2087                 break;
2088
2089         case ANEG_STATE_LINK_OK:
2090                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2091                 ret = ANEG_DONE;
2092                 break;
2093
2094         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2095                 /* ??? unimplemented */
2096                 break;
2097
2098         case ANEG_STATE_NEXT_PAGE_WAIT:
2099                 /* ??? unimplemented */
2100                 break;
2101
2102         default:
2103                 ret = ANEG_FAILED;
2104                 break;
2105         };
2106
2107         return ret;
2108 }
2109
2110 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2111 {
2112         int res = 0;
2113         struct tg3_fiber_aneginfo aninfo;
2114         int status = ANEG_FAILED;
2115         unsigned int tick;
2116         u32 tmp;
2117
2118         tw32_f(MAC_TX_AUTO_NEG, 0);
2119
2120         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2121         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2122         udelay(40);
2123
2124         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2125         udelay(40);
2126
2127         memset(&aninfo, 0, sizeof(aninfo));
2128         aninfo.flags |= MR_AN_ENABLE;
2129         aninfo.state = ANEG_STATE_UNKNOWN;
2130         aninfo.cur_time = 0;
2131         tick = 0;
2132         while (++tick < 195000) {
2133                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2134                 if (status == ANEG_DONE || status == ANEG_FAILED)
2135                         break;
2136
2137                 udelay(1);
2138         }
2139
2140         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2141         tw32_f(MAC_MODE, tp->mac_mode);
2142         udelay(40);
2143
2144         *flags = aninfo.flags;
2145
2146         if (status == ANEG_DONE &&
2147             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2148                              MR_LP_ADV_FULL_DUPLEX)))
2149                 res = 1;
2150
2151         return res;
2152 }
2153
2154 static void tg3_init_bcm8002(struct tg3 *tp)
2155 {
2156         u32 mac_status = tr32(MAC_STATUS);
2157         int i;
2158
2159         /* Reset when initting first time or we have a link. */
2160         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2161             !(mac_status & MAC_STATUS_PCS_SYNCED))
2162                 return;
2163
2164         /* Set PLL lock range. */
2165         tg3_writephy(tp, 0x16, 0x8007);
2166
2167         /* SW reset */
2168         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2169
2170         /* Wait for reset to complete. */
2171         /* XXX schedule_timeout() ... */
2172         for (i = 0; i < 500; i++)
2173                 udelay(10);
2174
2175         /* Config mode; select PMA/Ch 1 regs. */
2176         tg3_writephy(tp, 0x10, 0x8411);
2177
2178         /* Enable auto-lock and comdet, select txclk for tx. */
2179         tg3_writephy(tp, 0x11, 0x0a10);
2180
2181         tg3_writephy(tp, 0x18, 0x00a0);
2182         tg3_writephy(tp, 0x16, 0x41ff);
2183
2184         /* Assert and deassert POR. */
2185         tg3_writephy(tp, 0x13, 0x0400);
2186         udelay(40);
2187         tg3_writephy(tp, 0x13, 0x0000);
2188
2189         tg3_writephy(tp, 0x11, 0x0a50);
2190         udelay(40);
2191         tg3_writephy(tp, 0x11, 0x0a10);
2192
2193         /* Wait for signal to stabilize */
2194         /* XXX schedule_timeout() ... */
2195         for (i = 0; i < 15000; i++)
2196                 udelay(10);
2197
2198         /* Deselect the channel register so we can read the PHYID
2199          * later.
2200          */
2201         tg3_writephy(tp, 0x10, 0x8011);
2202 }
2203
2204 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2205 {
2206         u32 sg_dig_ctrl, sg_dig_status;
2207         u32 serdes_cfg, expected_sg_dig_ctrl;
2208         int workaround, port_a;
2209         int current_link_up;
2210
2211         serdes_cfg = 0;
2212         expected_sg_dig_ctrl = 0;
2213         workaround = 0;
2214         port_a = 1;
2215         current_link_up = 0;
2216
2217         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2218             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2219                 workaround = 1;
2220                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2221                         port_a = 0;
2222
2223                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2224                 /* preserve bits 20-23 for voltage regulator */
2225                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2226         }
2227
2228         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2229
2230         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2231                 if (sg_dig_ctrl & (1 << 31)) {
2232                         if (workaround) {
2233                                 u32 val = serdes_cfg;
2234
2235                                 if (port_a)
2236                                         val |= 0xc010000;
2237                                 else
2238                                         val |= 0x4010000;
2239                                 tw32_f(MAC_SERDES_CFG, val);
2240                         }
2241                         tw32_f(SG_DIG_CTRL, 0x01388400);
2242                 }
2243                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2244                         tg3_setup_flow_control(tp, 0, 0);
2245                         current_link_up = 1;
2246                 }
2247                 goto out;
2248         }
2249
2250         /* Want auto-negotiation.  */
2251         expected_sg_dig_ctrl = 0x81388400;
2252
2253         /* Pause capability */
2254         expected_sg_dig_ctrl |= (1 << 11);
2255
2256         /* Asymettric pause */
2257         expected_sg_dig_ctrl |= (1 << 12);
2258
2259         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2260                 if (workaround)
2261                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2262                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2263                 udelay(5);
2264                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2265
2266                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2267         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2268                                  MAC_STATUS_SIGNAL_DET)) {
2269                 int i;
2270
2271                 /* Giver time to negotiate (~200ms) */
2272                 for (i = 0; i < 40000; i++) {
2273                         sg_dig_status = tr32(SG_DIG_STATUS);
2274                         if (sg_dig_status & (0x3))
2275                                 break;
2276                         udelay(5);
2277                 }
2278                 mac_status = tr32(MAC_STATUS);
2279
2280                 if ((sg_dig_status & (1 << 1)) &&
2281                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2282                         u32 local_adv, remote_adv;
2283
2284                         local_adv = ADVERTISE_PAUSE_CAP;
2285                         remote_adv = 0;
2286                         if (sg_dig_status & (1 << 19))
2287                                 remote_adv |= LPA_PAUSE_CAP;
2288                         if (sg_dig_status & (1 << 20))
2289                                 remote_adv |= LPA_PAUSE_ASYM;
2290
2291                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2292                         current_link_up = 1;
2293                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2294                 } else if (!(sg_dig_status & (1 << 1))) {
2295                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2296                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2297                         else {
2298                                 if (workaround) {
2299                                         u32 val = serdes_cfg;
2300
2301                                         if (port_a)
2302                                                 val |= 0xc010000;
2303                                         else
2304                                                 val |= 0x4010000;
2305
2306                                         tw32_f(MAC_SERDES_CFG, val);
2307                                 }
2308
2309                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2310                                 udelay(40);
2311
2312                                 /* Link parallel detection - link is up */
2313                                 /* only if we have PCS_SYNC and not */
2314                                 /* receiving config code words */
2315                                 mac_status = tr32(MAC_STATUS);
2316                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2317                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2318                                         tg3_setup_flow_control(tp, 0, 0);
2319                                         current_link_up = 1;
2320                                 }
2321                         }
2322                 }
2323         }
2324
2325 out:
2326         return current_link_up;
2327 }
2328
2329 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2330 {
2331         int current_link_up = 0;
2332
2333         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2334                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2335                 goto out;
2336         }
2337
2338         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2339                 u32 flags;
2340                 int i;
2341
2342                 if (fiber_autoneg(tp, &flags)) {
2343                         u32 local_adv, remote_adv;
2344
2345                         local_adv = ADVERTISE_PAUSE_CAP;
2346                         remote_adv = 0;
2347                         if (flags & MR_LP_ADV_SYM_PAUSE)
2348                                 remote_adv |= LPA_PAUSE_CAP;
2349                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2350                                 remote_adv |= LPA_PAUSE_ASYM;
2351
2352                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2353
2354                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2355                         current_link_up = 1;
2356                 }
2357                 for (i = 0; i < 30; i++) {
2358                         udelay(20);
2359                         tw32_f(MAC_STATUS,
2360                                (MAC_STATUS_SYNC_CHANGED |
2361                                 MAC_STATUS_CFG_CHANGED));
2362                         udelay(40);
2363                         if ((tr32(MAC_STATUS) &
2364                              (MAC_STATUS_SYNC_CHANGED |
2365                               MAC_STATUS_CFG_CHANGED)) == 0)
2366                                 break;
2367                 }
2368
2369                 mac_status = tr32(MAC_STATUS);
2370                 if (current_link_up == 0 &&
2371                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2372                     !(mac_status & MAC_STATUS_RCVD_CFG))
2373                         current_link_up = 1;
2374         } else {
2375                 /* Forcing 1000FD link up. */
2376                 current_link_up = 1;
2377                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2378
2379                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2380                 udelay(40);
2381         }
2382
2383 out:
2384         return current_link_up;
2385 }
2386
2387 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2388 {
2389         u32 orig_pause_cfg;
2390         u16 orig_active_speed;
2391         u8 orig_active_duplex;
2392         u32 mac_status;
2393         int current_link_up;
2394         int i;
2395
2396         orig_pause_cfg =
2397                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2398                                   TG3_FLAG_TX_PAUSE));
2399         orig_active_speed = tp->link_config.active_speed;
2400         orig_active_duplex = tp->link_config.active_duplex;
2401
2402         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2403             netif_carrier_ok(tp->dev) &&
2404             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2405                 mac_status = tr32(MAC_STATUS);
2406                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2407                                MAC_STATUS_SIGNAL_DET |
2408                                MAC_STATUS_CFG_CHANGED |
2409                                MAC_STATUS_RCVD_CFG);
2410                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2411                                    MAC_STATUS_SIGNAL_DET)) {
2412                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2413                                             MAC_STATUS_CFG_CHANGED));
2414                         return 0;
2415                 }
2416         }
2417
2418         tw32_f(MAC_TX_AUTO_NEG, 0);
2419
2420         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2421         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2422         tw32_f(MAC_MODE, tp->mac_mode);
2423         udelay(40);
2424
2425         if (tp->phy_id == PHY_ID_BCM8002)
2426                 tg3_init_bcm8002(tp);
2427
2428         /* Enable link change event even when serdes polling.  */
2429         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2430         udelay(40);
2431
2432         current_link_up = 0;
2433         mac_status = tr32(MAC_STATUS);
2434
2435         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2436                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2437         else
2438                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2439
2440         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2441         tw32_f(MAC_MODE, tp->mac_mode);
2442         udelay(40);
2443
2444         tp->hw_status->status =
2445                 (SD_STATUS_UPDATED |
2446                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2447
2448         for (i = 0; i < 100; i++) {
2449                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2450                                     MAC_STATUS_CFG_CHANGED));
2451                 udelay(5);
2452                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2453                                          MAC_STATUS_CFG_CHANGED)) == 0)
2454                         break;
2455         }
2456
2457         mac_status = tr32(MAC_STATUS);
2458         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2459                 current_link_up = 0;
2460                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2461                         tw32_f(MAC_MODE, (tp->mac_mode |
2462                                           MAC_MODE_SEND_CONFIGS));
2463                         udelay(1);
2464                         tw32_f(MAC_MODE, tp->mac_mode);
2465                 }
2466         }
2467
2468         if (current_link_up == 1) {
2469                 tp->link_config.active_speed = SPEED_1000;
2470                 tp->link_config.active_duplex = DUPLEX_FULL;
2471                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2472                                     LED_CTRL_LNKLED_OVERRIDE |
2473                                     LED_CTRL_1000MBPS_ON));
2474         } else {
2475                 tp->link_config.active_speed = SPEED_INVALID;
2476                 tp->link_config.active_duplex = DUPLEX_INVALID;
2477                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2478                                     LED_CTRL_LNKLED_OVERRIDE |
2479                                     LED_CTRL_TRAFFIC_OVERRIDE));
2480         }
2481
2482         if (current_link_up != netif_carrier_ok(tp->dev)) {
2483                 if (current_link_up)
2484                         netif_carrier_on(tp->dev);
2485                 else
2486                         netif_carrier_off(tp->dev);
2487                 tg3_link_report(tp);
2488         } else {
2489                 u32 now_pause_cfg =
2490                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2491                                          TG3_FLAG_TX_PAUSE);
2492                 if (orig_pause_cfg != now_pause_cfg ||
2493                     orig_active_speed != tp->link_config.active_speed ||
2494                     orig_active_duplex != tp->link_config.active_duplex)
2495                         tg3_link_report(tp);
2496         }
2497
2498         return 0;
2499 }
2500
2501 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2502 {
2503         int err;
2504
2505         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2506                 err = tg3_setup_fiber_phy(tp, force_reset);
2507         } else {
2508                 err = tg3_setup_copper_phy(tp, force_reset);
2509         }
2510
2511         if (tp->link_config.active_speed == SPEED_1000 &&
2512             tp->link_config.active_duplex == DUPLEX_HALF)
2513                 tw32(MAC_TX_LENGTHS,
2514                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2515                       (6 << TX_LENGTHS_IPG_SHIFT) |
2516                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2517         else
2518                 tw32(MAC_TX_LENGTHS,
2519                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2520                       (6 << TX_LENGTHS_IPG_SHIFT) |
2521                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2522
2523         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2524                 if (netif_carrier_ok(tp->dev)) {
2525                         tw32(HOSTCC_STAT_COAL_TICKS,
2526                              tp->coal.stats_block_coalesce_usecs);
2527                 } else {
2528                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2529                 }
2530         }
2531
2532         return err;
2533 }
2534
2535 /* Tigon3 never reports partial packet sends.  So we do not
2536  * need special logic to handle SKBs that have not had all
2537  * of their frags sent yet, like SunGEM does.
2538  */
2539 static void tg3_tx(struct tg3 *tp)
2540 {
2541         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2542         u32 sw_idx = tp->tx_cons;
2543
2544         while (sw_idx != hw_idx) {
2545                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2546                 struct sk_buff *skb = ri->skb;
2547                 int i;
2548
2549                 if (unlikely(skb == NULL))
2550                         BUG();
2551
2552                 pci_unmap_single(tp->pdev,
2553                                  pci_unmap_addr(ri, mapping),
2554                                  skb_headlen(skb),
2555                                  PCI_DMA_TODEVICE);
2556
2557                 ri->skb = NULL;
2558
2559                 sw_idx = NEXT_TX(sw_idx);
2560
2561                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2562                         if (unlikely(sw_idx == hw_idx))
2563                                 BUG();
2564
2565                         ri = &tp->tx_buffers[sw_idx];
2566                         if (unlikely(ri->skb != NULL))
2567                                 BUG();
2568
2569                         pci_unmap_page(tp->pdev,
2570                                        pci_unmap_addr(ri, mapping),
2571                                        skb_shinfo(skb)->frags[i].size,
2572                                        PCI_DMA_TODEVICE);
2573
2574                         sw_idx = NEXT_TX(sw_idx);
2575                 }
2576
2577                 dev_kfree_skb(skb);
2578         }
2579
2580         tp->tx_cons = sw_idx;
2581
2582         if (netif_queue_stopped(tp->dev) &&
2583             (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2584                 netif_wake_queue(tp->dev);
2585 }
2586
2587 /* Returns size of skb allocated or < 0 on error.
2588  *
2589  * We only need to fill in the address because the other members
2590  * of the RX descriptor are invariant, see tg3_init_rings.
2591  *
2592  * Note the purposeful assymetry of cpu vs. chip accesses.  For
2593  * posting buffers we only dirty the first cache line of the RX
2594  * descriptor (containing the address).  Whereas for the RX status
2595  * buffers the cpu only reads the last cacheline of the RX descriptor
2596  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2597  */
2598 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2599                             int src_idx, u32 dest_idx_unmasked)
2600 {
2601         struct tg3_rx_buffer_desc *desc;
2602         struct ring_info *map, *src_map;
2603         struct sk_buff *skb;
2604         dma_addr_t mapping;
2605         int skb_size, dest_idx;
2606
2607         src_map = NULL;
2608         switch (opaque_key) {
2609         case RXD_OPAQUE_RING_STD:
2610                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2611                 desc = &tp->rx_std[dest_idx];
2612                 map = &tp->rx_std_buffers[dest_idx];
2613                 if (src_idx >= 0)
2614                         src_map = &tp->rx_std_buffers[src_idx];
2615                 skb_size = RX_PKT_BUF_SZ;
2616                 break;
2617
2618         case RXD_OPAQUE_RING_JUMBO:
2619                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2620                 desc = &tp->rx_jumbo[dest_idx];
2621                 map = &tp->rx_jumbo_buffers[dest_idx];
2622                 if (src_idx >= 0)
2623                         src_map = &tp->rx_jumbo_buffers[src_idx];
2624                 skb_size = RX_JUMBO_PKT_BUF_SZ;
2625                 break;
2626
2627         default:
2628                 return -EINVAL;
2629         };
2630
2631         /* Do not overwrite any of the map or rp information
2632          * until we are sure we can commit to a new buffer.
2633          *
2634          * Callers depend upon this behavior and assume that
2635          * we leave everything unchanged if we fail.
2636          */
2637         skb = dev_alloc_skb(skb_size);
2638         if (skb == NULL)
2639                 return -ENOMEM;
2640
2641         skb->dev = tp->dev;
2642         skb_reserve(skb, tp->rx_offset);
2643
2644         mapping = pci_map_single(tp->pdev, skb->data,
2645                                  skb_size - tp->rx_offset,
2646                                  PCI_DMA_FROMDEVICE);
2647
2648         map->skb = skb;
2649         pci_unmap_addr_set(map, mapping, mapping);
2650
2651         if (src_map != NULL)
2652                 src_map->skb = NULL;
2653
2654         desc->addr_hi = ((u64)mapping >> 32);
2655         desc->addr_lo = ((u64)mapping & 0xffffffff);
2656
2657         return skb_size;
2658 }
2659
2660 /* We only need to move over in the address because the other
2661  * members of the RX descriptor are invariant.  See notes above
2662  * tg3_alloc_rx_skb for full details.
2663  */
2664 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2665                            int src_idx, u32 dest_idx_unmasked)
2666 {
2667         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2668         struct ring_info *src_map, *dest_map;
2669         int dest_idx;
2670
2671         switch (opaque_key) {
2672         case RXD_OPAQUE_RING_STD:
2673                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2674                 dest_desc = &tp->rx_std[dest_idx];
2675                 dest_map = &tp->rx_std_buffers[dest_idx];
2676                 src_desc = &tp->rx_std[src_idx];
2677                 src_map = &tp->rx_std_buffers[src_idx];
2678                 break;
2679
2680         case RXD_OPAQUE_RING_JUMBO:
2681                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2682                 dest_desc = &tp->rx_jumbo[dest_idx];
2683                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2684                 src_desc = &tp->rx_jumbo[src_idx];
2685                 src_map = &tp->rx_jumbo_buffers[src_idx];
2686                 break;
2687
2688         default:
2689                 return;
2690         };
2691
2692         dest_map->skb = src_map->skb;
2693         pci_unmap_addr_set(dest_map, mapping,
2694                            pci_unmap_addr(src_map, mapping));
2695         dest_desc->addr_hi = src_desc->addr_hi;
2696         dest_desc->addr_lo = src_desc->addr_lo;
2697
2698         src_map->skb = NULL;
2699 }
2700
2701 #if TG3_VLAN_TAG_USED
2702 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2703 {
2704         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2705 }
2706 #endif
2707
2708 /* The RX ring scheme is composed of multiple rings which post fresh
2709  * buffers to the chip, and one special ring the chip uses to report
2710  * status back to the host.
2711  *
2712  * The special ring reports the status of received packets to the
2713  * host.  The chip does not write into the original descriptor the
2714  * RX buffer was obtained from.  The chip simply takes the original
2715  * descriptor as provided by the host, updates the status and length
2716  * field, then writes this into the next status ring entry.
2717  *
2718  * Each ring the host uses to post buffers to the chip is described
2719  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
2720  * it is first placed into the on-chip ram.  When the packet's length
2721  * is known, it walks down the TG3_BDINFO entries to select the ring.
2722  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2723  * which is within the range of the new packet's length is chosen.
2724  *
2725  * The "separate ring for rx status" scheme may sound queer, but it makes
2726  * sense from a cache coherency perspective.  If only the host writes
2727  * to the buffer post rings, and only the chip writes to the rx status
2728  * rings, then cache lines never move beyond shared-modified state.
2729  * If both the host and chip were to write into the same ring, cache line
2730  * eviction could occur since both entities want it in an exclusive state.
2731  */
2732 static int tg3_rx(struct tg3 *tp, int budget)
2733 {
2734         u32 work_mask;
2735         u32 sw_idx = tp->rx_rcb_ptr;
2736         u16 hw_idx;
2737         int received;
2738
2739         hw_idx = tp->hw_status->idx[0].rx_producer;
2740         /*
2741          * We need to order the read of hw_idx and the read of
2742          * the opaque cookie.
2743          */
2744         rmb();
2745         work_mask = 0;
2746         received = 0;
2747         while (sw_idx != hw_idx && budget > 0) {
2748                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2749                 unsigned int len;
2750                 struct sk_buff *skb;
2751                 dma_addr_t dma_addr;
2752                 u32 opaque_key, desc_idx, *post_ptr;
2753
2754                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2755                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2756                 if (opaque_key == RXD_OPAQUE_RING_STD) {
2757                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2758                                                   mapping);
2759                         skb = tp->rx_std_buffers[desc_idx].skb;
2760                         post_ptr = &tp->rx_std_ptr;
2761                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2762                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2763                                                   mapping);
2764                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
2765                         post_ptr = &tp->rx_jumbo_ptr;
2766                 }
2767                 else {
2768                         goto next_pkt_nopost;
2769                 }
2770
2771                 work_mask |= opaque_key;
2772
2773                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2774                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2775                 drop_it:
2776                         tg3_recycle_rx(tp, opaque_key,
2777                                        desc_idx, *post_ptr);
2778                 drop_it_no_recycle:
2779                         /* Other statistics kept track of by card. */
2780                         tp->net_stats.rx_dropped++;
2781                         goto next_pkt;
2782                 }
2783
2784                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2785
2786                 if (len > RX_COPY_THRESHOLD
2787                         && tp->rx_offset == 2
2788                         /* rx_offset != 2 iff this is a 5701 card running
2789                          * in PCI-X mode [see tg3_get_invariants()] */
2790                 ) {
2791                         int skb_size;
2792
2793                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2794                                                     desc_idx, *post_ptr);
2795                         if (skb_size < 0)
2796                                 goto drop_it;
2797
2798                         pci_unmap_single(tp->pdev, dma_addr,
2799                                          skb_size - tp->rx_offset,
2800                                          PCI_DMA_FROMDEVICE);
2801
2802                         skb_put(skb, len);
2803                 } else {
2804                         struct sk_buff *copy_skb;
2805
2806                         tg3_recycle_rx(tp, opaque_key,
2807                                        desc_idx, *post_ptr);
2808
2809                         copy_skb = dev_alloc_skb(len + 2);
2810                         if (copy_skb == NULL)
2811                                 goto drop_it_no_recycle;
2812
2813                         copy_skb->dev = tp->dev;
2814                         skb_reserve(copy_skb, 2);
2815                         skb_put(copy_skb, len);
2816                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2817                         memcpy(copy_skb->data, skb->data, len);
2818                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2819
2820                         /* We'll reuse the original ring buffer. */
2821                         skb = copy_skb;
2822                 }
2823
2824                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2825                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2826                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2827                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
2828                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2829                 else
2830                         skb->ip_summed = CHECKSUM_NONE;
2831
2832                 skb->protocol = eth_type_trans(skb, tp->dev);
2833 #if TG3_VLAN_TAG_USED
2834                 if (tp->vlgrp != NULL &&
2835                     desc->type_flags & RXD_FLAG_VLAN) {
2836                         tg3_vlan_rx(tp, skb,
2837                                     desc->err_vlan & RXD_VLAN_MASK);
2838                 } else
2839 #endif
2840                         netif_receive_skb(skb);
2841
2842                 tp->dev->last_rx = jiffies;
2843                 received++;
2844                 budget--;
2845
2846 next_pkt:
2847                 (*post_ptr)++;
2848 next_pkt_nopost:
2849                 sw_idx++;
2850                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
2851
2852                 /* Refresh hw_idx to see if there is new work */
2853                 if (sw_idx == hw_idx) {
2854                         hw_idx = tp->hw_status->idx[0].rx_producer;
2855                         rmb();
2856                 }
2857         }
2858
2859         /* ACK the status ring. */
2860         tp->rx_rcb_ptr = sw_idx;
2861         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
2862
2863         /* Refill RX ring(s). */
2864         if (work_mask & RXD_OPAQUE_RING_STD) {
2865                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2866                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2867                              sw_idx);
2868         }
2869         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2870                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2871                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2872                              sw_idx);
2873         }
2874         mmiowb();
2875
2876         return received;
2877 }
2878
2879 static int tg3_poll(struct net_device *netdev, int *budget)
2880 {
2881         struct tg3 *tp = netdev_priv(netdev);
2882         struct tg3_hw_status *sblk = tp->hw_status;
2883         int done;
2884
2885         /* handle link change and other phy events */
2886         if (!(tp->tg3_flags &
2887               (TG3_FLAG_USE_LINKCHG_REG |
2888                TG3_FLAG_POLL_SERDES))) {
2889                 if (sblk->status & SD_STATUS_LINK_CHG) {
2890                         sblk->status = SD_STATUS_UPDATED |
2891                                 (sblk->status & ~SD_STATUS_LINK_CHG);
2892                         spin_lock(&tp->lock);
2893                         tg3_setup_phy(tp, 0);
2894                         spin_unlock(&tp->lock);
2895                 }
2896         }
2897
2898         /* run TX completion thread */
2899         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2900                 spin_lock(&tp->tx_lock);
2901                 tg3_tx(tp);
2902                 spin_unlock(&tp->tx_lock);
2903         }
2904
2905         /* run RX thread, within the bounds set by NAPI.
2906          * All RX "locking" is done by ensuring outside
2907          * code synchronizes with dev->poll()
2908          */
2909         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2910                 int orig_budget = *budget;
2911                 int work_done;
2912
2913                 if (orig_budget > netdev->quota)
2914                         orig_budget = netdev->quota;
2915
2916                 work_done = tg3_rx(tp, orig_budget);
2917
2918                 *budget -= work_done;
2919                 netdev->quota -= work_done;
2920         }
2921
2922         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
2923                 tp->last_tag = sblk->status_tag;
2924         rmb();
2925         sblk->status &= ~SD_STATUS_UPDATED;
2926
2927         /* if no more work, tell net stack and NIC we're done */
2928         done = !tg3_has_work(tp);
2929         if (done) {
2930                 spin_lock(&tp->lock);
2931                 netif_rx_complete(netdev);
2932                 tg3_restart_ints(tp);
2933                 spin_unlock(&tp->lock);
2934         }
2935
2936         return (done ? 0 : 1);
2937 }
2938
2939 static void tg3_irq_quiesce(struct tg3 *tp)
2940 {
2941         BUG_ON(tp->irq_sync);
2942
2943         tp->irq_sync = 1;
2944         smp_mb();
2945
2946         synchronize_irq(tp->pdev->irq);
2947 }
2948
2949 static inline int tg3_irq_sync(struct tg3 *tp)
2950 {
2951         return tp->irq_sync;
2952 }
2953
2954 /* Fully shutdown all tg3 driver activity elsewhere in the system.
2955  * If irq_sync is non-zero, then the IRQ handler must be synchronized
2956  * with as well.  Most of the time, this is not necessary except when
2957  * shutting down the device.
2958  */
2959 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
2960 {
2961         if (irq_sync)
2962                 tg3_irq_quiesce(tp);
2963         spin_lock_bh(&tp->lock);
2964         spin_lock(&tp->tx_lock);
2965 }
2966
2967 static inline void tg3_full_unlock(struct tg3 *tp)
2968 {
2969         spin_unlock(&tp->tx_lock);
2970         spin_unlock_bh(&tp->lock);
2971 }
2972
2973 /* MSI ISR - No need to check for interrupt sharing and no need to
2974  * flush status block and interrupt mailbox. PCI ordering rules
2975  * guarantee that MSI will arrive after the status block.
2976  */
2977 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
2978 {
2979         struct net_device *dev = dev_id;
2980         struct tg3 *tp = netdev_priv(dev);
2981         struct tg3_hw_status *sblk = tp->hw_status;
2982
2983         /*
2984          * Writing any value to intr-mbox-0 clears PCI INTA# and
2985          * chip-internal interrupt pending events.
2986          * Writing non-zero to intr-mbox-0 additional tells the
2987          * NIC to stop sending us irqs, engaging "in-intr-handler"
2988          * event coalescing.
2989          */
2990         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
2991         tp->last_tag = sblk->status_tag;
2992         rmb();
2993         if (tg3_irq_sync(tp))
2994                 goto out;
2995         sblk->status &= ~SD_STATUS_UPDATED;
2996         if (likely(tg3_has_work(tp)))
2997                 netif_rx_schedule(dev);         /* schedule NAPI poll */
2998         else {
2999                 /* No work, re-enable interrupts.  */
3000                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3001                              tp->last_tag << 24);
3002         }
3003 out:
3004         return IRQ_RETVAL(1);
3005 }
3006
3007 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3008 {
3009         struct net_device *dev = dev_id;
3010         struct tg3 *tp = netdev_priv(dev);
3011         struct tg3_hw_status *sblk = tp->hw_status;
3012         unsigned int handled = 1;
3013
3014         /* In INTx mode, it is possible for the interrupt to arrive at
3015          * the CPU before the status block posted prior to the interrupt.
3016          * Reading the PCI State register will confirm whether the
3017          * interrupt is ours and will flush the status block.
3018          */
3019         if ((sblk->status & SD_STATUS_UPDATED) ||
3020             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3021                 /*
3022                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3023                  * chip-internal interrupt pending events.
3024                  * Writing non-zero to intr-mbox-0 additional tells the
3025                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3026                  * event coalescing.
3027                  */
3028                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3029                              0x00000001);
3030                 if (tg3_irq_sync(tp))
3031                         goto out;
3032                 sblk->status &= ~SD_STATUS_UPDATED;
3033                 if (likely(tg3_has_work(tp)))
3034                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3035                 else {
3036                         /* No work, shared interrupt perhaps?  re-enable
3037                          * interrupts, and flush that PCI write
3038                          */
3039                         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3040                                 0x00000000);
3041                         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3042                 }
3043         } else {        /* shared interrupt */
3044                 handled = 0;
3045         }
3046 out:
3047         return IRQ_RETVAL(handled);
3048 }
3049
3050 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3051 {
3052         struct net_device *dev = dev_id;
3053         struct tg3 *tp = netdev_priv(dev);
3054         struct tg3_hw_status *sblk = tp->hw_status;
3055         unsigned int handled = 1;
3056
3057         /* In INTx mode, it is possible for the interrupt to arrive at
3058          * the CPU before the status block posted prior to the interrupt.
3059          * Reading the PCI State register will confirm whether the
3060          * interrupt is ours and will flush the status block.
3061          */
3062         if ((sblk->status & SD_STATUS_UPDATED) ||
3063             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3064                 /*
3065                  * writing any value to intr-mbox-0 clears PCI INTA# and
3066                  * chip-internal interrupt pending events.
3067                  * writing non-zero to intr-mbox-0 additional tells the
3068                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3069                  * event coalescing.
3070                  */
3071                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3072                              0x00000001);
3073                 tp->last_tag = sblk->status_tag;
3074                 rmb();
3075                 if (tg3_irq_sync(tp))
3076                         goto out;
3077                 sblk->status &= ~SD_STATUS_UPDATED;
3078                 if (likely(tg3_has_work(tp)))
3079                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3080                 else {
3081                         /* no work, shared interrupt perhaps?  re-enable
3082                          * interrupts, and flush that PCI write
3083                          */
3084                         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3085                                      tp->last_tag << 24);
3086                         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3087                 }
3088         } else {        /* shared interrupt */
3089                 handled = 0;
3090         }
3091 out:
3092         return IRQ_RETVAL(handled);
3093 }
3094
3095 /* ISR for interrupt test */
3096 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3097                 struct pt_regs *regs)
3098 {
3099         struct net_device *dev = dev_id;
3100         struct tg3 *tp = netdev_priv(dev);
3101         struct tg3_hw_status *sblk = tp->hw_status;
3102
3103         if (sblk->status & SD_STATUS_UPDATED) {
3104                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3105                              0x00000001);
3106                 return IRQ_RETVAL(1);
3107         }
3108         return IRQ_RETVAL(0);
3109 }
3110
3111 static int tg3_init_hw(struct tg3 *);
3112 static int tg3_halt(struct tg3 *, int, int);
3113
3114 #ifdef CONFIG_NET_POLL_CONTROLLER
3115 static void tg3_poll_controller(struct net_device *dev)
3116 {
3117         struct tg3 *tp = netdev_priv(dev);
3118
3119         tg3_interrupt(tp->pdev->irq, dev, NULL);
3120 }
3121 #endif
3122
3123 static void tg3_reset_task(void *_data)
3124 {
3125         struct tg3 *tp = _data;
3126         unsigned int restart_timer;
3127
3128         tg3_netif_stop(tp);
3129
3130         tg3_full_lock(tp, 1);
3131
3132         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3133         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3134
3135         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3136         tg3_init_hw(tp);
3137
3138         tg3_netif_start(tp);
3139
3140         tg3_full_unlock(tp);
3141
3142         if (restart_timer)
3143                 mod_timer(&tp->timer, jiffies + 1);
3144 }
3145
3146 static void tg3_tx_timeout(struct net_device *dev)
3147 {
3148         struct tg3 *tp = netdev_priv(dev);
3149
3150         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3151                dev->name);
3152
3153         schedule_work(&tp->reset_task);
3154 }
3155
3156 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3157
3158 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3159                                        u32 guilty_entry, int guilty_len,
3160                                        u32 last_plus_one, u32 *start, u32 mss)
3161 {
3162         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3163         dma_addr_t new_addr;
3164         u32 entry = *start;
3165         int i;
3166
3167         if (!new_skb) {
3168                 dev_kfree_skb(skb);
3169                 return -1;
3170         }
3171
3172         /* New SKB is guaranteed to be linear. */
3173         entry = *start;
3174         new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3175                                   PCI_DMA_TODEVICE);
3176         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3177                     (skb->ip_summed == CHECKSUM_HW) ?
3178                     TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3179         *start = NEXT_TX(entry);
3180
3181         /* Now clean up the sw ring entries. */
3182         i = 0;
3183         while (entry != last_plus_one) {
3184                 int len;
3185
3186                 if (i == 0)
3187                         len = skb_headlen(skb);
3188                 else
3189                         len = skb_shinfo(skb)->frags[i-1].size;
3190                 pci_unmap_single(tp->pdev,
3191                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3192                                  len, PCI_DMA_TODEVICE);
3193                 if (i == 0) {
3194                         tp->tx_buffers[entry].skb = new_skb;
3195                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3196                 } else {
3197                         tp->tx_buffers[entry].skb = NULL;
3198                 }
3199                 entry = NEXT_TX(entry);
3200                 i++;
3201         }
3202
3203         dev_kfree_skb(skb);
3204
3205         return 0;
3206 }
3207
3208 static void tg3_set_txd(struct tg3 *tp, int entry,
3209                         dma_addr_t mapping, int len, u32 flags,
3210                         u32 mss_and_is_end)
3211 {
3212         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3213         int is_end = (mss_and_is_end & 0x1);
3214         u32 mss = (mss_and_is_end >> 1);
3215         u32 vlan_tag = 0;
3216
3217         if (is_end)
3218                 flags |= TXD_FLAG_END;
3219         if (flags & TXD_FLAG_VLAN) {
3220                 vlan_tag = flags >> 16;
3221                 flags &= 0xffff;
3222         }
3223         vlan_tag |= (mss << TXD_MSS_SHIFT);
3224
3225         txd->addr_hi = ((u64) mapping >> 32);
3226         txd->addr_lo = ((u64) mapping & 0xffffffff);
3227         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3228         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3229 }
3230
3231 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3232 {
3233         u32 base = (u32) mapping & 0xffffffff;
3234
3235         return ((base > 0xffffdcc0) &&
3236                 (base + len + 8 < base));
3237 }
3238
3239 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3240 {
3241         struct tg3 *tp = netdev_priv(dev);
3242         dma_addr_t mapping;
3243         unsigned int i;
3244         u32 len, entry, base_flags, mss;
3245         int would_hit_hwbug;
3246
3247         len = skb_headlen(skb);
3248
3249         /* No BH disabling for tx_lock here.  We are running in BH disabled
3250          * context and TX reclaim runs via tp->poll inside of a software
3251          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3252          * no IRQ context deadlocks to worry about either.  Rejoice!
3253          */
3254         if (!spin_trylock(&tp->tx_lock))
3255                 return NETDEV_TX_LOCKED;
3256
3257         /* This is a hard error, log it. */
3258         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3259                 netif_stop_queue(dev);
3260                 spin_unlock(&tp->tx_lock);
3261                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3262                        dev->name);
3263                 return NETDEV_TX_BUSY;
3264         }
3265
3266         entry = tp->tx_prod;
3267         base_flags = 0;
3268         if (skb->ip_summed == CHECKSUM_HW)
3269                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3270 #if TG3_TSO_SUPPORT != 0
3271         mss = 0;
3272         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3273             (mss = skb_shinfo(skb)->tso_size) != 0) {
3274                 int tcp_opt_len, ip_tcp_len;
3275
3276                 if (skb_header_cloned(skb) &&
3277                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3278                         dev_kfree_skb(skb);
3279                         goto out_unlock;
3280                 }
3281
3282                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3283                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3284
3285                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3286                                TXD_FLAG_CPU_POST_DMA);
3287
3288                 skb->nh.iph->check = 0;
3289                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3290                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3291                         skb->h.th->check = 0;
3292                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3293                 }
3294                 else {
3295                         skb->h.th->check =
3296                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3297                                                    skb->nh.iph->daddr,
3298                                                    0, IPPROTO_TCP, 0);
3299                 }
3300
3301                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3302                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3303                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3304                                 int tsflags;
3305
3306                                 tsflags = ((skb->nh.iph->ihl - 5) +
3307                                            (tcp_opt_len >> 2));
3308                                 mss |= (tsflags << 11);
3309                         }
3310                 } else {
3311                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3312                                 int tsflags;
3313
3314                                 tsflags = ((skb->nh.iph->ihl - 5) +
3315                                            (tcp_opt_len >> 2));
3316                                 base_flags |= tsflags << 12;
3317                         }
3318                 }
3319         }
3320 #else
3321         mss = 0;
3322 #endif
3323 #if TG3_VLAN_TAG_USED
3324         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3325                 base_flags |= (TXD_FLAG_VLAN |
3326                                (vlan_tx_tag_get(skb) << 16));
3327 #endif
3328
3329         /* Queue skb data, a.k.a. the main skb fragment. */
3330         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3331
3332         tp->tx_buffers[entry].skb = skb;
3333         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3334
3335         would_hit_hwbug = 0;
3336
3337         if (tg3_4g_overflow_test(mapping, len))
3338                 would_hit_hwbug = entry + 1;
3339
3340         tg3_set_txd(tp, entry, mapping, len, base_flags,
3341                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3342
3343         entry = NEXT_TX(entry);
3344
3345         /* Now loop through additional data fragments, and queue them. */
3346         if (skb_shinfo(skb)->nr_frags > 0) {
3347                 unsigned int i, last;
3348
3349                 last = skb_shinfo(skb)->nr_frags - 1;
3350                 for (i = 0; i <= last; i++) {
3351                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3352
3353                         len = frag->size;
3354                         mapping = pci_map_page(tp->pdev,
3355                                                frag->page,
3356                                                frag->page_offset,
3357                                                len, PCI_DMA_TODEVICE);
3358
3359                         tp->tx_buffers[entry].skb = NULL;
3360                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3361
3362                         if (tg3_4g_overflow_test(mapping, len)) {
3363                                 /* Only one should match. */
3364                                 if (would_hit_hwbug)
3365                                         BUG();
3366                                 would_hit_hwbug = entry + 1;
3367                         }
3368
3369                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3370                                 tg3_set_txd(tp, entry, mapping, len,
3371                                             base_flags, (i == last)|(mss << 1));
3372                         else
3373                                 tg3_set_txd(tp, entry, mapping, len,
3374                                             base_flags, (i == last));
3375
3376                         entry = NEXT_TX(entry);
3377                 }
3378         }
3379
3380         if (would_hit_hwbug) {
3381                 u32 last_plus_one = entry;
3382                 u32 start;
3383                 unsigned int len = 0;
3384
3385                 would_hit_hwbug -= 1;
3386                 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3387                 entry &= (TG3_TX_RING_SIZE - 1);
3388                 start = entry;
3389                 i = 0;
3390                 while (entry != last_plus_one) {
3391                         if (i == 0)
3392                                 len = skb_headlen(skb);
3393                         else
3394                                 len = skb_shinfo(skb)->frags[i-1].size;
3395
3396                         if (entry == would_hit_hwbug)
3397                                 break;
3398
3399                         i++;
3400                         entry = NEXT_TX(entry);
3401
3402                 }
3403
3404                 /* If the workaround fails due to memory/mapping
3405                  * failure, silently drop this packet.
3406                  */
3407                 if (tigon3_4gb_hwbug_workaround(tp, skb,
3408                                                 entry, len,
3409                                                 last_plus_one,
3410                                                 &start, mss))
3411                         goto out_unlock;
3412
3413                 entry = start;
3414         }
3415
3416         /* Packets are ready, update Tx producer idx local and on card. */
3417         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3418
3419         tp->tx_prod = entry;
3420         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3421                 netif_stop_queue(dev);
3422
3423 out_unlock:
3424         mmiowb();
3425         spin_unlock(&tp->tx_lock);
3426
3427         dev->trans_start = jiffies;
3428
3429         return NETDEV_TX_OK;
3430 }
3431
3432 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3433                                int new_mtu)
3434 {
3435         dev->mtu = new_mtu;
3436
3437         if (new_mtu > ETH_DATA_LEN)
3438                 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3439         else
3440                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3441 }
3442
3443 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3444 {
3445         struct tg3 *tp = netdev_priv(dev);
3446
3447         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3448                 return -EINVAL;
3449
3450         if (!netif_running(dev)) {
3451                 /* We'll just catch it later when the
3452                  * device is up'd.
3453                  */
3454                 tg3_set_mtu(dev, tp, new_mtu);
3455                 return 0;
3456         }
3457
3458         tg3_netif_stop(tp);
3459
3460         tg3_full_lock(tp, 1);
3461
3462         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3463
3464         tg3_set_mtu(dev, tp, new_mtu);
3465
3466         tg3_init_hw(tp);
3467
3468         tg3_netif_start(tp);
3469
3470         tg3_full_unlock(tp);
3471
3472         return 0;
3473 }
3474
3475 /* Free up pending packets in all rx/tx rings.
3476  *
3477  * The chip has been shut down and the driver detached from
3478  * the networking, so no interrupts or new tx packets will
3479  * end up in the driver.  tp->{tx,}lock is not held and we are not
3480  * in an interrupt context and thus may sleep.
3481  */
3482 static void tg3_free_rings(struct tg3 *tp)
3483 {
3484         struct ring_info *rxp;
3485         int i;
3486
3487         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3488                 rxp = &tp->rx_std_buffers[i];
3489
3490                 if (rxp->skb == NULL)
3491                         continue;
3492                 pci_unmap_single(tp->pdev,
3493                                  pci_unmap_addr(rxp, mapping),
3494                                  RX_PKT_BUF_SZ - tp->rx_offset,
3495                                  PCI_DMA_FROMDEVICE);
3496                 dev_kfree_skb_any(rxp->skb);
3497                 rxp->skb = NULL;
3498         }
3499
3500         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3501                 rxp = &tp->rx_jumbo_buffers[i];
3502
3503                 if (rxp->skb == NULL)
3504                         continue;
3505                 pci_unmap_single(tp->pdev,
3506                                  pci_unmap_addr(rxp, mapping),
3507                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3508                                  PCI_DMA_FROMDEVICE);
3509                 dev_kfree_skb_any(rxp->skb);
3510                 rxp->skb = NULL;
3511         }
3512
3513         for (i = 0; i < TG3_TX_RING_SIZE; ) {
3514                 struct tx_ring_info *txp;
3515                 struct sk_buff *skb;
3516                 int j;
3517
3518                 txp = &tp->tx_buffers[i];
3519                 skb = txp->skb;
3520
3521                 if (skb == NULL) {
3522                         i++;
3523                         continue;
3524                 }
3525
3526                 pci_unmap_single(tp->pdev,
3527                                  pci_unmap_addr(txp, mapping),
3528                                  skb_headlen(skb),
3529                                  PCI_DMA_TODEVICE);
3530                 txp->skb = NULL;
3531
3532                 i++;
3533
3534                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3535                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3536                         pci_unmap_page(tp->pdev,
3537                                        pci_unmap_addr(txp, mapping),
3538                                        skb_shinfo(skb)->frags[j].size,
3539                                        PCI_DMA_TODEVICE);
3540                         i++;
3541                 }
3542
3543                 dev_kfree_skb_any(skb);
3544         }
3545 }
3546
3547 /* Initialize tx/rx rings for packet processing.
3548  *
3549  * The chip has been shut down and the driver detached from
3550  * the networking, so no interrupts or new tx packets will
3551  * end up in the driver.  tp->{tx,}lock are held and thus
3552  * we may not sleep.
3553  */
3554 static void tg3_init_rings(struct tg3 *tp)
3555 {
3556         u32 i;
3557
3558         /* Free up all the SKBs. */
3559         tg3_free_rings(tp);
3560
3561         /* Zero out all descriptors. */
3562         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3563         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3564         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3565         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3566
3567         /* Initialize invariants of the rings, we only set this
3568          * stuff once.  This works because the card does not
3569          * write into the rx buffer posting rings.
3570          */
3571         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3572                 struct tg3_rx_buffer_desc *rxd;
3573
3574                 rxd = &tp->rx_std[i];
3575                 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3576                         << RXD_LEN_SHIFT;
3577                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3578                 rxd->opaque = (RXD_OPAQUE_RING_STD |
3579                                (i << RXD_OPAQUE_INDEX_SHIFT));
3580         }
3581
3582         if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3583                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3584                         struct tg3_rx_buffer_desc *rxd;
3585
3586                         rxd = &tp->rx_jumbo[i];
3587                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3588                                 << RXD_LEN_SHIFT;
3589                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3590                                 RXD_FLAG_JUMBO;
3591                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3592                                (i << RXD_OPAQUE_INDEX_SHIFT));
3593                 }
3594         }
3595
3596         /* Now allocate fresh SKBs for each rx ring. */
3597         for (i = 0; i < tp->rx_pending; i++) {
3598                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3599                                      -1, i) < 0)
3600                         break;
3601         }
3602
3603         if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3604                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3605                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3606                                              -1, i) < 0)
3607                                 break;
3608                 }
3609         }
3610 }
3611
3612 /*
3613  * Must not be invoked with interrupt sources disabled and
3614  * the hardware shutdown down.
3615  */
3616 static void tg3_free_consistent(struct tg3 *tp)
3617 {
3618         if (tp->rx_std_buffers) {
3619                 kfree(tp->rx_std_buffers);
3620                 tp->rx_std_buffers = NULL;
3621         }
3622         if (tp->rx_std) {
3623                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3624                                     tp->rx_std, tp->rx_std_mapping);
3625                 tp->rx_std = NULL;
3626         }
3627         if (tp->rx_jumbo) {
3628                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3629                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
3630                 tp->rx_jumbo = NULL;
3631         }
3632         if (tp->rx_rcb) {
3633                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3634                                     tp->rx_rcb, tp->rx_rcb_mapping);
3635                 tp->rx_rcb = NULL;
3636         }
3637         if (tp->tx_ring) {
3638                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3639                         tp->tx_ring, tp->tx_desc_mapping);
3640                 tp->tx_ring = NULL;
3641         }
3642         if (tp->hw_status) {
3643                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3644                                     tp->hw_status, tp->status_mapping);
3645                 tp->hw_status = NULL;
3646         }
3647         if (tp->hw_stats) {
3648                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3649                                     tp->hw_stats, tp->stats_mapping);
3650                 tp->hw_stats = NULL;
3651         }
3652 }
3653
3654 /*
3655  * Must not be invoked with interrupt sources disabled and
3656  * the hardware shutdown down.  Can sleep.
3657  */
3658 static int tg3_alloc_consistent(struct tg3 *tp)
3659 {
3660         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3661                                       (TG3_RX_RING_SIZE +
3662                                        TG3_RX_JUMBO_RING_SIZE)) +
3663                                      (sizeof(struct tx_ring_info) *
3664                                       TG3_TX_RING_SIZE),
3665                                      GFP_KERNEL);
3666         if (!tp->rx_std_buffers)
3667                 return -ENOMEM;
3668
3669         memset(tp->rx_std_buffers, 0,
3670                (sizeof(struct ring_info) *
3671                 (TG3_RX_RING_SIZE +
3672                  TG3_RX_JUMBO_RING_SIZE)) +
3673                (sizeof(struct tx_ring_info) *
3674                 TG3_TX_RING_SIZE));
3675
3676         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3677         tp->tx_buffers = (struct tx_ring_info *)
3678                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3679
3680         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3681                                           &tp->rx_std_mapping);
3682         if (!tp->rx_std)
3683                 goto err_out;
3684
3685         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3686                                             &tp->rx_jumbo_mapping);
3687
3688         if (!tp->rx_jumbo)
3689                 goto err_out;
3690
3691         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3692                                           &tp->rx_rcb_mapping);
3693         if (!tp->rx_rcb)
3694                 goto err_out;
3695
3696         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3697                                            &tp->tx_desc_mapping);
3698         if (!tp->tx_ring)
3699                 goto err_out;
3700
3701         tp->hw_status = pci_alloc_consistent(tp->pdev,
3702                                              TG3_HW_STATUS_SIZE,
3703                                              &tp->status_mapping);
3704         if (!tp->hw_status)
3705                 goto err_out;
3706
3707         tp->hw_stats = pci_alloc_consistent(tp->pdev,
3708                                             sizeof(struct tg3_hw_stats),
3709                                             &tp->stats_mapping);
3710         if (!tp->hw_stats)
3711                 goto err_out;
3712
3713         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3714         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3715
3716         return 0;
3717
3718 err_out:
3719         tg3_free_consistent(tp);
3720         return -ENOMEM;
3721 }
3722
3723 #define MAX_WAIT_CNT 1000
3724
3725 /* To stop a block, clear the enable bit and poll till it
3726  * clears.  tp->lock is held.
3727  */
3728 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
3729 {
3730         unsigned int i;
3731         u32 val;
3732
3733         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3734                 switch (ofs) {
3735                 case RCVLSC_MODE:
3736                 case DMAC_MODE:
3737                 case MBFREE_MODE:
3738                 case BUFMGR_MODE:
3739                 case MEMARB_MODE:
3740                         /* We can't enable/disable these bits of the
3741                          * 5705/5750, just say success.
3742                          */
3743                         return 0;
3744
3745                 default:
3746                         break;
3747                 };
3748         }
3749
3750         val = tr32(ofs);
3751         val &= ~enable_bit;
3752         tw32_f(ofs, val);
3753
3754         for (i = 0; i < MAX_WAIT_CNT; i++) {
3755                 udelay(100);
3756                 val = tr32(ofs);
3757                 if ((val & enable_bit) == 0)
3758                         break;
3759         }
3760
3761         if (i == MAX_WAIT_CNT && !silent) {
3762                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3763                        "ofs=%lx enable_bit=%x\n",
3764                        ofs, enable_bit);
3765                 return -ENODEV;
3766         }
3767
3768         return 0;
3769 }
3770
3771 /* tp->lock is held. */
3772 static int tg3_abort_hw(struct tg3 *tp, int silent)
3773 {
3774         int i, err;
3775
3776         tg3_disable_ints(tp);
3777
3778         tp->rx_mode &= ~RX_MODE_ENABLE;
3779         tw32_f(MAC_RX_MODE, tp->rx_mode);
3780         udelay(10);
3781
3782         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
3783         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
3784         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
3785         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
3786         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
3787         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
3788
3789         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
3790         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
3791         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
3792         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
3793         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
3794         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
3795         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
3796
3797         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3798         tw32_f(MAC_MODE, tp->mac_mode);
3799         udelay(40);
3800
3801         tp->tx_mode &= ~TX_MODE_ENABLE;
3802         tw32_f(MAC_TX_MODE, tp->tx_mode);
3803
3804         for (i = 0; i < MAX_WAIT_CNT; i++) {
3805                 udelay(100);
3806                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3807                         break;
3808         }
3809         if (i >= MAX_WAIT_CNT) {
3810                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3811                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3812                        tp->dev->name, tr32(MAC_TX_MODE));
3813                 err |= -ENODEV;
3814         }
3815
3816         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
3817         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
3818         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
3819
3820         tw32(FTQ_RESET, 0xffffffff);
3821         tw32(FTQ_RESET, 0x00000000);
3822
3823         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
3824         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
3825
3826         if (tp->hw_status)
3827                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3828         if (tp->hw_stats)
3829                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3830
3831         return err;
3832 }
3833
3834 /* tp->lock is held. */
3835 static int tg3_nvram_lock(struct tg3 *tp)
3836 {
3837         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3838                 int i;
3839
3840                 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3841                 for (i = 0; i < 8000; i++) {
3842                         if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3843                                 break;
3844                         udelay(20);
3845                 }
3846                 if (i == 8000)
3847                         return -ENODEV;
3848         }
3849         return 0;
3850 }
3851
3852 /* tp->lock is held. */
3853 static void tg3_nvram_unlock(struct tg3 *tp)
3854 {
3855         if (tp->tg3_flags & TG3_FLAG_NVRAM)
3856                 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3857 }
3858
3859 /* tp->lock is held. */
3860 static void tg3_enable_nvram_access(struct tg3 *tp)
3861 {
3862         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3863             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3864                 u32 nvaccess = tr32(NVRAM_ACCESS);
3865
3866                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3867         }
3868 }
3869
3870 /* tp->lock is held. */
3871 static void tg3_disable_nvram_access(struct tg3 *tp)
3872 {
3873         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3874             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3875                 u32 nvaccess = tr32(NVRAM_ACCESS);
3876
3877                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3878         }
3879 }
3880
3881 /* tp->lock is held. */
3882 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3883 {
3884         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3885                 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3886                               NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3887
3888         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3889                 switch (kind) {
3890                 case RESET_KIND_INIT:
3891                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3892                                       DRV_STATE_START);
3893                         break;
3894
3895                 case RESET_KIND_SHUTDOWN:
3896                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3897                                       DRV_STATE_UNLOAD);
3898                         break;
3899
3900                 case RESET_KIND_SUSPEND:
3901                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3902                                       DRV_STATE_SUSPEND);
3903                         break;
3904
3905                 default:
3906                         break;
3907                 };
3908         }
3909 }
3910
3911 /* tp->lock is held. */
3912 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3913 {
3914         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3915                 switch (kind) {
3916                 case RESET_KIND_INIT:
3917                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3918                                       DRV_STATE_START_DONE);
3919                         break;
3920
3921                 case RESET_KIND_SHUTDOWN:
3922                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3923                                       DRV_STATE_UNLOAD_DONE);
3924                         break;
3925
3926                 default:
3927                         break;
3928                 };
3929         }
3930 }
3931
3932 /* tp->lock is held. */
3933 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3934 {
3935         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3936                 switch (kind) {
3937                 case RESET_KIND_INIT:
3938                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3939                                       DRV_STATE_START);
3940                         break;
3941
3942                 case RESET_KIND_SHUTDOWN:
3943                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3944                                       DRV_STATE_UNLOAD);
3945                         break;
3946
3947                 case RESET_KIND_SUSPEND:
3948                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3949                                       DRV_STATE_SUSPEND);
3950                         break;
3951
3952                 default:
3953                         break;
3954                 };
3955         }
3956 }
3957
3958 static void tg3_stop_fw(struct tg3 *);
3959
3960 /* tp->lock is held. */
3961 static int tg3_chip_reset(struct tg3 *tp)
3962 {
3963         u32 val;
3964         u32 flags_save;
3965         int i;
3966
3967         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3968                 tg3_nvram_lock(tp);
3969
3970         /*
3971          * We must avoid the readl() that normally takes place.
3972          * It locks machines, causes machine checks, and other
3973          * fun things.  So, temporarily disable the 5701
3974          * hardware workaround, while we do the reset.
3975          */
3976         flags_save = tp->tg3_flags;
3977         tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3978
3979         /* do the reset */
3980         val = GRC_MISC_CFG_CORECLK_RESET;
3981
3982         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3983                 if (tr32(0x7e2c) == 0x60) {
3984                         tw32(0x7e2c, 0x20);
3985                 }
3986                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3987                         tw32(GRC_MISC_CFG, (1 << 29));
3988                         val |= (1 << 29);
3989                 }
3990         }
3991
3992         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3993                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3994         tw32(GRC_MISC_CFG, val);
3995
3996         /* restore 5701 hardware bug workaround flag */
3997         tp->tg3_flags = flags_save;
3998
3999         /* Unfortunately, we have to delay before the PCI read back.
4000          * Some 575X chips even will not respond to a PCI cfg access
4001          * when the reset command is given to the chip.
4002          *
4003          * How do these hardware designers expect things to work
4004          * properly if the PCI write is posted for a long period
4005          * of time?  It is always necessary to have some method by
4006          * which a register read back can occur to push the write
4007          * out which does the reset.
4008          *
4009          * For most tg3 variants the trick below was working.
4010          * Ho hum...
4011          */
4012         udelay(120);
4013
4014         /* Flush PCI posted writes.  The normal MMIO registers
4015          * are inaccessible at this time so this is the only
4016          * way to make this reliably (actually, this is no longer
4017          * the case, see above).  I tried to use indirect
4018          * register read/write but this upset some 5701 variants.
4019          */
4020         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4021
4022         udelay(120);
4023
4024         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4025                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4026                         int i;
4027                         u32 cfg_val;
4028
4029                         /* Wait for link training to complete.  */
4030                         for (i = 0; i < 5000; i++)
4031                                 udelay(100);
4032
4033                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4034                         pci_write_config_dword(tp->pdev, 0xc4,
4035                                                cfg_val | (1 << 15));
4036                 }
4037                 /* Set PCIE max payload size and clear error status.  */
4038                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4039         }
4040
4041         /* Re-enable indirect register accesses. */
4042         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4043                                tp->misc_host_ctrl);
4044
4045         /* Set MAX PCI retry to zero. */
4046         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4047         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4048             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4049                 val |= PCISTATE_RETRY_SAME_DMA;
4050         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4051
4052         pci_restore_state(tp->pdev);
4053
4054         /* Make sure PCI-X relaxed ordering bit is clear. */
4055         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4056         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4057         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4058
4059         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4060
4061         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4062                 tg3_stop_fw(tp);
4063                 tw32(0x5000, 0x400);
4064         }
4065
4066         tw32(GRC_MODE, tp->grc_mode);
4067
4068         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4069                 u32 val = tr32(0xc4);
4070
4071                 tw32(0xc4, val | (1 << 15));
4072         }
4073
4074         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4075             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4076                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4077                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4078                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4079                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4080         }
4081
4082         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4083                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4084                 tw32_f(MAC_MODE, tp->mac_mode);
4085         } else
4086                 tw32_f(MAC_MODE, 0);
4087         udelay(40);
4088
4089         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4090                 /* Wait for firmware initialization to complete. */
4091                 for (i = 0; i < 100000; i++) {
4092                         tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4093                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4094                                 break;
4095                         udelay(10);
4096                 }
4097                 if (i >= 100000) {
4098                         printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4099                                "firmware will not restart magic=%08x\n",
4100                                tp->dev->name, val);
4101                         return -ENODEV;
4102                 }
4103         }
4104
4105         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4106             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4107                 u32 val = tr32(0x7c00);
4108
4109                 tw32(0x7c00, val | (1 << 25));
4110         }
4111
4112         /* Reprobe ASF enable state.  */
4113         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4114         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4115         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4116         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4117                 u32 nic_cfg;
4118
4119                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4120                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4121                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4122                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4123                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4124                 }
4125         }
4126
4127         return 0;
4128 }
4129
4130 /* tp->lock is held. */
4131 static void tg3_stop_fw(struct tg3 *tp)
4132 {
4133         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4134                 u32 val;
4135                 int i;
4136
4137                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4138                 val = tr32(GRC_RX_CPU_EVENT);
4139                 val |= (1 << 14);
4140                 tw32(GRC_RX_CPU_EVENT, val);
4141
4142                 /* Wait for RX cpu to ACK the event.  */
4143                 for (i = 0; i < 100; i++) {
4144                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4145                                 break;
4146                         udelay(1);
4147                 }
4148         }
4149 }
4150
4151 /* tp->lock is held. */
4152 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4153 {
4154         int err;
4155
4156         tg3_stop_fw(tp);
4157
4158         tg3_write_sig_pre_reset(tp, kind);
4159
4160         tg3_abort_hw(tp, silent);
4161         err = tg3_chip_reset(tp);
4162
4163         tg3_write_sig_legacy(tp, kind);
4164         tg3_write_sig_post_reset(tp, kind);
4165
4166         if (err)
4167                 return err;
4168
4169         return 0;
4170 }
4171
4172 #define TG3_FW_RELEASE_MAJOR    0x0
4173 #define TG3_FW_RELASE_MINOR     0x0
4174 #define TG3_FW_RELEASE_FIX      0x0
4175 #define TG3_FW_START_ADDR       0x08000000
4176 #define TG3_FW_TEXT_ADDR        0x08000000
4177 #define TG3_FW_TEXT_LEN         0x9c0
4178 #define TG3_FW_RODATA_ADDR      0x080009c0
4179 #define TG3_FW_RODATA_LEN       0x60
4180 #define TG3_FW_DATA_ADDR        0x08000a40
4181 #define TG3_FW_DATA_LEN         0x20
4182 #define TG3_FW_SBSS_ADDR        0x08000a60
4183 #define TG3_FW_SBSS_LEN         0xc
4184 #define TG3_FW_BSS_ADDR         0x08000a70
4185 #define TG3_FW_BSS_LEN          0x10
4186
4187 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4188         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4189         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4190         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4191         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4192         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4193         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4194         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4195         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4196         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4197         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4198         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4199         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4200         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4201         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4202         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4203         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4204         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4205         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4206         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4207         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4208         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4209         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4210         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4211         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4212         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4213         0, 0, 0, 0, 0, 0,
4214         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4215         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4216         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4217         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4218         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4219         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4220         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4221         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4222         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4223         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4224         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4225         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4226         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4227         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4228         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4229         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4230         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4231         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4232         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4233         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4234         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4235         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4236         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4237         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4238         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4239         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4240         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4241         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4242         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4243         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4244         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4245         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4246         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4247         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4248         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4249         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4250         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4251         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4252         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4253         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4254         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4255         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4256         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4257         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4258         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4259         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4260         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4261         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4262         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4263         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4264         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4265         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4266         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4267         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4268         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4269         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4270         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4271         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4272         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4273         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4274         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4275         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4276         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4277         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4278         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4279 };
4280
4281 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4282         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4283         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4284         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4285         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4286         0x00000000
4287 };
4288
4289 #if 0 /* All zeros, don't eat up space with it. */
4290 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4291         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4292         0x00000000, 0x00000000, 0x00000000, 0x00000000
4293 };
4294 #endif
4295
4296 #define RX_CPU_SCRATCH_BASE     0x30000
4297 #define RX_CPU_SCRATCH_SIZE     0x04000
4298 #define TX_CPU_SCRATCH_BASE     0x34000
4299 #define TX_CPU_SCRATCH_SIZE     0x04000
4300
4301 /* tp->lock is held. */
4302 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4303 {
4304         int i;
4305
4306         if (offset == TX_CPU_BASE &&
4307             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4308                 BUG();
4309
4310         if (offset == RX_CPU_BASE) {
4311                 for (i = 0; i < 10000; i++) {
4312                         tw32(offset + CPU_STATE, 0xffffffff);
4313                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4314                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4315                                 break;
4316                 }
4317
4318                 tw32(offset + CPU_STATE, 0xffffffff);
4319                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4320                 udelay(10);
4321         } else {
4322                 for (i = 0; i < 10000; i++) {
4323                         tw32(offset + CPU_STATE, 0xffffffff);
4324                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4325                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4326                                 break;
4327                 }
4328         }
4329
4330         if (i >= 10000) {
4331                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4332                        "and %s CPU\n",
4333                        tp->dev->name,
4334                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4335                 return -ENODEV;
4336         }
4337         return 0;
4338 }
4339
4340 struct fw_info {
4341         unsigned int text_base;
4342         unsigned int text_len;
4343         u32 *text_data;
4344         unsigned int rodata_base;
4345         unsigned int rodata_len;
4346         u32 *rodata_data;
4347         unsigned int data_base;
4348         unsigned int data_len;
4349         u32 *data_data;
4350 };
4351
4352 /* tp->lock is held. */
4353 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4354                                  int cpu_scratch_size, struct fw_info *info)
4355 {
4356         int err, i;
4357         u32 orig_tg3_flags = tp->tg3_flags;
4358         void (*write_op)(struct tg3 *, u32, u32);
4359
4360         if (cpu_base == TX_CPU_BASE &&
4361             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4362                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4363                        "TX cpu firmware on %s which is 5705.\n",
4364                        tp->dev->name);
4365                 return -EINVAL;
4366         }
4367
4368         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4369                 write_op = tg3_write_mem;
4370         else
4371                 write_op = tg3_write_indirect_reg32;
4372
4373         /* Force use of PCI config space for indirect register
4374          * write calls.
4375          */
4376         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4377
4378         /* It is possible that bootcode is still loading at this point.
4379          * Get the nvram lock first before halting the cpu.
4380          */
4381         tg3_nvram_lock(tp);
4382         err = tg3_halt_cpu(tp, cpu_base);
4383         tg3_nvram_unlock(tp);
4384         if (err)
4385                 goto out;
4386
4387         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4388                 write_op(tp, cpu_scratch_base + i, 0);
4389         tw32(cpu_base + CPU_STATE, 0xffffffff);
4390         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4391         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4392                 write_op(tp, (cpu_scratch_base +
4393                               (info->text_base & 0xffff) +
4394                               (i * sizeof(u32))),
4395                          (info->text_data ?
4396                           info->text_data[i] : 0));
4397         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4398                 write_op(tp, (cpu_scratch_base +
4399                               (info->rodata_base & 0xffff) +
4400                               (i * sizeof(u32))),
4401                          (info->rodata_data ?
4402                           info->rodata_data[i] : 0));
4403         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4404                 write_op(tp, (cpu_scratch_base +
4405                               (info->data_base & 0xffff) +
4406                               (i * sizeof(u32))),
4407                          (info->data_data ?
4408                           info->data_data[i] : 0));
4409
4410         err = 0;
4411
4412 out:
4413         tp->tg3_flags = orig_tg3_flags;
4414         return err;
4415 }
4416
4417 /* tp->lock is held. */
4418 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4419 {
4420         struct fw_info info;
4421         int err, i;
4422
4423         info.text_base = TG3_FW_TEXT_ADDR;
4424         info.text_len = TG3_FW_TEXT_LEN;
4425         info.text_data = &tg3FwText[0];
4426         info.rodata_base = TG3_FW_RODATA_ADDR;
4427         info.rodata_len = TG3_FW_RODATA_LEN;
4428         info.rodata_data = &tg3FwRodata[0];
4429         info.data_base = TG3_FW_DATA_ADDR;
4430         info.data_len = TG3_FW_DATA_LEN;
4431         info.data_data = NULL;
4432
4433         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4434                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4435                                     &info);
4436         if (err)
4437                 return err;
4438
4439         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4440                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4441                                     &info);
4442         if (err)
4443                 return err;
4444
4445         /* Now startup only the RX cpu. */
4446         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4447         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4448
4449         for (i = 0; i < 5; i++) {
4450                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4451                         break;
4452                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4453                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
4454                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4455                 udelay(1000);
4456         }
4457         if (i >= 5) {
4458                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4459                        "to set RX CPU PC, is %08x should be %08x\n",
4460                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4461                        TG3_FW_TEXT_ADDR);
4462                 return -ENODEV;
4463         }
4464         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4465         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
4466
4467         return 0;
4468 }
4469
4470 #if TG3_TSO_SUPPORT != 0
4471
4472 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
4473 #define TG3_TSO_FW_RELASE_MINOR         0x6
4474 #define TG3_TSO_FW_RELEASE_FIX          0x0
4475 #define TG3_TSO_FW_START_ADDR           0x08000000
4476 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
4477 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
4478 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
4479 #define TG3_TSO_FW_RODATA_LEN           0x60
4480 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
4481 #define TG3_TSO_FW_DATA_LEN             0x30
4482 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
4483 #define TG3_TSO_FW_SBSS_LEN             0x2c
4484 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
4485 #define TG3_TSO_FW_BSS_LEN              0x894
4486
4487 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4488         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4489         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4490         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4491         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4492         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4493         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4494         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4495         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4496         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4497         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4498         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4499         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4500         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4501         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4502         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4503         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4504         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4505         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4506         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4507         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4508         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4509         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4510         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4511         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4512         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4513         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4514         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4515         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4516         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4517         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4518         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4519         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4520         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4521         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4522         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4523         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4524         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4525         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4526         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4527         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4528         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4529         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4530         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4531         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4532         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4533         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4534         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4535         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4536         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4537         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4538         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4539         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4540         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4541         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4542         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4543         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4544         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4545         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4546         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4547         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4548         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4549         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4550         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4551         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4552         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4553         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4554         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4555         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4556         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4557         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4558         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4559         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4560         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4561         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4562         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4563         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4564         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4565         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4566         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4567         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4568         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4569         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4570         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4571         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4572         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4573         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4574         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4575         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4576         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4577         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4578         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4579         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4580         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4581         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4582         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4583         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4584         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4585         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4586         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4587         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4588         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4589         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4590         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4591         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4592         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4593         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4594         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4595         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4596         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4597         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4598         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4599         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4600         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4601         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4602         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4603         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4604         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4605         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4606         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4607         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4608         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4609         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4610         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4611         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4612         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4613         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4614         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4615         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4616         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4617         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4618         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4619         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4620         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4621         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4622         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4623         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4624         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4625         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4626         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4627         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4628         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4629         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4630         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4631         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4632         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4633         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4634         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4635         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4636         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4637         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4638         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4639         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4640         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4641         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4642         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4643         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4644         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4645         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4646         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4647         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4648         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4649         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4650         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4651         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4652         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4653         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4654         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4655         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4656         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4657         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4658         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4659         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4660         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4661         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4662         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4663         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4664         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4665         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4666         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4667         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4668         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4669         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4670         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4671         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4672         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4673         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4674         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4675         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4676         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4677         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4678         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4679         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4680         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4681         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4682         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4683         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4684         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4685         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4686         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4687         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4688         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4689         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4690         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4691         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4692         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4693         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4694         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4695         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4696         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4697         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4698         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4699         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4700         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4701         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4702         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4703         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4704         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4705         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4706         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4707         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4708         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4709         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4710         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4711         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4712         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4713         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4714         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4715         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4716         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4717         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4718         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4719         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4720         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4721         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4722         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4723         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4724         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4725         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4726         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4727         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4728         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4729         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4730         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4731         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4732         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4733         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4734         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4735         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4736         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4737         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4738         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4739         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4740         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4741         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4742         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4743         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4744         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4745         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4746         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4747         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4748         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4749         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4750         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4751         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4752         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4753         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4754         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4755         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4756         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4757         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4758         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4759         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4760         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4761         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4762         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4763         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4764         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4765         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4766         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4767         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4768         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4769         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4770         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4771         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4772 };
4773
4774 static u32 tg3TsoFwRodata[] = {
4775         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4776         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4777         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4778         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4779         0x00000000,
4780 };
4781
4782 static u32 tg3TsoFwData[] = {
4783         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4784         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4785         0x00000000,
4786 };
4787
4788 /* 5705 needs a special version of the TSO firmware.  */
4789 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
4790 #define TG3_TSO5_FW_RELASE_MINOR        0x2
4791 #define TG3_TSO5_FW_RELEASE_FIX         0x0
4792 #define TG3_TSO5_FW_START_ADDR          0x00010000
4793 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
4794 #define TG3_TSO5_FW_TEXT_LEN            0xe90
4795 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
4796 #define TG3_TSO5_FW_RODATA_LEN          0x50
4797 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
4798 #define TG3_TSO5_FW_DATA_LEN            0x20
4799 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
4800 #define TG3_TSO5_FW_SBSS_LEN            0x28
4801 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
4802 #define TG3_TSO5_FW_BSS_LEN             0x88
4803
4804 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4805         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4806         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4807         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4808         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4809         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4810         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4811         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4812         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4813         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4814         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4815         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4816         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4817         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4818         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4819         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4820         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4821         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4822         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4823         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4824         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4825         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4826         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4827         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4828         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4829         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4830         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4831         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4832         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4833         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4834         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4835         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4836         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4837         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4838         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4839         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4840         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4841         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4842         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4843         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4844         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4845         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4846         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4847         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4848         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4849         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4850         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4851         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4852         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4853         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4854         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4855         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4856         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4857         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4858         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4859         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4860         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4861         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4862         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4863         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4864         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4865         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4866         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4867         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4868         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4869         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4870         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4871         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4872         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4873         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4874         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4875         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4876         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4877         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4878         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4879         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4880         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4881         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4882         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4883         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4884         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4885         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4886         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4887         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4888         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4889         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4890         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4891         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4892         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4893         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4894         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4895         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4896         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4897         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4898         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4899         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4900         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4901         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4902         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4903         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4904         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4905         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4906         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4907         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4908         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4909         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4910         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4911         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4912         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4913         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4914         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4915         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4916         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4917         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4918         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4919         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4920         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4921         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4922         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4923         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4924         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4925         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4926         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4927         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4928         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4929         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4930         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4931         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4932         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4933         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4934         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4935         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4936         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4937         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4938         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4939         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4940         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4941         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4942         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4943         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4944         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4945         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4946         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4947         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4948         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4949         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4950         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4951         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4952         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4953         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4954         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4955         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4956         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4957         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4958         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4959         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4960         0x00000000, 0x00000000, 0x00000000,
4961 };
4962
4963 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4964         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4965         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4966         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4967         0x00000000, 0x00000000, 0x00000000,
4968 };
4969
4970 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4971         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4972         0x00000000, 0x00000000, 0x00000000,
4973 };
4974
4975 /* tp->lock is held. */
4976 static int tg3_load_tso_firmware(struct tg3 *tp)
4977 {
4978         struct fw_info info;
4979         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4980         int err, i;
4981
4982         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4983                 return 0;
4984
4985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4986                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4987                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4988                 info.text_data = &tg3Tso5FwText[0];
4989                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4990                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4991                 info.rodata_data = &tg3Tso5FwRodata[0];
4992                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4993                 info.data_len = TG3_TSO5_FW_DATA_LEN;
4994                 info.data_data = &tg3Tso5FwData[0];
4995                 cpu_base = RX_CPU_BASE;
4996                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4997                 cpu_scratch_size = (info.text_len +
4998                                     info.rodata_len +
4999                                     info.data_len +
5000                                     TG3_TSO5_FW_SBSS_LEN +
5001                                     TG3_TSO5_FW_BSS_LEN);
5002         } else {
5003                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5004                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5005                 info.text_data = &tg3TsoFwText[0];
5006                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5007                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5008                 info.rodata_data = &tg3TsoFwRodata[0];
5009                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5010                 info.data_len = TG3_TSO_FW_DATA_LEN;
5011                 info.data_data = &tg3TsoFwData[0];
5012                 cpu_base = TX_CPU_BASE;
5013                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5014                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5015         }
5016
5017         err = tg3_load_firmware_cpu(tp, cpu_base,
5018                                     cpu_scratch_base, cpu_scratch_size,
5019                                     &info);
5020         if (err)
5021                 return err;
5022
5023         /* Now startup the cpu. */
5024         tw32(cpu_base + CPU_STATE, 0xffffffff);
5025         tw32_f(cpu_base + CPU_PC,    info.text_base);
5026
5027         for (i = 0; i < 5; i++) {
5028                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5029                         break;
5030                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5031                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5032                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5033                 udelay(1000);
5034         }
5035         if (i >= 5) {
5036                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5037                        "to set CPU PC, is %08x should be %08x\n",
5038                        tp->dev->name, tr32(cpu_base + CPU_PC),
5039                        info.text_base);
5040                 return -ENODEV;
5041         }
5042         tw32(cpu_base + CPU_STATE, 0xffffffff);
5043         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5044         return 0;
5045 }
5046
5047 #endif /* TG3_TSO_SUPPORT != 0 */
5048
5049 /* tp->lock is held. */
5050 static void __tg3_set_mac_addr(struct tg3 *tp)
5051 {
5052         u32 addr_high, addr_low;
5053         int i;
5054
5055         addr_high = ((tp->dev->dev_addr[0] << 8) |
5056                      tp->dev->dev_addr[1]);
5057         addr_low = ((tp->dev->dev_addr[2] << 24) |
5058                     (tp->dev->dev_addr[3] << 16) |
5059                     (tp->dev->dev_addr[4] <<  8) |
5060                     (tp->dev->dev_addr[5] <<  0));
5061         for (i = 0; i < 4; i++) {
5062                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5063                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5064         }
5065
5066         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5068                 for (i = 0; i < 12; i++) {
5069                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5070                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5071                 }
5072         }
5073
5074         addr_high = (tp->dev->dev_addr[0] +
5075                      tp->dev->dev_addr[1] +
5076                      tp->dev->dev_addr[2] +
5077                      tp->dev->dev_addr[3] +
5078                      tp->dev->dev_addr[4] +
5079                      tp->dev->dev_addr[5]) &
5080                 TX_BACKOFF_SEED_MASK;
5081         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5082 }
5083
5084 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5085 {
5086         struct tg3 *tp = netdev_priv(dev);
5087         struct sockaddr *addr = p;
5088
5089         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5090
5091         spin_lock_bh(&tp->lock);
5092         __tg3_set_mac_addr(tp);
5093         spin_unlock_bh(&tp->lock);
5094
5095         return 0;
5096 }
5097
5098 /* tp->lock is held. */
5099 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5100                            dma_addr_t mapping, u32 maxlen_flags,
5101                            u32 nic_addr)
5102 {
5103         tg3_write_mem(tp,
5104                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5105                       ((u64) mapping >> 32));
5106         tg3_write_mem(tp,
5107                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5108                       ((u64) mapping & 0xffffffff));
5109         tg3_write_mem(tp,
5110                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5111                        maxlen_flags);
5112
5113         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5114                 tg3_write_mem(tp,
5115                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5116                               nic_addr);
5117 }
5118
5119 static void __tg3_set_rx_mode(struct net_device *);
5120 static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5121 {
5122         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5123         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5124         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5125         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5126         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5127                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5128                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5129         }
5130         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5131         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5132         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5133                 u32 val = ec->stats_block_coalesce_usecs;
5134
5135                 if (!netif_carrier_ok(tp->dev))
5136                         val = 0;
5137
5138                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5139         }
5140 }
5141
5142 /* tp->lock is held. */
5143 static int tg3_reset_hw(struct tg3 *tp)
5144 {
5145         u32 val, rdmac_mode;
5146         int i, err, limit;
5147
5148         tg3_disable_ints(tp);
5149
5150         tg3_stop_fw(tp);
5151
5152         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5153
5154         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5155                 tg3_abort_hw(tp, 1);
5156         }
5157
5158         err = tg3_chip_reset(tp);
5159         if (err)
5160                 return err;
5161
5162         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5163
5164         /* This works around an issue with Athlon chipsets on
5165          * B3 tigon3 silicon.  This bit has no effect on any
5166          * other revision.  But do not set this on PCI Express
5167          * chips.
5168          */
5169         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5170                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5171         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5172
5173         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5174             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5175                 val = tr32(TG3PCI_PCISTATE);
5176                 val |= PCISTATE_RETRY_SAME_DMA;
5177                 tw32(TG3PCI_PCISTATE, val);
5178         }
5179
5180         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5181                 /* Enable some hw fixes.  */
5182                 val = tr32(TG3PCI_MSI_DATA);
5183                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5184                 tw32(TG3PCI_MSI_DATA, val);
5185         }
5186
5187         /* Descriptor ring init may make accesses to the
5188          * NIC SRAM area to setup the TX descriptors, so we
5189          * can only do this after the hardware has been
5190          * successfully reset.
5191          */
5192         tg3_init_rings(tp);
5193
5194         /* This value is determined during the probe time DMA
5195          * engine test, tg3_test_dma.
5196          */
5197         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5198
5199         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5200                           GRC_MODE_4X_NIC_SEND_RINGS |
5201                           GRC_MODE_NO_TX_PHDR_CSUM |
5202                           GRC_MODE_NO_RX_PHDR_CSUM);
5203         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5204         if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5205                 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5206         if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5207                 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5208
5209         tw32(GRC_MODE,
5210              tp->grc_mode |
5211              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5212
5213         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5214         val = tr32(GRC_MISC_CFG);
5215         val &= ~0xff;
5216         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5217         tw32(GRC_MISC_CFG, val);
5218
5219         /* Initialize MBUF/DESC pool. */
5220         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5221                 /* Do nothing.  */
5222         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5223                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5224                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5225                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5226                 else
5227                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5228                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5229                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5230         }
5231 #if TG3_TSO_SUPPORT != 0
5232         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5233                 int fw_len;
5234
5235                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5236                           TG3_TSO5_FW_RODATA_LEN +
5237                           TG3_TSO5_FW_DATA_LEN +
5238                           TG3_TSO5_FW_SBSS_LEN +
5239                           TG3_TSO5_FW_BSS_LEN);
5240                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5241                 tw32(BUFMGR_MB_POOL_ADDR,
5242                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5243                 tw32(BUFMGR_MB_POOL_SIZE,
5244                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5245         }
5246 #endif
5247
5248         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5249                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5250                      tp->bufmgr_config.mbuf_read_dma_low_water);
5251                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5252                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5253                 tw32(BUFMGR_MB_HIGH_WATER,
5254                      tp->bufmgr_config.mbuf_high_water);
5255         } else {
5256                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5257                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5258                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5259                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5260                 tw32(BUFMGR_MB_HIGH_WATER,
5261                      tp->bufmgr_config.mbuf_high_water_jumbo);
5262         }
5263         tw32(BUFMGR_DMA_LOW_WATER,
5264              tp->bufmgr_config.dma_low_water);
5265         tw32(BUFMGR_DMA_HIGH_WATER,
5266              tp->bufmgr_config.dma_high_water);
5267
5268         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5269         for (i = 0; i < 2000; i++) {
5270                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5271                         break;
5272                 udelay(10);
5273         }
5274         if (i >= 2000) {
5275                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5276                        tp->dev->name);
5277                 return -ENODEV;
5278         }
5279
5280         /* Setup replenish threshold. */
5281         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5282
5283         /* Initialize TG3_BDINFO's at:
5284          *  RCVDBDI_STD_BD:     standard eth size rx ring
5285          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5286          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5287          *
5288          * like so:
5289          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5290          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5291          *                              ring attribute flags
5292          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5293          *
5294          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5295          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5296          *
5297          * The size of each ring is fixed in the firmware, but the location is
5298          * configurable.
5299          */
5300         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5301              ((u64) tp->rx_std_mapping >> 32));
5302         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5303              ((u64) tp->rx_std_mapping & 0xffffffff));
5304         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5305              NIC_SRAM_RX_BUFFER_DESC);
5306
5307         /* Don't even try to program the JUMBO/MINI buffer descriptor
5308          * configs on 5705.
5309          */
5310         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5311                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5312                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5313         } else {
5314                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5315                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5316
5317                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5318                      BDINFO_FLAGS_DISABLED);
5319
5320                 /* Setup replenish threshold. */
5321                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5322
5323                 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5324                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5325                              ((u64) tp->rx_jumbo_mapping >> 32));
5326                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5327                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5328                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5329                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5330                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5331                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5332                 } else {
5333                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5334                              BDINFO_FLAGS_DISABLED);
5335                 }
5336
5337         }
5338
5339         /* There is only one send ring on 5705/5750, no need to explicitly
5340          * disable the others.
5341          */
5342         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5343                 /* Clear out send RCB ring in SRAM. */
5344                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5345                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5346                                       BDINFO_FLAGS_DISABLED);
5347         }
5348
5349         tp->tx_prod = 0;
5350         tp->tx_cons = 0;
5351         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5352         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5353
5354         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5355                        tp->tx_desc_mapping,
5356                        (TG3_TX_RING_SIZE <<
5357                         BDINFO_FLAGS_MAXLEN_SHIFT),
5358                        NIC_SRAM_TX_BUFFER_DESC);
5359
5360         /* There is only one receive return ring on 5705/5750, no need
5361          * to explicitly disable the others.
5362          */
5363         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5364                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5365                      i += TG3_BDINFO_SIZE) {
5366                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5367                                       BDINFO_FLAGS_DISABLED);
5368                 }
5369         }
5370
5371         tp->rx_rcb_ptr = 0;
5372         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5373
5374         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5375                        tp->rx_rcb_mapping,
5376                        (TG3_RX_RCB_RING_SIZE(tp) <<
5377                         BDINFO_FLAGS_MAXLEN_SHIFT),
5378                        0);
5379
5380         tp->rx_std_ptr = tp->rx_pending;
5381         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5382                      tp->rx_std_ptr);
5383
5384         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5385                                                 tp->rx_jumbo_pending : 0;
5386         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5387                      tp->rx_jumbo_ptr);
5388
5389         /* Initialize MAC address and backoff seed. */
5390         __tg3_set_mac_addr(tp);
5391
5392         /* MTU + ethernet header + FCS + optional VLAN tag */
5393         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5394
5395         /* The slot time is changed by tg3_setup_phy if we
5396          * run at gigabit with half duplex.
5397          */
5398         tw32(MAC_TX_LENGTHS,
5399              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5400              (6 << TX_LENGTHS_IPG_SHIFT) |
5401              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5402
5403         /* Receive rules. */
5404         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5405         tw32(RCVLPC_CONFIG, 0x0181);
5406
5407         /* Calculate RDMAC_MODE setting early, we need it to determine
5408          * the RCVLPC_STATE_ENABLE mask.
5409          */
5410         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5411                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5412                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5413                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5414                       RDMAC_MODE_LNGREAD_ENAB);
5415         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5416                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5417
5418         /* If statement applies to 5705 and 5750 PCI devices only */
5419         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5420              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5421             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5422                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5423                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5424                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5425                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5426                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5427                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5428                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5429                 }
5430         }
5431
5432         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5433                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5434
5435 #if TG3_TSO_SUPPORT != 0
5436         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5437                 rdmac_mode |= (1 << 27);
5438 #endif
5439
5440         /* Receive/send statistics. */
5441         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5442             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5443                 val = tr32(RCVLPC_STATS_ENABLE);
5444                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5445                 tw32(RCVLPC_STATS_ENABLE, val);
5446         } else {
5447                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5448         }
5449         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5450         tw32(SNDDATAI_STATSENAB, 0xffffff);
5451         tw32(SNDDATAI_STATSCTRL,
5452              (SNDDATAI_SCTRL_ENABLE |
5453               SNDDATAI_SCTRL_FASTUPD));
5454
5455         /* Setup host coalescing engine. */
5456         tw32(HOSTCC_MODE, 0);
5457         for (i = 0; i < 2000; i++) {
5458                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5459                         break;
5460                 udelay(10);
5461         }
5462
5463         tg3_set_coalesce(tp, &tp->coal);
5464
5465         /* set status block DMA address */
5466         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5467              ((u64) tp->status_mapping >> 32));
5468         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5469              ((u64) tp->status_mapping & 0xffffffff));
5470
5471         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5472                 /* Status/statistics block address.  See tg3_timer,
5473                  * the tg3_periodic_fetch_stats call there, and
5474                  * tg3_get_stats to see how this works for 5705/5750 chips.
5475                  */
5476                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5477                      ((u64) tp->stats_mapping >> 32));
5478                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5479                      ((u64) tp->stats_mapping & 0xffffffff));
5480                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5481                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5482         }
5483
5484         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5485
5486         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5487         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5488         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5489                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5490
5491         /* Clear statistics/status block in chip, and status block in ram. */
5492         for (i = NIC_SRAM_STATS_BLK;
5493              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5494              i += sizeof(u32)) {
5495                 tg3_write_mem(tp, i, 0);
5496                 udelay(40);
5497         }
5498         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5499
5500         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5501                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5502         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5503         udelay(40);
5504
5505         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5506          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5507          * register to preserve the GPIO settings for LOMs. The GPIOs,
5508          * whether used as inputs or outputs, are set by boot code after
5509          * reset.
5510          */
5511         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5512                 u32 gpio_mask;
5513
5514                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5515                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5516
5517                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5518                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5519                                      GRC_LCLCTRL_GPIO_OUTPUT3;
5520
5521                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5522
5523                 /* GPIO1 must be driven high for eeprom write protect */
5524                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5525                                        GRC_LCLCTRL_GPIO_OUTPUT1);
5526         }
5527         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5528         udelay(100);
5529
5530         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5531         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5532         tp->last_tag = 0;
5533
5534         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5535                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5536                 udelay(40);
5537         }
5538
5539         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5540                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5541                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5542                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5543                WDMAC_MODE_LNGREAD_ENAB);
5544
5545         /* If statement applies to 5705 and 5750 PCI devices only */
5546         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5547              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5548             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5549                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5550                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5551                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5552                         /* nothing */
5553                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5554                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5555                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5556                         val |= WDMAC_MODE_RX_ACCEL;
5557                 }
5558         }
5559
5560         tw32_f(WDMAC_MODE, val);
5561         udelay(40);
5562
5563         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5564                 val = tr32(TG3PCI_X_CAPS);
5565                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5566                         val &= ~PCIX_CAPS_BURST_MASK;
5567                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5568                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5569                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5570                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5571                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5572                                 val |= (tp->split_mode_max_reqs <<
5573                                         PCIX_CAPS_SPLIT_SHIFT);
5574                 }
5575                 tw32(TG3PCI_X_CAPS, val);
5576         }
5577
5578         tw32_f(RDMAC_MODE, rdmac_mode);
5579         udelay(40);
5580
5581         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5582         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5583                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5584         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5585         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5586         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5587         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5588         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5589 #if TG3_TSO_SUPPORT != 0
5590         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5591                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5592 #endif
5593         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5594         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5595
5596         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5597                 err = tg3_load_5701_a0_firmware_fix(tp);
5598                 if (err)
5599                         return err;
5600         }
5601
5602 #if TG3_TSO_SUPPORT != 0
5603         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5604                 err = tg3_load_tso_firmware(tp);
5605                 if (err)
5606                         return err;
5607         }
5608 #endif
5609
5610         tp->tx_mode = TX_MODE_ENABLE;
5611         tw32_f(MAC_TX_MODE, tp->tx_mode);
5612         udelay(100);
5613
5614         tp->rx_mode = RX_MODE_ENABLE;
5615         tw32_f(MAC_RX_MODE, tp->rx_mode);
5616         udelay(10);
5617
5618         if (tp->link_config.phy_is_low_power) {
5619                 tp->link_config.phy_is_low_power = 0;
5620                 tp->link_config.speed = tp->link_config.orig_speed;
5621                 tp->link_config.duplex = tp->link_config.orig_duplex;
5622                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5623         }
5624
5625         tp->mi_mode = MAC_MI_MODE_BASE;
5626         tw32_f(MAC_MI_MODE, tp->mi_mode);
5627         udelay(80);
5628
5629         tw32(MAC_LED_CTRL, tp->led_ctrl);
5630
5631         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5632         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5633                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5634                 udelay(10);
5635         }
5636         tw32_f(MAC_RX_MODE, tp->rx_mode);
5637         udelay(10);
5638
5639         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5640                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5641                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5642                         /* Set drive transmission level to 1.2V  */
5643                         /* only if the signal pre-emphasis bit is not set  */
5644                         val = tr32(MAC_SERDES_CFG);
5645                         val &= 0xfffff000;
5646                         val |= 0x880;
5647                         tw32(MAC_SERDES_CFG, val);
5648                 }
5649                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5650                         tw32(MAC_SERDES_CFG, 0x616000);
5651         }
5652
5653         /* Prevent chip from dropping frames when flow control
5654          * is enabled.
5655          */
5656         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5657
5658         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5659             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5660                 /* Use hardware link auto-negotiation */
5661                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5662         }
5663
5664         err = tg3_setup_phy(tp, 1);
5665         if (err)
5666                 return err;
5667
5668         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5669                 u32 tmp;
5670
5671                 /* Clear CRC stats. */
5672                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5673                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
5674                         tg3_readphy(tp, 0x14, &tmp);
5675                 }
5676         }
5677
5678         __tg3_set_rx_mode(tp->dev);
5679
5680         /* Initialize receive rules. */
5681         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
5682         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5683         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
5684         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5685
5686         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5687                 limit = 8;
5688         else
5689                 limit = 16;
5690         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5691                 limit -= 4;
5692         switch (limit) {
5693         case 16:
5694                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
5695         case 15:
5696                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
5697         case 14:
5698                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
5699         case 13:
5700                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
5701         case 12:
5702                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
5703         case 11:
5704                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
5705         case 10:
5706                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
5707         case 9:
5708                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
5709         case 8:
5710                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
5711         case 7:
5712                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
5713         case 6:
5714                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
5715         case 5:
5716                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
5717         case 4:
5718                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
5719         case 3:
5720                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
5721         case 2:
5722         case 1:
5723
5724         default:
5725                 break;
5726         };
5727
5728         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5729
5730         return 0;
5731 }
5732
5733 /* Called at device open time to get the chip ready for
5734  * packet processing.  Invoked with tp->lock held.
5735  */
5736 static int tg3_init_hw(struct tg3 *tp)
5737 {
5738         int err;
5739
5740         /* Force the chip into D0. */
5741         err = tg3_set_power_state(tp, 0);
5742         if (err)
5743                 goto out;
5744
5745         tg3_switch_clocks(tp);
5746
5747         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5748
5749         err = tg3_reset_hw(tp);
5750
5751 out:
5752         return err;
5753 }
5754
5755 #define TG3_STAT_ADD32(PSTAT, REG) \
5756 do {    u32 __val = tr32(REG); \
5757         (PSTAT)->low += __val; \
5758         if ((PSTAT)->low < __val) \
5759                 (PSTAT)->high += 1; \
5760 } while (0)
5761
5762 static void tg3_periodic_fetch_stats(struct tg3 *tp)
5763 {
5764         struct tg3_hw_stats *sp = tp->hw_stats;
5765
5766         if (!netif_carrier_ok(tp->dev))
5767                 return;
5768
5769         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5770         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5771         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5772         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5773         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5774         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5775         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5776         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5777         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5778         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5779         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5780         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5781         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5782
5783         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5784         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5785         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5786         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5787         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5788         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5789         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5790         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5791         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5792         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5793         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5794         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5795         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5796         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5797 }
5798
5799 static void tg3_timer(unsigned long __opaque)
5800 {
5801         struct tg3 *tp = (struct tg3 *) __opaque;
5802
5803         spin_lock(&tp->lock);
5804
5805         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
5806                 /* All of this garbage is because when using non-tagged
5807                  * IRQ status the mailbox/status_block protocol the chip
5808                  * uses with the cpu is race prone.
5809                  */
5810                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5811                         tw32(GRC_LOCAL_CTRL,
5812                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5813                 } else {
5814                         tw32(HOSTCC_MODE, tp->coalesce_mode |
5815                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5816                 }
5817
5818                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5819                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5820                         spin_unlock(&tp->lock);
5821                         schedule_work(&tp->reset_task);
5822                         return;
5823                 }
5824         }
5825
5826         /* This part only runs once per second. */
5827         if (!--tp->timer_counter) {
5828                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5829                         tg3_periodic_fetch_stats(tp);
5830
5831                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5832                         u32 mac_stat;
5833                         int phy_event;
5834
5835                         mac_stat = tr32(MAC_STATUS);
5836
5837                         phy_event = 0;
5838                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5839                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5840                                         phy_event = 1;
5841                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5842                                 phy_event = 1;
5843
5844                         if (phy_event)
5845                                 tg3_setup_phy(tp, 0);
5846                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5847                         u32 mac_stat = tr32(MAC_STATUS);
5848                         int need_setup = 0;
5849
5850                         if (netif_carrier_ok(tp->dev) &&
5851                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5852                                 need_setup = 1;
5853                         }
5854                         if (! netif_carrier_ok(tp->dev) &&
5855                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
5856                                          MAC_STATUS_SIGNAL_DET))) {
5857                                 need_setup = 1;
5858                         }
5859                         if (need_setup) {
5860                                 tw32_f(MAC_MODE,
5861                                      (tp->mac_mode &
5862                                       ~MAC_MODE_PORT_MODE_MASK));
5863                                 udelay(40);
5864                                 tw32_f(MAC_MODE, tp->mac_mode);
5865                                 udelay(40);
5866                                 tg3_setup_phy(tp, 0);
5867                         }
5868                 }
5869
5870                 tp->timer_counter = tp->timer_multiplier;
5871         }
5872
5873         /* Heartbeat is only sent once every 120 seconds.  */
5874         if (!--tp->asf_counter) {
5875                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5876                         u32 val;
5877
5878                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5879                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5880                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5881                         val = tr32(GRC_RX_CPU_EVENT);
5882                         val |= (1 << 14);
5883                         tw32(GRC_RX_CPU_EVENT, val);
5884                 }
5885                 tp->asf_counter = tp->asf_multiplier;
5886         }
5887
5888         spin_unlock(&tp->lock);
5889
5890         tp->timer.expires = jiffies + tp->timer_offset;
5891         add_timer(&tp->timer);
5892 }
5893
5894 static int tg3_test_interrupt(struct tg3 *tp)
5895 {
5896         struct net_device *dev = tp->dev;
5897         int err, i;
5898         u32 int_mbox = 0;
5899
5900         if (!netif_running(dev))
5901                 return -ENODEV;
5902
5903         tg3_disable_ints(tp);
5904
5905         free_irq(tp->pdev->irq, dev);
5906
5907         err = request_irq(tp->pdev->irq, tg3_test_isr,
5908                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5909         if (err)
5910                 return err;
5911
5912         tg3_enable_ints(tp);
5913
5914         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
5915                HOSTCC_MODE_NOW);
5916
5917         for (i = 0; i < 5; i++) {
5918                 int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5919                 if (int_mbox != 0)
5920                         break;
5921                 msleep(10);
5922         }
5923
5924         tg3_disable_ints(tp);
5925
5926         free_irq(tp->pdev->irq, dev);
5927
5928         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5929                 err = request_irq(tp->pdev->irq, tg3_msi,
5930                                   SA_SAMPLE_RANDOM, dev->name, dev);
5931         else {
5932                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5933                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5934                         fn = tg3_interrupt_tagged;
5935                 err = request_irq(tp->pdev->irq, fn,
5936                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5937         }
5938
5939         if (err)
5940                 return err;
5941
5942         if (int_mbox != 0)
5943                 return 0;
5944
5945         return -EIO;
5946 }
5947
5948 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5949  * successfully restored
5950  */
5951 static int tg3_test_msi(struct tg3 *tp)
5952 {
5953         struct net_device *dev = tp->dev;
5954         int err;
5955         u16 pci_cmd;
5956
5957         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
5958                 return 0;
5959
5960         /* Turn off SERR reporting in case MSI terminates with Master
5961          * Abort.
5962          */
5963         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
5964         pci_write_config_word(tp->pdev, PCI_COMMAND,
5965                               pci_cmd & ~PCI_COMMAND_SERR);
5966
5967         err = tg3_test_interrupt(tp);
5968
5969         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
5970
5971         if (!err)
5972                 return 0;
5973
5974         /* other failures */
5975         if (err != -EIO)
5976                 return err;
5977
5978         /* MSI test failed, go back to INTx mode */
5979         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
5980                "switching to INTx mode. Please report this failure to "
5981                "the PCI maintainer and include system chipset information.\n",
5982                        tp->dev->name);
5983
5984         free_irq(tp->pdev->irq, dev);
5985         pci_disable_msi(tp->pdev);
5986
5987         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
5988
5989         {
5990                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5991                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5992                         fn = tg3_interrupt_tagged;
5993
5994                 err = request_irq(tp->pdev->irq, fn,
5995                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5996         }
5997         if (err)
5998                 return err;
5999
6000         /* Need to reset the chip because the MSI cycle may have terminated
6001          * with Master Abort.
6002          */
6003         tg3_full_lock(tp, 1);
6004
6005         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6006         err = tg3_init_hw(tp);
6007
6008         tg3_full_unlock(tp);
6009
6010         if (err)
6011                 free_irq(tp->pdev->irq, dev);
6012
6013         return err;
6014 }
6015
6016 static int tg3_open(struct net_device *dev)
6017 {
6018         struct tg3 *tp = netdev_priv(dev);
6019         int err;
6020
6021         tg3_full_lock(tp, 0);
6022
6023         tg3_disable_ints(tp);
6024         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6025
6026         tg3_full_unlock(tp);
6027
6028         /* The placement of this call is tied
6029          * to the setup and use of Host TX descriptors.
6030          */
6031         err = tg3_alloc_consistent(tp);
6032         if (err)
6033                 return err;
6034
6035         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6036             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6037             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
6038                 /* All MSI supporting chips should support tagged
6039                  * status.  Assert that this is the case.
6040                  */
6041                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6042                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6043                                "Not using MSI.\n", tp->dev->name);
6044                 } else if (pci_enable_msi(tp->pdev) == 0) {
6045                         u32 msi_mode;
6046
6047                         msi_mode = tr32(MSGINT_MODE);
6048                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6049                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6050                 }
6051         }
6052         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6053                 err = request_irq(tp->pdev->irq, tg3_msi,
6054                                   SA_SAMPLE_RANDOM, dev->name, dev);
6055         else {
6056                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6057                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6058                         fn = tg3_interrupt_tagged;
6059
6060                 err = request_irq(tp->pdev->irq, fn,
6061                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6062         }
6063
6064         if (err) {
6065                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6066                         pci_disable_msi(tp->pdev);
6067                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6068                 }
6069                 tg3_free_consistent(tp);
6070                 return err;
6071         }
6072
6073         tg3_full_lock(tp, 0);
6074
6075         err = tg3_init_hw(tp);
6076         if (err) {
6077                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6078                 tg3_free_rings(tp);
6079         } else {
6080                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6081                         tp->timer_offset = HZ;
6082                 else
6083                         tp->timer_offset = HZ / 10;
6084
6085                 BUG_ON(tp->timer_offset > HZ);
6086                 tp->timer_counter = tp->timer_multiplier =
6087                         (HZ / tp->timer_offset);
6088                 tp->asf_counter = tp->asf_multiplier =
6089                         ((HZ / tp->timer_offset) * 120);
6090
6091                 init_timer(&tp->timer);
6092                 tp->timer.expires = jiffies + tp->timer_offset;
6093                 tp->timer.data = (unsigned long) tp;
6094                 tp->timer.function = tg3_timer;
6095         }
6096
6097         tg3_full_unlock(tp);
6098
6099         if (err) {
6100                 free_irq(tp->pdev->irq, dev);
6101                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6102                         pci_disable_msi(tp->pdev);
6103                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6104                 }
6105                 tg3_free_consistent(tp);
6106                 return err;
6107         }
6108
6109         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6110                 err = tg3_test_msi(tp);
6111
6112                 if (err) {
6113                         tg3_full_lock(tp, 0);
6114
6115                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6116                                 pci_disable_msi(tp->pdev);
6117                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6118                         }
6119                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6120                         tg3_free_rings(tp);
6121                         tg3_free_consistent(tp);
6122
6123                         tg3_full_unlock(tp);
6124
6125                         return err;
6126                 }
6127         }
6128
6129         tg3_full_lock(tp, 0);
6130
6131         add_timer(&tp->timer);
6132         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6133         tg3_enable_ints(tp);
6134
6135         tg3_full_unlock(tp);
6136
6137         netif_start_queue(dev);
6138
6139         return 0;
6140 }
6141
6142 #if 0
6143 /*static*/ void tg3_dump_state(struct tg3 *tp)
6144 {
6145         u32 val32, val32_2, val32_3, val32_4, val32_5;
6146         u16 val16;
6147         int i;
6148
6149         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6150         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6151         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6152                val16, val32);
6153
6154         /* MAC block */
6155         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6156                tr32(MAC_MODE), tr32(MAC_STATUS));
6157         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6158                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6159         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6160                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6161         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6162                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6163
6164         /* Send data initiator control block */
6165         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6166                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6167         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6168                tr32(SNDDATAI_STATSCTRL));
6169
6170         /* Send data completion control block */
6171         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6172
6173         /* Send BD ring selector block */
6174         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6175                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6176
6177         /* Send BD initiator control block */
6178         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6179                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6180
6181         /* Send BD completion control block */
6182         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6183
6184         /* Receive list placement control block */
6185         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6186                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6187         printk("       RCVLPC_STATSCTRL[%08x]\n",
6188                tr32(RCVLPC_STATSCTRL));
6189
6190         /* Receive data and receive BD initiator control block */
6191         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6192                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6193
6194         /* Receive data completion control block */
6195         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6196                tr32(RCVDCC_MODE));
6197
6198         /* Receive BD initiator control block */
6199         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6200                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6201
6202         /* Receive BD completion control block */
6203         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6204                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6205
6206         /* Receive list selector control block */
6207         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6208                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6209
6210         /* Mbuf cluster free block */
6211         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6212                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6213
6214         /* Host coalescing control block */
6215         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6216                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6217         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6218                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6219                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6220         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6221                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6222                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6223         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6224                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6225         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6226                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6227
6228         /* Memory arbiter control block */
6229         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6230                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6231
6232         /* Buffer manager control block */
6233         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6234                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6235         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6236                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6237         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6238                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6239                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6240                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6241
6242         /* Read DMA control block */
6243         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6244                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6245
6246         /* Write DMA control block */
6247         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6248                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6249
6250         /* DMA completion block */
6251         printk("DEBUG: DMAC_MODE[%08x]\n",
6252                tr32(DMAC_MODE));
6253
6254         /* GRC block */
6255         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6256                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6257         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6258                tr32(GRC_LOCAL_CTRL));
6259
6260         /* TG3_BDINFOs */
6261         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6262                tr32(RCVDBDI_JUMBO_BD + 0x0),
6263                tr32(RCVDBDI_JUMBO_BD + 0x4),
6264                tr32(RCVDBDI_JUMBO_BD + 0x8),
6265                tr32(RCVDBDI_JUMBO_BD + 0xc));
6266         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6267                tr32(RCVDBDI_STD_BD + 0x0),
6268                tr32(RCVDBDI_STD_BD + 0x4),
6269                tr32(RCVDBDI_STD_BD + 0x8),
6270                tr32(RCVDBDI_STD_BD + 0xc));
6271         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6272                tr32(RCVDBDI_MINI_BD + 0x0),
6273                tr32(RCVDBDI_MINI_BD + 0x4),
6274                tr32(RCVDBDI_MINI_BD + 0x8),
6275                tr32(RCVDBDI_MINI_BD + 0xc));
6276
6277         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6278         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6279         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6280         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6281         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6282                val32, val32_2, val32_3, val32_4);
6283
6284         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6285         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6286         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6287         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6288         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6289                val32, val32_2, val32_3, val32_4);
6290
6291         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6292         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6293         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6294         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6295         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6296         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6297                val32, val32_2, val32_3, val32_4, val32_5);
6298
6299         /* SW status block */
6300         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6301                tp->hw_status->status,
6302                tp->hw_status->status_tag,
6303                tp->hw_status->rx_jumbo_consumer,
6304                tp->hw_status->rx_consumer,
6305                tp->hw_status->rx_mini_consumer,
6306                tp->hw_status->idx[0].rx_producer,
6307                tp->hw_status->idx[0].tx_consumer);
6308
6309         /* SW statistics block */
6310         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6311                ((u32 *)tp->hw_stats)[0],
6312                ((u32 *)tp->hw_stats)[1],
6313                ((u32 *)tp->hw_stats)[2],
6314                ((u32 *)tp->hw_stats)[3]);
6315
6316         /* Mailboxes */
6317         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6318                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6319                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6320                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6321                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6322
6323         /* NIC side send descriptors. */
6324         for (i = 0; i < 6; i++) {
6325                 unsigned long txd;
6326
6327                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6328                         + (i * sizeof(struct tg3_tx_buffer_desc));
6329                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6330                        i,
6331                        readl(txd + 0x0), readl(txd + 0x4),
6332                        readl(txd + 0x8), readl(txd + 0xc));
6333         }
6334
6335         /* NIC side RX descriptors. */
6336         for (i = 0; i < 6; i++) {
6337                 unsigned long rxd;
6338
6339                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6340                         + (i * sizeof(struct tg3_rx_buffer_desc));
6341                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6342                        i,
6343                        readl(rxd + 0x0), readl(rxd + 0x4),
6344                        readl(rxd + 0x8), readl(rxd + 0xc));
6345                 rxd += (4 * sizeof(u32));
6346                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6347                        i,
6348                        readl(rxd + 0x0), readl(rxd + 0x4),
6349                        readl(rxd + 0x8), readl(rxd + 0xc));
6350         }
6351
6352         for (i = 0; i < 6; i++) {
6353                 unsigned long rxd;
6354
6355                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6356                         + (i * sizeof(struct tg3_rx_buffer_desc));
6357                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6358                        i,
6359                        readl(rxd + 0x0), readl(rxd + 0x4),
6360                        readl(rxd + 0x8), readl(rxd + 0xc));
6361                 rxd += (4 * sizeof(u32));
6362                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6363                        i,
6364                        readl(rxd + 0x0), readl(rxd + 0x4),
6365                        readl(rxd + 0x8), readl(rxd + 0xc));
6366         }
6367 }
6368 #endif
6369
6370 static struct net_device_stats *tg3_get_stats(struct net_device *);
6371 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6372
6373 static int tg3_close(struct net_device *dev)
6374 {
6375         struct tg3 *tp = netdev_priv(dev);
6376
6377         netif_stop_queue(dev);
6378
6379         del_timer_sync(&tp->timer);
6380
6381         tg3_full_lock(tp, 1);
6382 #if 0
6383         tg3_dump_state(tp);
6384 #endif
6385
6386         tg3_disable_ints(tp);
6387
6388         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6389         tg3_free_rings(tp);
6390         tp->tg3_flags &=
6391                 ~(TG3_FLAG_INIT_COMPLETE |
6392                   TG3_FLAG_GOT_SERDES_FLOWCTL);
6393         netif_carrier_off(tp->dev);
6394
6395         tg3_full_unlock(tp);
6396
6397         free_irq(tp->pdev->irq, dev);
6398         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6399                 pci_disable_msi(tp->pdev);
6400                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6401         }
6402
6403         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6404                sizeof(tp->net_stats_prev));
6405         memcpy(&tp->estats_prev, tg3_get_estats(tp),
6406                sizeof(tp->estats_prev));
6407
6408         tg3_free_consistent(tp);
6409
6410         return 0;
6411 }
6412
6413 static inline unsigned long get_stat64(tg3_stat64_t *val)
6414 {
6415         unsigned long ret;
6416
6417 #if (BITS_PER_LONG == 32)
6418         ret = val->low;
6419 #else
6420         ret = ((u64)val->high << 32) | ((u64)val->low);
6421 #endif
6422         return ret;
6423 }
6424
6425 static unsigned long calc_crc_errors(struct tg3 *tp)
6426 {
6427         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6428
6429         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6430             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6431              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6432                 u32 val;
6433
6434                 spin_lock_bh(&tp->lock);
6435                 if (!tg3_readphy(tp, 0x1e, &val)) {
6436                         tg3_writephy(tp, 0x1e, val | 0x8000);
6437                         tg3_readphy(tp, 0x14, &val);
6438                 } else
6439                         val = 0;
6440                 spin_unlock_bh(&tp->lock);
6441
6442                 tp->phy_crc_errors += val;
6443
6444                 return tp->phy_crc_errors;
6445         }
6446
6447         return get_stat64(&hw_stats->rx_fcs_errors);
6448 }
6449
6450 #define ESTAT_ADD(member) \
6451         estats->member =        old_estats->member + \
6452                                 get_stat64(&hw_stats->member)
6453
6454 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6455 {
6456         struct tg3_ethtool_stats *estats = &tp->estats;
6457         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6458         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6459
6460         if (!hw_stats)
6461                 return old_estats;
6462
6463         ESTAT_ADD(rx_octets);
6464         ESTAT_ADD(rx_fragments);
6465         ESTAT_ADD(rx_ucast_packets);
6466         ESTAT_ADD(rx_mcast_packets);
6467         ESTAT_ADD(rx_bcast_packets);
6468         ESTAT_ADD(rx_fcs_errors);
6469         ESTAT_ADD(rx_align_errors);
6470         ESTAT_ADD(rx_xon_pause_rcvd);
6471         ESTAT_ADD(rx_xoff_pause_rcvd);
6472         ESTAT_ADD(rx_mac_ctrl_rcvd);
6473         ESTAT_ADD(rx_xoff_entered);
6474         ESTAT_ADD(rx_frame_too_long_errors);
6475         ESTAT_ADD(rx_jabbers);
6476         ESTAT_ADD(rx_undersize_packets);
6477         ESTAT_ADD(rx_in_length_errors);
6478         ESTAT_ADD(rx_out_length_errors);
6479         ESTAT_ADD(rx_64_or_less_octet_packets);
6480         ESTAT_ADD(rx_65_to_127_octet_packets);
6481         ESTAT_ADD(rx_128_to_255_octet_packets);
6482         ESTAT_ADD(rx_256_to_511_octet_packets);
6483         ESTAT_ADD(rx_512_to_1023_octet_packets);
6484         ESTAT_ADD(rx_1024_to_1522_octet_packets);
6485         ESTAT_ADD(rx_1523_to_2047_octet_packets);
6486         ESTAT_ADD(rx_2048_to_4095_octet_packets);
6487         ESTAT_ADD(rx_4096_to_8191_octet_packets);
6488         ESTAT_ADD(rx_8192_to_9022_octet_packets);
6489
6490         ESTAT_ADD(tx_octets);
6491         ESTAT_ADD(tx_collisions);
6492         ESTAT_ADD(tx_xon_sent);
6493         ESTAT_ADD(tx_xoff_sent);
6494         ESTAT_ADD(tx_flow_control);
6495         ESTAT_ADD(tx_mac_errors);
6496         ESTAT_ADD(tx_single_collisions);
6497         ESTAT_ADD(tx_mult_collisions);
6498         ESTAT_ADD(tx_deferred);
6499         ESTAT_ADD(tx_excessive_collisions);
6500         ESTAT_ADD(tx_late_collisions);
6501         ESTAT_ADD(tx_collide_2times);
6502         ESTAT_ADD(tx_collide_3times);
6503         ESTAT_ADD(tx_collide_4times);
6504         ESTAT_ADD(tx_collide_5times);
6505         ESTAT_ADD(tx_collide_6times);
6506         ESTAT_ADD(tx_collide_7times);
6507         ESTAT_ADD(tx_collide_8times);
6508         ESTAT_ADD(tx_collide_9times);
6509         ESTAT_ADD(tx_collide_10times);
6510         ESTAT_ADD(tx_collide_11times);
6511         ESTAT_ADD(tx_collide_12times);
6512         ESTAT_ADD(tx_collide_13times);
6513         ESTAT_ADD(tx_collide_14times);
6514         ESTAT_ADD(tx_collide_15times);
6515         ESTAT_ADD(tx_ucast_packets);
6516         ESTAT_ADD(tx_mcast_packets);
6517         ESTAT_ADD(tx_bcast_packets);
6518         ESTAT_ADD(tx_carrier_sense_errors);
6519         ESTAT_ADD(tx_discards);
6520         ESTAT_ADD(tx_errors);
6521
6522         ESTAT_ADD(dma_writeq_full);
6523         ESTAT_ADD(dma_write_prioq_full);
6524         ESTAT_ADD(rxbds_empty);
6525         ESTAT_ADD(rx_discards);
6526         ESTAT_ADD(rx_errors);
6527         ESTAT_ADD(rx_threshold_hit);
6528
6529         ESTAT_ADD(dma_readq_full);
6530         ESTAT_ADD(dma_read_prioq_full);
6531         ESTAT_ADD(tx_comp_queue_full);
6532
6533         ESTAT_ADD(ring_set_send_prod_index);
6534         ESTAT_ADD(ring_status_update);
6535         ESTAT_ADD(nic_irqs);
6536         ESTAT_ADD(nic_avoided_irqs);
6537         ESTAT_ADD(nic_tx_threshold_hit);
6538
6539         return estats;
6540 }
6541
6542 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6543 {
6544         struct tg3 *tp = netdev_priv(dev);
6545         struct net_device_stats *stats = &tp->net_stats;
6546         struct net_device_stats *old_stats = &tp->net_stats_prev;
6547         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6548
6549         if (!hw_stats)
6550                 return old_stats;
6551
6552         stats->rx_packets = old_stats->rx_packets +
6553                 get_stat64(&hw_stats->rx_ucast_packets) +
6554                 get_stat64(&hw_stats->rx_mcast_packets) +
6555                 get_stat64(&hw_stats->rx_bcast_packets);
6556
6557         stats->tx_packets = old_stats->tx_packets +
6558                 get_stat64(&hw_stats->tx_ucast_packets) +
6559                 get_stat64(&hw_stats->tx_mcast_packets) +
6560                 get_stat64(&hw_stats->tx_bcast_packets);
6561
6562         stats->rx_bytes = old_stats->rx_bytes +
6563                 get_stat64(&hw_stats->rx_octets);
6564         stats->tx_bytes = old_stats->tx_bytes +
6565                 get_stat64(&hw_stats->tx_octets);
6566
6567         stats->rx_errors = old_stats->rx_errors +
6568                 get_stat64(&hw_stats->rx_errors) +
6569                 get_stat64(&hw_stats->rx_discards);
6570         stats->tx_errors = old_stats->tx_errors +
6571                 get_stat64(&hw_stats->tx_errors) +
6572                 get_stat64(&hw_stats->tx_mac_errors) +
6573                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6574                 get_stat64(&hw_stats->tx_discards);
6575
6576         stats->multicast = old_stats->multicast +
6577                 get_stat64(&hw_stats->rx_mcast_packets);
6578         stats->collisions = old_stats->collisions +
6579                 get_stat64(&hw_stats->tx_collisions);
6580
6581         stats->rx_length_errors = old_stats->rx_length_errors +
6582                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6583                 get_stat64(&hw_stats->rx_undersize_packets);
6584
6585         stats->rx_over_errors = old_stats->rx_over_errors +
6586                 get_stat64(&hw_stats->rxbds_empty);
6587         stats->rx_frame_errors = old_stats->rx_frame_errors +
6588                 get_stat64(&hw_stats->rx_align_errors);
6589         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6590                 get_stat64(&hw_stats->tx_discards);
6591         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6592                 get_stat64(&hw_stats->tx_carrier_sense_errors);
6593
6594         stats->rx_crc_errors = old_stats->rx_crc_errors +
6595                 calc_crc_errors(tp);
6596
6597         return stats;
6598 }
6599
6600 static inline u32 calc_crc(unsigned char *buf, int len)
6601 {
6602         u32 reg;
6603         u32 tmp;
6604         int j, k;
6605
6606         reg = 0xffffffff;
6607
6608         for (j = 0; j < len; j++) {
6609                 reg ^= buf[j];
6610
6611                 for (k = 0; k < 8; k++) {
6612                         tmp = reg & 0x01;
6613
6614                         reg >>= 1;
6615
6616                         if (tmp) {
6617                                 reg ^= 0xedb88320;
6618                         }
6619                 }
6620         }
6621
6622         return ~reg;
6623 }
6624
6625 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6626 {
6627         /* accept or reject all multicast frames */
6628         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6629         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6630         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6631         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6632 }
6633
6634 static void __tg3_set_rx_mode(struct net_device *dev)
6635 {
6636         struct tg3 *tp = netdev_priv(dev);
6637         u32 rx_mode;
6638
6639         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6640                                   RX_MODE_KEEP_VLAN_TAG);
6641
6642         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6643          * flag clear.
6644          */
6645 #if TG3_VLAN_TAG_USED
6646         if (!tp->vlgrp &&
6647             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6648                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6649 #else
6650         /* By definition, VLAN is disabled always in this
6651          * case.
6652          */
6653         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6654                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6655 #endif
6656
6657         if (dev->flags & IFF_PROMISC) {
6658                 /* Promiscuous mode. */
6659                 rx_mode |= RX_MODE_PROMISC;
6660         } else if (dev->flags & IFF_ALLMULTI) {
6661                 /* Accept all multicast. */
6662                 tg3_set_multi (tp, 1);
6663         } else if (dev->mc_count < 1) {
6664                 /* Reject all multicast. */
6665                 tg3_set_multi (tp, 0);
6666         } else {
6667                 /* Accept one or more multicast(s). */
6668                 struct dev_mc_list *mclist;
6669                 unsigned int i;
6670                 u32 mc_filter[4] = { 0, };
6671                 u32 regidx;
6672                 u32 bit;
6673                 u32 crc;
6674
6675                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6676                      i++, mclist = mclist->next) {
6677
6678                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6679                         bit = ~crc & 0x7f;
6680                         regidx = (bit & 0x60) >> 5;
6681                         bit &= 0x1f;
6682                         mc_filter[regidx] |= (1 << bit);
6683                 }
6684
6685                 tw32(MAC_HASH_REG_0, mc_filter[0]);
6686                 tw32(MAC_HASH_REG_1, mc_filter[1]);
6687                 tw32(MAC_HASH_REG_2, mc_filter[2]);
6688                 tw32(MAC_HASH_REG_3, mc_filter[3]);
6689         }
6690
6691         if (rx_mode != tp->rx_mode) {
6692                 tp->rx_mode = rx_mode;
6693                 tw32_f(MAC_RX_MODE, rx_mode);
6694                 udelay(10);
6695         }
6696 }
6697
6698 static void tg3_set_rx_mode(struct net_device *dev)
6699 {
6700         struct tg3 *tp = netdev_priv(dev);
6701
6702         tg3_full_lock(tp, 0);
6703         __tg3_set_rx_mode(dev);
6704         tg3_full_unlock(tp);
6705 }
6706
6707 #define TG3_REGDUMP_LEN         (32 * 1024)
6708
6709 static int tg3_get_regs_len(struct net_device *dev)
6710 {
6711         return TG3_REGDUMP_LEN;
6712 }
6713
6714 static void tg3_get_regs(struct net_device *dev,
6715                 struct ethtool_regs *regs, void *_p)
6716 {
6717         u32 *p = _p;
6718         struct tg3 *tp = netdev_priv(dev);
6719         u8 *orig_p = _p;
6720         int i;
6721
6722         regs->version = 0;
6723
6724         memset(p, 0, TG3_REGDUMP_LEN);
6725
6726         tg3_full_lock(tp, 0);
6727
6728 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
6729 #define GET_REG32_LOOP(base,len)                \
6730 do {    p = (u32 *)(orig_p + (base));           \
6731         for (i = 0; i < len; i += 4)            \
6732                 __GET_REG32((base) + i);        \
6733 } while (0)
6734 #define GET_REG32_1(reg)                        \
6735 do {    p = (u32 *)(orig_p + (reg));            \
6736         __GET_REG32((reg));                     \
6737 } while (0)
6738
6739         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6740         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6741         GET_REG32_LOOP(MAC_MODE, 0x4f0);
6742         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6743         GET_REG32_1(SNDDATAC_MODE);
6744         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6745         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6746         GET_REG32_1(SNDBDC_MODE);
6747         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6748         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6749         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6750         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6751         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6752         GET_REG32_1(RCVDCC_MODE);
6753         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6754         GET_REG32_LOOP(RCVCC_MODE, 0x14);
6755         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6756         GET_REG32_1(MBFREE_MODE);
6757         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6758         GET_REG32_LOOP(MEMARB_MODE, 0x10);
6759         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6760         GET_REG32_LOOP(RDMAC_MODE, 0x08);
6761         GET_REG32_LOOP(WDMAC_MODE, 0x08);
6762         GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6763         GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6764         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6765         GET_REG32_LOOP(FTQ_RESET, 0x120);
6766         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6767         GET_REG32_1(DMAC_MODE);
6768         GET_REG32_LOOP(GRC_MODE, 0x4c);
6769         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6770                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6771
6772 #undef __GET_REG32
6773 #undef GET_REG32_LOOP
6774 #undef GET_REG32_1
6775
6776         tg3_full_unlock(tp);
6777 }
6778
6779 static int tg3_get_eeprom_len(struct net_device *dev)
6780 {
6781         struct tg3 *tp = netdev_priv(dev);
6782
6783         return tp->nvram_size;
6784 }
6785
6786 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6787
6788 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6789 {
6790         struct tg3 *tp = netdev_priv(dev);
6791         int ret;
6792         u8  *pd;
6793         u32 i, offset, len, val, b_offset, b_count;
6794
6795         offset = eeprom->offset;
6796         len = eeprom->len;
6797         eeprom->len = 0;
6798
6799         eeprom->magic = TG3_EEPROM_MAGIC;
6800
6801         if (offset & 3) {
6802                 /* adjustments to start on required 4 byte boundary */
6803                 b_offset = offset & 3;
6804                 b_count = 4 - b_offset;
6805                 if (b_count > len) {
6806                         /* i.e. offset=1 len=2 */
6807                         b_count = len;
6808                 }
6809                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6810                 if (ret)
6811                         return ret;
6812                 val = cpu_to_le32(val);
6813                 memcpy(data, ((char*)&val) + b_offset, b_count);
6814                 len -= b_count;
6815                 offset += b_count;
6816                 eeprom->len += b_count;
6817         }
6818
6819         /* read bytes upto the last 4 byte boundary */
6820         pd = &data[eeprom->len];
6821         for (i = 0; i < (len - (len & 3)); i += 4) {
6822                 ret = tg3_nvram_read(tp, offset + i, &val);
6823                 if (ret) {
6824                         eeprom->len += i;
6825                         return ret;
6826                 }
6827                 val = cpu_to_le32(val);
6828                 memcpy(pd + i, &val, 4);
6829         }
6830         eeprom->len += i;
6831
6832         if (len & 3) {
6833                 /* read last bytes not ending on 4 byte boundary */
6834                 pd = &data[eeprom->len];
6835                 b_count = len & 3;
6836                 b_offset = offset + len - b_count;
6837                 ret = tg3_nvram_read(tp, b_offset, &val);
6838                 if (ret)
6839                         return ret;
6840                 val = cpu_to_le32(val);
6841                 memcpy(pd, ((char*)&val), b_count);
6842                 eeprom->len += b_count;
6843         }
6844         return 0;
6845 }
6846
6847 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6848
6849 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6850 {
6851         struct tg3 *tp = netdev_priv(dev);
6852         int ret;
6853         u32 offset, len, b_offset, odd_len, start, end;
6854         u8 *buf;
6855
6856         if (eeprom->magic != TG3_EEPROM_MAGIC)
6857                 return -EINVAL;
6858
6859         offset = eeprom->offset;
6860         len = eeprom->len;
6861
6862         if ((b_offset = (offset & 3))) {
6863                 /* adjustments to start on required 4 byte boundary */
6864                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6865                 if (ret)
6866                         return ret;
6867                 start = cpu_to_le32(start);
6868                 len += b_offset;
6869                 offset &= ~3;
6870                 if (len < 4)
6871                         len = 4;
6872         }
6873
6874         odd_len = 0;
6875         if (len & 3) {
6876                 /* adjustments to end on required 4 byte boundary */
6877                 odd_len = 1;
6878                 len = (len + 3) & ~3;
6879                 ret = tg3_nvram_read(tp, offset+len-4, &end);
6880                 if (ret)
6881                         return ret;
6882                 end = cpu_to_le32(end);
6883         }
6884
6885         buf = data;
6886         if (b_offset || odd_len) {
6887                 buf = kmalloc(len, GFP_KERNEL);
6888                 if (buf == 0)
6889                         return -ENOMEM;
6890                 if (b_offset)
6891                         memcpy(buf, &start, 4);
6892                 if (odd_len)
6893                         memcpy(buf+len-4, &end, 4);
6894                 memcpy(buf + b_offset, data, eeprom->len);
6895         }
6896
6897         ret = tg3_nvram_write_block(tp, offset, len, buf);
6898
6899         if (buf != data)
6900                 kfree(buf);
6901
6902         return ret;
6903 }
6904
6905 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6906 {
6907         struct tg3 *tp = netdev_priv(dev);
6908
6909         cmd->supported = (SUPPORTED_Autoneg);
6910
6911         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6912                 cmd->supported |= (SUPPORTED_1000baseT_Half |
6913                                    SUPPORTED_1000baseT_Full);
6914
6915         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6916                 cmd->supported |= (SUPPORTED_100baseT_Half |
6917                                   SUPPORTED_100baseT_Full |
6918                                   SUPPORTED_10baseT_Half |
6919                                   SUPPORTED_10baseT_Full |
6920                                   SUPPORTED_MII);
6921         else
6922                 cmd->supported |= SUPPORTED_FIBRE;
6923
6924         cmd->advertising = tp->link_config.advertising;
6925         if (netif_running(dev)) {
6926                 cmd->speed = tp->link_config.active_speed;
6927                 cmd->duplex = tp->link_config.active_duplex;
6928         }
6929         cmd->port = 0;
6930         cmd->phy_address = PHY_ADDR;
6931         cmd->transceiver = 0;
6932         cmd->autoneg = tp->link_config.autoneg;
6933         cmd->maxtxpkt = 0;
6934         cmd->maxrxpkt = 0;
6935         return 0;
6936 }
6937
6938 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6939 {
6940         struct tg3 *tp = netdev_priv(dev);
6941
6942         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6943                 /* These are the only valid advertisement bits allowed.  */
6944                 if (cmd->autoneg == AUTONEG_ENABLE &&
6945                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6946                                           ADVERTISED_1000baseT_Full |
6947                                           ADVERTISED_Autoneg |
6948                                           ADVERTISED_FIBRE)))
6949                         return -EINVAL;
6950         }
6951
6952         tg3_full_lock(tp, 0);
6953
6954         tp->link_config.autoneg = cmd->autoneg;
6955         if (cmd->autoneg == AUTONEG_ENABLE) {
6956                 tp->link_config.advertising = cmd->advertising;
6957                 tp->link_config.speed = SPEED_INVALID;
6958                 tp->link_config.duplex = DUPLEX_INVALID;
6959         } else {
6960                 tp->link_config.advertising = 0;
6961                 tp->link_config.speed = cmd->speed;
6962                 tp->link_config.duplex = cmd->duplex;
6963         }
6964
6965         if (netif_running(dev))
6966                 tg3_setup_phy(tp, 1);
6967
6968         tg3_full_unlock(tp);
6969
6970         return 0;
6971 }
6972
6973 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6974 {
6975         struct tg3 *tp = netdev_priv(dev);
6976
6977         strcpy(info->driver, DRV_MODULE_NAME);
6978         strcpy(info->version, DRV_MODULE_VERSION);
6979         strcpy(info->bus_info, pci_name(tp->pdev));
6980 }
6981
6982 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6983 {
6984         struct tg3 *tp = netdev_priv(dev);
6985
6986         wol->supported = WAKE_MAGIC;
6987         wol->wolopts = 0;
6988         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
6989                 wol->wolopts = WAKE_MAGIC;
6990         memset(&wol->sopass, 0, sizeof(wol->sopass));
6991 }
6992
6993 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6994 {
6995         struct tg3 *tp = netdev_priv(dev);
6996
6997         if (wol->wolopts & ~WAKE_MAGIC)
6998                 return -EINVAL;
6999         if ((wol->wolopts & WAKE_MAGIC) &&
7000             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7001             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7002                 return -EINVAL;
7003
7004         spin_lock_bh(&tp->lock);
7005         if (wol->wolopts & WAKE_MAGIC)
7006                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7007         else
7008                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7009         spin_unlock_bh(&tp->lock);
7010
7011         return 0;
7012 }
7013
7014 static u32 tg3_get_msglevel(struct net_device *dev)
7015 {
7016         struct tg3 *tp = netdev_priv(dev);
7017         return tp->msg_enable;
7018 }
7019
7020 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7021 {
7022         struct tg3 *tp = netdev_priv(dev);
7023         tp->msg_enable = value;
7024 }
7025
7026 #if TG3_TSO_SUPPORT != 0
7027 static int tg3_set_tso(struct net_device *dev, u32 value)
7028 {
7029         struct tg3 *tp = netdev_priv(dev);
7030
7031         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7032                 if (value)
7033                         return -EINVAL;
7034                 return 0;
7035         }
7036         return ethtool_op_set_tso(dev, value);
7037 }
7038 #endif
7039
7040 static int tg3_nway_reset(struct net_device *dev)
7041 {
7042         struct tg3 *tp = netdev_priv(dev);
7043         u32 bmcr;
7044         int r;
7045
7046         if (!netif_running(dev))
7047                 return -EAGAIN;
7048
7049         spin_lock_bh(&tp->lock);
7050         r = -EINVAL;
7051         tg3_readphy(tp, MII_BMCR, &bmcr);
7052         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7053             (bmcr & BMCR_ANENABLE)) {
7054                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
7055                 r = 0;
7056         }
7057         spin_unlock_bh(&tp->lock);
7058
7059         return r;
7060 }
7061
7062 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7063 {
7064         struct tg3 *tp = netdev_priv(dev);
7065
7066         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7067         ering->rx_mini_max_pending = 0;
7068         ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7069
7070         ering->rx_pending = tp->rx_pending;
7071         ering->rx_mini_pending = 0;
7072         ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7073         ering->tx_pending = tp->tx_pending;
7074 }
7075
7076 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7077 {
7078         struct tg3 *tp = netdev_priv(dev);
7079         int irq_sync = 0;
7080
7081         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7082             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7083             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7084                 return -EINVAL;
7085
7086         if (netif_running(dev)) {
7087                 tg3_netif_stop(tp);
7088                 irq_sync = 1;
7089         }
7090
7091         tg3_full_lock(tp, irq_sync);
7092
7093         tp->rx_pending = ering->rx_pending;
7094
7095         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7096             tp->rx_pending > 63)
7097                 tp->rx_pending = 63;
7098         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7099         tp->tx_pending = ering->tx_pending;
7100
7101         if (netif_running(dev)) {
7102                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7103                 tg3_init_hw(tp);
7104                 tg3_netif_start(tp);
7105         }
7106
7107         tg3_full_unlock(tp);
7108
7109         return 0;
7110 }
7111
7112 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7113 {
7114         struct tg3 *tp = netdev_priv(dev);
7115
7116         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7117         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7118         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7119 }
7120
7121 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7122 {
7123         struct tg3 *tp = netdev_priv(dev);
7124         int irq_sync = 0;
7125
7126         if (netif_running(dev)) {
7127                 tg3_netif_stop(tp);
7128                 irq_sync = 1;
7129         }
7130
7131         tg3_full_lock(tp, irq_sync);
7132
7133         if (epause->autoneg)
7134                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7135         else
7136                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7137         if (epause->rx_pause)
7138                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7139         else
7140                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7141         if (epause->tx_pause)
7142                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7143         else
7144                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7145
7146         if (netif_running(dev)) {
7147                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7148                 tg3_init_hw(tp);
7149                 tg3_netif_start(tp);
7150         }
7151
7152         tg3_full_unlock(tp);
7153
7154         return 0;
7155 }
7156
7157 static u32 tg3_get_rx_csum(struct net_device *dev)
7158 {
7159         struct tg3 *tp = netdev_priv(dev);
7160         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7161 }
7162
7163 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7164 {
7165         struct tg3 *tp = netdev_priv(dev);
7166
7167         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7168                 if (data != 0)
7169                         return -EINVAL;
7170                 return 0;
7171         }
7172
7173         spin_lock_bh(&tp->lock);
7174         if (data)
7175                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7176         else
7177                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7178         spin_unlock_bh(&tp->lock);
7179
7180         return 0;
7181 }
7182
7183 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7184 {
7185         struct tg3 *tp = netdev_priv(dev);
7186
7187         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7188                 if (data != 0)
7189                         return -EINVAL;
7190                 return 0;
7191         }
7192
7193         if (data)
7194                 dev->features |= NETIF_F_IP_CSUM;
7195         else
7196                 dev->features &= ~NETIF_F_IP_CSUM;
7197
7198         return 0;
7199 }
7200
7201 static int tg3_get_stats_count (struct net_device *dev)
7202 {
7203         return TG3_NUM_STATS;
7204 }
7205
7206 static int tg3_get_test_count (struct net_device *dev)
7207 {
7208         return TG3_NUM_TEST;
7209 }
7210
7211 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7212 {
7213         switch (stringset) {
7214         case ETH_SS_STATS:
7215                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7216                 break;
7217         case ETH_SS_TEST:
7218                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7219                 break;
7220         default:
7221                 WARN_ON(1);     /* we need a WARN() */
7222                 break;
7223         }
7224 }
7225
7226 static void tg3_get_ethtool_stats (struct net_device *dev,
7227                                    struct ethtool_stats *estats, u64 *tmp_stats)
7228 {
7229         struct tg3 *tp = netdev_priv(dev);
7230         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7231 }
7232
7233 #define NVRAM_TEST_SIZE 0x100
7234
7235 static int tg3_test_nvram(struct tg3 *tp)
7236 {
7237         u32 *buf, csum;
7238         int i, j, err = 0;
7239
7240         buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7241         if (buf == NULL)
7242                 return -ENOMEM;
7243
7244         for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7245                 u32 val;
7246
7247                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7248                         break;
7249                 buf[j] = cpu_to_le32(val);
7250         }
7251         if (i < NVRAM_TEST_SIZE)
7252                 goto out;
7253
7254         err = -EIO;
7255         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7256                 goto out;
7257
7258         /* Bootstrap checksum at offset 0x10 */
7259         csum = calc_crc((unsigned char *) buf, 0x10);
7260         if(csum != cpu_to_le32(buf[0x10/4]))
7261                 goto out;
7262
7263         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7264         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7265         if (csum != cpu_to_le32(buf[0xfc/4]))
7266                  goto out;
7267
7268         err = 0;
7269
7270 out:
7271         kfree(buf);
7272         return err;
7273 }
7274
7275 #define TG3_SERDES_TIMEOUT_SEC  2
7276 #define TG3_COPPER_TIMEOUT_SEC  6
7277
7278 static int tg3_test_link(struct tg3 *tp)
7279 {
7280         int i, max;
7281
7282         if (!netif_running(tp->dev))
7283                 return -ENODEV;
7284
7285         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7286                 max = TG3_SERDES_TIMEOUT_SEC;
7287         else
7288                 max = TG3_COPPER_TIMEOUT_SEC;
7289
7290         for (i = 0; i < max; i++) {
7291                 if (netif_carrier_ok(tp->dev))
7292                         return 0;
7293
7294                 if (msleep_interruptible(1000))
7295                         break;
7296         }
7297
7298         return -EIO;
7299 }
7300
7301 /* Only test the commonly used registers */
7302 static int tg3_test_registers(struct tg3 *tp)
7303 {
7304         int i, is_5705;
7305         u32 offset, read_mask, write_mask, val, save_val, read_val;
7306         static struct {
7307                 u16 offset;
7308                 u16 flags;
7309 #define TG3_FL_5705     0x1
7310 #define TG3_FL_NOT_5705 0x2
7311 #define TG3_FL_NOT_5788 0x4
7312                 u32 read_mask;
7313                 u32 write_mask;
7314         } reg_tbl[] = {
7315                 /* MAC Control Registers */
7316                 { MAC_MODE, TG3_FL_NOT_5705,
7317                         0x00000000, 0x00ef6f8c },
7318                 { MAC_MODE, TG3_FL_5705,
7319                         0x00000000, 0x01ef6b8c },
7320                 { MAC_STATUS, TG3_FL_NOT_5705,
7321                         0x03800107, 0x00000000 },
7322                 { MAC_STATUS, TG3_FL_5705,
7323                         0x03800100, 0x00000000 },
7324                 { MAC_ADDR_0_HIGH, 0x0000,
7325                         0x00000000, 0x0000ffff },
7326                 { MAC_ADDR_0_LOW, 0x0000,
7327                         0x00000000, 0xffffffff },
7328                 { MAC_RX_MTU_SIZE, 0x0000,
7329                         0x00000000, 0x0000ffff },
7330                 { MAC_TX_MODE, 0x0000,
7331                         0x00000000, 0x00000070 },
7332                 { MAC_TX_LENGTHS, 0x0000,
7333                         0x00000000, 0x00003fff },
7334                 { MAC_RX_MODE, TG3_FL_NOT_5705,
7335                         0x00000000, 0x000007fc },
7336                 { MAC_RX_MODE, TG3_FL_5705,
7337                         0x00000000, 0x000007dc },
7338                 { MAC_HASH_REG_0, 0x0000,
7339                         0x00000000, 0xffffffff },
7340                 { MAC_HASH_REG_1, 0x0000,
7341                         0x00000000, 0xffffffff },
7342                 { MAC_HASH_REG_2, 0x0000,
7343                         0x00000000, 0xffffffff },
7344                 { MAC_HASH_REG_3, 0x0000,
7345                         0x00000000, 0xffffffff },
7346
7347                 /* Receive Data and Receive BD Initiator Control Registers. */
7348                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7349                         0x00000000, 0xffffffff },
7350                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7351                         0x00000000, 0xffffffff },
7352                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7353                         0x00000000, 0x00000003 },
7354                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7355                         0x00000000, 0xffffffff },
7356                 { RCVDBDI_STD_BD+0, 0x0000,
7357                         0x00000000, 0xffffffff },
7358                 { RCVDBDI_STD_BD+4, 0x0000,
7359                         0x00000000, 0xffffffff },
7360                 { RCVDBDI_STD_BD+8, 0x0000,
7361                         0x00000000, 0xffff0002 },
7362                 { RCVDBDI_STD_BD+0xc, 0x0000,
7363                         0x00000000, 0xffffffff },
7364
7365                 /* Receive BD Initiator Control Registers. */
7366                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7367                         0x00000000, 0xffffffff },
7368                 { RCVBDI_STD_THRESH, TG3_FL_5705,
7369                         0x00000000, 0x000003ff },
7370                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7371                         0x00000000, 0xffffffff },
7372
7373                 /* Host Coalescing Control Registers. */
7374                 { HOSTCC_MODE, TG3_FL_NOT_5705,
7375                         0x00000000, 0x00000004 },
7376                 { HOSTCC_MODE, TG3_FL_5705,
7377                         0x00000000, 0x000000f6 },
7378                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7379                         0x00000000, 0xffffffff },
7380                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7381                         0x00000000, 0x000003ff },
7382                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7383                         0x00000000, 0xffffffff },
7384                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7385                         0x00000000, 0x000003ff },
7386                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7387                         0x00000000, 0xffffffff },
7388                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7389                         0x00000000, 0x000000ff },
7390                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7391                         0x00000000, 0xffffffff },
7392                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7393                         0x00000000, 0x000000ff },
7394                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7395                         0x00000000, 0xffffffff },
7396                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7397                         0x00000000, 0xffffffff },
7398                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7399                         0x00000000, 0xffffffff },
7400                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7401                         0x00000000, 0x000000ff },
7402                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7403                         0x00000000, 0xffffffff },
7404                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7405                         0x00000000, 0x000000ff },
7406                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7407                         0x00000000, 0xffffffff },
7408                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7409                         0x00000000, 0xffffffff },
7410                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7411                         0x00000000, 0xffffffff },
7412                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7413                         0x00000000, 0xffffffff },
7414                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7415                         0x00000000, 0xffffffff },
7416                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7417                         0xffffffff, 0x00000000 },
7418                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7419                         0xffffffff, 0x00000000 },
7420
7421                 /* Buffer Manager Control Registers. */
7422                 { BUFMGR_MB_POOL_ADDR, 0x0000,
7423                         0x00000000, 0x007fff80 },
7424                 { BUFMGR_MB_POOL_SIZE, 0x0000,
7425                         0x00000000, 0x007fffff },
7426                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7427                         0x00000000, 0x0000003f },
7428                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7429                         0x00000000, 0x000001ff },
7430                 { BUFMGR_MB_HIGH_WATER, 0x0000,
7431                         0x00000000, 0x000001ff },
7432                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7433                         0xffffffff, 0x00000000 },
7434                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7435                         0xffffffff, 0x00000000 },
7436
7437                 /* Mailbox Registers */
7438                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7439                         0x00000000, 0x000001ff },
7440                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7441                         0x00000000, 0x000001ff },
7442                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7443                         0x00000000, 0x000007ff },
7444                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7445                         0x00000000, 0x000001ff },
7446
7447                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7448         };
7449
7450         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7451                 is_5705 = 1;
7452         else
7453                 is_5705 = 0;
7454
7455         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7456                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7457                         continue;
7458
7459                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7460                         continue;
7461
7462                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7463                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
7464                         continue;
7465
7466                 offset = (u32) reg_tbl[i].offset;
7467                 read_mask = reg_tbl[i].read_mask;
7468                 write_mask = reg_tbl[i].write_mask;
7469
7470                 /* Save the original register content */
7471                 save_val = tr32(offset);
7472
7473                 /* Determine the read-only value. */
7474                 read_val = save_val & read_mask;
7475
7476                 /* Write zero to the register, then make sure the read-only bits
7477                  * are not changed and the read/write bits are all zeros.
7478                  */
7479                 tw32(offset, 0);
7480
7481                 val = tr32(offset);
7482
7483                 /* Test the read-only and read/write bits. */
7484                 if (((val & read_mask) != read_val) || (val & write_mask))
7485                         goto out;
7486
7487                 /* Write ones to all the bits defined by RdMask and WrMask, then
7488                  * make sure the read-only bits are not changed and the
7489                  * read/write bits are all ones.
7490                  */
7491                 tw32(offset, read_mask | write_mask);
7492
7493                 val = tr32(offset);
7494
7495                 /* Test the read-only bits. */
7496                 if ((val & read_mask) != read_val)
7497                         goto out;
7498
7499                 /* Test the read/write bits. */
7500                 if ((val & write_mask) != write_mask)
7501                         goto out;
7502
7503                 tw32(offset, save_val);
7504         }
7505
7506         return 0;
7507
7508 out:
7509         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7510         tw32(offset, save_val);
7511         return -EIO;
7512 }
7513
7514 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7515 {
7516         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7517         int i;
7518         u32 j;
7519
7520         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7521                 for (j = 0; j < len; j += 4) {
7522                         u32 val;
7523
7524                         tg3_write_mem(tp, offset + j, test_pattern[i]);
7525                         tg3_read_mem(tp, offset + j, &val);
7526                         if (val != test_pattern[i])
7527                                 return -EIO;
7528                 }
7529         }
7530         return 0;
7531 }
7532
7533 static int tg3_test_memory(struct tg3 *tp)
7534 {
7535         static struct mem_entry {
7536                 u32 offset;
7537                 u32 len;
7538         } mem_tbl_570x[] = {
7539                 { 0x00000000, 0x01000},
7540                 { 0x00002000, 0x1c000},
7541                 { 0xffffffff, 0x00000}
7542         }, mem_tbl_5705[] = {
7543                 { 0x00000100, 0x0000c},
7544                 { 0x00000200, 0x00008},
7545                 { 0x00000b50, 0x00400},
7546                 { 0x00004000, 0x00800},
7547                 { 0x00006000, 0x01000},
7548                 { 0x00008000, 0x02000},
7549                 { 0x00010000, 0x0e000},
7550                 { 0xffffffff, 0x00000}
7551         };
7552         struct mem_entry *mem_tbl;
7553         int err = 0;
7554         int i;
7555
7556         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7557                 mem_tbl = mem_tbl_5705;
7558         else
7559                 mem_tbl = mem_tbl_570x;
7560
7561         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7562                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7563                     mem_tbl[i].len)) != 0)
7564                         break;
7565         }
7566
7567         return err;
7568 }
7569
7570 static int tg3_test_loopback(struct tg3 *tp)
7571 {
7572         u32 mac_mode, send_idx, rx_start_idx, rx_idx, tx_idx, opaque_key;
7573         u32 desc_idx;
7574         struct sk_buff *skb, *rx_skb;
7575         u8 *tx_data;
7576         dma_addr_t map;
7577         int num_pkts, tx_len, rx_len, i, err;
7578         struct tg3_rx_buffer_desc *desc;
7579
7580         if (!netif_running(tp->dev))
7581                 return -ENODEV;
7582
7583         err = -EIO;
7584
7585         tg3_abort_hw(tp, 1);
7586
7587         tg3_reset_hw(tp);
7588
7589         mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7590                    MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7591                    MAC_MODE_PORT_MODE_GMII;
7592         tw32(MAC_MODE, mac_mode);
7593
7594         tx_len = 1514;
7595         skb = dev_alloc_skb(tx_len);
7596         tx_data = skb_put(skb, tx_len);
7597         memcpy(tx_data, tp->dev->dev_addr, 6);
7598         memset(tx_data + 6, 0x0, 8);
7599
7600         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
7601
7602         for (i = 14; i < tx_len; i++)
7603                 tx_data[i] = (u8) (i & 0xff);
7604
7605         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
7606
7607         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7608              HOSTCC_MODE_NOW);
7609
7610         udelay(10);
7611
7612         rx_start_idx = tp->hw_status->idx[0].rx_producer;
7613
7614         send_idx = 0;
7615         num_pkts = 0;
7616
7617         tg3_set_txd(tp, send_idx, map, tx_len, 0, 1);
7618
7619         send_idx++;
7620         num_pkts++;
7621
7622         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx);
7623         tr32(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
7624
7625         udelay(10);
7626
7627         for (i = 0; i < 10; i++) {
7628                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7629                        HOSTCC_MODE_NOW);
7630
7631                 udelay(10);
7632
7633                 tx_idx = tp->hw_status->idx[0].tx_consumer;
7634                 rx_idx = tp->hw_status->idx[0].rx_producer;
7635                 if ((tx_idx == send_idx) &&
7636                     (rx_idx == (rx_start_idx + num_pkts)))
7637                         break;
7638         }
7639
7640         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
7641         dev_kfree_skb(skb);
7642
7643         if (tx_idx != send_idx)
7644                 goto out;
7645
7646         if (rx_idx != rx_start_idx + num_pkts)
7647                 goto out;
7648
7649         desc = &tp->rx_rcb[rx_start_idx];
7650         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
7651         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
7652         if (opaque_key != RXD_OPAQUE_RING_STD)
7653                 goto out;
7654
7655         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
7656             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
7657                 goto out;
7658
7659         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
7660         if (rx_len != tx_len)
7661                 goto out;
7662
7663         rx_skb = tp->rx_std_buffers[desc_idx].skb;
7664
7665         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
7666         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
7667
7668         for (i = 14; i < tx_len; i++) {
7669                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
7670                         goto out;
7671         }
7672         err = 0;
7673
7674         /* tg3_free_rings will unmap and free the rx_skb */
7675 out:
7676         return err;
7677 }
7678
7679 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
7680                           u64 *data)
7681 {
7682         struct tg3 *tp = netdev_priv(dev);
7683
7684         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
7685
7686         if (tg3_test_nvram(tp) != 0) {
7687                 etest->flags |= ETH_TEST_FL_FAILED;
7688                 data[0] = 1;
7689         }
7690         if (tg3_test_link(tp) != 0) {
7691                 etest->flags |= ETH_TEST_FL_FAILED;
7692                 data[1] = 1;
7693         }
7694         if (etest->flags & ETH_TEST_FL_OFFLINE) {
7695                 int irq_sync = 0;
7696
7697                 if (netif_running(dev)) {
7698                         tg3_netif_stop(tp);
7699                         irq_sync = 1;
7700                 }
7701
7702                 tg3_full_lock(tp, irq_sync);
7703
7704                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
7705                 tg3_nvram_lock(tp);
7706                 tg3_halt_cpu(tp, RX_CPU_BASE);
7707                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7708                         tg3_halt_cpu(tp, TX_CPU_BASE);
7709                 tg3_nvram_unlock(tp);
7710
7711                 if (tg3_test_registers(tp) != 0) {
7712                         etest->flags |= ETH_TEST_FL_FAILED;
7713                         data[2] = 1;
7714                 }
7715                 if (tg3_test_memory(tp) != 0) {
7716                         etest->flags |= ETH_TEST_FL_FAILED;
7717                         data[3] = 1;
7718                 }
7719                 if (tg3_test_loopback(tp) != 0) {
7720                         etest->flags |= ETH_TEST_FL_FAILED;
7721                         data[4] = 1;
7722                 }
7723
7724                 tg3_full_unlock(tp);
7725
7726                 if (tg3_test_interrupt(tp) != 0) {
7727                         etest->flags |= ETH_TEST_FL_FAILED;
7728                         data[5] = 1;
7729                 }
7730
7731                 tg3_full_lock(tp, 0);
7732
7733                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7734                 if (netif_running(dev)) {
7735                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7736                         tg3_init_hw(tp);
7737                         tg3_netif_start(tp);
7738                 }
7739
7740                 tg3_full_unlock(tp);
7741         }
7742 }
7743
7744 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7745 {
7746         struct mii_ioctl_data *data = if_mii(ifr);
7747         struct tg3 *tp = netdev_priv(dev);
7748         int err;
7749
7750         switch(cmd) {
7751         case SIOCGMIIPHY:
7752                 data->phy_id = PHY_ADDR;
7753
7754                 /* fallthru */
7755         case SIOCGMIIREG: {
7756                 u32 mii_regval;
7757
7758                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7759                         break;                  /* We have no PHY */
7760
7761                 spin_lock_bh(&tp->lock);
7762                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
7763                 spin_unlock_bh(&tp->lock);
7764
7765                 data->val_out = mii_regval;
7766
7767                 return err;
7768         }
7769
7770         case SIOCSMIIREG:
7771                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7772                         break;                  /* We have no PHY */
7773
7774                 if (!capable(CAP_NET_ADMIN))
7775                         return -EPERM;
7776
7777                 spin_lock_bh(&tp->lock);
7778                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
7779                 spin_unlock_bh(&tp->lock);
7780
7781                 return err;
7782
7783         default:
7784                 /* do nothing */
7785                 break;
7786         }
7787         return -EOPNOTSUPP;
7788 }
7789
7790 #if TG3_VLAN_TAG_USED
7791 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
7792 {
7793         struct tg3 *tp = netdev_priv(dev);
7794
7795         tg3_full_lock(tp, 0);
7796
7797         tp->vlgrp = grp;
7798
7799         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7800         __tg3_set_rx_mode(dev);
7801
7802         tg3_full_unlock(tp);
7803 }
7804
7805 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7806 {
7807         struct tg3 *tp = netdev_priv(dev);
7808
7809         tg3_full_lock(tp, 0);
7810         if (tp->vlgrp)
7811                 tp->vlgrp->vlan_devices[vid] = NULL;
7812         tg3_full_unlock(tp);
7813 }
7814 #endif
7815
7816 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7817 {
7818         struct tg3 *tp = netdev_priv(dev);
7819
7820         memcpy(ec, &tp->coal, sizeof(*ec));
7821         return 0;
7822 }
7823
7824 static struct ethtool_ops tg3_ethtool_ops = {
7825         .get_settings           = tg3_get_settings,
7826         .set_settings           = tg3_set_settings,
7827         .get_drvinfo            = tg3_get_drvinfo,
7828         .get_regs_len           = tg3_get_regs_len,
7829         .get_regs               = tg3_get_regs,
7830         .get_wol                = tg3_get_wol,
7831         .set_wol                = tg3_set_wol,
7832         .get_msglevel           = tg3_get_msglevel,
7833         .set_msglevel           = tg3_set_msglevel,
7834         .nway_reset             = tg3_nway_reset,
7835         .get_link               = ethtool_op_get_link,
7836         .get_eeprom_len         = tg3_get_eeprom_len,
7837         .get_eeprom             = tg3_get_eeprom,
7838         .set_eeprom             = tg3_set_eeprom,
7839         .get_ringparam          = tg3_get_ringparam,
7840         .set_ringparam          = tg3_set_ringparam,
7841         .get_pauseparam         = tg3_get_pauseparam,
7842         .set_pauseparam         = tg3_set_pauseparam,
7843         .get_rx_csum            = tg3_get_rx_csum,
7844         .set_rx_csum            = tg3_set_rx_csum,
7845         .get_tx_csum            = ethtool_op_get_tx_csum,
7846         .set_tx_csum            = tg3_set_tx_csum,
7847         .get_sg                 = ethtool_op_get_sg,
7848         .set_sg                 = ethtool_op_set_sg,
7849 #if TG3_TSO_SUPPORT != 0
7850         .get_tso                = ethtool_op_get_tso,
7851         .set_tso                = tg3_set_tso,
7852 #endif
7853         .self_test_count        = tg3_get_test_count,
7854         .self_test              = tg3_self_test,
7855         .get_strings            = tg3_get_strings,
7856         .get_stats_count        = tg3_get_stats_count,
7857         .get_ethtool_stats      = tg3_get_ethtool_stats,
7858         .get_coalesce           = tg3_get_coalesce,
7859 };
7860
7861 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7862 {
7863         u32 cursize, val;
7864
7865         tp->nvram_size = EEPROM_CHIP_SIZE;
7866
7867         if (tg3_nvram_read(tp, 0, &val) != 0)
7868                 return;
7869
7870         if (swab32(val) != TG3_EEPROM_MAGIC)
7871                 return;
7872
7873         /*
7874          * Size the chip by reading offsets at increasing powers of two.
7875          * When we encounter our validation signature, we know the addressing
7876          * has wrapped around, and thus have our chip size.
7877          */
7878         cursize = 0x800;
7879
7880         while (cursize < tp->nvram_size) {
7881                 if (tg3_nvram_read(tp, cursize, &val) != 0)
7882                         return;
7883
7884                 if (swab32(val) == TG3_EEPROM_MAGIC)
7885                         break;
7886
7887                 cursize <<= 1;
7888         }
7889
7890         tp->nvram_size = cursize;
7891 }
7892
7893 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7894 {
7895         u32 val;
7896
7897         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7898                 if (val != 0) {
7899                         tp->nvram_size = (val >> 16) * 1024;
7900                         return;
7901                 }
7902         }
7903         tp->nvram_size = 0x20000;
7904 }
7905
7906 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7907 {
7908         u32 nvcfg1;
7909
7910         nvcfg1 = tr32(NVRAM_CFG1);
7911         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
7912                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7913         }
7914         else {
7915                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7916                 tw32(NVRAM_CFG1, nvcfg1);
7917         }
7918
7919         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7920                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7921                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7922                                 tp->nvram_jedecnum = JEDEC_ATMEL;
7923                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7924                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7925                                 break;
7926                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
7927                                 tp->nvram_jedecnum = JEDEC_ATMEL;
7928                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
7929                                 break;
7930                         case FLASH_VENDOR_ATMEL_EEPROM:
7931                                 tp->nvram_jedecnum = JEDEC_ATMEL;
7932                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7933                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7934                                 break;
7935                         case FLASH_VENDOR_ST:
7936                                 tp->nvram_jedecnum = JEDEC_ST;
7937                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
7938                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7939                                 break;
7940                         case FLASH_VENDOR_SAIFUN:
7941                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
7942                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
7943                                 break;
7944                         case FLASH_VENDOR_SST_SMALL:
7945                         case FLASH_VENDOR_SST_LARGE:
7946                                 tp->nvram_jedecnum = JEDEC_SST;
7947                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
7948                                 break;
7949                 }
7950         }
7951         else {
7952                 tp->nvram_jedecnum = JEDEC_ATMEL;
7953                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7954                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7955         }
7956 }
7957
7958 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
7959 {
7960         u32 nvcfg1;
7961
7962         nvcfg1 = tr32(NVRAM_CFG1);
7963
7964         /* NVRAM protection for TPM */
7965         if (nvcfg1 & (1 << 27))
7966                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
7967
7968         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
7969                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
7970                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
7971                         tp->nvram_jedecnum = JEDEC_ATMEL;
7972                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7973                         break;
7974                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
7975                         tp->nvram_jedecnum = JEDEC_ATMEL;
7976                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7977                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
7978                         break;
7979                 case FLASH_5752VENDOR_ST_M45PE10:
7980                 case FLASH_5752VENDOR_ST_M45PE20:
7981                 case FLASH_5752VENDOR_ST_M45PE40:
7982                         tp->nvram_jedecnum = JEDEC_ST;
7983                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7984                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
7985                         break;
7986         }
7987
7988         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
7989                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
7990                         case FLASH_5752PAGE_SIZE_256:
7991                                 tp->nvram_pagesize = 256;
7992                                 break;
7993                         case FLASH_5752PAGE_SIZE_512:
7994                                 tp->nvram_pagesize = 512;
7995                                 break;
7996                         case FLASH_5752PAGE_SIZE_1K:
7997                                 tp->nvram_pagesize = 1024;
7998                                 break;
7999                         case FLASH_5752PAGE_SIZE_2K:
8000                                 tp->nvram_pagesize = 2048;
8001                                 break;
8002                         case FLASH_5752PAGE_SIZE_4K:
8003                                 tp->nvram_pagesize = 4096;
8004                                 break;
8005                         case FLASH_5752PAGE_SIZE_264:
8006                                 tp->nvram_pagesize = 264;
8007                                 break;
8008                 }
8009         }
8010         else {
8011                 /* For eeprom, set pagesize to maximum eeprom size */
8012                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8013
8014                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8015                 tw32(NVRAM_CFG1, nvcfg1);
8016         }
8017 }
8018
8019 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
8020 static void __devinit tg3_nvram_init(struct tg3 *tp)
8021 {
8022         int j;
8023
8024         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8025                 return;
8026
8027         tw32_f(GRC_EEPROM_ADDR,
8028              (EEPROM_ADDR_FSM_RESET |
8029               (EEPROM_DEFAULT_CLOCK_PERIOD <<
8030                EEPROM_ADDR_CLKPERD_SHIFT)));
8031
8032         /* XXX schedule_timeout() ... */
8033         for (j = 0; j < 100; j++)
8034                 udelay(10);
8035
8036         /* Enable seeprom accesses. */
8037         tw32_f(GRC_LOCAL_CTRL,
8038              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8039         udelay(100);
8040
8041         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8042             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8043                 tp->tg3_flags |= TG3_FLAG_NVRAM;
8044
8045                 tg3_enable_nvram_access(tp);
8046
8047                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8048                         tg3_get_5752_nvram_info(tp);
8049                 else
8050                         tg3_get_nvram_info(tp);
8051
8052                 tg3_get_nvram_size(tp);
8053
8054                 tg3_disable_nvram_access(tp);
8055
8056         } else {
8057                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8058
8059                 tg3_get_eeprom_size(tp);
8060         }
8061 }
8062
8063 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8064                                         u32 offset, u32 *val)
8065 {
8066         u32 tmp;
8067         int i;
8068
8069         if (offset > EEPROM_ADDR_ADDR_MASK ||
8070             (offset % 4) != 0)
8071                 return -EINVAL;
8072
8073         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8074                                         EEPROM_ADDR_DEVID_MASK |
8075                                         EEPROM_ADDR_READ);
8076         tw32(GRC_EEPROM_ADDR,
8077              tmp |
8078              (0 << EEPROM_ADDR_DEVID_SHIFT) |
8079              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8080               EEPROM_ADDR_ADDR_MASK) |
8081              EEPROM_ADDR_READ | EEPROM_ADDR_START);
8082
8083         for (i = 0; i < 10000; i++) {
8084                 tmp = tr32(GRC_EEPROM_ADDR);
8085
8086                 if (tmp & EEPROM_ADDR_COMPLETE)
8087                         break;
8088                 udelay(100);
8089         }
8090         if (!(tmp & EEPROM_ADDR_COMPLETE))
8091                 return -EBUSY;
8092
8093         *val = tr32(GRC_EEPROM_DATA);
8094         return 0;
8095 }
8096
8097 #define NVRAM_CMD_TIMEOUT 10000
8098
8099 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8100 {
8101         int i;
8102
8103         tw32(NVRAM_CMD, nvram_cmd);
8104         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8105                 udelay(10);
8106                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8107                         udelay(10);
8108                         break;
8109                 }
8110         }
8111         if (i == NVRAM_CMD_TIMEOUT) {
8112                 return -EBUSY;
8113         }
8114         return 0;
8115 }
8116
8117 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8118 {
8119         int ret;
8120
8121         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8122                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8123                 return -EINVAL;
8124         }
8125
8126         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8127                 return tg3_nvram_read_using_eeprom(tp, offset, val);
8128
8129         if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8130                 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8131                 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8132
8133                 offset = ((offset / tp->nvram_pagesize) <<
8134                           ATMEL_AT45DB0X1B_PAGE_POS) +
8135                         (offset % tp->nvram_pagesize);
8136         }
8137
8138         if (offset > NVRAM_ADDR_MSK)
8139                 return -EINVAL;
8140
8141         tg3_nvram_lock(tp);
8142
8143         tg3_enable_nvram_access(tp);
8144
8145         tw32(NVRAM_ADDR, offset);
8146         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8147                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8148
8149         if (ret == 0)
8150                 *val = swab32(tr32(NVRAM_RDDATA));
8151
8152         tg3_nvram_unlock(tp);
8153
8154         tg3_disable_nvram_access(tp);
8155
8156         return ret;
8157 }
8158
8159 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8160                                     u32 offset, u32 len, u8 *buf)
8161 {
8162         int i, j, rc = 0;
8163         u32 val;
8164
8165         for (i = 0; i < len; i += 4) {
8166                 u32 addr, data;
8167
8168                 addr = offset + i;
8169
8170                 memcpy(&data, buf + i, 4);
8171
8172                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8173
8174                 val = tr32(GRC_EEPROM_ADDR);
8175                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8176
8177                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8178                         EEPROM_ADDR_READ);
8179                 tw32(GRC_EEPROM_ADDR, val |
8180                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
8181                         (addr & EEPROM_ADDR_ADDR_MASK) |
8182                         EEPROM_ADDR_START |
8183                         EEPROM_ADDR_WRITE);
8184
8185                 for (j = 0; j < 10000; j++) {
8186                         val = tr32(GRC_EEPROM_ADDR);
8187
8188                         if (val & EEPROM_ADDR_COMPLETE)
8189                                 break;
8190                         udelay(100);
8191                 }
8192                 if (!(val & EEPROM_ADDR_COMPLETE)) {
8193                         rc = -EBUSY;
8194                         break;
8195                 }
8196         }
8197
8198         return rc;
8199 }
8200
8201 /* offset and length are dword aligned */
8202 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8203                 u8 *buf)
8204 {
8205         int ret = 0;
8206         u32 pagesize = tp->nvram_pagesize;
8207         u32 pagemask = pagesize - 1;
8208         u32 nvram_cmd;
8209         u8 *tmp;
8210
8211         tmp = kmalloc(pagesize, GFP_KERNEL);
8212         if (tmp == NULL)
8213                 return -ENOMEM;
8214
8215         while (len) {
8216                 int j;
8217                 u32 phy_addr, page_off, size;
8218
8219                 phy_addr = offset & ~pagemask;
8220
8221                 for (j = 0; j < pagesize; j += 4) {
8222                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
8223                                                 (u32 *) (tmp + j))))
8224                                 break;
8225                 }
8226                 if (ret)
8227                         break;
8228
8229                 page_off = offset & pagemask;
8230                 size = pagesize;
8231                 if (len < size)
8232                         size = len;
8233
8234                 len -= size;
8235
8236                 memcpy(tmp + page_off, buf, size);
8237
8238                 offset = offset + (pagesize - page_off);
8239
8240                 tg3_enable_nvram_access(tp);
8241
8242                 /*
8243                  * Before we can erase the flash page, we need
8244                  * to issue a special "write enable" command.
8245                  */
8246                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8247
8248                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8249                         break;
8250
8251                 /* Erase the target page */
8252                 tw32(NVRAM_ADDR, phy_addr);
8253
8254                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8255                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8256
8257                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8258                         break;
8259
8260                 /* Issue another write enable to start the write. */
8261                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8262
8263                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8264                         break;
8265
8266                 for (j = 0; j < pagesize; j += 4) {
8267                         u32 data;
8268
8269                         data = *((u32 *) (tmp + j));
8270                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
8271
8272                         tw32(NVRAM_ADDR, phy_addr + j);
8273
8274                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8275                                 NVRAM_CMD_WR;
8276
8277                         if (j == 0)
8278                                 nvram_cmd |= NVRAM_CMD_FIRST;
8279                         else if (j == (pagesize - 4))
8280                                 nvram_cmd |= NVRAM_CMD_LAST;
8281
8282                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8283                                 break;
8284                 }
8285                 if (ret)
8286                         break;
8287         }
8288
8289         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8290         tg3_nvram_exec_cmd(tp, nvram_cmd);
8291
8292         kfree(tmp);
8293
8294         return ret;
8295 }
8296
8297 /* offset and length are dword aligned */
8298 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8299                 u8 *buf)
8300 {
8301         int i, ret = 0;
8302
8303         for (i = 0; i < len; i += 4, offset += 4) {
8304                 u32 data, page_off, phy_addr, nvram_cmd;
8305
8306                 memcpy(&data, buf + i, 4);
8307                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8308
8309                 page_off = offset % tp->nvram_pagesize;
8310
8311                 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8312                         (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8313
8314                         phy_addr = ((offset / tp->nvram_pagesize) <<
8315                                     ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8316                 }
8317                 else {
8318                         phy_addr = offset;
8319                 }
8320
8321                 tw32(NVRAM_ADDR, phy_addr);
8322
8323                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8324
8325                 if ((page_off == 0) || (i == 0))
8326                         nvram_cmd |= NVRAM_CMD_FIRST;
8327                 else if (page_off == (tp->nvram_pagesize - 4))
8328                         nvram_cmd |= NVRAM_CMD_LAST;
8329
8330                 if (i == (len - 4))
8331                         nvram_cmd |= NVRAM_CMD_LAST;
8332
8333                 if ((tp->nvram_jedecnum == JEDEC_ST) &&
8334                         (nvram_cmd & NVRAM_CMD_FIRST)) {
8335
8336                         if ((ret = tg3_nvram_exec_cmd(tp,
8337                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8338                                 NVRAM_CMD_DONE)))
8339
8340                                 break;
8341                 }
8342                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8343                         /* We always do complete word writes to eeprom. */
8344                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8345                 }
8346
8347                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8348                         break;
8349         }
8350         return ret;
8351 }
8352
8353 /* offset and length are dword aligned */
8354 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8355 {
8356         int ret;
8357
8358         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8359                 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8360                 return -EINVAL;
8361         }
8362
8363         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8364                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8365                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
8366                 udelay(40);
8367         }
8368
8369         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8370                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8371         }
8372         else {
8373                 u32 grc_mode;
8374
8375                 tg3_nvram_lock(tp);
8376
8377                 tg3_enable_nvram_access(tp);
8378                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8379                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
8380                         tw32(NVRAM_WRITE1, 0x406);
8381
8382                 grc_mode = tr32(GRC_MODE);
8383                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8384
8385                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8386                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8387
8388                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
8389                                 buf);
8390                 }
8391                 else {
8392                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8393                                 buf);
8394                 }
8395
8396                 grc_mode = tr32(GRC_MODE);
8397                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8398
8399                 tg3_disable_nvram_access(tp);
8400                 tg3_nvram_unlock(tp);
8401         }
8402
8403         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8404                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8405                 udelay(40);
8406         }
8407
8408         return ret;
8409 }
8410
8411 struct subsys_tbl_ent {
8412         u16 subsys_vendor, subsys_devid;
8413         u32 phy_id;
8414 };
8415
8416 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8417         /* Broadcom boards. */
8418         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8419         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8420         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8421         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
8422         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8423         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8424         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
8425         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8426         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8427         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8428         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8429
8430         /* 3com boards. */
8431         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8432         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8433         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
8434         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8435         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8436
8437         /* DELL boards. */
8438         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8439         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8440         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8441         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8442
8443         /* Compaq boards. */
8444         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8445         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8446         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
8447         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8448         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8449
8450         /* IBM boards. */
8451         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8452 };
8453
8454 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8455 {
8456         int i;
8457
8458         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8459                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8460                      tp->pdev->subsystem_vendor) &&
8461                     (subsys_id_to_phy_id[i].subsys_devid ==
8462                      tp->pdev->subsystem_device))
8463                         return &subsys_id_to_phy_id[i];
8464         }
8465         return NULL;
8466 }
8467
8468 /* Since this function may be called in D3-hot power state during
8469  * tg3_init_one(), only config cycles are allowed.
8470  */
8471 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
8472 {
8473         u32 val;
8474
8475         /* Make sure register accesses (indirect or otherwise)
8476          * will function correctly.
8477          */
8478         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8479                                tp->misc_host_ctrl);
8480
8481         tp->phy_id = PHY_ID_INVALID;
8482         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8483
8484         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8485         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8486                 u32 nic_cfg, led_cfg;
8487                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
8488                 int eeprom_phy_serdes = 0;
8489
8490                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8491                 tp->nic_sram_data_cfg = nic_cfg;
8492
8493                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
8494                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
8495                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8496                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8497                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
8498                     (ver > 0) && (ver < 0x100))
8499                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
8500
8501                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
8502                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
8503                         eeprom_phy_serdes = 1;
8504
8505                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
8506                 if (nic_phy_id != 0) {
8507                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
8508                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
8509
8510                         eeprom_phy_id  = (id1 >> 16) << 10;
8511                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
8512                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
8513                 } else
8514                         eeprom_phy_id = 0;
8515
8516                 tp->phy_id = eeprom_phy_id;
8517                 if (eeprom_phy_serdes)
8518                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8519
8520                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8521                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
8522                                     SHASTA_EXT_LED_MODE_MASK);
8523                 else
8524                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8525
8526                 switch (led_cfg) {
8527                 default:
8528                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8529                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8530                         break;
8531
8532                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
8533                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8534                         break;
8535
8536                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
8537                         tp->led_ctrl = LED_CTRL_MODE_MAC;
8538
8539                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
8540                          * read on some older 5700/5701 bootcode.
8541                          */
8542                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
8543                             ASIC_REV_5700 ||
8544                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
8545                             ASIC_REV_5701)
8546                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8547
8548                         break;
8549
8550                 case SHASTA_EXT_LED_SHARED:
8551                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
8552                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8553                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
8554                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8555                                                  LED_CTRL_MODE_PHY_2);
8556                         break;
8557
8558                 case SHASTA_EXT_LED_MAC:
8559                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
8560                         break;
8561
8562                 case SHASTA_EXT_LED_COMBO:
8563                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
8564                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
8565                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8566                                                  LED_CTRL_MODE_PHY_2);
8567                         break;
8568
8569                 };
8570
8571                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8572                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
8573                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
8574                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8575
8576                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8577                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8578                     (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
8579                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
8580
8581                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8582                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
8583                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8584                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
8585                 }
8586                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
8587                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
8588
8589                 if (cfg2 & (1 << 17))
8590                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
8591
8592                 /* serdes signal pre-emphasis in register 0x590 set by */
8593                 /* bootcode if bit 18 is set */
8594                 if (cfg2 & (1 << 18))
8595                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8596         }
8597 }
8598
8599 static int __devinit tg3_phy_probe(struct tg3 *tp)
8600 {
8601         u32 hw_phy_id_1, hw_phy_id_2;
8602         u32 hw_phy_id, hw_phy_id_masked;
8603         int err;
8604
8605         /* Reading the PHY ID register can conflict with ASF
8606          * firwmare access to the PHY hardware.
8607          */
8608         err = 0;
8609         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
8610                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
8611         } else {
8612                 /* Now read the physical PHY_ID from the chip and verify
8613                  * that it is sane.  If it doesn't look good, we fall back
8614                  * to either the hard-coded table based PHY_ID and failing
8615                  * that the value found in the eeprom area.
8616                  */
8617                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
8618                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
8619
8620                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
8621                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
8622                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
8623
8624                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
8625         }
8626
8627         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
8628                 tp->phy_id = hw_phy_id;
8629                 if (hw_phy_id_masked == PHY_ID_BCM8002)
8630                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8631         } else {
8632                 if (tp->phy_id != PHY_ID_INVALID) {
8633                         /* Do nothing, phy ID already set up in
8634                          * tg3_get_eeprom_hw_cfg().
8635                          */
8636                 } else {
8637                         struct subsys_tbl_ent *p;
8638
8639                         /* No eeprom signature?  Try the hardcoded
8640                          * subsys device table.
8641                          */
8642                         p = lookup_by_subsys(tp);
8643                         if (!p)
8644                                 return -ENODEV;
8645
8646                         tp->phy_id = p->phy_id;
8647                         if (!tp->phy_id ||
8648                             tp->phy_id == PHY_ID_BCM8002)
8649                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8650                 }
8651         }
8652
8653         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8654             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
8655                 u32 bmsr, adv_reg, tg3_ctrl;
8656
8657                 tg3_readphy(tp, MII_BMSR, &bmsr);
8658                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
8659                     (bmsr & BMSR_LSTATUS))
8660                         goto skip_phy_reset;
8661
8662                 err = tg3_phy_reset(tp);
8663                 if (err)
8664                         return err;
8665
8666                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
8667                            ADVERTISE_100HALF | ADVERTISE_100FULL |
8668                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
8669                 tg3_ctrl = 0;
8670                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
8671                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
8672                                     MII_TG3_CTRL_ADV_1000_FULL);
8673                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8674                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
8675                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
8676                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
8677                 }
8678
8679                 if (!tg3_copper_is_advertising_all(tp)) {
8680                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8681
8682                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8683                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8684
8685                         tg3_writephy(tp, MII_BMCR,
8686                                      BMCR_ANENABLE | BMCR_ANRESTART);
8687                 }
8688                 tg3_phy_set_wirespeed(tp);
8689
8690                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8691                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8692                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8693         }
8694
8695 skip_phy_reset:
8696         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8697                 err = tg3_init_5401phy_dsp(tp);
8698                 if (err)
8699                         return err;
8700         }
8701
8702         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
8703                 err = tg3_init_5401phy_dsp(tp);
8704         }
8705
8706         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8707                 tp->link_config.advertising =
8708                         (ADVERTISED_1000baseT_Half |
8709                          ADVERTISED_1000baseT_Full |
8710                          ADVERTISED_Autoneg |
8711                          ADVERTISED_FIBRE);
8712         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8713                 tp->link_config.advertising &=
8714                         ~(ADVERTISED_1000baseT_Half |
8715                           ADVERTISED_1000baseT_Full);
8716
8717         return err;
8718 }
8719
8720 static void __devinit tg3_read_partno(struct tg3 *tp)
8721 {
8722         unsigned char vpd_data[256];
8723         int i;
8724
8725         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8726                 /* Sun decided not to put the necessary bits in the
8727                  * NVRAM of their onboard tg3 parts :(
8728                  */
8729                 strcpy(tp->board_part_number, "Sun 570X");
8730                 return;
8731         }
8732
8733         for (i = 0; i < 256; i += 4) {
8734                 u32 tmp;
8735
8736                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
8737                         goto out_not_found;
8738
8739                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
8740                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
8741                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
8742                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
8743         }
8744
8745         /* Now parse and find the part number. */
8746         for (i = 0; i < 256; ) {
8747                 unsigned char val = vpd_data[i];
8748                 int block_end;
8749
8750                 if (val == 0x82 || val == 0x91) {
8751                         i = (i + 3 +
8752                              (vpd_data[i + 1] +
8753                               (vpd_data[i + 2] << 8)));
8754                         continue;
8755                 }
8756
8757                 if (val != 0x90)
8758                         goto out_not_found;
8759
8760                 block_end = (i + 3 +
8761                              (vpd_data[i + 1] +
8762                               (vpd_data[i + 2] << 8)));
8763                 i += 3;
8764                 while (i < block_end) {
8765                         if (vpd_data[i + 0] == 'P' &&
8766                             vpd_data[i + 1] == 'N') {
8767                                 int partno_len = vpd_data[i + 2];
8768
8769                                 if (partno_len > 24)
8770                                         goto out_not_found;
8771
8772                                 memcpy(tp->board_part_number,
8773                                        &vpd_data[i + 3],
8774                                        partno_len);
8775
8776                                 /* Success. */
8777                                 return;
8778                         }
8779                 }
8780
8781                 /* Part number not found. */
8782                 goto out_not_found;
8783         }
8784
8785 out_not_found:
8786         strcpy(tp->board_part_number, "none");
8787 }
8788
8789 #ifdef CONFIG_SPARC64
8790 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
8791 {
8792         struct pci_dev *pdev = tp->pdev;
8793         struct pcidev_cookie *pcp = pdev->sysdata;
8794
8795         if (pcp != NULL) {
8796                 int node = pcp->prom_node;
8797                 u32 venid;
8798                 int err;
8799
8800                 err = prom_getproperty(node, "subsystem-vendor-id",
8801                                        (char *) &venid, sizeof(venid));
8802                 if (err == 0 || err == -1)
8803                         return 0;
8804                 if (venid == PCI_VENDOR_ID_SUN)
8805                         return 1;
8806         }
8807         return 0;
8808 }
8809 #endif
8810
8811 static int __devinit tg3_get_invariants(struct tg3 *tp)
8812 {
8813         static struct pci_device_id write_reorder_chipsets[] = {
8814                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8815                              PCI_DEVICE_ID_INTEL_82801AA_8) },
8816                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8817                              PCI_DEVICE_ID_INTEL_82801AB_8) },
8818                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8819                              PCI_DEVICE_ID_INTEL_82801BA_11) },
8820                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8821                              PCI_DEVICE_ID_INTEL_82801BA_6) },
8822                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
8823                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
8824                 { },
8825         };
8826         u32 misc_ctrl_reg;
8827         u32 cacheline_sz_reg;
8828         u32 pci_state_reg, grc_misc_cfg;
8829         u32 val;
8830         u16 pci_cmd;
8831         int err;
8832
8833 #ifdef CONFIG_SPARC64
8834         if (tg3_is_sun_570X(tp))
8835                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
8836 #endif
8837
8838         /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8839          * reordering to the mailbox registers done by the host
8840          * controller can cause major troubles.  We read back from
8841          * every mailbox register write to force the writes to be
8842          * posted to the chip in order.
8843          */
8844         if (pci_dev_present(write_reorder_chipsets))
8845                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
8846
8847         /* Force memory write invalidate off.  If we leave it on,
8848          * then on 5700_BX chips we have to enable a workaround.
8849          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8850          * to match the cacheline size.  The Broadcom driver have this
8851          * workaround but turns MWI off all the times so never uses
8852          * it.  This seems to suggest that the workaround is insufficient.
8853          */
8854         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8855         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
8856         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8857
8858         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8859          * has the register indirect write enable bit set before
8860          * we try to access any of the MMIO registers.  It is also
8861          * critical that the PCI-X hw workaround situation is decided
8862          * before that as well.
8863          */
8864         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8865                               &misc_ctrl_reg);
8866
8867         tp->pci_chip_rev_id = (misc_ctrl_reg >>
8868                                MISC_HOST_CTRL_CHIPREV_SHIFT);
8869
8870         /* Wrong chip ID in 5752 A0. This code can be removed later
8871          * as A0 is not in production.
8872          */
8873         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8874                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8875
8876         /* Initialize misc host control in PCI block. */
8877         tp->misc_host_ctrl |= (misc_ctrl_reg &
8878                                MISC_HOST_CTRL_CHIPREV);
8879         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8880                                tp->misc_host_ctrl);
8881
8882         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8883                               &cacheline_sz_reg);
8884
8885         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
8886         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
8887         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
8888         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
8889
8890         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8891             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8892                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8893
8894         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
8895             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
8896                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
8897
8898         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8899                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8900
8901         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8902                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8903
8904         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8905             tp->pci_lat_timer < 64) {
8906                 tp->pci_lat_timer = 64;
8907
8908                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
8909                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
8910                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
8911                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
8912
8913                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8914                                        cacheline_sz_reg);
8915         }
8916
8917         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8918                               &pci_state_reg);
8919
8920         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
8921                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
8922
8923                 /* If this is a 5700 BX chipset, and we are in PCI-X
8924                  * mode, enable register write workaround.
8925                  *
8926                  * The workaround is to use indirect register accesses
8927                  * for all chip writes not to mailbox registers.
8928                  */
8929                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
8930                         u32 pm_reg;
8931                         u16 pci_cmd;
8932
8933                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8934
8935                         /* The chip can have it's power management PCI config
8936                          * space registers clobbered due to this bug.
8937                          * So explicitly force the chip into D0 here.
8938                          */
8939                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8940                                               &pm_reg);
8941                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
8942                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
8943                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8944                                                pm_reg);
8945
8946                         /* Also, force SERR#/PERR# in PCI command. */
8947                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8948                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
8949                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8950                 }
8951         }
8952
8953         /* Back to back register writes can cause problems on this chip,
8954          * the workaround is to read back all reg writes except those to
8955          * mailbox regs.  See tg3_write_indirect_reg32().
8956          *
8957          * PCI Express 5750_A0 rev chips need this workaround too.
8958          */
8959         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8960             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
8961              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
8962                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
8963
8964         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
8965                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
8966         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
8967                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
8968
8969         /* Chip-specific fixup from Broadcom driver */
8970         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
8971             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
8972                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
8973                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
8974         }
8975
8976         /* Get eeprom hw config before calling tg3_set_power_state().
8977          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8978          * determined before calling tg3_set_power_state() so that
8979          * we know whether or not to switch out of Vaux power.
8980          * When the flag is set, it means that GPIO1 is used for eeprom
8981          * write protect and also implies that it is a LOM where GPIOs
8982          * are not used to switch power.
8983          */
8984         tg3_get_eeprom_hw_cfg(tp);
8985
8986         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8987          * GPIO1 driven high will bring 5700's external PHY out of reset.
8988          * It is also used as eeprom write protect on LOMs.
8989          */
8990         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
8991         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8992             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
8993                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8994                                        GRC_LCLCTRL_GPIO_OUTPUT1);
8995         /* Unused GPIO3 must be driven as output on 5752 because there
8996          * are no pull-up resistors on unused GPIO pins.
8997          */
8998         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8999                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
9000
9001         /* Force the chip into D0. */
9002         err = tg3_set_power_state(tp, 0);
9003         if (err) {
9004                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9005                        pci_name(tp->pdev));
9006                 return err;
9007         }
9008
9009         /* 5700 B0 chips do not support checksumming correctly due
9010          * to hardware bugs.
9011          */
9012         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9013                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9014
9015         /* Pseudo-header checksum is done by hardware logic and not
9016          * the offload processers, so make the chip do the pseudo-
9017          * header checksums on receive.  For transmit it is more
9018          * convenient to do the pseudo-header checksum in software
9019          * as Linux does that on transmit for us in all cases.
9020          */
9021         tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9022         tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9023
9024         /* Derive initial jumbo mode from MTU assigned in
9025          * ether_setup() via the alloc_etherdev() call
9026          */
9027         if (tp->dev->mtu > ETH_DATA_LEN)
9028                 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
9029
9030         /* Determine WakeOnLan speed to use. */
9031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9032             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9033             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9034             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9035                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9036         } else {
9037                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9038         }
9039
9040         /* A few boards don't want Ethernet@WireSpeed phy feature */
9041         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9042             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9043              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9044              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
9045                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9046
9047         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9048             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9049                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9050         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9051                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9052
9053         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9054                 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9055
9056         tp->coalesce_mode = 0;
9057         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9058             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9059                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9060
9061         /* Initialize MAC MI mode, polling disabled. */
9062         tw32_f(MAC_MI_MODE, tp->mi_mode);
9063         udelay(80);
9064
9065         /* Initialize data/descriptor byte/word swapping. */
9066         val = tr32(GRC_MODE);
9067         val &= GRC_MODE_HOST_STACKUP;
9068         tw32(GRC_MODE, val | tp->grc_mode);
9069
9070         tg3_switch_clocks(tp);
9071
9072         /* Clear this out for sanity. */
9073         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9074
9075         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9076                               &pci_state_reg);
9077         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9078             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9079                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9080
9081                 if (chiprevid == CHIPREV_ID_5701_A0 ||
9082                     chiprevid == CHIPREV_ID_5701_B0 ||
9083                     chiprevid == CHIPREV_ID_5701_B2 ||
9084                     chiprevid == CHIPREV_ID_5701_B5) {
9085                         void __iomem *sram_base;
9086
9087                         /* Write some dummy words into the SRAM status block
9088                          * area, see if it reads back correctly.  If the return
9089                          * value is bad, force enable the PCIX workaround.
9090                          */
9091                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9092
9093                         writel(0x00000000, sram_base);
9094                         writel(0x00000000, sram_base + 4);
9095                         writel(0xffffffff, sram_base + 4);
9096                         if (readl(sram_base) != 0x00000000)
9097                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9098                 }
9099         }
9100
9101         udelay(50);
9102         tg3_nvram_init(tp);
9103
9104         grc_misc_cfg = tr32(GRC_MISC_CFG);
9105         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9106
9107         /* Broadcom's driver says that CIOBE multisplit has a bug */
9108 #if 0
9109         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9110             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9111                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9112                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9113         }
9114 #endif
9115         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9116             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9117              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9118                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9119
9120         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9121             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9122                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9123         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9124                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9125                                       HOSTCC_MODE_CLRTICK_TXBD);
9126
9127                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9128                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9129                                        tp->misc_host_ctrl);
9130         }
9131
9132         /* these are limited to 10/100 only */
9133         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9134              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9135             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9136              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9137              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9138               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9139               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9140             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9141              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9142               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9143                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9144
9145         err = tg3_phy_probe(tp);
9146         if (err) {
9147                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9148                        pci_name(tp->pdev), err);
9149                 /* ... but do not return immediately ... */
9150         }
9151
9152         tg3_read_partno(tp);
9153
9154         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9155                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9156         } else {
9157                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9158                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9159                 else
9160                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9161         }
9162
9163         /* 5700 {AX,BX} chips have a broken status block link
9164          * change bit implementation, so we must use the
9165          * status register in those cases.
9166          */
9167         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9168                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9169         else
9170                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9171
9172         /* The led_ctrl is set during tg3_phy_probe, here we might
9173          * have to force the link status polling mechanism based
9174          * upon subsystem IDs.
9175          */
9176         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9177             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9178                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9179                                   TG3_FLAG_USE_LINKCHG_REG);
9180         }
9181
9182         /* For all SERDES we poll the MAC status register. */
9183         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9184                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9185         else
9186                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9187
9188         /* 5700 BX chips need to have their TX producer index mailboxes
9189          * written twice to workaround a bug.
9190          */
9191         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9192                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9193         else
9194                 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
9195
9196         /* It seems all chips can get confused if TX buffers
9197          * straddle the 4GB address boundary in some cases.
9198          */
9199         tp->dev->hard_start_xmit = tg3_start_xmit;
9200
9201         tp->rx_offset = 2;
9202         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9203             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9204                 tp->rx_offset = 0;
9205
9206         /* By default, disable wake-on-lan.  User can change this
9207          * using ETHTOOL_SWOL.
9208          */
9209         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9210
9211         return err;
9212 }
9213
9214 #ifdef CONFIG_SPARC64
9215 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9216 {
9217         struct net_device *dev = tp->dev;
9218         struct pci_dev *pdev = tp->pdev;
9219         struct pcidev_cookie *pcp = pdev->sysdata;
9220
9221         if (pcp != NULL) {
9222                 int node = pcp->prom_node;
9223
9224                 if (prom_getproplen(node, "local-mac-address") == 6) {
9225                         prom_getproperty(node, "local-mac-address",
9226                                          dev->dev_addr, 6);
9227                         return 0;
9228                 }
9229         }
9230         return -ENODEV;
9231 }
9232
9233 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9234 {
9235         struct net_device *dev = tp->dev;
9236
9237         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9238         return 0;
9239 }
9240 #endif
9241
9242 static int __devinit tg3_get_device_address(struct tg3 *tp)
9243 {
9244         struct net_device *dev = tp->dev;
9245         u32 hi, lo, mac_offset;
9246
9247 #ifdef CONFIG_SPARC64
9248         if (!tg3_get_macaddr_sparc(tp))
9249                 return 0;
9250 #endif
9251
9252         mac_offset = 0x7c;
9253         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9254             !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
9255                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9256                         mac_offset = 0xcc;
9257                 if (tg3_nvram_lock(tp))
9258                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9259                 else
9260                         tg3_nvram_unlock(tp);
9261         }
9262
9263         /* First try to get it from MAC address mailbox. */
9264         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9265         if ((hi >> 16) == 0x484b) {
9266                 dev->dev_addr[0] = (hi >>  8) & 0xff;
9267                 dev->dev_addr[1] = (hi >>  0) & 0xff;
9268
9269                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9270                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9271                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9272                 dev->dev_addr[4] = (lo >>  8) & 0xff;
9273                 dev->dev_addr[5] = (lo >>  0) & 0xff;
9274         }
9275         /* Next, try NVRAM. */
9276         else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9277                  !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9278                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9279                 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9280                 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9281                 dev->dev_addr[2] = ((lo >>  0) & 0xff);
9282                 dev->dev_addr[3] = ((lo >>  8) & 0xff);
9283                 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9284                 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9285         }
9286         /* Finally just fetch it out of the MAC control regs. */
9287         else {
9288                 hi = tr32(MAC_ADDR_0_HIGH);
9289                 lo = tr32(MAC_ADDR_0_LOW);
9290
9291                 dev->dev_addr[5] = lo & 0xff;
9292                 dev->dev_addr[4] = (lo >> 8) & 0xff;
9293                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9294                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9295                 dev->dev_addr[1] = hi & 0xff;
9296                 dev->dev_addr[0] = (hi >> 8) & 0xff;
9297         }
9298
9299         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9300 #ifdef CONFIG_SPARC64
9301                 if (!tg3_get_default_macaddr_sparc(tp))
9302                         return 0;
9303 #endif
9304                 return -EINVAL;
9305         }
9306         return 0;
9307 }
9308
9309 #define BOUNDARY_SINGLE_CACHELINE       1
9310 #define BOUNDARY_MULTI_CACHELINE        2
9311
9312 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9313 {
9314         int cacheline_size;
9315         u8 byte;
9316         int goal;
9317
9318         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9319         if (byte == 0)
9320                 cacheline_size = 1024;
9321         else
9322                 cacheline_size = (int) byte * 4;
9323
9324         /* On 5703 and later chips, the boundary bits have no
9325          * effect.
9326          */
9327         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9328             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9329             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9330                 goto out;
9331
9332 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9333         goal = BOUNDARY_MULTI_CACHELINE;
9334 #else
9335 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9336         goal = BOUNDARY_SINGLE_CACHELINE;
9337 #else
9338         goal = 0;
9339 #endif
9340 #endif
9341
9342         if (!goal)
9343                 goto out;
9344
9345         /* PCI controllers on most RISC systems tend to disconnect
9346          * when a device tries to burst across a cache-line boundary.
9347          * Therefore, letting tg3 do so just wastes PCI bandwidth.
9348          *
9349          * Unfortunately, for PCI-E there are only limited
9350          * write-side controls for this, and thus for reads
9351          * we will still get the disconnects.  We'll also waste
9352          * these PCI cycles for both read and write for chips
9353          * other than 5700 and 5701 which do not implement the
9354          * boundary bits.
9355          */
9356         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9357             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9358                 switch (cacheline_size) {
9359                 case 16:
9360                 case 32:
9361                 case 64:
9362                 case 128:
9363                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9364                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9365                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9366                         } else {
9367                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9368                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9369                         }
9370                         break;
9371
9372                 case 256:
9373                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9374                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9375                         break;
9376
9377                 default:
9378                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9379                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9380                         break;
9381                 };
9382         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9383                 switch (cacheline_size) {
9384                 case 16:
9385                 case 32:
9386                 case 64:
9387                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9388                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9389                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9390                                 break;
9391                         }
9392                         /* fallthrough */
9393                 case 128:
9394                 default:
9395                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9396                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9397                         break;
9398                 };
9399         } else {
9400                 switch (cacheline_size) {
9401                 case 16:
9402                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9403                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9404                                         DMA_RWCTRL_WRITE_BNDRY_16);
9405                                 break;
9406                         }
9407                         /* fallthrough */
9408                 case 32:
9409                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9410                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9411                                         DMA_RWCTRL_WRITE_BNDRY_32);
9412                                 break;
9413                         }
9414                         /* fallthrough */
9415                 case 64:
9416                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9417                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9418                                         DMA_RWCTRL_WRITE_BNDRY_64);
9419                                 break;
9420                         }
9421                         /* fallthrough */
9422                 case 128:
9423                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9424                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
9425                                         DMA_RWCTRL_WRITE_BNDRY_128);
9426                                 break;
9427                         }
9428                         /* fallthrough */
9429                 case 256:
9430                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
9431                                 DMA_RWCTRL_WRITE_BNDRY_256);
9432                         break;
9433                 case 512:
9434                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
9435                                 DMA_RWCTRL_WRITE_BNDRY_512);
9436                         break;
9437                 case 1024:
9438                 default:
9439                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
9440                                 DMA_RWCTRL_WRITE_BNDRY_1024);
9441                         break;
9442                 };
9443         }
9444
9445 out:
9446         return val;
9447 }
9448
9449 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
9450 {
9451         struct tg3_internal_buffer_desc test_desc;
9452         u32 sram_dma_descs;
9453         int i, ret;
9454
9455         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
9456
9457         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
9458         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
9459         tw32(RDMAC_STATUS, 0);
9460         tw32(WDMAC_STATUS, 0);
9461
9462         tw32(BUFMGR_MODE, 0);
9463         tw32(FTQ_RESET, 0);
9464
9465         test_desc.addr_hi = ((u64) buf_dma) >> 32;
9466         test_desc.addr_lo = buf_dma & 0xffffffff;
9467         test_desc.nic_mbuf = 0x00002100;
9468         test_desc.len = size;
9469
9470         /*
9471          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
9472          * the *second* time the tg3 driver was getting loaded after an
9473          * initial scan.
9474          *
9475          * Broadcom tells me:
9476          *   ...the DMA engine is connected to the GRC block and a DMA
9477          *   reset may affect the GRC block in some unpredictable way...
9478          *   The behavior of resets to individual blocks has not been tested.
9479          *
9480          * Broadcom noted the GRC reset will also reset all sub-components.
9481          */
9482         if (to_device) {
9483                 test_desc.cqid_sqid = (13 << 8) | 2;
9484
9485                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
9486                 udelay(40);
9487         } else {
9488                 test_desc.cqid_sqid = (16 << 8) | 7;
9489
9490                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
9491                 udelay(40);
9492         }
9493         test_desc.flags = 0x00000005;
9494
9495         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
9496                 u32 val;
9497
9498                 val = *(((u32 *)&test_desc) + i);
9499                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
9500                                        sram_dma_descs + (i * sizeof(u32)));
9501                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
9502         }
9503         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
9504
9505         if (to_device) {
9506                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
9507         } else {
9508                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
9509         }
9510
9511         ret = -ENODEV;
9512         for (i = 0; i < 40; i++) {
9513                 u32 val;
9514
9515                 if (to_device)
9516                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
9517                 else
9518                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
9519                 if ((val & 0xffff) == sram_dma_descs) {
9520                         ret = 0;
9521                         break;
9522                 }
9523
9524                 udelay(100);
9525         }
9526
9527         return ret;
9528 }
9529
9530 #define TEST_BUFFER_SIZE        0x2000
9531
9532 static int __devinit tg3_test_dma(struct tg3 *tp)
9533 {
9534         dma_addr_t buf_dma;
9535         u32 *buf, saved_dma_rwctrl;
9536         int ret;
9537
9538         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
9539         if (!buf) {
9540                 ret = -ENOMEM;
9541                 goto out_nofree;
9542         }
9543
9544         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
9545                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
9546
9547         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
9548
9549         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9550                 /* DMA read watermark not used on PCIE */
9551                 tp->dma_rwctrl |= 0x00180000;
9552         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
9553                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
9554                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
9555                         tp->dma_rwctrl |= 0x003f0000;
9556                 else
9557                         tp->dma_rwctrl |= 0x003f000f;
9558         } else {
9559                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9560                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9561                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
9562
9563                         if (ccval == 0x6 || ccval == 0x7)
9564                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
9565
9566                         /* Set bit 23 to enable PCIX hw bug fix */
9567                         tp->dma_rwctrl |= 0x009f0000;
9568                 } else {
9569                         tp->dma_rwctrl |= 0x001b000f;
9570                 }
9571         }
9572
9573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9574             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9575                 tp->dma_rwctrl &= 0xfffffff0;
9576
9577         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9578             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
9579                 /* Remove this if it causes problems for some boards. */
9580                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
9581
9582                 /* On 5700/5701 chips, we need to set this bit.
9583                  * Otherwise the chip will issue cacheline transactions
9584                  * to streamable DMA memory with not all the byte
9585                  * enables turned on.  This is an error on several
9586                  * RISC PCI controllers, in particular sparc64.
9587                  *
9588                  * On 5703/5704 chips, this bit has been reassigned
9589                  * a different meaning.  In particular, it is used
9590                  * on those chips to enable a PCI-X workaround.
9591                  */
9592                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
9593         }
9594
9595         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9596
9597 #if 0
9598         /* Unneeded, already done by tg3_get_invariants.  */
9599         tg3_switch_clocks(tp);
9600 #endif
9601
9602         ret = 0;
9603         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9604             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
9605                 goto out;
9606
9607         /* It is best to perform DMA test with maximum write burst size
9608          * to expose the 5700/5701 write DMA bug.
9609          */
9610         saved_dma_rwctrl = tp->dma_rwctrl;
9611         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9612         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9613
9614         while (1) {
9615                 u32 *p = buf, i;
9616
9617                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
9618                         p[i] = i;
9619
9620                 /* Send the buffer to the chip. */
9621                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
9622                 if (ret) {
9623                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
9624                         break;
9625                 }
9626
9627 #if 0
9628                 /* validate data reached card RAM correctly. */
9629                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9630                         u32 val;
9631                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
9632                         if (le32_to_cpu(val) != p[i]) {
9633                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
9634                                 /* ret = -ENODEV here? */
9635                         }
9636                         p[i] = 0;
9637                 }
9638 #endif
9639                 /* Now read it back. */
9640                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
9641                 if (ret) {
9642                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
9643
9644                         break;
9645                 }
9646
9647                 /* Verify it. */
9648                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9649                         if (p[i] == i)
9650                                 continue;
9651
9652                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9653                             DMA_RWCTRL_WRITE_BNDRY_16) {
9654                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9655                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9656                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9657                                 break;
9658                         } else {
9659                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
9660                                 ret = -ENODEV;
9661                                 goto out;
9662                         }
9663                 }
9664
9665                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
9666                         /* Success. */
9667                         ret = 0;
9668                         break;
9669                 }
9670         }
9671         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9672             DMA_RWCTRL_WRITE_BNDRY_16) {
9673                 static struct pci_device_id dma_wait_state_chipsets[] = {
9674                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
9675                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
9676                         { },
9677                 };
9678
9679                 /* DMA test passed without adjusting DMA boundary,
9680                  * now look for chipsets that are known to expose the
9681                  * DMA bug without failing the test.
9682                  */
9683                 if (pci_dev_present(dma_wait_state_chipsets)) {
9684                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9685                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9686                 }
9687                 else
9688                         /* Safe to use the calculated DMA boundary. */
9689                         tp->dma_rwctrl = saved_dma_rwctrl;
9690
9691                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9692         }
9693
9694 out:
9695         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
9696 out_nofree:
9697         return ret;
9698 }
9699
9700 static void __devinit tg3_init_link_config(struct tg3 *tp)
9701 {
9702         tp->link_config.advertising =
9703                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
9704                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
9705                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
9706                  ADVERTISED_Autoneg | ADVERTISED_MII);
9707         tp->link_config.speed = SPEED_INVALID;
9708         tp->link_config.duplex = DUPLEX_INVALID;
9709         tp->link_config.autoneg = AUTONEG_ENABLE;
9710         netif_carrier_off(tp->dev);
9711         tp->link_config.active_speed = SPEED_INVALID;
9712         tp->link_config.active_duplex = DUPLEX_INVALID;
9713         tp->link_config.phy_is_low_power = 0;
9714         tp->link_config.orig_speed = SPEED_INVALID;
9715         tp->link_config.orig_duplex = DUPLEX_INVALID;
9716         tp->link_config.orig_autoneg = AUTONEG_INVALID;
9717 }
9718
9719 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
9720 {
9721         tp->bufmgr_config.mbuf_read_dma_low_water =
9722                 DEFAULT_MB_RDMA_LOW_WATER;
9723         tp->bufmgr_config.mbuf_mac_rx_low_water =
9724                 DEFAULT_MB_MACRX_LOW_WATER;
9725         tp->bufmgr_config.mbuf_high_water =
9726                 DEFAULT_MB_HIGH_WATER;
9727
9728         tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9729                 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
9730         tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9731                 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
9732         tp->bufmgr_config.mbuf_high_water_jumbo =
9733                 DEFAULT_MB_HIGH_WATER_JUMBO;
9734
9735         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
9736         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
9737 }
9738
9739 static char * __devinit tg3_phy_string(struct tg3 *tp)
9740 {
9741         switch (tp->phy_id & PHY_ID_MASK) {
9742         case PHY_ID_BCM5400:    return "5400";
9743         case PHY_ID_BCM5401:    return "5401";
9744         case PHY_ID_BCM5411:    return "5411";
9745         case PHY_ID_BCM5701:    return "5701";
9746         case PHY_ID_BCM5703:    return "5703";
9747         case PHY_ID_BCM5704:    return "5704";
9748         case PHY_ID_BCM5705:    return "5705";
9749         case PHY_ID_BCM5750:    return "5750";
9750         case PHY_ID_BCM5752:    return "5752";
9751         case PHY_ID_BCM8002:    return "8002/serdes";
9752         case 0:                 return "serdes";
9753         default:                return "unknown";
9754         };
9755 }
9756
9757 static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
9758 {
9759         struct pci_dev *peer;
9760         unsigned int func, devnr = tp->pdev->devfn & ~7;
9761
9762         for (func = 0; func < 8; func++) {
9763                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
9764                 if (peer && peer != tp->pdev)
9765                         break;
9766                 pci_dev_put(peer);
9767         }
9768         if (!peer || peer == tp->pdev)
9769                 BUG();
9770
9771         /*
9772          * We don't need to keep the refcount elevated; there's no way
9773          * to remove one half of this device without removing the other
9774          */
9775         pci_dev_put(peer);
9776
9777         return peer;
9778 }
9779
9780 static void __devinit tg3_init_coal(struct tg3 *tp)
9781 {
9782         struct ethtool_coalesce *ec = &tp->coal;
9783
9784         memset(ec, 0, sizeof(*ec));
9785         ec->cmd = ETHTOOL_GCOALESCE;
9786         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
9787         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
9788         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
9789         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
9790         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
9791         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
9792         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
9793         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
9794         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
9795
9796         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
9797                                  HOSTCC_MODE_CLRTICK_TXBD)) {
9798                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
9799                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
9800                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
9801                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
9802         }
9803 }
9804
9805 static int __devinit tg3_init_one(struct pci_dev *pdev,
9806                                   const struct pci_device_id *ent)
9807 {
9808         static int tg3_version_printed = 0;
9809         unsigned long tg3reg_base, tg3reg_len;
9810         struct net_device *dev;
9811         struct tg3 *tp;
9812         int i, err, pci_using_dac, pm_cap;
9813
9814         if (tg3_version_printed++ == 0)
9815                 printk(KERN_INFO "%s", version);
9816
9817         err = pci_enable_device(pdev);
9818         if (err) {
9819                 printk(KERN_ERR PFX "Cannot enable PCI device, "
9820                        "aborting.\n");
9821                 return err;
9822         }
9823
9824         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9825                 printk(KERN_ERR PFX "Cannot find proper PCI device "
9826                        "base address, aborting.\n");
9827                 err = -ENODEV;
9828                 goto err_out_disable_pdev;
9829         }
9830
9831         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9832         if (err) {
9833                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
9834                        "aborting.\n");
9835                 goto err_out_disable_pdev;
9836         }
9837
9838         pci_set_master(pdev);
9839
9840         /* Find power-management capability. */
9841         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9842         if (pm_cap == 0) {
9843                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
9844                        "aborting.\n");
9845                 err = -EIO;
9846                 goto err_out_free_res;
9847         }
9848
9849         /* Configure DMA attributes. */
9850         err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
9851         if (!err) {
9852                 pci_using_dac = 1;
9853                 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
9854                 if (err < 0) {
9855                         printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
9856                                "for consistent allocations\n");
9857                         goto err_out_free_res;
9858                 }
9859         } else {
9860                 err = pci_set_dma_mask(pdev, 0xffffffffULL);
9861                 if (err) {
9862                         printk(KERN_ERR PFX "No usable DMA configuration, "
9863                                "aborting.\n");
9864                         goto err_out_free_res;
9865                 }
9866                 pci_using_dac = 0;
9867         }
9868
9869         tg3reg_base = pci_resource_start(pdev, 0);
9870         tg3reg_len = pci_resource_len(pdev, 0);
9871
9872         dev = alloc_etherdev(sizeof(*tp));
9873         if (!dev) {
9874                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
9875                 err = -ENOMEM;
9876                 goto err_out_free_res;
9877         }
9878
9879         SET_MODULE_OWNER(dev);
9880         SET_NETDEV_DEV(dev, &pdev->dev);
9881
9882         if (pci_using_dac)
9883                 dev->features |= NETIF_F_HIGHDMA;
9884         dev->features |= NETIF_F_LLTX;
9885 #if TG3_VLAN_TAG_USED
9886         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
9887         dev->vlan_rx_register = tg3_vlan_rx_register;
9888         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
9889 #endif
9890
9891         tp = netdev_priv(dev);
9892         tp->pdev = pdev;
9893         tp->dev = dev;
9894         tp->pm_cap = pm_cap;
9895         tp->mac_mode = TG3_DEF_MAC_MODE;
9896         tp->rx_mode = TG3_DEF_RX_MODE;
9897         tp->tx_mode = TG3_DEF_TX_MODE;
9898         tp->mi_mode = MAC_MI_MODE_BASE;
9899         if (tg3_debug > 0)
9900                 tp->msg_enable = tg3_debug;
9901         else
9902                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
9903
9904         /* The word/byte swap controls here control register access byte
9905          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
9906          * setting below.
9907          */
9908         tp->misc_host_ctrl =
9909                 MISC_HOST_CTRL_MASK_PCI_INT |
9910                 MISC_HOST_CTRL_WORD_SWAP |
9911                 MISC_HOST_CTRL_INDIR_ACCESS |
9912                 MISC_HOST_CTRL_PCISTATE_RW;
9913
9914         /* The NONFRM (non-frame) byte/word swap controls take effect
9915          * on descriptor entries, anything which isn't packet data.
9916          *
9917          * The StrongARM chips on the board (one for tx, one for rx)
9918          * are running in big-endian mode.
9919          */
9920         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
9921                         GRC_MODE_WSWAP_NONFRM_DATA);
9922 #ifdef __BIG_ENDIAN
9923         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
9924 #endif
9925         spin_lock_init(&tp->lock);
9926         spin_lock_init(&tp->tx_lock);
9927         spin_lock_init(&tp->indirect_lock);
9928         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
9929
9930         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
9931         if (tp->regs == 0UL) {
9932                 printk(KERN_ERR PFX "Cannot map device registers, "
9933                        "aborting.\n");
9934                 err = -ENOMEM;
9935                 goto err_out_free_dev;
9936         }
9937
9938         tg3_init_link_config(tp);
9939
9940         tg3_init_bufmgr_config(tp);
9941
9942         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
9943         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
9944         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
9945
9946         dev->open = tg3_open;
9947         dev->stop = tg3_close;
9948         dev->get_stats = tg3_get_stats;
9949         dev->set_multicast_list = tg3_set_rx_mode;
9950         dev->set_mac_address = tg3_set_mac_addr;
9951         dev->do_ioctl = tg3_ioctl;
9952         dev->tx_timeout = tg3_tx_timeout;
9953         dev->poll = tg3_poll;
9954         dev->ethtool_ops = &tg3_ethtool_ops;
9955         dev->weight = 64;
9956         dev->watchdog_timeo = TG3_TX_TIMEOUT;
9957         dev->change_mtu = tg3_change_mtu;
9958         dev->irq = pdev->irq;
9959 #ifdef CONFIG_NET_POLL_CONTROLLER
9960         dev->poll_controller = tg3_poll_controller;
9961 #endif
9962
9963         err = tg3_get_invariants(tp);
9964         if (err) {
9965                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
9966                        "aborting.\n");
9967                 goto err_out_iounmap;
9968         }
9969
9970         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9971                 tp->bufmgr_config.mbuf_read_dma_low_water =
9972                         DEFAULT_MB_RDMA_LOW_WATER_5705;
9973                 tp->bufmgr_config.mbuf_mac_rx_low_water =
9974                         DEFAULT_MB_MACRX_LOW_WATER_5705;
9975                 tp->bufmgr_config.mbuf_high_water =
9976                         DEFAULT_MB_HIGH_WATER_5705;
9977         }
9978
9979 #if TG3_TSO_SUPPORT != 0
9980         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
9981                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9982         }
9983         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9985             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
9986             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
9987                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9988         } else {
9989                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9990         }
9991
9992         /* TSO is off by default, user can enable using ethtool.  */
9993 #if 0
9994         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
9995                 dev->features |= NETIF_F_TSO;
9996 #endif
9997
9998 #endif
9999
10000         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10001             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10002             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10003                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10004                 tp->rx_pending = 63;
10005         }
10006
10007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10008                 tp->pdev_peer = tg3_find_5704_peer(tp);
10009
10010         err = tg3_get_device_address(tp);
10011         if (err) {
10012                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10013                        "aborting.\n");
10014                 goto err_out_iounmap;
10015         }
10016
10017         /*
10018          * Reset chip in case UNDI or EFI driver did not shutdown
10019          * DMA self test will enable WDMAC and we'll see (spurious)
10020          * pending DMA on the PCI bus at that point.
10021          */
10022         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10023             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10024                 pci_save_state(tp->pdev);
10025                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
10026                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10027         }
10028
10029         err = tg3_test_dma(tp);
10030         if (err) {
10031                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10032                 goto err_out_iounmap;
10033         }
10034
10035         /* Tigon3 can do ipv4 only... and some chips have buggy
10036          * checksumming.
10037          */
10038         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10039                 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10040                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10041         } else
10042                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10043
10044         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10045                 dev->features &= ~NETIF_F_HIGHDMA;
10046
10047         /* flow control autonegotiation is default behavior */
10048         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10049
10050         tg3_init_coal(tp);
10051
10052         err = register_netdev(dev);
10053         if (err) {
10054                 printk(KERN_ERR PFX "Cannot register net device, "
10055                        "aborting.\n");
10056                 goto err_out_iounmap;
10057         }
10058
10059         pci_set_drvdata(pdev, dev);
10060
10061         /* Now that we have fully setup the chip, save away a snapshot
10062          * of the PCI config space.  We need to restore this after
10063          * GRC_MISC_CFG core clock resets and some resume events.
10064          */
10065         pci_save_state(tp->pdev);
10066
10067         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
10068                dev->name,
10069                tp->board_part_number,
10070                tp->pci_chip_rev_id,
10071                tg3_phy_string(tp),
10072                ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
10073                ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
10074                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
10075                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
10076                ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
10077                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10078
10079         for (i = 0; i < 6; i++)
10080                 printk("%2.2x%c", dev->dev_addr[i],
10081                        i == 5 ? '\n' : ':');
10082
10083         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10084                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10085                "TSOcap[%d] \n",
10086                dev->name,
10087                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10088                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10089                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10090                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10091                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10092                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10093                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10094         printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10095                dev->name, tp->dma_rwctrl);
10096
10097         return 0;
10098
10099 err_out_iounmap:
10100         iounmap(tp->regs);
10101
10102 err_out_free_dev:
10103         free_netdev(dev);
10104
10105 err_out_free_res:
10106         pci_release_regions(pdev);
10107
10108 err_out_disable_pdev:
10109         pci_disable_device(pdev);
10110         pci_set_drvdata(pdev, NULL);
10111         return err;
10112 }
10113
10114 static void __devexit tg3_remove_one(struct pci_dev *pdev)
10115 {
10116         struct net_device *dev = pci_get_drvdata(pdev);
10117
10118         if (dev) {
10119                 struct tg3 *tp = netdev_priv(dev);
10120
10121                 unregister_netdev(dev);
10122                 iounmap(tp->regs);
10123                 free_netdev(dev);
10124                 pci_release_regions(pdev);
10125                 pci_disable_device(pdev);
10126                 pci_set_drvdata(pdev, NULL);
10127         }
10128 }
10129
10130 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10131 {
10132         struct net_device *dev = pci_get_drvdata(pdev);
10133         struct tg3 *tp = netdev_priv(dev);
10134         int err;
10135
10136         if (!netif_running(dev))
10137                 return 0;
10138
10139         tg3_netif_stop(tp);
10140
10141         del_timer_sync(&tp->timer);
10142
10143         tg3_full_lock(tp, 1);
10144         tg3_disable_ints(tp);
10145         tg3_full_unlock(tp);
10146
10147         netif_device_detach(dev);
10148
10149         tg3_full_lock(tp, 0);
10150         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10151         tg3_full_unlock(tp);
10152
10153         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10154         if (err) {
10155                 tg3_full_lock(tp, 0);
10156
10157                 tg3_init_hw(tp);
10158
10159                 tp->timer.expires = jiffies + tp->timer_offset;
10160                 add_timer(&tp->timer);
10161
10162                 netif_device_attach(dev);
10163                 tg3_netif_start(tp);
10164
10165                 tg3_full_unlock(tp);
10166         }
10167
10168         return err;
10169 }
10170
10171 static int tg3_resume(struct pci_dev *pdev)
10172 {
10173         struct net_device *dev = pci_get_drvdata(pdev);
10174         struct tg3 *tp = netdev_priv(dev);
10175         int err;
10176
10177         if (!netif_running(dev))
10178                 return 0;
10179
10180         pci_restore_state(tp->pdev);
10181
10182         err = tg3_set_power_state(tp, 0);
10183         if (err)
10184                 return err;
10185
10186         netif_device_attach(dev);
10187
10188         tg3_full_lock(tp, 0);
10189
10190         tg3_init_hw(tp);
10191
10192         tp->timer.expires = jiffies + tp->timer_offset;
10193         add_timer(&tp->timer);
10194
10195         tg3_netif_start(tp);
10196
10197         tg3_full_unlock(tp);
10198
10199         return 0;
10200 }
10201
10202 static struct pci_driver tg3_driver = {
10203         .name           = DRV_MODULE_NAME,
10204         .id_table       = tg3_pci_tbl,
10205         .probe          = tg3_init_one,
10206         .remove         = __devexit_p(tg3_remove_one),
10207         .suspend        = tg3_suspend,
10208         .resume         = tg3_resume
10209 };
10210
10211 static int __init tg3_init(void)
10212 {
10213         return pci_module_init(&tg3_driver);
10214 }
10215
10216 static void __exit tg3_cleanup(void)
10217 {
10218         pci_unregister_driver(&tg3_driver);
10219 }
10220
10221 module_init(tg3_init);
10222 module_exit(tg3_cleanup);