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   1 /*
   2  *  linux/drivers/serial/cpm_uart_cpm2.c
   3  *
   4  *  Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
   5  *
   6  *  Maintainer: Kumar Gala (kumar.gala@freescale.com) (CPM2)
   7  *              Pantelis Antoniou (panto@intracom.gr) (CPM1)
   8  *
   9  *  Copyright (C) 2004 Freescale Semiconductor, Inc.
  10  *            (C) 2004 Intracom, S.A.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  25  *
  26  */
  27
  28 #include <linux/config.h>
  29 #include <linux/module.h>
  30 #include <linux/tty.h>
  31 #include <linux/ioport.h>
  32 #include <linux/init.h>
  33 #include <linux/serial.h>
  34 #include <linux/console.h>
  35 #include <linux/sysrq.h>
  36 #include <linux/device.h>
  37 #include <linux/bootmem.h>
  38 #include <linux/dma-mapping.h>
  39
  40 #include <asm/io.h>
  41 #include <asm/irq.h>
  42
  43 #include <linux/serial_core.h>
  44 #include <linux/kernel.h>
  45
  46 #include "cpm_uart.h"
  47
  48 /**************************************************************/
  49
  50 void cpm_line_cr_cmd(int line, int cmd)
  51 {
  52         volatile cpm_cpm2_t *cp = cpmp;
  53         ulong val;
  54
  55         switch (line) {
  56         case UART_SMC1:
  57                 val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
  58                                 cmd) | CPM_CR_FLG;
  59                 break;
  60         case UART_SMC2:
  61                 val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
  62                                 cmd) | CPM_CR_FLG;
  63                 break;
  64         case UART_SCC1:
  65                 val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
  66                                 cmd) | CPM_CR_FLG;
  67                 break;
  68         case UART_SCC2:
  69                 val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
  70                                 cmd) | CPM_CR_FLG;
  71                 break;
  72         case UART_SCC3:
  73                 val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
  74                                 cmd) | CPM_CR_FLG;
  75                 break;
  76         case UART_SCC4:
  77                 val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
  78                                 cmd) | CPM_CR_FLG;
  79                 break;
  80         default:
  81                 return;
  82
  83         }
  84         cp->cp_cpcr = val;
  85         while (cp->cp_cpcr & CPM_CR_FLG) ;
  86 }
  87
  88 void smc1_lineif(struct uart_cpm_port *pinfo)
  89 {
  90         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
  91
  92         /* SMC1 is only on port D */
  93         io->iop_ppard |= 0x00c00000;
  94         io->iop_pdird |= 0x00400000;
  95         io->iop_pdird &= ~0x00800000;
  96         io->iop_psord &= ~0x00c00000;
  97
  98         /* Wire BRG1 to SMC1 */
  99         cpm2_immr->im_cpmux.cmx_smr &= 0x0f;
 100         pinfo->brg = 1;
 101 }
 102
 103 void smc2_lineif(struct uart_cpm_port *pinfo)
 104 {
 105         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 106
 107         /* SMC2 is only on port A */
 108         io->iop_ppara |= 0x00c00000;
 109         io->iop_pdira |= 0x00400000;
 110         io->iop_pdira &= ~0x00800000;
 111         io->iop_psora &= ~0x00c00000;
 112
 113         /* Wire BRG2 to SMC2 */
 114         cpm2_immr->im_cpmux.cmx_smr &= 0xf0;
 115         pinfo->brg = 2;
 116 }
 117
 118 void scc1_lineif(struct uart_cpm_port *pinfo)
 119 {
 120         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 121
 122         /* Use Port D for SCC1 instead of other functions.  */
 123         io->iop_ppard |= 0x00000003;
 124         io->iop_psord &= ~0x00000001;   /* Rx */
 125         io->iop_psord |= 0x00000002;    /* Tx */
 126         io->iop_pdird &= ~0x00000001;   /* Rx */
 127         io->iop_pdird |= 0x00000002;    /* Tx */
 128
 129         /* Wire BRG1 to SCC1 */
 130         cpm2_immr->im_cpmux.cmx_scr &= 0x00ffffff;
 131         cpm2_immr->im_cpmux.cmx_scr |= 0x00000000;
 132         pinfo->brg = 1;
 133 }
 134
 135 void scc2_lineif(struct uart_cpm_port *pinfo)
 136 {
 137         /*
 138          * STx GP3 uses the SCC2 secondary option pin assignment
 139          * which this driver doesn't account for in the static
 140          * pin assignments. This kind of board specific info
 141          * really has to get out of the driver so boards can
 142          * be supported in a sane fashion.
 143          */
 144 #ifndef CONFIG_STX_GP3
 145         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 146         io->iop_pparb |= 0x008b0000;
 147         io->iop_pdirb |= 0x00880000;
 148         io->iop_psorb |= 0x00880000;
 149         io->iop_pdirb &= ~0x00030000;
 150         io->iop_psorb &= ~0x00030000;
 151 #endif
 152         cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff;
 153         cpm2_immr->im_cpmux.cmx_scr |= 0x00090000;
 154         pinfo->brg = 2;
 155 }
 156
 157 void scc3_lineif(struct uart_cpm_port *pinfo)
 158 {
 159         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 160         io->iop_pparb |= 0x008b0000;
 161         io->iop_pdirb |= 0x00880000;
 162         io->iop_psorb |= 0x00880000;
 163         io->iop_pdirb &= ~0x00030000;
 164         io->iop_psorb &= ~0x00030000;
 165         cpm2_immr->im_cpmux.cmx_scr &= 0xffff00ff;
 166         cpm2_immr->im_cpmux.cmx_scr |= 0x00001200;
 167         pinfo->brg = 3;
 168 }
 169
 170 void scc4_lineif(struct uart_cpm_port *pinfo)
 171 {
 172         volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
 173
 174         io->iop_ppard |= 0x00000600;
 175         io->iop_psord &= ~0x00000600;   /* Tx/Rx */
 176         io->iop_pdird &= ~0x00000200;   /* Rx */
 177         io->iop_pdird |= 0x00000400;    /* Tx */
 178
 179         cpm2_immr->im_cpmux.cmx_scr &= 0xffffff00;
 180         cpm2_immr->im_cpmux.cmx_scr |= 0x0000001b;
 181         pinfo->brg = 4;
 182 }
 183
 184 /*
 185  * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
 186  * receive buffer descriptors from dual port ram, and a character
 187  * buffer area from host mem. If we are allocating for the console we need
 188  * to do it from bootmem
 189  */
 190 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
 191 {
 192         int dpmemsz, memsz;
 193         u8 *dp_mem;
 194         uint dp_offset;
 195         u8 *mem_addr;
 196         dma_addr_t dma_addr = 0;
 197
 198         pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
 199
 200         dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
 201         dp_offset = cpm_dpalloc(dpmemsz, 8);
 202         if (IS_DPERR(dp_offset)) {
 203                 printk(KERN_ERR
 204                        "cpm_uart_cpm.c: could not allocate buffer descriptors\n");
 205                 return -ENOMEM;
 206         }
 207
 208         dp_mem = cpm_dpram_addr(dp_offset);
 209
 210         memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
 211             L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
 212         if (is_con)
 213                 mem_addr = alloc_bootmem(memsz);
 214         else
 215                 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
 216                                               GFP_KERNEL);
 217
 218         if (mem_addr == NULL) {
 219                 cpm_dpfree(dp_offset);
 220                 printk(KERN_ERR
 221                        "cpm_uart_cpm.c: could not allocate coherent memory\n");
 222                 return -ENOMEM;
 223         }
 224
 225         pinfo->dp_addr = dp_offset;
 226         pinfo->mem_addr = mem_addr;
 227         pinfo->dma_addr = dma_addr;
 228
 229         pinfo->rx_buf = mem_addr;
 230         pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
 231                                                        * pinfo->rx_fifosize);
 232
 233         pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
 234         pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
 235
 236         return 0;
 237 }
 238
 239 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
 240 {
 241         dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
 242                                                pinfo->rx_fifosize) +
 243                           L1_CACHE_ALIGN(pinfo->tx_nrfifos *
 244                                          pinfo->tx_fifosize), pinfo->mem_addr,
 245                           pinfo->dma_addr);
 246
 247         cpm_dpfree(pinfo->dp_addr);
 248 }
 249
 250 /* Setup any dynamic params in the uart desc */
 251 int cpm_uart_init_portdesc(void)
 252 {
 253         pr_debug("CPM uart[-]:init portdesc\n");
 254
 255         cpm_uart_nr = 0;
 256 #ifdef CONFIG_SERIAL_CPM_SMC1
 257         cpm_uart_ports[UART_SMC1].smcp = (smc_t *) & cpm2_immr->im_smc[0];
 258         cpm_uart_ports[UART_SMC1].smcup =
 259             (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC1];
 260         cpm_uart_ports[UART_SMC1].port.mapbase =
 261             (unsigned long)&cpm2_immr->im_smc[0];
 262         cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
 263         cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 264         cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 265         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
 266 #endif
 267
 268 #ifdef CONFIG_SERIAL_CPM_SMC2
 269         cpm_uart_ports[UART_SMC2].smcp = (smc_t *) & cpm2_immr->im_smc[1];
 270         cpm_uart_ports[UART_SMC2].smcup =
 271             (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC2];
 272         cpm_uart_ports[UART_SMC2].port.mapbase =
 273             (unsigned long)&cpm2_immr->im_smc[1];
 274         cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
 275         cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 276         cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 277         cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
 278 #endif
 279
 280 #ifdef CONFIG_SERIAL_CPM_SCC1
 281         cpm_uart_ports[UART_SCC1].sccp = (scc_t *) & cpm2_immr->im_scc[0];
 282         cpm_uart_ports[UART_SCC1].sccup =
 283             (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC1];
 284         cpm_uart_ports[UART_SCC1].port.mapbase =
 285             (unsigned long)&cpm2_immr->im_scc[0];
 286         cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
 287             ~(UART_SCCM_TX | UART_SCCM_RX);
 288         cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
 289             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 290         cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 291         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
 292 #endif
 293
 294 #ifdef CONFIG_SERIAL_CPM_SCC2
 295         cpm_uart_ports[UART_SCC2].sccp = (scc_t *) & cpm2_immr->im_scc[1];
 296         cpm_uart_ports[UART_SCC2].sccup =
 297             (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC2];
 298         cpm_uart_ports[UART_SCC2].port.mapbase =
 299             (unsigned long)&cpm2_immr->im_scc[1];
 300         cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
 301             ~(UART_SCCM_TX | UART_SCCM_RX);
 302         cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
 303             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 304         cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 305         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
 306 #endif
 307
 308 #ifdef CONFIG_SERIAL_CPM_SCC3
 309         cpm_uart_ports[UART_SCC3].sccp = (scc_t *) & cpm2_immr->im_scc[2];
 310         cpm_uart_ports[UART_SCC3].sccup =
 311             (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC3];
 312         cpm_uart_ports[UART_SCC3].port.mapbase =
 313             (unsigned long)&cpm2_immr->im_scc[2];
 314         cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
 315             ~(UART_SCCM_TX | UART_SCCM_RX);
 316         cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
 317             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 318         cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 319         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
 320 #endif
 321
 322 #ifdef CONFIG_SERIAL_CPM_SCC4
 323         cpm_uart_ports[UART_SCC4].sccp = (scc_t *) & cpm2_immr->im_scc[3];
 324         cpm_uart_ports[UART_SCC4].sccup =
 325             (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC4];
 326         cpm_uart_ports[UART_SCC4].port.mapbase =
 327             (unsigned long)&cpm2_immr->im_scc[3];
 328         cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
 329             ~(UART_SCCM_TX | UART_SCCM_RX);
 330         cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
 331             ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 332         cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq);
 333         cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
 334 #endif
 335
 336         return 0;
 337 }