git.oblomov.eu Git - linux-2.6/blob - drivers/serial/jsm/jsm_neo.c

   1 /************************************************************************
   2  * Copyright 2003 Digi International (www.digi.com)
   3  *
   4  * Copyright (C) 2004 IBM Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2, or (at your option)
   9  * any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
  13  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  14  * PURPOSE.  See the GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
  19  * MA  02111-1307, USA.
  20  *
  21  * Contact Information:
  22  * Scott H Kilau <Scott_Kilau@digi.com>
  23  * Wendy Xiong   <wendyx@us.ltcfwd.linux.ibm.com>
  24  *
  25  ***********************************************************************/
  26 #include <linux/delay.h>        /* For udelay */
  27 #include <linux/serial_reg.h>   /* For the various UART offsets */
  28 #include <linux/tty.h>
  29 #include <linux/pci.h>
  30 #include <asm/io.h>
  31
  32 #include "jsm.h"                /* Driver main header file */
  33
  34 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
  35
  36 /*
  37  * This function allows calls to ensure that all outstanding
  38  * PCI writes have been completed, by doing a PCI read against
  39  * a non-destructive, read-only location on the Neo card.
  40  *
  41  * In this case, we are reading the DVID (Read-only Device Identification)
  42  * value of the Neo card.
  43  */
  44 static inline void neo_pci_posting_flush(struct jsm_board *bd)
  45 {
  46       readb(bd->re_map_membase + 0x8D);
  47 }
  48
  49 static void neo_set_cts_flow_control(struct jsm_channel *ch)
  50 {
  51         u8 ier = readb(&ch->ch_neo_uart->ier);
  52         u8 efr = readb(&ch->ch_neo_uart->efr);
  53
  54         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
  55
  56         /* Turn on auto CTS flow control */
  57         ier |= (UART_17158_IER_CTSDSR);
  58         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
  59
  60         /* Turn off auto Xon flow control */
  61         efr &= ~(UART_17158_EFR_IXON);
  62
  63         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
  64         writeb(0, &ch->ch_neo_uart->efr);
  65
  66         /* Turn on UART enhanced bits */
  67         writeb(efr, &ch->ch_neo_uart->efr);
  68
  69         /* Turn on table D, with 8 char hi/low watermarks */
  70         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
  71
  72         /* Feed the UART our trigger levels */
  73         writeb(8, &ch->ch_neo_uart->tfifo);
  74         ch->ch_t_tlevel = 8;
  75
  76         writeb(ier, &ch->ch_neo_uart->ier);
  77 }
  78
  79 static void neo_set_rts_flow_control(struct jsm_channel *ch)
  80 {
  81         u8 ier = readb(&ch->ch_neo_uart->ier);
  82         u8 efr = readb(&ch->ch_neo_uart->efr);
  83
  84         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
  85
  86         /* Turn on auto RTS flow control */
  87         ier |= (UART_17158_IER_RTSDTR);
  88         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
  89
  90         /* Turn off auto Xoff flow control */
  91         ier &= ~(UART_17158_IER_XOFF);
  92         efr &= ~(UART_17158_EFR_IXOFF);
  93
  94         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
  95         writeb(0, &ch->ch_neo_uart->efr);
  96
  97         /* Turn on UART enhanced bits */
  98         writeb(efr, &ch->ch_neo_uart->efr);
  99
 100         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
 101         ch->ch_r_watermark = 4;
 102
 103         writeb(56, &ch->ch_neo_uart->rfifo);
 104         ch->ch_r_tlevel = 56;
 105
 106         writeb(ier, &ch->ch_neo_uart->ier);
 107
 108         /*
 109          * From the Neo UART spec sheet:
 110          * The auto RTS/DTR function must be started by asserting
 111          * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
 112          * it is enabled.
 113          */
 114         ch->ch_mostat |= (UART_MCR_RTS);
 115 }
 116
 117
 118 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
 119 {
 120         u8 ier = readb(&ch->ch_neo_uart->ier);
 121         u8 efr = readb(&ch->ch_neo_uart->efr);
 122
 123         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
 124
 125         /* Turn off auto CTS flow control */
 126         ier &= ~(UART_17158_IER_CTSDSR);
 127         efr &= ~(UART_17158_EFR_CTSDSR);
 128
 129         /* Turn on auto Xon flow control */
 130         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
 131
 132         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
 133         writeb(0, &ch->ch_neo_uart->efr);
 134
 135         /* Turn on UART enhanced bits */
 136         writeb(efr, &ch->ch_neo_uart->efr);
 137
 138         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
 139         ch->ch_r_watermark = 4;
 140
 141         writeb(32, &ch->ch_neo_uart->rfifo);
 142         ch->ch_r_tlevel = 32;
 143
 144         /* Tell UART what start/stop chars it should be looking for */
 145         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
 146         writeb(0, &ch->ch_neo_uart->xonchar2);
 147
 148         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
 149         writeb(0, &ch->ch_neo_uart->xoffchar2);
 150
 151         writeb(ier, &ch->ch_neo_uart->ier);
 152 }
 153
 154 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
 155 {
 156         u8 ier = readb(&ch->ch_neo_uart->ier);
 157         u8 efr = readb(&ch->ch_neo_uart->efr);
 158
 159         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
 160
 161         /* Turn off auto RTS flow control */
 162         ier &= ~(UART_17158_IER_RTSDTR);
 163         efr &= ~(UART_17158_EFR_RTSDTR);
 164
 165         /* Turn on auto Xoff flow control */
 166         ier |= (UART_17158_IER_XOFF);
 167         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
 168
 169         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
 170         writeb(0, &ch->ch_neo_uart->efr);
 171
 172         /* Turn on UART enhanced bits */
 173         writeb(efr, &ch->ch_neo_uart->efr);
 174
 175         /* Turn on table D, with 8 char hi/low watermarks */
 176         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
 177
 178         writeb(8, &ch->ch_neo_uart->tfifo);
 179         ch->ch_t_tlevel = 8;
 180
 181         /* Tell UART what start/stop chars it should be looking for */
 182         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
 183         writeb(0, &ch->ch_neo_uart->xonchar2);
 184
 185         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
 186         writeb(0, &ch->ch_neo_uart->xoffchar2);
 187
 188         writeb(ier, &ch->ch_neo_uart->ier);
 189 }
 190
 191 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
 192 {
 193         u8 ier = readb(&ch->ch_neo_uart->ier);
 194         u8 efr = readb(&ch->ch_neo_uart->efr);
 195
 196         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
 197
 198         /* Turn off auto RTS flow control */
 199         ier &= ~(UART_17158_IER_RTSDTR);
 200         efr &= ~(UART_17158_EFR_RTSDTR);
 201
 202         /* Turn off auto Xoff flow control */
 203         ier &= ~(UART_17158_IER_XOFF);
 204         if (ch->ch_c_iflag & IXON)
 205                 efr &= ~(UART_17158_EFR_IXOFF);
 206         else
 207                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
 208
 209         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
 210         writeb(0, &ch->ch_neo_uart->efr);
 211
 212         /* Turn on UART enhanced bits */
 213         writeb(efr, &ch->ch_neo_uart->efr);
 214
 215         /* Turn on table D, with 8 char hi/low watermarks */
 216         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
 217
 218         ch->ch_r_watermark = 0;
 219
 220         writeb(16, &ch->ch_neo_uart->tfifo);
 221         ch->ch_t_tlevel = 16;
 222
 223         writeb(16, &ch->ch_neo_uart->rfifo);
 224         ch->ch_r_tlevel = 16;
 225
 226         writeb(ier, &ch->ch_neo_uart->ier);
 227 }
 228
 229 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
 230 {
 231         u8 ier = readb(&ch->ch_neo_uart->ier);
 232         u8 efr = readb(&ch->ch_neo_uart->efr);
 233
 234         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
 235
 236         /* Turn off auto CTS flow control */
 237         ier &= ~(UART_17158_IER_CTSDSR);
 238         efr &= ~(UART_17158_EFR_CTSDSR);
 239
 240         /* Turn off auto Xon flow control */
 241         if (ch->ch_c_iflag & IXOFF)
 242                 efr &= ~(UART_17158_EFR_IXON);
 243         else
 244                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
 245
 246         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
 247         writeb(0, &ch->ch_neo_uart->efr);
 248
 249         /* Turn on UART enhanced bits */
 250         writeb(efr, &ch->ch_neo_uart->efr);
 251
 252         /* Turn on table D, with 8 char hi/low watermarks */
 253         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
 254
 255         ch->ch_r_watermark = 0;
 256
 257         writeb(16, &ch->ch_neo_uart->tfifo);
 258         ch->ch_t_tlevel = 16;
 259
 260         writeb(16, &ch->ch_neo_uart->rfifo);
 261         ch->ch_r_tlevel = 16;
 262
 263         writeb(ier, &ch->ch_neo_uart->ier);
 264 }
 265
 266 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
 267 {
 268
 269         /* if hardware flow control is set, then skip this whole thing */
 270         if (ch->ch_c_cflag & CRTSCTS)
 271                 return;
 272
 273         jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "start\n");
 274
 275         /* Tell UART what start/stop chars it should be looking for */
 276         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
 277         writeb(0, &ch->ch_neo_uart->xonchar2);
 278
 279         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
 280         writeb(0, &ch->ch_neo_uart->xoffchar2);
 281 }
 282
 283 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
 284 {
 285         int qleft = 0;
 286         u8 linestatus = 0;
 287         u8 error_mask = 0;
 288         int n = 0;
 289         int total = 0;
 290         u16 head;
 291         u16 tail;
 292
 293         if (!ch)
 294                 return;
 295
 296         /* cache head and tail of queue */
 297         head = ch->ch_r_head & RQUEUEMASK;
 298         tail = ch->ch_r_tail & RQUEUEMASK;
 299
 300         /* Get our cached LSR */
 301         linestatus = ch->ch_cached_lsr;
 302         ch->ch_cached_lsr = 0;
 303
 304         /* Store how much space we have left in the queue */
 305         if ((qleft = tail - head - 1) < 0)
 306                 qleft += RQUEUEMASK + 1;
 307
 308         /*
 309          * If the UART is not in FIFO mode, force the FIFO copy to
 310          * NOT be run, by setting total to 0.
 311          *
 312          * On the other hand, if the UART IS in FIFO mode, then ask
 313          * the UART to give us an approximation of data it has RX'ed.
 314          */
 315         if (!(ch->ch_flags & CH_FIFO_ENABLED))
 316                 total = 0;
 317         else {
 318                 total = readb(&ch->ch_neo_uart->rfifo);
 319
 320                 /*
 321                  * EXAR chip bug - RX FIFO COUNT - Fudge factor.
 322                  *
 323                  * This resolves a problem/bug with the Exar chip that sometimes
 324                  * returns a bogus value in the rfifo register.
 325                  * The count can be any where from 0-3 bytes "off".
 326                  * Bizarre, but true.
 327                  */
 328                 total -= 3;
 329         }
 330
 331         /*
 332          * Finally, bound the copy to make sure we don't overflow
 333          * our own queue...
 334          * The byte by byte copy loop below this loop this will
 335          * deal with the queue overflow possibility.
 336          */
 337         total = min(total, qleft);
 338
 339         while (total > 0) {
 340                 /*
 341                  * Grab the linestatus register, we need to check
 342                  * to see if there are any errors in the FIFO.
 343                  */
 344                 linestatus = readb(&ch->ch_neo_uart->lsr);
 345
 346                 /*
 347                  * Break out if there is a FIFO error somewhere.
 348                  * This will allow us to go byte by byte down below,
 349                  * finding the exact location of the error.
 350                  */
 351                 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
 352                         break;
 353
 354                 /* Make sure we don't go over the end of our queue */
 355                 n = min(((u32) total), (RQUEUESIZE - (u32) head));
 356
 357                 /*
 358                  * Cut down n even further if needed, this is to fix
 359                  * a problem with memcpy_fromio() with the Neo on the
 360                  * IBM pSeries platform.
 361                  * 15 bytes max appears to be the magic number.
 362                  */
 363                 n = min((u32) n, (u32) 12);
 364
 365                 /*
 366                  * Since we are grabbing the linestatus register, which
 367                  * will reset some bits after our read, we need to ensure
 368                  * we don't miss our TX FIFO emptys.
 369                  */
 370                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
 371                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 372
 373                 linestatus = 0;
 374
 375                 /* Copy data from uart to the queue */
 376                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
 377                 /*
 378                  * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
 379                  * that all the data currently in the FIFO is free of
 380                  * breaks and parity/frame/orun errors.
 381                  */
 382                 memset(ch->ch_equeue + head, 0, n);
 383
 384                 /* Add to and flip head if needed */
 385                 head = (head + n) & RQUEUEMASK;
 386                 total -= n;
 387                 qleft -= n;
 388                 ch->ch_rxcount += n;
 389         }
 390
 391         /*
 392          * Create a mask to determine whether we should
 393          * insert the character (if any) into our queue.
 394          */
 395         if (ch->ch_c_iflag & IGNBRK)
 396                 error_mask |= UART_LSR_BI;
 397
 398         /*
 399          * Now cleanup any leftover bytes still in the UART.
 400          * Also deal with any possible queue overflow here as well.
 401          */
 402         while (1) {
 403
 404                 /*
 405                  * Its possible we have a linestatus from the loop above
 406                  * this, so we "OR" on any extra bits.
 407                  */
 408                 linestatus |= readb(&ch->ch_neo_uart->lsr);
 409
 410                 /*
 411                  * If the chip tells us there is no more data pending to
 412                  * be read, we can then leave.
 413                  * But before we do, cache the linestatus, just in case.
 414                  */
 415                 if (!(linestatus & UART_LSR_DR)) {
 416                         ch->ch_cached_lsr = linestatus;
 417                         break;
 418                 }
 419
 420                 /* No need to store this bit */
 421                 linestatus &= ~UART_LSR_DR;
 422
 423                 /*
 424                  * Since we are grabbing the linestatus register, which
 425                  * will reset some bits after our read, we need to ensure
 426                  * we don't miss our TX FIFO emptys.
 427                  */
 428                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
 429                         linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
 430                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 431                 }
 432
 433                 /*
 434                  * Discard character if we are ignoring the error mask.
 435                  */
 436                 if (linestatus & error_mask) {
 437                         u8 discard;
 438                         linestatus = 0;
 439                         memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
 440                         continue;
 441                 }
 442
 443                 /*
 444                  * If our queue is full, we have no choice but to drop some data.
 445                  * The assumption is that HWFLOW or SWFLOW should have stopped
 446                  * things way way before we got to this point.
 447                  *
 448                  * I decided that I wanted to ditch the oldest data first,
 449                  * I hope thats okay with everyone? Yes? Good.
 450                  */
 451                 while (qleft < 1) {
 452                         jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
 453                                 "Queue full, dropping DATA:%x LSR:%x\n",
 454                                 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
 455
 456                         ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
 457                         ch->ch_err_overrun++;
 458                         qleft++;
 459                 }
 460
 461                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
 462                 ch->ch_equeue[head] = (u8) linestatus;
 463
 464                 jsm_printk(READ, INFO, &ch->ch_bd->pci_dev,
 465                                 "DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]);
 466
 467                 /* Ditch any remaining linestatus value. */
 468                 linestatus = 0;
 469
 470                 /* Add to and flip head if needed */
 471                 head = (head + 1) & RQUEUEMASK;
 472
 473                 qleft--;
 474                 ch->ch_rxcount++;
 475         }
 476
 477         /*
 478          * Write new final heads to channel structure.
 479          */
 480         ch->ch_r_head = head & RQUEUEMASK;
 481         ch->ch_e_head = head & EQUEUEMASK;
 482         jsm_input(ch);
 483 }
 484
 485 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
 486 {
 487         u16 head;
 488         u16 tail;
 489         int n;
 490         int s;
 491         int qlen;
 492         u32 len_written = 0;
 493
 494         if (!ch)
 495                 return;
 496
 497         /* No data to write to the UART */
 498         if (ch->ch_w_tail == ch->ch_w_head)
 499                 return;
 500
 501         /* If port is "stopped", don't send any data to the UART */
 502         if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
 503                 return;
 504         /*
 505          * If FIFOs are disabled. Send data directly to txrx register
 506          */
 507         if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
 508                 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
 509
 510                 ch->ch_cached_lsr |= lsrbits;
 511                 if (ch->ch_cached_lsr & UART_LSR_THRE) {
 512                         ch->ch_cached_lsr &= ~(UART_LSR_THRE);
 513
 514                         writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
 515                         jsm_printk(WRITE, INFO, &ch->ch_bd->pci_dev,
 516                                         "Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]);
 517                         ch->ch_w_tail++;
 518                         ch->ch_w_tail &= WQUEUEMASK;
 519                         ch->ch_txcount++;
 520                 }
 521                 return;
 522         }
 523
 524         /*
 525          * We have to do it this way, because of the EXAR TXFIFO count bug.
 526          */
 527         if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
 528                 return;
 529
 530         len_written = 0;
 531         n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
 532
 533         /* cache head and tail of queue */
 534         head = ch->ch_w_head & WQUEUEMASK;
 535         tail = ch->ch_w_tail & WQUEUEMASK;
 536         qlen = (head - tail) & WQUEUEMASK;
 537
 538         /* Find minimum of the FIFO space, versus queue length */
 539         n = min(n, qlen);
 540
 541         while (n > 0) {
 542
 543                 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
 544                 s = min(s, n);
 545
 546                 if (s <= 0)
 547                         break;
 548
 549                 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
 550                 /* Add and flip queue if needed */
 551                 tail = (tail + s) & WQUEUEMASK;
 552                 n -= s;
 553                 ch->ch_txcount += s;
 554                 len_written += s;
 555         }
 556
 557         /* Update the final tail */
 558         ch->ch_w_tail = tail & WQUEUEMASK;
 559
 560         if (len_written >= ch->ch_t_tlevel)
 561                 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 562
 563         if (!jsm_tty_write(&ch->uart_port))
 564                 uart_write_wakeup(&ch->uart_port);
 565 }
 566
 567 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
 568 {
 569         u8 msignals = signals;
 570
 571         jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
 572                         "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals);
 573
 574         if (!ch)
 575                 return;
 576
 577         /* Scrub off lower bits. They signify delta's, which I don't care about */
 578         msignals &= 0xf0;
 579
 580         if (msignals & UART_MSR_DCD)
 581                 ch->ch_mistat |= UART_MSR_DCD;
 582         else
 583                 ch->ch_mistat &= ~UART_MSR_DCD;
 584
 585         if (msignals & UART_MSR_DSR)
 586                 ch->ch_mistat |= UART_MSR_DSR;
 587         else
 588                 ch->ch_mistat &= ~UART_MSR_DSR;
 589
 590         if (msignals & UART_MSR_RI)
 591                 ch->ch_mistat |= UART_MSR_RI;
 592         else
 593                 ch->ch_mistat &= ~UART_MSR_RI;
 594
 595         if (msignals & UART_MSR_CTS)
 596                 ch->ch_mistat |= UART_MSR_CTS;
 597         else
 598                 ch->ch_mistat &= ~UART_MSR_CTS;
 599
 600         jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev,
 601                         "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
 602                 ch->ch_portnum,
 603                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
 604                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
 605                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
 606                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
 607                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
 608                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
 609 }
 610
 611 /* Make the UART raise any of the output signals we want up */
 612 static void neo_assert_modem_signals(struct jsm_channel *ch)
 613 {
 614         u8 out;
 615
 616         if (!ch)
 617                 return;
 618
 619         out = ch->ch_mostat;
 620
 621         writeb(out, &ch->ch_neo_uart->mcr);
 622
 623         /* flush write operation */
 624         neo_pci_posting_flush(ch->ch_bd);
 625 }
 626
 627 /*
 628  * Flush the WRITE FIFO on the Neo.
 629  *
 630  * NOTE: Channel lock MUST be held before calling this function!
 631  */
 632 static void neo_flush_uart_write(struct jsm_channel *ch)
 633 {
 634         u8 tmp = 0;
 635         int i = 0;
 636
 637         if (!ch)
 638                 return;
 639
 640         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
 641
 642         for (i = 0; i < 10; i++) {
 643
 644                 /* Check to see if the UART feels it completely flushed the FIFO. */
 645                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
 646                 if (tmp & 4) {
 647                         jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
 648                                         "Still flushing TX UART... i: %d\n", i);
 649                         udelay(10);
 650                 }
 651                 else
 652                         break;
 653         }
 654
 655         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 656 }
 657
 658
 659 /*
 660  * Flush the READ FIFO on the Neo.
 661  *
 662  * NOTE: Channel lock MUST be held before calling this function!
 663  */
 664 static void neo_flush_uart_read(struct jsm_channel *ch)
 665 {
 666         u8 tmp = 0;
 667         int i = 0;
 668
 669         if (!ch)
 670                 return;
 671
 672         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
 673
 674         for (i = 0; i < 10; i++) {
 675
 676                 /* Check to see if the UART feels it completely flushed the FIFO. */
 677                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
 678                 if (tmp & 2) {
 679                         jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
 680                                         "Still flushing RX UART... i: %d\n", i);
 681                         udelay(10);
 682                 }
 683                 else
 684                         break;
 685         }
 686 }
 687
 688 /*
 689  * No locks are assumed to be held when calling this function.
 690  */
 691 static void neo_clear_break(struct jsm_channel *ch, int force)
 692 {
 693         unsigned long lock_flags;
 694
 695         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 696
 697         /* Turn break off, and unset some variables */
 698         if (ch->ch_flags & CH_BREAK_SENDING) {
 699                 u8 temp = readb(&ch->ch_neo_uart->lcr);
 700                 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
 701
 702                 ch->ch_flags &= ~(CH_BREAK_SENDING);
 703                 jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
 704                                 "clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies);
 705
 706                 /* flush write operation */
 707                 neo_pci_posting_flush(ch->ch_bd);
 708         }
 709         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 710 }
 711
 712 /*
 713  * Parse the ISR register.
 714  */
 715 static inline void neo_parse_isr(struct jsm_board *brd, u32 port)
 716 {
 717         struct jsm_channel *ch;
 718         u8 isr;
 719         u8 cause;
 720         unsigned long lock_flags;
 721
 722         if (!brd)
 723                 return;
 724
 725         if (port > brd->maxports)
 726                 return;
 727
 728         ch = brd->channels[port];
 729         if (!ch)
 730                 return;
 731
 732         /* Here we try to figure out what caused the interrupt to happen */
 733         while (1) {
 734
 735                 isr = readb(&ch->ch_neo_uart->isr_fcr);
 736
 737                 /* Bail if no pending interrupt */
 738                 if (isr & UART_IIR_NO_INT)
 739                         break;
 740
 741                 /*
 742                  * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
 743                  */
 744                 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
 745
 746                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
 747                                 "%s:%d isr: %x\n", __FILE__, __LINE__, isr);
 748
 749                 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
 750                         /* Read data from uart -> queue */
 751                         neo_copy_data_from_uart_to_queue(ch);
 752
 753                         /* Call our tty layer to enforce queue flow control if needed. */
 754                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 755                         jsm_check_queue_flow_control(ch);
 756                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 757                 }
 758
 759                 if (isr & UART_IIR_THRI) {
 760                         /* Transfer data (if any) from Write Queue -> UART. */
 761                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 762                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 763                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 764                         neo_copy_data_from_queue_to_uart(ch);
 765                 }
 766
 767                 if (isr & UART_17158_IIR_XONXOFF) {
 768                         cause = readb(&ch->ch_neo_uart->xoffchar1);
 769
 770                         jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
 771                                         "Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause);
 772
 773                         /*
 774                          * Since the UART detected either an XON or
 775                          * XOFF match, we need to figure out which
 776                          * one it was, so we can suspend or resume data flow.
 777                          */
 778                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 779                         if (cause == UART_17158_XON_DETECT) {
 780                                 /* Is output stopped right now, if so, resume it */
 781                                 if (brd->channels[port]->ch_flags & CH_STOP) {
 782                                         ch->ch_flags &= ~(CH_STOP);
 783                                 }
 784                                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
 785                                                 "Port %d. XON detected in incoming data\n", port);
 786                         }
 787                         else if (cause == UART_17158_XOFF_DETECT) {
 788                                 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
 789                                         ch->ch_flags |= CH_STOP;
 790                                         jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
 791                                                         "Setting CH_STOP\n");
 792                                 }
 793                                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
 794                                                 "Port: %d. XOFF detected in incoming data\n", port);
 795                         }
 796                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 797                 }
 798
 799                 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
 800                         /*
 801                          * If we get here, this means the hardware is doing auto flow control.
 802                          * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
 803                          */
 804                         cause = readb(&ch->ch_neo_uart->mcr);
 805
 806                         /* Which pin is doing auto flow? RTS or DTR? */
 807                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 808                         if ((cause & 0x4) == 0) {
 809                                 if (cause & UART_MCR_RTS)
 810                                         ch->ch_mostat |= UART_MCR_RTS;
 811                                 else
 812                                         ch->ch_mostat &= ~(UART_MCR_RTS);
 813                         } else {
 814                                 if (cause & UART_MCR_DTR)
 815                                         ch->ch_mostat |= UART_MCR_DTR;
 816                                 else
 817                                         ch->ch_mostat &= ~(UART_MCR_DTR);
 818                         }
 819                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 820                 }
 821
 822                 /* Parse any modem signal changes */
 823                 jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
 824                                 "MOD_STAT: sending to parse_modem_sigs\n");
 825                 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
 826         }
 827 }
 828
 829 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
 830 {
 831         struct jsm_channel *ch;
 832         int linestatus;
 833         unsigned long lock_flags;
 834
 835         if (!brd)
 836                 return;
 837
 838         if (port > brd->maxports)
 839                 return;
 840
 841         ch = brd->channels[port];
 842         if (!ch)
 843                 return;
 844
 845         linestatus = readb(&ch->ch_neo_uart->lsr);
 846
 847         jsm_printk(INTR, INFO, &ch->ch_bd->pci_dev,
 848                         "%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus);
 849
 850         ch->ch_cached_lsr |= linestatus;
 851
 852         if (ch->ch_cached_lsr & UART_LSR_DR) {
 853                 /* Read data from uart -> queue */
 854                 neo_copy_data_from_uart_to_queue(ch);
 855                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
 856                 jsm_check_queue_flow_control(ch);
 857                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 858         }
 859
 860         /*
 861          * This is a special flag. It indicates that at least 1
 862          * RX error (parity, framing, or break) has happened.
 863          * Mark this in our struct, which will tell me that I have
 864          *to do the special RX+LSR read for this FIFO load.
 865          */
 866         if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
 867                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
 868                         "%s:%d Port: %d Got an RX error, need to parse LSR\n",
 869                         __FILE__, __LINE__, port);
 870
 871         /*
 872          * The next 3 tests should *NOT* happen, as the above test
 873          * should encapsulate all 3... At least, thats what Exar says.
 874          */
 875
 876         if (linestatus & UART_LSR_PE) {
 877                 ch->ch_err_parity++;
 878                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
 879                         "%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port);
 880         }
 881
 882         if (linestatus & UART_LSR_FE) {
 883                 ch->ch_err_frame++;
 884                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
 885                         "%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port);
 886         }
 887
 888         if (linestatus & UART_LSR_BI) {
 889                 ch->ch_err_break++;
 890                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
 891                         "%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port);
 892         }
 893
 894         if (linestatus & UART_LSR_OE) {
 895                 /*
 896                  * Rx Oruns. Exar says that an orun will NOT corrupt
 897                  * the FIFO. It will just replace the holding register
 898                  * with this new data byte. So basically just ignore this.
 899                  * Probably we should eventually have an orun stat in our driver...
 900                  */
 901                 ch->ch_err_overrun++;
 902                 jsm_printk(INTR, DEBUG, &ch->ch_bd->pci_dev,
 903                         "%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port);
 904         }
 905
 906         if (linestatus & UART_LSR_THRE) {
 907                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
 908                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 909                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 910
 911                 /* Transfer data (if any) from Write Queue -> UART. */
 912                 neo_copy_data_from_queue_to_uart(ch);
 913         }
 914         else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
 915                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
 916                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 917                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 918
 919                 /* Transfer data (if any) from Write Queue -> UART. */
 920                 neo_copy_data_from_queue_to_uart(ch);
 921         }
 922 }
 923
 924 /*
 925  * neo_param()
 926  * Send any/all changes to the line to the UART.
 927  */
 928 static void neo_param(struct jsm_channel *ch)
 929 {
 930         u8 lcr = 0;
 931         u8 uart_lcr = 0;
 932         u8 ier = 0;
 933         u32 baud = 9600;
 934         int quot = 0;
 935         struct jsm_board *bd;
 936
 937         bd = ch->ch_bd;
 938         if (!bd)
 939                 return;
 940
 941         /*
 942          * If baud rate is zero, flush queues, and set mval to drop DTR.
 943          */
 944         if ((ch->ch_c_cflag & (CBAUD)) == 0) {
 945                 ch->ch_r_head = ch->ch_r_tail = 0;
 946                 ch->ch_e_head = ch->ch_e_tail = 0;
 947                 ch->ch_w_head = ch->ch_w_tail = 0;
 948
 949                 neo_flush_uart_write(ch);
 950                 neo_flush_uart_read(ch);
 951
 952                 ch->ch_flags |= (CH_BAUD0);
 953                 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
 954                 neo_assert_modem_signals(ch);
 955                 ch->ch_old_baud = 0;
 956                 return;
 957
 958         } else if (ch->ch_custom_speed) {
 959                         baud = ch->ch_custom_speed;
 960                         if (ch->ch_flags & CH_BAUD0)
 961                                 ch->ch_flags &= ~(CH_BAUD0);
 962                 } else {
 963                         int iindex = 0;
 964                         int jindex = 0;
 965
 966                         const u64 bauds[4][16] = {
 967                                 {
 968                                         0,      50,     75,     110,
 969                                         134,    150,    200,    300,
 970                                         600,    1200,   1800,   2400,
 971                                         4800,   9600,   19200,  38400 },
 972                                 {
 973                                         0,      57600,  115200, 230400,
 974                                         460800, 150,    200,    921600,
 975                                         600,    1200,   1800,   2400,
 976                                         4800,   9600,   19200,  38400 },
 977                                 {
 978                                         0,      57600,  76800, 115200,
 979                                         131657, 153600, 230400, 460800,
 980                                         921600, 1200,   1800,   2400,
 981                                         4800,   9600,   19200,  38400 },
 982                                 {
 983                                         0,      57600,  115200, 230400,
 984                                         460800, 150,    200,    921600,
 985                                         600,    1200,   1800,   2400,
 986                                         4800,   9600,   19200,  38400 }
 987                         };
 988
 989                         baud = C_BAUD(ch->uart_port.info->tty) & 0xff;
 990
 991                         if (ch->ch_c_cflag & CBAUDEX)
 992                                 iindex = 1;
 993
 994                         jindex = baud;
 995
 996                         if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16))
 997                                 baud = bauds[iindex][jindex];
 998                         else {
 999                                 jsm_printk(IOCTL, DEBUG, &ch->ch_bd->pci_dev,
1000                                         "baud indices were out of range (%d)(%d)",
1001                                 iindex, jindex);
1002                                 baud = 0;
1003                         }
1004
1005                         if (baud == 0)
1006                                 baud = 9600;
1007
1008                         if (ch->ch_flags & CH_BAUD0)
1009                                 ch->ch_flags &= ~(CH_BAUD0);
1010                 }
1011
1012         if (ch->ch_c_cflag & PARENB)
1013                 lcr |= UART_LCR_PARITY;
1014
1015         if (!(ch->ch_c_cflag & PARODD))
1016                 lcr |= UART_LCR_EPAR;
1017
1018         /*
1019          * Not all platforms support mark/space parity,
1020          * so this will hide behind an ifdef.
1021          */
1022 #ifdef CMSPAR
1023         if (ch->ch_c_cflag & CMSPAR)
1024                 lcr |= UART_LCR_SPAR;
1025 #endif
1026
1027         if (ch->ch_c_cflag & CSTOPB)
1028                 lcr |= UART_LCR_STOP;
1029
1030         switch (ch->ch_c_cflag & CSIZE) {
1031                 case CS5:
1032                         lcr |= UART_LCR_WLEN5;
1033                         break;
1034                 case CS6:
1035                         lcr |= UART_LCR_WLEN6;
1036                         break;
1037                 case CS7:
1038                         lcr |= UART_LCR_WLEN7;
1039                         break;
1040                 case CS8:
1041                 default:
1042                         lcr |= UART_LCR_WLEN8;
1043                 break;
1044         }
1045
1046         ier = readb(&ch->ch_neo_uart->ier);
1047         uart_lcr = readb(&ch->ch_neo_uart->lcr);
1048
1049         if (baud == 0)
1050                 baud = 9600;
1051
1052         quot = ch->ch_bd->bd_dividend / baud;
1053
1054         if (quot != 0) {
1055                 ch->ch_old_baud = baud;
1056                 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1057                 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1058                 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1059                 writeb(lcr, &ch->ch_neo_uart->lcr);
1060         }
1061
1062         if (uart_lcr != lcr)
1063                 writeb(lcr, &ch->ch_neo_uart->lcr);
1064
1065         if (ch->ch_c_cflag & CREAD)
1066                 ier |= (UART_IER_RDI | UART_IER_RLSI);
1067
1068         ier |= (UART_IER_THRI | UART_IER_MSI);
1069
1070         writeb(ier, &ch->ch_neo_uart->ier);
1071
1072         /* Set new start/stop chars */
1073         neo_set_new_start_stop_chars(ch);
1074
1075         if (ch->ch_c_cflag & CRTSCTS)
1076                 neo_set_cts_flow_control(ch);
1077         else if (ch->ch_c_iflag & IXON) {
1078                 /* If start/stop is set to disable, then we should disable flow control */
1079                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1080                         neo_set_no_output_flow_control(ch);
1081                 else
1082                         neo_set_ixon_flow_control(ch);
1083         }
1084         else
1085                 neo_set_no_output_flow_control(ch);
1086
1087         if (ch->ch_c_cflag & CRTSCTS)
1088                 neo_set_rts_flow_control(ch);
1089         else if (ch->ch_c_iflag & IXOFF) {
1090                 /* If start/stop is set to disable, then we should disable flow control */
1091                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1092                         neo_set_no_input_flow_control(ch);
1093                 else
1094                         neo_set_ixoff_flow_control(ch);
1095         }
1096         else
1097                 neo_set_no_input_flow_control(ch);
1098         /*
1099          * Adjust the RX FIFO Trigger level if baud is less than 9600.
1100          * Not exactly elegant, but this is needed because of the Exar chip's
1101          * delay on firing off the RX FIFO interrupt on slower baud rates.
1102          */
1103         if (baud < 9600) {
1104                 writeb(1, &ch->ch_neo_uart->rfifo);
1105                 ch->ch_r_tlevel = 1;
1106         }
1107
1108         neo_assert_modem_signals(ch);
1109
1110         /* Get current status of the modem signals now */
1111         neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1112         return;
1113 }
1114
1115 /*
1116  * jsm_neo_intr()
1117  *
1118  * Neo specific interrupt handler.
1119  */
1120 static irqreturn_t neo_intr(int irq, void *voidbrd, struct pt_regs *regs)
1121 {
1122         struct jsm_board *brd = (struct jsm_board *) voidbrd;
1123         struct jsm_channel *ch;
1124         int port = 0;
1125         int type = 0;
1126         int current_port;
1127         u32 tmp;
1128         u32 uart_poll;
1129         unsigned long lock_flags;
1130         unsigned long lock_flags2;
1131         int outofloop_count = 0;
1132
1133         brd->intr_count++;
1134
1135         /* Lock out the slow poller from running on this board. */
1136         spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1137
1138         /*
1139          * Read in "extended" IRQ information from the 32bit Neo register.
1140          * Bits 0-7: What port triggered the interrupt.
1141          * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1142          */
1143         uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1144
1145         jsm_printk(INTR, INFO, &brd->pci_dev,
1146                 "%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll);
1147
1148         if (!uart_poll) {
1149                 jsm_printk(INTR, INFO, &brd->pci_dev,
1150                         "Kernel interrupted to me, but no pending interrupts...\n");
1151                 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1152                 return IRQ_NONE;
1153         }
1154
1155         /* At this point, we have at least SOMETHING to service, dig further... */
1156
1157         current_port = 0;
1158
1159         /* Loop on each port */
1160         while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1161
1162                 tmp = uart_poll;
1163                 outofloop_count++;
1164
1165                 /* Check current port to see if it has interrupt pending */
1166                 if ((tmp & jsm_offset_table[current_port]) != 0) {
1167                         port = current_port;
1168                         type = tmp >> (8 + (port * 3));
1169                         type &= 0x7;
1170                 } else {
1171                         current_port++;
1172                         continue;
1173                 }
1174
1175                 jsm_printk(INTR, INFO, &brd->pci_dev,
1176                 "%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type);
1177
1178                 /* Remove this port + type from uart_poll */
1179                 uart_poll &= ~(jsm_offset_table[port]);
1180
1181                 if (!type) {
1182                         /* If no type, just ignore it, and move onto next port */
1183                         jsm_printk(INTR, ERR, &brd->pci_dev,
1184                                 "Interrupt with no type! port: %d\n", port);
1185                         continue;
1186                 }
1187
1188                 /* Switch on type of interrupt we have */
1189                 switch (type) {
1190
1191                 case UART_17158_RXRDY_TIMEOUT:
1192                         /*
1193                          * RXRDY Time-out is cleared by reading data in the
1194                         * RX FIFO until it falls below the trigger level.
1195                          */
1196
1197                         /* Verify the port is in range. */
1198                         if (port > brd->nasync)
1199                                 continue;
1200
1201                         ch = brd->channels[port];
1202                         neo_copy_data_from_uart_to_queue(ch);
1203
1204                         /* Call our tty layer to enforce queue flow control if needed. */
1205                         spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1206                         jsm_check_queue_flow_control(ch);
1207                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1208
1209                         continue;
1210
1211                 case UART_17158_RX_LINE_STATUS:
1212                         /*
1213                          * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1214                          */
1215                         neo_parse_lsr(brd, port);
1216                         continue;
1217
1218                 case UART_17158_TXRDY:
1219                         /*
1220                          * TXRDY interrupt clears after reading ISR register for the UART channel.
1221                          */
1222
1223                         /*
1224                          * Yes, this is odd...
1225                          * Why would I check EVERY possibility of type of
1226                          * interrupt, when we know its TXRDY???
1227                          * Becuz for some reason, even tho we got triggered for TXRDY,
1228                          * it seems to be occassionally wrong. Instead of TX, which
1229                          * it should be, I was getting things like RXDY too. Weird.
1230                          */
1231                         neo_parse_isr(brd, port);
1232                         continue;
1233
1234                 case UART_17158_MSR:
1235                         /*
1236                          * MSR or flow control was seen.
1237                          */
1238                         neo_parse_isr(brd, port);
1239                         continue;
1240
1241                 default:
1242                         /*
1243                          * The UART triggered us with a bogus interrupt type.
1244                          * It appears the Exar chip, when REALLY bogged down, will throw
1245                          * these once and awhile.
1246                          * Its harmless, just ignore it and move on.
1247                          */
1248                         jsm_printk(INTR, ERR, &brd->pci_dev,
1249                                 "%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type);
1250                         continue;
1251                 }
1252         }
1253
1254         spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1255
1256         jsm_printk(INTR, INFO, &brd->pci_dev, "finish.\n");
1257         return IRQ_HANDLED;
1258 }
1259
1260 /*
1261  * Neo specific way of turning off the receiver.
1262  * Used as a way to enforce queue flow control when in
1263  * hardware flow control mode.
1264  */
1265 static void neo_disable_receiver(struct jsm_channel *ch)
1266 {
1267         u8 tmp = readb(&ch->ch_neo_uart->ier);
1268         tmp &= ~(UART_IER_RDI);
1269         writeb(tmp, &ch->ch_neo_uart->ier);
1270
1271         /* flush write operation */
1272         neo_pci_posting_flush(ch->ch_bd);
1273 }
1274
1275
1276 /*
1277  * Neo specific way of turning on the receiver.
1278  * Used as a way to un-enforce queue flow control when in
1279  * hardware flow control mode.
1280  */
1281 static void neo_enable_receiver(struct jsm_channel *ch)
1282 {
1283         u8 tmp = readb(&ch->ch_neo_uart->ier);
1284         tmp |= (UART_IER_RDI);
1285         writeb(tmp, &ch->ch_neo_uart->ier);
1286
1287         /* flush write operation */
1288         neo_pci_posting_flush(ch->ch_bd);
1289 }
1290
1291 static void neo_send_start_character(struct jsm_channel *ch)
1292 {
1293         if (!ch)
1294                 return;
1295
1296         if (ch->ch_startc != __DISABLED_CHAR) {
1297                 ch->ch_xon_sends++;
1298                 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1299
1300                 /* flush write operation */
1301                 neo_pci_posting_flush(ch->ch_bd);
1302         }
1303 }
1304
1305 static void neo_send_stop_character(struct jsm_channel *ch)
1306 {
1307         if (!ch)
1308                 return;
1309
1310         if (ch->ch_stopc != __DISABLED_CHAR) {
1311                 ch->ch_xoff_sends++;
1312                 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1313
1314                 /* flush write operation */
1315                 neo_pci_posting_flush(ch->ch_bd);
1316         }
1317 }
1318
1319 /*
1320  * neo_uart_init
1321  */
1322 static void neo_uart_init(struct jsm_channel *ch)
1323 {
1324         writeb(0, &ch->ch_neo_uart->ier);
1325         writeb(0, &ch->ch_neo_uart->efr);
1326         writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1327
1328         /* Clear out UART and FIFO */
1329         readb(&ch->ch_neo_uart->txrx);
1330         writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1331         readb(&ch->ch_neo_uart->lsr);
1332         readb(&ch->ch_neo_uart->msr);
1333
1334         ch->ch_flags |= CH_FIFO_ENABLED;
1335
1336         /* Assert any signals we want up */
1337         writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1338 }
1339
1340 /*
1341  * Make the UART completely turn off.
1342  */
1343 static void neo_uart_off(struct jsm_channel *ch)
1344 {
1345         /* Turn off UART enhanced bits */
1346         writeb(0, &ch->ch_neo_uart->efr);
1347
1348         /* Stop all interrupts from occurring. */
1349         writeb(0, &ch->ch_neo_uart->ier);
1350 }
1351
1352 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1353 {
1354         u8 left = 0;
1355         u8 lsr = readb(&ch->ch_neo_uart->lsr);
1356
1357         /* We must cache the LSR as some of the bits get reset once read... */
1358         ch->ch_cached_lsr |= lsr;
1359
1360         /* Determine whether the Transmitter is empty or not */
1361         if (!(lsr & UART_LSR_TEMT))
1362                 left = 1;
1363         else {
1364                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1365                 left = 0;
1366         }
1367
1368         return left;
1369 }
1370
1371 /* Channel lock MUST be held by the calling function! */
1372 static void neo_send_break(struct jsm_channel *ch)
1373 {
1374         /*
1375          * Set the time we should stop sending the break.
1376          * If we are already sending a break, toss away the existing
1377          * time to stop, and use this new value instead.
1378          */
1379
1380         /* Tell the UART to start sending the break */
1381         if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1382                 u8 temp = readb(&ch->ch_neo_uart->lcr);
1383                 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1384                 ch->ch_flags |= (CH_BREAK_SENDING);
1385
1386                 /* flush write operation */
1387                 neo_pci_posting_flush(ch->ch_bd);
1388         }
1389 }
1390
1391 /*
1392  * neo_send_immediate_char.
1393  *
1394  * Sends a specific character as soon as possible to the UART,
1395  * jumping over any bytes that might be in the write queue.
1396  *
1397  * The channel lock MUST be held by the calling function.
1398  */
1399 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1400 {
1401         if (!ch)
1402                 return;
1403
1404         writeb(c, &ch->ch_neo_uart->txrx);
1405
1406         /* flush write operation */
1407         neo_pci_posting_flush(ch->ch_bd);
1408 }
1409
1410 struct board_ops jsm_neo_ops = {
1411         .intr                           = neo_intr,
1412         .uart_init                      = neo_uart_init,
1413         .uart_off                       = neo_uart_off,
1414         .param                          = neo_param,
1415         .assert_modem_signals           = neo_assert_modem_signals,
1416         .flush_uart_write               = neo_flush_uart_write,
1417         .flush_uart_read                = neo_flush_uart_read,
1418         .disable_receiver               = neo_disable_receiver,
1419         .enable_receiver                = neo_enable_receiver,
1420         .send_break                     = neo_send_break,
1421         .clear_break                    = neo_clear_break,
1422         .send_start_character           = neo_send_start_character,
1423         .send_stop_character            = neo_send_stop_character,
1424         .copy_data_from_queue_to_uart   = neo_copy_data_from_queue_to_uart,
1425         .get_uart_bytes_left            = neo_get_uart_bytes_left,
1426         .send_immediate_char            = neo_send_immediate_char
1427 };