Merge branch 'pmtimer-overflow' into release
[linux-2.6] / arch / mips / kernel / cpu-probe.c
1 /*
2  * Processor capabilities determination functions.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004  MIPS Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
18
19 #include <asm/bugs.h>
20 #include <asm/cpu.h>
21 #include <asm/fpu.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
24 #include <asm/watch.h>
25
26 /*
27  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28  * the implementation of the "wait" feature differs between CPU families. This
29  * points to the function that implements CPU specific wait.
30  * The wait instruction stops the pipeline and reduces the power consumption of
31  * the CPU very much.
32  */
33 void (*cpu_wait)(void) = NULL;
34
35 static void r3081_wait(void)
36 {
37         unsigned long cfg = read_c0_conf();
38         write_c0_conf(cfg | R30XX_CONF_HALT);
39 }
40
41 static void r39xx_wait(void)
42 {
43         local_irq_disable();
44         if (!need_resched())
45                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
46         local_irq_enable();
47 }
48
49 extern void r4k_wait(void);
50
51 /*
52  * This variant is preferable as it allows testing need_resched and going to
53  * sleep depending on the outcome atomically.  Unfortunately the "It is
54  * implementation-dependent whether the pipeline restarts when a non-enabled
55  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
56  * using this version a gamble.
57  */
58 void r4k_wait_irqoff(void)
59 {
60         local_irq_disable();
61         if (!need_resched())
62                 __asm__("       .set    push            \n"
63                         "       .set    mips3           \n"
64                         "       wait                    \n"
65                         "       .set    pop             \n");
66         local_irq_enable();
67         __asm__("       .globl __pastwait       \n"
68                 "__pastwait:                    \n");
69         return;
70 }
71
72 /*
73  * The RM7000 variant has to handle erratum 38.  The workaround is to not
74  * have any pending stores when the WAIT instruction is executed.
75  */
76 static void rm7k_wait_irqoff(void)
77 {
78         local_irq_disable();
79         if (!need_resched())
80                 __asm__(
81                 "       .set    push                                    \n"
82                 "       .set    mips3                                   \n"
83                 "       .set    noat                                    \n"
84                 "       mfc0    $1, $12                                 \n"
85                 "       sync                                            \n"
86                 "       mtc0    $1, $12         # stalls until W stage  \n"
87                 "       wait                                            \n"
88                 "       mtc0    $1, $12         # stalls until W stage  \n"
89                 "       .set    pop                                     \n");
90         local_irq_enable();
91 }
92
93 /* The Au1xxx wait is available only if using 32khz counter or
94  * external timer source, but specifically not CP0 Counter. */
95 int allow_au1k_wait;
96
97 static void au1k_wait(void)
98 {
99         if (!allow_au1k_wait)
100                 return;
101
102         /* using the wait instruction makes CP0 counter unusable */
103         __asm__("       .set    mips3                   \n"
104                 "       cache   0x14, 0(%0)             \n"
105                 "       cache   0x14, 32(%0)            \n"
106                 "       sync                            \n"
107                 "       nop                             \n"
108                 "       wait                            \n"
109                 "       nop                             \n"
110                 "       nop                             \n"
111                 "       nop                             \n"
112                 "       nop                             \n"
113                 "       .set    mips0                   \n"
114                 : : "r" (au1k_wait));
115 }
116
117 static int __initdata nowait = 0;
118
119 static int __init wait_disable(char *s)
120 {
121         nowait = 1;
122
123         return 1;
124 }
125
126 __setup("nowait", wait_disable);
127
128 void __init check_wait(void)
129 {
130         struct cpuinfo_mips *c = &current_cpu_data;
131
132         if (nowait) {
133                 printk("Wait instruction disabled.\n");
134                 return;
135         }
136
137         switch (c->cputype) {
138         case CPU_R3081:
139         case CPU_R3081E:
140                 cpu_wait = r3081_wait;
141                 break;
142         case CPU_TX3927:
143                 cpu_wait = r39xx_wait;
144                 break;
145         case CPU_R4200:
146 /*      case CPU_R4300: */
147         case CPU_R4600:
148         case CPU_R4640:
149         case CPU_R4650:
150         case CPU_R4700:
151         case CPU_R5000:
152         case CPU_R5500:
153         case CPU_NEVADA:
154         case CPU_4KC:
155         case CPU_4KEC:
156         case CPU_4KSC:
157         case CPU_5KC:
158         case CPU_25KF:
159         case CPU_PR4450:
160         case CPU_BCM3302:
161         case CPU_CAVIUM_OCTEON:
162                 cpu_wait = r4k_wait;
163                 break;
164
165         case CPU_RM7000:
166                 cpu_wait = rm7k_wait_irqoff;
167                 break;
168
169         case CPU_24K:
170         case CPU_34K:
171         case CPU_1004K:
172                 cpu_wait = r4k_wait;
173                 if (read_c0_config7() & MIPS_CONF7_WII)
174                         cpu_wait = r4k_wait_irqoff;
175                 break;
176
177         case CPU_74K:
178                 cpu_wait = r4k_wait;
179                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
180                         cpu_wait = r4k_wait_irqoff;
181                 break;
182
183         case CPU_TX49XX:
184                 cpu_wait = r4k_wait_irqoff;
185                 break;
186         case CPU_AU1000:
187         case CPU_AU1100:
188         case CPU_AU1500:
189         case CPU_AU1550:
190         case CPU_AU1200:
191         case CPU_AU1210:
192         case CPU_AU1250:
193                 cpu_wait = au1k_wait;
194                 break;
195         case CPU_20KC:
196                 /*
197                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
198                  * WAIT on Rev2.0 and Rev3.0 has E16.
199                  * Rev3.1 WAIT is nop, why bother
200                  */
201                 if ((c->processor_id & 0xff) <= 0x64)
202                         break;
203
204                 /*
205                  * Another rev is incremeting c0_count at a reduced clock
206                  * rate while in WAIT mode.  So we basically have the choice
207                  * between using the cp0 timer as clocksource or avoiding
208                  * the WAIT instruction.  Until more details are known,
209                  * disable the use of WAIT for 20Kc entirely.
210                    cpu_wait = r4k_wait;
211                  */
212                 break;
213         case CPU_RM9000:
214                 if ((c->processor_id & 0x00ff) >= 0x40)
215                         cpu_wait = r4k_wait;
216                 break;
217         default:
218                 break;
219         }
220 }
221
222 static inline void check_errata(void)
223 {
224         struct cpuinfo_mips *c = &current_cpu_data;
225
226         switch (c->cputype) {
227         case CPU_34K:
228                 /*
229                  * Erratum "RPS May Cause Incorrect Instruction Execution"
230                  * This code only handles VPE0, any SMP/SMTC/RTOS code
231                  * making use of VPE1 will be responsable for that VPE.
232                  */
233                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
234                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
235                 break;
236         default:
237                 break;
238         }
239 }
240
241 void __init check_bugs32(void)
242 {
243         check_errata();
244 }
245
246 /*
247  * Probe whether cpu has config register by trying to play with
248  * alternate cache bit and see whether it matters.
249  * It's used by cpu_probe to distinguish between R3000A and R3081.
250  */
251 static inline int cpu_has_confreg(void)
252 {
253 #ifdef CONFIG_CPU_R3000
254         extern unsigned long r3k_cache_size(unsigned long);
255         unsigned long size1, size2;
256         unsigned long cfg = read_c0_conf();
257
258         size1 = r3k_cache_size(ST0_ISC);
259         write_c0_conf(cfg ^ R30XX_CONF_AC);
260         size2 = r3k_cache_size(ST0_ISC);
261         write_c0_conf(cfg);
262         return size1 != size2;
263 #else
264         return 0;
265 #endif
266 }
267
268 /*
269  * Get the FPU Implementation/Revision.
270  */
271 static inline unsigned long cpu_get_fpu_id(void)
272 {
273         unsigned long tmp, fpu_id;
274
275         tmp = read_c0_status();
276         __enable_fpu();
277         fpu_id = read_32bit_cp1_register(CP1_REVISION);
278         write_c0_status(tmp);
279         return fpu_id;
280 }
281
282 /*
283  * Check the CPU has an FPU the official way.
284  */
285 static inline int __cpu_has_fpu(void)
286 {
287         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
288 }
289
290 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
291                 | MIPS_CPU_COUNTER)
292
293 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
294 {
295         switch (c->processor_id & 0xff00) {
296         case PRID_IMP_R2000:
297                 c->cputype = CPU_R2000;
298                 __cpu_name[cpu] = "R2000";
299                 c->isa_level = MIPS_CPU_ISA_I;
300                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
301                              MIPS_CPU_NOFPUEX;
302                 if (__cpu_has_fpu())
303                         c->options |= MIPS_CPU_FPU;
304                 c->tlbsize = 64;
305                 break;
306         case PRID_IMP_R3000:
307                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
308                         if (cpu_has_confreg()) {
309                                 c->cputype = CPU_R3081E;
310                                 __cpu_name[cpu] = "R3081";
311                         } else {
312                                 c->cputype = CPU_R3000A;
313                                 __cpu_name[cpu] = "R3000A";
314                         }
315                         break;
316                 } else {
317                         c->cputype = CPU_R3000;
318                         __cpu_name[cpu] = "R3000";
319                 }
320                 c->isa_level = MIPS_CPU_ISA_I;
321                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
322                              MIPS_CPU_NOFPUEX;
323                 if (__cpu_has_fpu())
324                         c->options |= MIPS_CPU_FPU;
325                 c->tlbsize = 64;
326                 break;
327         case PRID_IMP_R4000:
328                 if (read_c0_config() & CONF_SC) {
329                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
330                                 c->cputype = CPU_R4400PC;
331                                 __cpu_name[cpu] = "R4400PC";
332                         } else {
333                                 c->cputype = CPU_R4000PC;
334                                 __cpu_name[cpu] = "R4000PC";
335                         }
336                 } else {
337                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
338                                 c->cputype = CPU_R4400SC;
339                                 __cpu_name[cpu] = "R4400SC";
340                         } else {
341                                 c->cputype = CPU_R4000SC;
342                                 __cpu_name[cpu] = "R4000SC";
343                         }
344                 }
345
346                 c->isa_level = MIPS_CPU_ISA_III;
347                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
348                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
349                              MIPS_CPU_LLSC;
350                 c->tlbsize = 48;
351                 break;
352         case PRID_IMP_VR41XX:
353                 switch (c->processor_id & 0xf0) {
354                 case PRID_REV_VR4111:
355                         c->cputype = CPU_VR4111;
356                         __cpu_name[cpu] = "NEC VR4111";
357                         break;
358                 case PRID_REV_VR4121:
359                         c->cputype = CPU_VR4121;
360                         __cpu_name[cpu] = "NEC VR4121";
361                         break;
362                 case PRID_REV_VR4122:
363                         if ((c->processor_id & 0xf) < 0x3) {
364                                 c->cputype = CPU_VR4122;
365                                 __cpu_name[cpu] = "NEC VR4122";
366                         } else {
367                                 c->cputype = CPU_VR4181A;
368                                 __cpu_name[cpu] = "NEC VR4181A";
369                         }
370                         break;
371                 case PRID_REV_VR4130:
372                         if ((c->processor_id & 0xf) < 0x4) {
373                                 c->cputype = CPU_VR4131;
374                                 __cpu_name[cpu] = "NEC VR4131";
375                         } else {
376                                 c->cputype = CPU_VR4133;
377                                 __cpu_name[cpu] = "NEC VR4133";
378                         }
379                         break;
380                 default:
381                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
382                         c->cputype = CPU_VR41XX;
383                         __cpu_name[cpu] = "NEC Vr41xx";
384                         break;
385                 }
386                 c->isa_level = MIPS_CPU_ISA_III;
387                 c->options = R4K_OPTS;
388                 c->tlbsize = 32;
389                 break;
390         case PRID_IMP_R4300:
391                 c->cputype = CPU_R4300;
392                 __cpu_name[cpu] = "R4300";
393                 c->isa_level = MIPS_CPU_ISA_III;
394                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
395                              MIPS_CPU_LLSC;
396                 c->tlbsize = 32;
397                 break;
398         case PRID_IMP_R4600:
399                 c->cputype = CPU_R4600;
400                 __cpu_name[cpu] = "R4600";
401                 c->isa_level = MIPS_CPU_ISA_III;
402                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
403                              MIPS_CPU_LLSC;
404                 c->tlbsize = 48;
405                 break;
406         #if 0
407         case PRID_IMP_R4650:
408                 /*
409                  * This processor doesn't have an MMU, so it's not
410                  * "real easy" to run Linux on it. It is left purely
411                  * for documentation.  Commented out because it shares
412                  * it's c0_prid id number with the TX3900.
413                  */
414                 c->cputype = CPU_R4650;
415                 __cpu_name[cpu] = "R4650";
416                 c->isa_level = MIPS_CPU_ISA_III;
417                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
418                 c->tlbsize = 48;
419                 break;
420         #endif
421         case PRID_IMP_TX39:
422                 c->isa_level = MIPS_CPU_ISA_I;
423                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
424
425                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
426                         c->cputype = CPU_TX3927;
427                         __cpu_name[cpu] = "TX3927";
428                         c->tlbsize = 64;
429                 } else {
430                         switch (c->processor_id & 0xff) {
431                         case PRID_REV_TX3912:
432                                 c->cputype = CPU_TX3912;
433                                 __cpu_name[cpu] = "TX3912";
434                                 c->tlbsize = 32;
435                                 break;
436                         case PRID_REV_TX3922:
437                                 c->cputype = CPU_TX3922;
438                                 __cpu_name[cpu] = "TX3922";
439                                 c->tlbsize = 64;
440                                 break;
441                         }
442                 }
443                 break;
444         case PRID_IMP_R4700:
445                 c->cputype = CPU_R4700;
446                 __cpu_name[cpu] = "R4700";
447                 c->isa_level = MIPS_CPU_ISA_III;
448                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
449                              MIPS_CPU_LLSC;
450                 c->tlbsize = 48;
451                 break;
452         case PRID_IMP_TX49:
453                 c->cputype = CPU_TX49XX;
454                 __cpu_name[cpu] = "R49XX";
455                 c->isa_level = MIPS_CPU_ISA_III;
456                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
457                 if (!(c->processor_id & 0x08))
458                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
459                 c->tlbsize = 48;
460                 break;
461         case PRID_IMP_R5000:
462                 c->cputype = CPU_R5000;
463                 __cpu_name[cpu] = "R5000";
464                 c->isa_level = MIPS_CPU_ISA_IV;
465                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
466                              MIPS_CPU_LLSC;
467                 c->tlbsize = 48;
468                 break;
469         case PRID_IMP_R5432:
470                 c->cputype = CPU_R5432;
471                 __cpu_name[cpu] = "R5432";
472                 c->isa_level = MIPS_CPU_ISA_IV;
473                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
474                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
475                 c->tlbsize = 48;
476                 break;
477         case PRID_IMP_R5500:
478                 c->cputype = CPU_R5500;
479                 __cpu_name[cpu] = "R5500";
480                 c->isa_level = MIPS_CPU_ISA_IV;
481                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
482                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
483                 c->tlbsize = 48;
484                 break;
485         case PRID_IMP_NEVADA:
486                 c->cputype = CPU_NEVADA;
487                 __cpu_name[cpu] = "Nevada";
488                 c->isa_level = MIPS_CPU_ISA_IV;
489                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
490                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
491                 c->tlbsize = 48;
492                 break;
493         case PRID_IMP_R6000:
494                 c->cputype = CPU_R6000;
495                 __cpu_name[cpu] = "R6000";
496                 c->isa_level = MIPS_CPU_ISA_II;
497                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
498                              MIPS_CPU_LLSC;
499                 c->tlbsize = 32;
500                 break;
501         case PRID_IMP_R6000A:
502                 c->cputype = CPU_R6000A;
503                 __cpu_name[cpu] = "R6000A";
504                 c->isa_level = MIPS_CPU_ISA_II;
505                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
506                              MIPS_CPU_LLSC;
507                 c->tlbsize = 32;
508                 break;
509         case PRID_IMP_RM7000:
510                 c->cputype = CPU_RM7000;
511                 __cpu_name[cpu] = "RM7000";
512                 c->isa_level = MIPS_CPU_ISA_IV;
513                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
514                              MIPS_CPU_LLSC;
515                 /*
516                  * Undocumented RM7000:  Bit 29 in the info register of
517                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
518                  * entries.
519                  *
520                  * 29      1 =>    64 entry JTLB
521                  *         0 =>    48 entry JTLB
522                  */
523                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
524                 break;
525         case PRID_IMP_RM9000:
526                 c->cputype = CPU_RM9000;
527                 __cpu_name[cpu] = "RM9000";
528                 c->isa_level = MIPS_CPU_ISA_IV;
529                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
530                              MIPS_CPU_LLSC;
531                 /*
532                  * Bit 29 in the info register of the RM9000
533                  * indicates if the TLB has 48 or 64 entries.
534                  *
535                  * 29      1 =>    64 entry JTLB
536                  *         0 =>    48 entry JTLB
537                  */
538                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
539                 break;
540         case PRID_IMP_R8000:
541                 c->cputype = CPU_R8000;
542                 __cpu_name[cpu] = "RM8000";
543                 c->isa_level = MIPS_CPU_ISA_IV;
544                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
545                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
546                              MIPS_CPU_LLSC;
547                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
548                 break;
549         case PRID_IMP_R10000:
550                 c->cputype = CPU_R10000;
551                 __cpu_name[cpu] = "R10000";
552                 c->isa_level = MIPS_CPU_ISA_IV;
553                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
554                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
555                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
556                              MIPS_CPU_LLSC;
557                 c->tlbsize = 64;
558                 break;
559         case PRID_IMP_R12000:
560                 c->cputype = CPU_R12000;
561                 __cpu_name[cpu] = "R12000";
562                 c->isa_level = MIPS_CPU_ISA_IV;
563                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
564                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
565                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
566                              MIPS_CPU_LLSC;
567                 c->tlbsize = 64;
568                 break;
569         case PRID_IMP_R14000:
570                 c->cputype = CPU_R14000;
571                 __cpu_name[cpu] = "R14000";
572                 c->isa_level = MIPS_CPU_ISA_IV;
573                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
574                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
575                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
576                              MIPS_CPU_LLSC;
577                 c->tlbsize = 64;
578                 break;
579         case PRID_IMP_LOONGSON2:
580                 c->cputype = CPU_LOONGSON2;
581                 __cpu_name[cpu] = "ICT Loongson-2";
582                 c->isa_level = MIPS_CPU_ISA_III;
583                 c->options = R4K_OPTS |
584                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
585                              MIPS_CPU_32FPR;
586                 c->tlbsize = 64;
587                 break;
588         }
589 }
590
591 static char unknown_isa[] __cpuinitdata = KERN_ERR \
592         "Unsupported ISA type, c0.config0: %d.";
593
594 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
595 {
596         unsigned int config0;
597         int isa;
598
599         config0 = read_c0_config();
600
601         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
602                 c->options |= MIPS_CPU_TLB;
603         isa = (config0 & MIPS_CONF_AT) >> 13;
604         switch (isa) {
605         case 0:
606                 switch ((config0 & MIPS_CONF_AR) >> 10) {
607                 case 0:
608                         c->isa_level = MIPS_CPU_ISA_M32R1;
609                         break;
610                 case 1:
611                         c->isa_level = MIPS_CPU_ISA_M32R2;
612                         break;
613                 default:
614                         goto unknown;
615                 }
616                 break;
617         case 2:
618                 switch ((config0 & MIPS_CONF_AR) >> 10) {
619                 case 0:
620                         c->isa_level = MIPS_CPU_ISA_M64R1;
621                         break;
622                 case 1:
623                         c->isa_level = MIPS_CPU_ISA_M64R2;
624                         break;
625                 default:
626                         goto unknown;
627                 }
628                 break;
629         default:
630                 goto unknown;
631         }
632
633         return config0 & MIPS_CONF_M;
634
635 unknown:
636         panic(unknown_isa, config0);
637 }
638
639 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
640 {
641         unsigned int config1;
642
643         config1 = read_c0_config1();
644
645         if (config1 & MIPS_CONF1_MD)
646                 c->ases |= MIPS_ASE_MDMX;
647         if (config1 & MIPS_CONF1_WR)
648                 c->options |= MIPS_CPU_WATCH;
649         if (config1 & MIPS_CONF1_CA)
650                 c->ases |= MIPS_ASE_MIPS16;
651         if (config1 & MIPS_CONF1_EP)
652                 c->options |= MIPS_CPU_EJTAG;
653         if (config1 & MIPS_CONF1_FP) {
654                 c->options |= MIPS_CPU_FPU;
655                 c->options |= MIPS_CPU_32FPR;
656         }
657         if (cpu_has_tlb)
658                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
659
660         return config1 & MIPS_CONF_M;
661 }
662
663 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
664 {
665         unsigned int config2;
666
667         config2 = read_c0_config2();
668
669         if (config2 & MIPS_CONF2_SL)
670                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
671
672         return config2 & MIPS_CONF_M;
673 }
674
675 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
676 {
677         unsigned int config3;
678
679         config3 = read_c0_config3();
680
681         if (config3 & MIPS_CONF3_SM)
682                 c->ases |= MIPS_ASE_SMARTMIPS;
683         if (config3 & MIPS_CONF3_DSP)
684                 c->ases |= MIPS_ASE_DSP;
685         if (config3 & MIPS_CONF3_VINT)
686                 c->options |= MIPS_CPU_VINT;
687         if (config3 & MIPS_CONF3_VEIC)
688                 c->options |= MIPS_CPU_VEIC;
689         if (config3 & MIPS_CONF3_MT)
690                 c->ases |= MIPS_ASE_MIPSMT;
691         if (config3 & MIPS_CONF3_ULRI)
692                 c->options |= MIPS_CPU_ULRI;
693
694         return config3 & MIPS_CONF_M;
695 }
696
697 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
698 {
699         int ok;
700
701         /* MIPS32 or MIPS64 compliant CPU.  */
702         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
703                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
704
705         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
706
707         ok = decode_config0(c);                 /* Read Config registers.  */
708         BUG_ON(!ok);                            /* Arch spec violation!  */
709         if (ok)
710                 ok = decode_config1(c);
711         if (ok)
712                 ok = decode_config2(c);
713         if (ok)
714                 ok = decode_config3(c);
715
716         mips_probe_watch_registers(c);
717 }
718
719 #ifdef CONFIG_CPU_MIPSR2
720 extern void spram_config(void);
721 #else
722 static inline void spram_config(void) {}
723 #endif
724
725 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
726 {
727         decode_configs(c);
728         switch (c->processor_id & 0xff00) {
729         case PRID_IMP_4KC:
730                 c->cputype = CPU_4KC;
731                 __cpu_name[cpu] = "MIPS 4Kc";
732                 break;
733         case PRID_IMP_4KEC:
734                 c->cputype = CPU_4KEC;
735                 __cpu_name[cpu] = "MIPS 4KEc";
736                 break;
737         case PRID_IMP_4KECR2:
738                 c->cputype = CPU_4KEC;
739                 __cpu_name[cpu] = "MIPS 4KEc";
740                 break;
741         case PRID_IMP_4KSC:
742         case PRID_IMP_4KSD:
743                 c->cputype = CPU_4KSC;
744                 __cpu_name[cpu] = "MIPS 4KSc";
745                 break;
746         case PRID_IMP_5KC:
747                 c->cputype = CPU_5KC;
748                 __cpu_name[cpu] = "MIPS 5Kc";
749                 break;
750         case PRID_IMP_20KC:
751                 c->cputype = CPU_20KC;
752                 __cpu_name[cpu] = "MIPS 20Kc";
753                 break;
754         case PRID_IMP_24K:
755         case PRID_IMP_24KE:
756                 c->cputype = CPU_24K;
757                 __cpu_name[cpu] = "MIPS 24Kc";
758                 break;
759         case PRID_IMP_25KF:
760                 c->cputype = CPU_25KF;
761                 __cpu_name[cpu] = "MIPS 25Kc";
762                 break;
763         case PRID_IMP_34K:
764                 c->cputype = CPU_34K;
765                 __cpu_name[cpu] = "MIPS 34Kc";
766                 break;
767         case PRID_IMP_74K:
768                 c->cputype = CPU_74K;
769                 __cpu_name[cpu] = "MIPS 74Kc";
770                 break;
771         case PRID_IMP_1004K:
772                 c->cputype = CPU_1004K;
773                 __cpu_name[cpu] = "MIPS 1004Kc";
774                 break;
775         }
776
777         spram_config();
778 }
779
780 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
781 {
782         decode_configs(c);
783         switch (c->processor_id & 0xff00) {
784         case PRID_IMP_AU1_REV1:
785         case PRID_IMP_AU1_REV2:
786                 switch ((c->processor_id >> 24) & 0xff) {
787                 case 0:
788                         c->cputype = CPU_AU1000;
789                         __cpu_name[cpu] = "Au1000";
790                         break;
791                 case 1:
792                         c->cputype = CPU_AU1500;
793                         __cpu_name[cpu] = "Au1500";
794                         break;
795                 case 2:
796                         c->cputype = CPU_AU1100;
797                         __cpu_name[cpu] = "Au1100";
798                         break;
799                 case 3:
800                         c->cputype = CPU_AU1550;
801                         __cpu_name[cpu] = "Au1550";
802                         break;
803                 case 4:
804                         c->cputype = CPU_AU1200;
805                         __cpu_name[cpu] = "Au1200";
806                         if ((c->processor_id & 0xff) == 2) {
807                                 c->cputype = CPU_AU1250;
808                                 __cpu_name[cpu] = "Au1250";
809                         }
810                         break;
811                 case 5:
812                         c->cputype = CPU_AU1210;
813                         __cpu_name[cpu] = "Au1210";
814                         break;
815                 default:
816                         panic("Unknown Au Core!");
817                         break;
818                 }
819                 break;
820         }
821 }
822
823 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
824 {
825         decode_configs(c);
826
827         switch (c->processor_id & 0xff00) {
828         case PRID_IMP_SB1:
829                 c->cputype = CPU_SB1;
830                 __cpu_name[cpu] = "SiByte SB1";
831                 /* FPU in pass1 is known to have issues. */
832                 if ((c->processor_id & 0xff) < 0x02)
833                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
834                 break;
835         case PRID_IMP_SB1A:
836                 c->cputype = CPU_SB1A;
837                 __cpu_name[cpu] = "SiByte SB1A";
838                 break;
839         }
840 }
841
842 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
843 {
844         decode_configs(c);
845         switch (c->processor_id & 0xff00) {
846         case PRID_IMP_SR71000:
847                 c->cputype = CPU_SR71000;
848                 __cpu_name[cpu] = "Sandcraft SR71000";
849                 c->scache.ways = 8;
850                 c->tlbsize = 64;
851                 break;
852         }
853 }
854
855 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
856 {
857         decode_configs(c);
858         switch (c->processor_id & 0xff00) {
859         case PRID_IMP_PR4450:
860                 c->cputype = CPU_PR4450;
861                 __cpu_name[cpu] = "Philips PR4450";
862                 c->isa_level = MIPS_CPU_ISA_M32R1;
863                 break;
864         }
865 }
866
867 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
868 {
869         decode_configs(c);
870         switch (c->processor_id & 0xff00) {
871         case PRID_IMP_BCM3302:
872                 c->cputype = CPU_BCM3302;
873                 __cpu_name[cpu] = "Broadcom BCM3302";
874                 break;
875         case PRID_IMP_BCM4710:
876                 c->cputype = CPU_BCM4710;
877                 __cpu_name[cpu] = "Broadcom BCM4710";
878                 break;
879         }
880 }
881
882 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
883 {
884         decode_configs(c);
885         switch (c->processor_id & 0xff00) {
886         case PRID_IMP_CAVIUM_CN38XX:
887         case PRID_IMP_CAVIUM_CN31XX:
888         case PRID_IMP_CAVIUM_CN30XX:
889         case PRID_IMP_CAVIUM_CN58XX:
890         case PRID_IMP_CAVIUM_CN56XX:
891         case PRID_IMP_CAVIUM_CN50XX:
892         case PRID_IMP_CAVIUM_CN52XX:
893                 c->cputype = CPU_CAVIUM_OCTEON;
894                 __cpu_name[cpu] = "Cavium Octeon";
895                 break;
896         default:
897                 printk(KERN_INFO "Unknown Octeon chip!\n");
898                 c->cputype = CPU_UNKNOWN;
899                 break;
900         }
901 }
902
903 const char *__cpu_name[NR_CPUS];
904
905 __cpuinit void cpu_probe(void)
906 {
907         struct cpuinfo_mips *c = &current_cpu_data;
908         unsigned int cpu = smp_processor_id();
909
910         c->processor_id = PRID_IMP_UNKNOWN;
911         c->fpu_id       = FPIR_IMP_NONE;
912         c->cputype      = CPU_UNKNOWN;
913
914         c->processor_id = read_c0_prid();
915         switch (c->processor_id & 0xff0000) {
916         case PRID_COMP_LEGACY:
917                 cpu_probe_legacy(c, cpu);
918                 break;
919         case PRID_COMP_MIPS:
920                 cpu_probe_mips(c, cpu);
921                 break;
922         case PRID_COMP_ALCHEMY:
923                 cpu_probe_alchemy(c, cpu);
924                 break;
925         case PRID_COMP_SIBYTE:
926                 cpu_probe_sibyte(c, cpu);
927                 break;
928         case PRID_COMP_BROADCOM:
929                 cpu_probe_broadcom(c, cpu);
930                 break;
931         case PRID_COMP_SANDCRAFT:
932                 cpu_probe_sandcraft(c, cpu);
933                 break;
934         case PRID_COMP_NXP:
935                 cpu_probe_nxp(c, cpu);
936                 break;
937         case PRID_COMP_CAVIUM:
938                 cpu_probe_cavium(c, cpu);
939                 break;
940         }
941
942         BUG_ON(!__cpu_name[cpu]);
943         BUG_ON(c->cputype == CPU_UNKNOWN);
944
945         /*
946          * Platform code can force the cpu type to optimize code
947          * generation. In that case be sure the cpu type is correctly
948          * manually setup otherwise it could trigger some nasty bugs.
949          */
950         BUG_ON(current_cpu_type() != c->cputype);
951
952         if (c->options & MIPS_CPU_FPU) {
953                 c->fpu_id = cpu_get_fpu_id();
954
955                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
956                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
957                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
958                     c->isa_level == MIPS_CPU_ISA_M64R2) {
959                         if (c->fpu_id & MIPS_FPIR_3D)
960                                 c->ases |= MIPS_ASE_MIPS3D;
961                 }
962         }
963
964         if (cpu_has_mips_r2)
965                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
966         else
967                 c->srsets = 1;
968 }
969
970 __cpuinit void cpu_report(void)
971 {
972         struct cpuinfo_mips *c = &current_cpu_data;
973
974         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
975                c->processor_id, cpu_name_string());
976         if (c->options & MIPS_CPU_FPU)
977                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
978 }