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   1 /*
   2  * linux/arch/arm/plat-omap/mux.c
   3  *
   4  * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
   5  *
   6  * Copyright (C) 2003 - 2005 Nokia Corporation
   7  *
   8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23  *
  24  */
  25 #include <linux/config.h>
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <asm/system.h>
  30 #include <asm/io.h>
  31 #include <linux/spinlock.h>
  32 #include <asm/arch/mux.h>
  33
  34 #ifdef CONFIG_OMAP_MUX
  35
  36 #define OMAP24XX_L4_BASE        0x48000000
  37 #define OMAP24XX_PULL_ENA       (1 << 3)
  38 #define OMAP24XX_PULL_UP        (1 << 4)
  39
  40 static struct pin_config * pin_table;
  41 static unsigned long pin_table_sz;
  42
  43 extern struct pin_config * omap730_pins;
  44 extern struct pin_config * omap1xxx_pins;
  45 extern struct pin_config * omap24xx_pins;
  46
  47 int __init omap_mux_register(struct pin_config * pins, unsigned long size)
  48 {
  49         pin_table = pins;
  50         pin_table_sz = size;
  51
  52         return 0;
  53 }
  54
  55 /*
  56  * Sets the Omap MUX and PULL_DWN registers based on the table
  57  */
  58 int __init_or_module omap_cfg_reg(const unsigned long index)
  59 {
  60         static DEFINE_SPINLOCK(mux_spin_lock);
  61
  62         unsigned long flags;
  63         struct pin_config *cfg;
  64         unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
  65                 pull_orig = 0, pull = 0;
  66         unsigned int mask, warn = 0;
  67
  68         if (!pin_table)
  69                 BUG();
  70
  71         if (index >= pin_table_sz) {
  72                 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
  73                        index, pin_table_sz);
  74                 dump_stack();
  75                 return -ENODEV;
  76         }
  77
  78         cfg = (struct pin_config *)&pin_table[index];
  79         if (cpu_is_omap24xx()) {
  80                 u8 reg = 0;
  81
  82                 reg |= cfg->mask & 0x7;
  83                 if (cfg->pull_val)
  84                         reg |= OMAP24XX_PULL_ENA;
  85                 if(cfg->pu_pd_val)
  86                         reg |= OMAP24XX_PULL_UP;
  87 #ifdef CONFIG_OMAP_MUX_DEBUG
  88                 printk("Muxing %s (0x%08x): 0x%02x -> 0x%02x\n",
  89                        cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg,
  90                        omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg), reg);
  91 #endif
  92                 omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
  93
  94                 return 0;
  95         }
  96
  97         /* Check the mux register in question */
  98         if (cfg->mux_reg) {
  99                 unsigned        tmp1, tmp2;
 100
 101                 spin_lock_irqsave(&mux_spin_lock, flags);
 102                 reg_orig = omap_readl(cfg->mux_reg);
 103
 104                 /* The mux registers always seem to be 3 bits long */
 105                 mask = (0x7 << cfg->mask_offset);
 106                 tmp1 = reg_orig & mask;
 107                 reg = reg_orig & ~mask;
 108
 109                 tmp2 = (cfg->mask << cfg->mask_offset);
 110                 reg |= tmp2;
 111
 112                 if (tmp1 != tmp2)
 113                         warn = 1;
 114
 115                 omap_writel(reg, cfg->mux_reg);
 116                 spin_unlock_irqrestore(&mux_spin_lock, flags);
 117         }
 118
 119         /* Check for pull up or pull down selection on 1610 */
 120         if (!cpu_is_omap1510()) {
 121                 if (cfg->pu_pd_reg && cfg->pull_val) {
 122                         spin_lock_irqsave(&mux_spin_lock, flags);
 123                         pu_pd_orig = omap_readl(cfg->pu_pd_reg);
 124                         mask = 1 << cfg->pull_bit;
 125
 126                         if (cfg->pu_pd_val) {
 127                                 if (!(pu_pd_orig & mask))
 128                                         warn = 1;
 129                                 /* Use pull up */
 130                                 pu_pd = pu_pd_orig | mask;
 131                         } else {
 132                                 if (pu_pd_orig & mask)
 133                                         warn = 1;
 134                                 /* Use pull down */
 135                                 pu_pd = pu_pd_orig & ~mask;
 136                         }
 137                         omap_writel(pu_pd, cfg->pu_pd_reg);
 138                         spin_unlock_irqrestore(&mux_spin_lock, flags);
 139                 }
 140         }
 141
 142         /* Check for an associated pull down register */
 143         if (cfg->pull_reg) {
 144                 spin_lock_irqsave(&mux_spin_lock, flags);
 145                 pull_orig = omap_readl(cfg->pull_reg);
 146                 mask = 1 << cfg->pull_bit;
 147
 148                 if (cfg->pull_val) {
 149                         if (pull_orig & mask)
 150                                 warn = 1;
 151                         /* Low bit = pull enabled */
 152                         pull = pull_orig & ~mask;
 153                 } else {
 154                         if (!(pull_orig & mask))
 155                                 warn = 1;
 156                         /* High bit = pull disabled */
 157                         pull = pull_orig | mask;
 158                 }
 159
 160                 omap_writel(pull, cfg->pull_reg);
 161                 spin_unlock_irqrestore(&mux_spin_lock, flags);
 162         }
 163
 164         if (warn) {
 165 #ifdef CONFIG_OMAP_MUX_WARNINGS
 166                 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
 167 #endif
 168         }
 169
 170 #ifdef CONFIG_OMAP_MUX_DEBUG
 171         if (cfg->debug || warn) {
 172                 printk("MUX: Setting register %s\n", cfg->name);
 173                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
 174                        cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
 175
 176                 if (!cpu_is_omap1510()) {
 177                         if (cfg->pu_pd_reg && cfg->pull_val) {
 178                                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
 179                                        cfg->pu_pd_name, cfg->pu_pd_reg,
 180                                        pu_pd_orig, pu_pd);
 181                         }
 182                 }
 183
 184                 if (cfg->pull_reg)
 185                         printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
 186                                cfg->pull_name, cfg->pull_reg, pull_orig, pull);
 187         }
 188 #endif
 189
 190 #ifdef CONFIG_OMAP_MUX_ERRORS
 191         return warn ? -ETXTBSY : 0;
 192 #else
 193         return 0;
 194 #endif
 195 }
 196 EXPORT_SYMBOL(omap_cfg_reg);
 197 #else
 198 #define omap_mux_init() do {} while(0)
 199 #define omap_cfg_reg(x) do {} while(0)
 200 #endif  /* CONFIG_OMAP_MUX */