git.oblomov.eu Git - linux-2.6/blob - drivers/usb/gadget/pxa2xx_udc.c

   1 /*
   2  * linux/drivers/usb/gadget/pxa2xx_udc.c
   3  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
   4  *
   5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
   6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
   7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
   8  * Copyright (C) 2003 David Brownell
   9  * Copyright (C) 2003 Joshua Wise
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  *
  25  */
  26
  27 #undef  DEBUG
  28 // #define      VERBOSE DBG_VERBOSE
  29
  30 #include <linux/config.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/ioport.h>
  34 #include <linux/types.h>
  35 #include <linux/errno.h>
  36 #include <linux/delay.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/init.h>
  40 #include <linux/timer.h>
  41 #include <linux/list.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/proc_fs.h>
  44 #include <linux/mm.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/dma-mapping.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/dma.h>
  50 #include <asm/io.h>
  51 #include <asm/irq.h>
  52 #include <asm/system.h>
  53 #include <asm/mach-types.h>
  54 #include <asm/unaligned.h>
  55 #include <asm/hardware.h>
  56 #include <asm/arch/pxa-regs.h>
  57
  58 #include <linux/usb_ch9.h>
  59 #include <linux/usb_gadget.h>
  60
  61 #include <asm/arch/udc.h>
  62
  63
  64 /*
  65  * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
  66  * series processors.  The UDC for the IXP 4xx series is very similar.
  67  * There are fifteen endpoints, in addition to ep0.
  68  *
  69  * Such controller drivers work with a gadget driver.  The gadget driver
  70  * returns descriptors, implements configuration and data protocols used
  71  * by the host to interact with this device, and allocates endpoints to
  72  * the different protocol interfaces.  The controller driver virtualizes
  73  * usb hardware so that the gadget drivers will be more portable.
  74  *
  75  * This UDC hardware wants to implement a bit too much USB protocol, so
  76  * it constrains the sorts of USB configuration change events that work.
  77  * The errata for these chips are misleading; some "fixed" bugs from
  78  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
  79  */
  80
  81 #define DRIVER_VERSION  "4-May-2005"
  82 #define DRIVER_DESC     "PXA 25x USB Device Controller driver"
  83
  84
  85 static const char driver_name [] = "pxa2xx_udc";
  86
  87 static const char ep0name [] = "ep0";
  88
  89
  90 // #define      USE_DMA
  91 // #define      USE_OUT_DMA
  92 // #define      DISABLE_TEST_MODE
  93
  94 #ifdef CONFIG_ARCH_IXP4XX
  95 #undef USE_DMA
  96
  97 /* cpu-specific register addresses are compiled in to this code */
  98 #ifdef CONFIG_ARCH_PXA
  99 #error "Can't configure both IXP and PXA"
 100 #endif
 101
 102 #endif
 103
 104 #include "pxa2xx_udc.h"
 105
 106
 107 #ifdef  USE_DMA
 108 static int use_dma = 1;
 109 module_param(use_dma, bool, 0);
 110 MODULE_PARM_DESC (use_dma, "true to use dma");
 111
 112 static void dma_nodesc_handler (int dmach, void *_ep, struct pt_regs *r);
 113 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req);
 114
 115 #ifdef USE_OUT_DMA
 116 #define DMASTR " (dma support)"
 117 #else
 118 #define DMASTR " (dma in)"
 119 #endif
 120
 121 #else   /* !USE_DMA */
 122 #define DMASTR " (pio only)"
 123 #undef  USE_OUT_DMA
 124 #endif
 125
 126 #ifdef  CONFIG_USB_PXA2XX_SMALL
 127 #define SIZE_STR        " (small)"
 128 #else
 129 #define SIZE_STR        ""
 130 #endif
 131
 132 #ifdef DISABLE_TEST_MODE
 133 /* (mode == 0) == no undocumented chip tweaks
 134  * (mode & 1)  == double buffer bulk IN
 135  * (mode & 2)  == double buffer bulk OUT
 136  * ... so mode = 3 (or 7, 15, etc) does it for both
 137  */
 138 static ushort fifo_mode = 0;
 139 module_param(fifo_mode, ushort, 0);
 140 MODULE_PARM_DESC (fifo_mode, "pxa2xx udc fifo mode");
 141 #endif
 142
 143 /* ---------------------------------------------------------------------------
 144  *      endpoint related parts of the api to the usb controller hardware,
 145  *      used by gadget driver; and the inner talker-to-hardware core.
 146  * ---------------------------------------------------------------------------
 147  */
 148
 149 static void pxa2xx_ep_fifo_flush (struct usb_ep *ep);
 150 static void nuke (struct pxa2xx_ep *, int status);
 151
 152 static void pio_irq_enable(int bEndpointAddress)
 153 {
 154         bEndpointAddress &= 0xf;
 155         if (bEndpointAddress < 8)
 156                 UICR0 &= ~(1 << bEndpointAddress);
 157         else {
 158                 bEndpointAddress -= 8;
 159                 UICR1 &= ~(1 << bEndpointAddress);
 160         }
 161 }
 162
 163 static void pio_irq_disable(int bEndpointAddress)
 164 {
 165         bEndpointAddress &= 0xf;
 166         if (bEndpointAddress < 8)
 167                 UICR0 |= 1 << bEndpointAddress;
 168         else {
 169                 bEndpointAddress -= 8;
 170                 UICR1 |= 1 << bEndpointAddress;
 171         }
 172 }
 173
 174 /* The UDCCR reg contains mask and interrupt status bits,
 175  * so using '|=' isn't safe as it may ack an interrupt.
 176  */
 177 #define UDCCR_MASK_BITS         (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
 178
 179 static inline void udc_set_mask_UDCCR(int mask)
 180 {
 181         UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
 182 }
 183
 184 static inline void udc_clear_mask_UDCCR(int mask)
 185 {
 186         UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
 187 }
 188
 189 static inline void udc_ack_int_UDCCR(int mask)
 190 {
 191         /* udccr contains the bits we dont want to change */
 192         __u32 udccr = UDCCR & UDCCR_MASK_BITS;
 193
 194         UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
 195 }
 196
 197 /*
 198  * endpoint enable/disable
 199  *
 200  * we need to verify the descriptors used to enable endpoints.  since pxa2xx
 201  * endpoint configurations are fixed, and are pretty much always enabled,
 202  * there's not a lot to manage here.
 203  *
 204  * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
 205  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 206  * for a single interface (with only the default altsetting) and for gadget
 207  * drivers that don't halt endpoints (not reset by set_interface).  that also
 208  * means that if you use ISO, you must violate the USB spec rule that all
 209  * iso endpoints must be in non-default altsettings.
 210  */
 211 static int pxa2xx_ep_enable (struct usb_ep *_ep,
 212                 const struct usb_endpoint_descriptor *desc)
 213 {
 214         struct pxa2xx_ep        *ep;
 215         struct pxa2xx_udc       *dev;
 216
 217         ep = container_of (_ep, struct pxa2xx_ep, ep);
 218         if (!_ep || !desc || ep->desc || _ep->name == ep0name
 219                         || desc->bDescriptorType != USB_DT_ENDPOINT
 220                         || ep->bEndpointAddress != desc->bEndpointAddress
 221                         || ep->fifo_size < le16_to_cpu
 222                                                 (desc->wMaxPacketSize)) {
 223                 DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
 224                 return -EINVAL;
 225         }
 226
 227         /* xfer types must match, except that interrupt ~= bulk */
 228         if (ep->bmAttributes != desc->bmAttributes
 229                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 230                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 231                 DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 232                 return -EINVAL;
 233         }
 234
 235         /* hardware _could_ do smaller, but driver doesn't */
 236         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 237                                 && le16_to_cpu (desc->wMaxPacketSize)
 238                                                 != BULK_FIFO_SIZE)
 239                         || !desc->wMaxPacketSize) {
 240                 DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 241                 return -ERANGE;
 242         }
 243
 244         dev = ep->dev;
 245         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 246                 DMSG("%s, bogus device state\n", __FUNCTION__);
 247                 return -ESHUTDOWN;
 248         }
 249
 250         ep->desc = desc;
 251         ep->dma = -1;
 252         ep->stopped = 0;
 253         ep->pio_irqs = ep->dma_irqs = 0;
 254         ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
 255
 256         /* flush fifo (mostly for OUT buffers) */
 257         pxa2xx_ep_fifo_flush (_ep);
 258
 259         /* ... reset halt state too, if we could ... */
 260
 261 #ifdef  USE_DMA
 262         /* for (some) bulk and ISO endpoints, try to get a DMA channel and
 263          * bind it to the endpoint.  otherwise use PIO.
 264          */
 265         switch (ep->bmAttributes) {
 266         case USB_ENDPOINT_XFER_ISOC:
 267                 if (le16_to_cpu(desc->wMaxPacketSize) % 32)
 268                         break;
 269                 // fall through
 270         case USB_ENDPOINT_XFER_BULK:
 271                 if (!use_dma || !ep->reg_drcmr)
 272                         break;
 273                 ep->dma = pxa_request_dma ((char *)_ep->name,
 274                                 (le16_to_cpu (desc->wMaxPacketSize) > 64)
 275                                         ? DMA_PRIO_MEDIUM /* some iso */
 276                                         : DMA_PRIO_LOW,
 277                                 dma_nodesc_handler, ep);
 278                 if (ep->dma >= 0) {
 279                         *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
 280                         DMSG("%s using dma%d\n", _ep->name, ep->dma);
 281                 }
 282         }
 283 #endif
 284
 285         DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
 286         return 0;
 287 }
 288
 289 static int pxa2xx_ep_disable (struct usb_ep *_ep)
 290 {
 291         struct pxa2xx_ep        *ep;
 292         unsigned long           flags;
 293
 294         ep = container_of (_ep, struct pxa2xx_ep, ep);
 295         if (!_ep || !ep->desc) {
 296                 DMSG("%s, %s not enabled\n", __FUNCTION__,
 297                         _ep ? ep->ep.name : NULL);
 298                 return -EINVAL;
 299         }
 300         local_irq_save(flags);
 301
 302         nuke (ep, -ESHUTDOWN);
 303
 304 #ifdef  USE_DMA
 305         if (ep->dma >= 0) {
 306                 *ep->reg_drcmr = 0;
 307                 pxa_free_dma (ep->dma);
 308                 ep->dma = -1;
 309         }
 310 #endif
 311
 312         /* flush fifo (mostly for IN buffers) */
 313         pxa2xx_ep_fifo_flush (_ep);
 314
 315         ep->desc = NULL;
 316         ep->stopped = 1;
 317
 318         local_irq_restore(flags);
 319         DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
 320         return 0;
 321 }
 322
 323 /*-------------------------------------------------------------------------*/
 324
 325 /* for the pxa2xx, these can just wrap kmalloc/kfree.  gadget drivers
 326  * must still pass correctly initialized endpoints, since other controller
 327  * drivers may care about how it's currently set up (dma issues etc).
 328  */
 329
 330 /*
 331  *      pxa2xx_ep_alloc_request - allocate a request data structure
 332  */
 333 static struct usb_request *
 334 pxa2xx_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
 335 {
 336         struct pxa2xx_request *req;
 337
 338         req = kmalloc (sizeof *req, gfp_flags);
 339         if (!req)
 340                 return NULL;
 341
 342         memset (req, 0, sizeof *req);
 343         INIT_LIST_HEAD (&req->queue);
 344         return &req->req;
 345 }
 346
 347
 348 /*
 349  *      pxa2xx_ep_free_request - deallocate a request data structure
 350  */
 351 static void
 352 pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 353 {
 354         struct pxa2xx_request   *req;
 355
 356         req = container_of (_req, struct pxa2xx_request, req);
 357         WARN_ON (!list_empty (&req->queue));
 358         kfree(req);
 359 }
 360
 361
 362 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
 363  * no device-affinity and the heap works perfectly well for i/o buffers.
 364  * It wastes much less memory than dma_alloc_coherent() would, and even
 365  * prevents cacheline (32 bytes wide) sharing problems.
 366  */
 367 static void *
 368 pxa2xx_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
 369         dma_addr_t *dma, gfp_t gfp_flags)
 370 {
 371         char                    *retval;
 372
 373         retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
 374         if (retval)
 375 #ifdef  USE_DMA
 376                 *dma = virt_to_bus (retval);
 377 #else
 378                 *dma = (dma_addr_t)~0;
 379 #endif
 380         return retval;
 381 }
 382
 383 static void
 384 pxa2xx_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
 385                 unsigned bytes)
 386 {
 387         kfree (buf);
 388 }
 389
 390 /*-------------------------------------------------------------------------*/
 391
 392 /*
 393  *      done - retire a request; caller blocked irqs
 394  */
 395 static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status)
 396 {
 397         unsigned                stopped = ep->stopped;
 398
 399         list_del_init(&req->queue);
 400
 401         if (likely (req->req.status == -EINPROGRESS))
 402                 req->req.status = status;
 403         else
 404                 status = req->req.status;
 405
 406         if (status && status != -ESHUTDOWN)
 407                 DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
 408                         ep->ep.name, &req->req, status,
 409                         req->req.actual, req->req.length);
 410
 411         /* don't modify queue heads during completion callback */
 412         ep->stopped = 1;
 413         req->req.complete(&ep->ep, &req->req);
 414         ep->stopped = stopped;
 415 }
 416
 417
 418 static inline void ep0_idle (struct pxa2xx_udc *dev)
 419 {
 420         dev->ep0state = EP0_IDLE;
 421 }
 422
 423 static int
 424 write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max)
 425 {
 426         u8              *buf;
 427         unsigned        length, count;
 428
 429         buf = req->req.buf + req->req.actual;
 430         prefetch(buf);
 431
 432         /* how big will this packet be? */
 433         length = min(req->req.length - req->req.actual, max);
 434         req->req.actual += length;
 435
 436         count = length;
 437         while (likely(count--))
 438                 *uddr = *buf++;
 439
 440         return length;
 441 }
 442
 443 /*
 444  * write to an IN endpoint fifo, as many packets as possible.
 445  * irqs will use this to write the rest later.
 446  * caller guarantees at least one packet buffer is ready (or a zlp).
 447  */
 448 static int
 449 write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 450 {
 451         unsigned                max;
 452
 453         max = le16_to_cpu(ep->desc->wMaxPacketSize);
 454         do {
 455                 unsigned        count;
 456                 int             is_last, is_short;
 457
 458                 count = write_packet(ep->reg_uddr, req, max);
 459
 460                 /* last packet is usually short (or a zlp) */
 461                 if (unlikely (count != max))
 462                         is_last = is_short = 1;
 463                 else {
 464                         if (likely(req->req.length != req->req.actual)
 465                                         || req->req.zero)
 466                                 is_last = 0;
 467                         else
 468                                 is_last = 1;
 469                         /* interrupt/iso maxpacket may not fill the fifo */
 470                         is_short = unlikely (max < ep->fifo_size);
 471                 }
 472
 473                 DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
 474                         ep->ep.name, count,
 475                         is_last ? "/L" : "", is_short ? "/S" : "",
 476                         req->req.length - req->req.actual, req);
 477
 478                 /* let loose that packet. maybe try writing another one,
 479                  * double buffering might work.  TSP, TPC, and TFS
 480                  * bit values are the same for all normal IN endpoints.
 481                  */
 482                 *ep->reg_udccs = UDCCS_BI_TPC;
 483                 if (is_short)
 484                         *ep->reg_udccs = UDCCS_BI_TSP;
 485
 486                 /* requests complete when all IN data is in the FIFO */
 487                 if (is_last) {
 488                         done (ep, req, 0);
 489                         if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
 490                                 pio_irq_disable (ep->bEndpointAddress);
 491 #ifdef USE_DMA
 492                                 /* unaligned data and zlps couldn't use dma */
 493                                 if (unlikely(!list_empty(&ep->queue))) {
 494                                         req = list_entry(ep->queue.next,
 495                                                 struct pxa2xx_request, queue);
 496                                         kick_dma(ep,req);
 497                                         return 0;
 498                                 }
 499 #endif
 500                         }
 501                         return 1;
 502                 }
 503
 504                 // TODO experiment: how robust can fifo mode tweaking be?
 505                 // double buffering is off in the default fifo mode, which
 506                 // prevents TFS from being set here.
 507
 508         } while (*ep->reg_udccs & UDCCS_BI_TFS);
 509         return 0;
 510 }
 511
 512 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
 513  * ep0 data stage.  these chips want very simple state transitions.
 514  */
 515 static inline
 516 void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag)
 517 {
 518         UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR;
 519         USIR0 = USIR0_IR0;
 520         dev->req_pending = 0;
 521         DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
 522                 __FUNCTION__, tag, UDCCS0, flags);
 523 }
 524
 525 static int
 526 write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 527 {
 528         unsigned        count;
 529         int             is_short;
 530
 531         count = write_packet(&UDDR0, req, EP0_FIFO_SIZE);
 532         ep->dev->stats.write.bytes += count;
 533
 534         /* last packet "must be" short (or a zlp) */
 535         is_short = (count != EP0_FIFO_SIZE);
 536
 537         DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
 538                 req->req.length - req->req.actual, req);
 539
 540         if (unlikely (is_short)) {
 541                 if (ep->dev->req_pending)
 542                         ep0start(ep->dev, UDCCS0_IPR, "short IN");
 543                 else
 544                         UDCCS0 = UDCCS0_IPR;
 545
 546                 count = req->req.length;
 547                 done (ep, req, 0);
 548                 ep0_idle(ep->dev);
 549 #if 1
 550                 /* This seems to get rid of lost status irqs in some cases:
 551                  * host responds quickly, or next request involves config
 552                  * change automagic, or should have been hidden, or ...
 553                  *
 554                  * FIXME get rid of all udelays possible...
 555                  */
 556                 if (count >= EP0_FIFO_SIZE) {
 557                         count = 100;
 558                         do {
 559                                 if ((UDCCS0 & UDCCS0_OPR) != 0) {
 560                                         /* clear OPR, generate ack */
 561                                         UDCCS0 = UDCCS0_OPR;
 562                                         break;
 563                                 }
 564                                 count--;
 565                                 udelay(1);
 566                         } while (count);
 567                 }
 568 #endif
 569         } else if (ep->dev->req_pending)
 570                 ep0start(ep->dev, 0, "IN");
 571         return is_short;
 572 }
 573
 574
 575 /*
 576  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 577  * transfers and put them into the request.  caller should have made
 578  * sure there's at least one packet ready.
 579  *
 580  * returns true if the request completed because of short packet or the
 581  * request buffer having filled (and maybe overran till end-of-packet).
 582  */
 583 static int
 584 read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 585 {
 586         for (;;) {
 587                 u32             udccs;
 588                 u8              *buf;
 589                 unsigned        bufferspace, count, is_short;
 590
 591                 /* make sure there's a packet in the FIFO.
 592                  * UDCCS_{BO,IO}_RPC are all the same bit value.
 593                  * UDCCS_{BO,IO}_RNE are all the same bit value.
 594                  */
 595                 udccs = *ep->reg_udccs;
 596                 if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
 597                         break;
 598                 buf = req->req.buf + req->req.actual;
 599                 prefetchw(buf);
 600                 bufferspace = req->req.length - req->req.actual;
 601
 602                 /* read all bytes from this packet */
 603                 if (likely (udccs & UDCCS_BO_RNE)) {
 604                         count = 1 + (0x0ff & *ep->reg_ubcr);
 605                         req->req.actual += min (count, bufferspace);
 606                 } else /* zlp */
 607                         count = 0;
 608                 is_short = (count < ep->ep.maxpacket);
 609                 DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
 610                         ep->ep.name, udccs, count,
 611                         is_short ? "/S" : "",
 612                         req, req->req.actual, req->req.length);
 613                 while (likely (count-- != 0)) {
 614                         u8      byte = (u8) *ep->reg_uddr;
 615
 616                         if (unlikely (bufferspace == 0)) {
 617                                 /* this happens when the driver's buffer
 618                                  * is smaller than what the host sent.
 619                                  * discard the extra data.
 620                                  */
 621                                 if (req->req.status != -EOVERFLOW)
 622                                         DMSG("%s overflow %d\n",
 623                                                 ep->ep.name, count);
 624                                 req->req.status = -EOVERFLOW;
 625                         } else {
 626                                 *buf++ = byte;
 627                                 bufferspace--;
 628                         }
 629                 }
 630                 *ep->reg_udccs =  UDCCS_BO_RPC;
 631                 /* RPC/RSP/RNE could now reflect the other packet buffer */
 632
 633                 /* iso is one request per packet */
 634                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 635                         if (udccs & UDCCS_IO_ROF)
 636                                 req->req.status = -EHOSTUNREACH;
 637                         /* more like "is_done" */
 638                         is_short = 1;
 639                 }
 640
 641                 /* completion */
 642                 if (is_short || req->req.actual == req->req.length) {
 643                         done (ep, req, 0);
 644                         if (list_empty(&ep->queue))
 645                                 pio_irq_disable (ep->bEndpointAddress);
 646                         return 1;
 647                 }
 648
 649                 /* finished that packet.  the next one may be waiting... */
 650         }
 651         return 0;
 652 }
 653
 654 /*
 655  * special ep0 version of the above.  no UBCR0 or double buffering; status
 656  * handshaking is magic.  most device protocols don't need control-OUT.
 657  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 658  * protocols do use them.
 659  */
 660 static int
 661 read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 662 {
 663         u8              *buf, byte;
 664         unsigned        bufferspace;
 665
 666         buf = req->req.buf + req->req.actual;
 667         bufferspace = req->req.length - req->req.actual;
 668
 669         while (UDCCS0 & UDCCS0_RNE) {
 670                 byte = (u8) UDDR0;
 671
 672                 if (unlikely (bufferspace == 0)) {
 673                         /* this happens when the driver's buffer
 674                          * is smaller than what the host sent.
 675                          * discard the extra data.
 676                          */
 677                         if (req->req.status != -EOVERFLOW)
 678                                 DMSG("%s overflow\n", ep->ep.name);
 679                         req->req.status = -EOVERFLOW;
 680                 } else {
 681                         *buf++ = byte;
 682                         req->req.actual++;
 683                         bufferspace--;
 684                 }
 685         }
 686
 687         UDCCS0 = UDCCS0_OPR | UDCCS0_IPR;
 688
 689         /* completion */
 690         if (req->req.actual >= req->req.length)
 691                 return 1;
 692
 693         /* finished that packet.  the next one may be waiting... */
 694         return 0;
 695 }
 696
 697 #ifdef  USE_DMA
 698
 699 #define MAX_IN_DMA      ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
 700
 701 static void
 702 start_dma_nodesc(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int is_in)
 703 {
 704         u32     dcmd = req->req.length;
 705         u32     buf = req->req.dma;
 706         u32     fifo = io_v2p ((u32)ep->reg_uddr);
 707
 708         /* caller guarantees there's a packet or more remaining
 709          *  - IN may end with a short packet (TSP set separately),
 710          *  - OUT is always full length
 711          */
 712         buf += req->req.actual;
 713         dcmd -= req->req.actual;
 714         ep->dma_fixup = 0;
 715
 716         /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
 717         DCSR(ep->dma) = DCSR_NODESC;
 718         if (is_in) {
 719                 DSADR(ep->dma) = buf;
 720                 DTADR(ep->dma) = fifo;
 721                 if (dcmd > MAX_IN_DMA)
 722                         dcmd = MAX_IN_DMA;
 723                 else
 724                         ep->dma_fixup = (dcmd % ep->ep.maxpacket) != 0;
 725                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 726                         | DCMD_FLOWTRG | DCMD_INCSRCADDR;
 727         } else {
 728 #ifdef USE_OUT_DMA
 729                 DSADR(ep->dma) = fifo;
 730                 DTADR(ep->dma) = buf;
 731                 if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
 732                         dcmd = ep->ep.maxpacket;
 733                 dcmd |= DCMD_BURST32 | DCMD_WIDTH1
 734                         | DCMD_FLOWSRC | DCMD_INCTRGADDR;
 735 #endif
 736         }
 737         DCMD(ep->dma) = dcmd;
 738         DCSR(ep->dma) = DCSR_RUN | DCSR_NODESC
 739                 | (unlikely(is_in)
 740                         ? DCSR_STOPIRQEN        /* use dma_nodesc_handler() */
 741                         : 0);                   /* use handle_ep() */
 742 }
 743
 744 static void kick_dma(struct pxa2xx_ep *ep, struct pxa2xx_request *req)
 745 {
 746         int     is_in = ep->bEndpointAddress & USB_DIR_IN;
 747
 748         if (is_in) {
 749                 /* unaligned tx buffers and zlps only work with PIO */
 750                 if ((req->req.dma & 0x0f) != 0
 751                                 || unlikely((req->req.length - req->req.actual)
 752                                                 == 0)) {
 753                         pio_irq_enable(ep->bEndpointAddress);
 754                         if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0)
 755                                 (void) write_fifo(ep, req);
 756                 } else {
 757                         start_dma_nodesc(ep, req, USB_DIR_IN);
 758                 }
 759         } else {
 760                 if ((req->req.length - req->req.actual) < ep->ep.maxpacket) {
 761                         DMSG("%s short dma read...\n", ep->ep.name);
 762                         /* we're always set up for pio out */
 763                         read_fifo (ep, req);
 764                 } else {
 765                         *ep->reg_udccs = UDCCS_BO_DME
 766                                 | (*ep->reg_udccs & UDCCS_BO_FST);
 767                         start_dma_nodesc(ep, req, USB_DIR_OUT);
 768                 }
 769         }
 770 }
 771
 772 static void cancel_dma(struct pxa2xx_ep *ep)
 773 {
 774         struct pxa2xx_request   *req;
 775         u32                     tmp;
 776
 777         if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
 778                 return;
 779
 780         DCSR(ep->dma) = 0;
 781         while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
 782                 cpu_relax();
 783
 784         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 785         tmp = DCMD(ep->dma) & DCMD_LENGTH;
 786         req->req.actual = req->req.length - (tmp & DCMD_LENGTH);
 787
 788         /* the last tx packet may be incomplete, so flush the fifo.
 789          * FIXME correct req.actual if we can
 790          */
 791         if (ep->bEndpointAddress & USB_DIR_IN)
 792                 *ep->reg_udccs = UDCCS_BI_FTF;
 793 }
 794
 795 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
 796 static void dma_nodesc_handler(int dmach, void *_ep, struct pt_regs *r)
 797 {
 798         struct pxa2xx_ep        *ep = _ep;
 799         struct pxa2xx_request   *req;
 800         u32                     tmp, completed;
 801
 802         local_irq_disable();
 803
 804         req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 805
 806         ep->dma_irqs++;
 807         ep->dev->stats.irqs++;
 808         HEX_DISPLAY(ep->dev->stats.irqs);
 809
 810         /* ack/clear */
 811         tmp = DCSR(ep->dma);
 812         DCSR(ep->dma) = tmp;
 813         if ((tmp & DCSR_STOPSTATE) == 0
 814                         || (DDADR(ep->dma) & DDADR_STOP) != 0) {
 815                 DBG(DBG_VERBOSE, "%s, dcsr %08x ddadr %08x\n",
 816                         ep->ep.name, DCSR(ep->dma), DDADR(ep->dma));
 817                 goto done;
 818         }
 819         DCSR(ep->dma) = 0;      /* clear DCSR_STOPSTATE */
 820
 821         /* update transfer status */
 822         completed = tmp & DCSR_BUSERR;
 823         if (ep->bEndpointAddress & USB_DIR_IN)
 824                 tmp = DSADR(ep->dma);
 825         else
 826                 tmp = DTADR(ep->dma);
 827         req->req.actual = tmp - req->req.dma;
 828
 829         /* FIXME seems we sometimes see partial transfers... */
 830
 831         if (unlikely(completed != 0))
 832                 req->req.status = -EIO;
 833         else if (req->req.actual) {
 834                 /* these registers have zeroes in low bits; they miscount
 835                  * some (end-of-transfer) short packets:  tx 14 as tx 12
 836                  */
 837                 if (ep->dma_fixup)
 838                         req->req.actual = min(req->req.actual + 3,
 839                                                 req->req.length);
 840
 841                 tmp = (req->req.length - req->req.actual);
 842                 completed = (tmp == 0);
 843                 if (completed && (ep->bEndpointAddress & USB_DIR_IN)) {
 844
 845                         /* maybe validate final short packet ... */
 846                         if ((req->req.actual % ep->ep.maxpacket) != 0)
 847                                 *ep->reg_udccs = UDCCS_BI_TSP/*|UDCCS_BI_TPC*/;
 848
 849                         /* ... or zlp, using pio fallback */
 850                         else if (ep->bmAttributes == USB_ENDPOINT_XFER_BULK
 851                                         && req->req.zero) {
 852                                 DMSG("%s zlp terminate ...\n", ep->ep.name);
 853                                 completed = 0;
 854                         }
 855                 }
 856         }
 857
 858         if (likely(completed)) {
 859                 done(ep, req, 0);
 860
 861                 /* maybe re-activate after completion */
 862                 if (ep->stopped || list_empty(&ep->queue))
 863                         goto done;
 864                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
 865         }
 866         kick_dma(ep, req);
 867 done:
 868         local_irq_enable();
 869 }
 870
 871 #endif
 872
 873 /*-------------------------------------------------------------------------*/
 874
 875 static int
 876 pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 877 {
 878         struct pxa2xx_request   *req;
 879         struct pxa2xx_ep        *ep;
 880         struct pxa2xx_udc       *dev;
 881         unsigned long           flags;
 882
 883         req = container_of(_req, struct pxa2xx_request, req);
 884         if (unlikely (!_req || !_req->complete || !_req->buf
 885                         || !list_empty(&req->queue))) {
 886                 DMSG("%s, bad params\n", __FUNCTION__);
 887                 return -EINVAL;
 888         }
 889
 890         ep = container_of(_ep, struct pxa2xx_ep, ep);
 891         if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 892                 DMSG("%s, bad ep\n", __FUNCTION__);
 893                 return -EINVAL;
 894         }
 895
 896         dev = ep->dev;
 897         if (unlikely (!dev->driver
 898                         || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 899                 DMSG("%s, bogus device state\n", __FUNCTION__);
 900                 return -ESHUTDOWN;
 901         }
 902
 903         /* iso is always one packet per request, that's the only way
 904          * we can report per-packet status.  that also helps with dma.
 905          */
 906         if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 907                         && req->req.length > le16_to_cpu
 908                                                 (ep->desc->wMaxPacketSize)))
 909                 return -EMSGSIZE;
 910
 911 #ifdef  USE_DMA
 912         // FIXME caller may already have done the dma mapping
 913         if (ep->dma >= 0) {
 914                 _req->dma = dma_map_single(dev->dev,
 915                         _req->buf, _req->length,
 916                         ((ep->bEndpointAddress & USB_DIR_IN) != 0)
 917                                 ? DMA_TO_DEVICE
 918                                 : DMA_FROM_DEVICE);
 919         }
 920 #endif
 921
 922         DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
 923              _ep->name, _req, _req->length, _req->buf);
 924
 925         local_irq_save(flags);
 926
 927         _req->status = -EINPROGRESS;
 928         _req->actual = 0;
 929
 930         /* kickstart this i/o queue? */
 931         if (list_empty(&ep->queue) && !ep->stopped) {
 932                 if (ep->desc == 0 /* ep0 */) {
 933                         unsigned        length = _req->length;
 934
 935                         switch (dev->ep0state) {
 936                         case EP0_IN_DATA_PHASE:
 937                                 dev->stats.write.ops++;
 938                                 if (write_ep0_fifo(ep, req))
 939                                         req = NULL;
 940                                 break;
 941
 942                         case EP0_OUT_DATA_PHASE:
 943                                 dev->stats.read.ops++;
 944                                 /* messy ... */
 945                                 if (dev->req_config) {
 946                                         DBG(DBG_VERBOSE, "ep0 config ack%s\n",
 947                                                 dev->has_cfr ?  "" : " raced");
 948                                         if (dev->has_cfr)
 949                                                 UDCCFR = UDCCFR_AREN|UDCCFR_ACM
 950                                                         |UDCCFR_MB1;
 951                                         done(ep, req, 0);
 952                                         dev->ep0state = EP0_END_XFER;
 953                                         local_irq_restore (flags);
 954                                         return 0;
 955                                 }
 956                                 if (dev->req_pending)
 957                                         ep0start(dev, UDCCS0_IPR, "OUT");
 958                                 if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0
 959                                                 && read_ep0_fifo(ep, req))) {
 960                                         ep0_idle(dev);
 961                                         done(ep, req, 0);
 962                                         req = NULL;
 963                                 }
 964                                 break;
 965
 966                         default:
 967                                 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
 968                                 local_irq_restore (flags);
 969                                 return -EL2HLT;
 970                         }
 971 #ifdef  USE_DMA
 972                 /* either start dma or prime pio pump */
 973                 } else if (ep->dma >= 0) {
 974                         kick_dma(ep, req);
 975 #endif
 976                 /* can the FIFO can satisfy the request immediately? */
 977                 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
 978                         if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0
 979                                         && write_fifo(ep, req))
 980                                 req = NULL;
 981                 } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0
 982                                 && read_fifo(ep, req)) {
 983                         req = NULL;
 984                 }
 985
 986                 if (likely (req && ep->desc) && ep->dma < 0)
 987                         pio_irq_enable(ep->bEndpointAddress);
 988         }
 989
 990         /* pio or dma irq handler advances the queue. */
 991         if (likely (req != 0))
 992                 list_add_tail(&req->queue, &ep->queue);
 993         local_irq_restore(flags);
 994
 995         return 0;
 996 }
 997
 998
 999 /*
1000  *      nuke - dequeue ALL requests
1001  */
1002 static void nuke(struct pxa2xx_ep *ep, int status)
1003 {
1004         struct pxa2xx_request *req;
1005
1006         /* called with irqs blocked */
1007 #ifdef  USE_DMA
1008         if (ep->dma >= 0 && !ep->stopped)
1009                 cancel_dma(ep);
1010 #endif
1011         while (!list_empty(&ep->queue)) {
1012                 req = list_entry(ep->queue.next,
1013                                 struct pxa2xx_request,
1014                                 queue);
1015                 done(ep, req, status);
1016         }
1017         if (ep->desc)
1018                 pio_irq_disable (ep->bEndpointAddress);
1019 }
1020
1021
1022 /* dequeue JUST ONE request */
1023 static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1024 {
1025         struct pxa2xx_ep        *ep;
1026         struct pxa2xx_request   *req;
1027         unsigned long           flags;
1028
1029         ep = container_of(_ep, struct pxa2xx_ep, ep);
1030         if (!_ep || ep->ep.name == ep0name)
1031                 return -EINVAL;
1032
1033         local_irq_save(flags);
1034
1035         /* make sure it's actually queued on this endpoint */
1036         list_for_each_entry (req, &ep->queue, queue) {
1037                 if (&req->req == _req)
1038                         break;
1039         }
1040         if (&req->req != _req) {
1041                 local_irq_restore(flags);
1042                 return -EINVAL;
1043         }
1044
1045 #ifdef  USE_DMA
1046         if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1047                 cancel_dma(ep);
1048                 done(ep, req, -ECONNRESET);
1049                 /* restart i/o */
1050                 if (!list_empty(&ep->queue)) {
1051                         req = list_entry(ep->queue.next,
1052                                         struct pxa2xx_request, queue);
1053                         kick_dma(ep, req);
1054                 }
1055         } else
1056 #endif
1057                 done(ep, req, -ECONNRESET);
1058
1059         local_irq_restore(flags);
1060         return 0;
1061 }
1062
1063 /*-------------------------------------------------------------------------*/
1064
1065 static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value)
1066 {
1067         struct pxa2xx_ep        *ep;
1068         unsigned long           flags;
1069
1070         ep = container_of(_ep, struct pxa2xx_ep, ep);
1071         if (unlikely (!_ep
1072                         || (!ep->desc && ep->ep.name != ep0name))
1073                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1074                 DMSG("%s, bad ep\n", __FUNCTION__);
1075                 return -EINVAL;
1076         }
1077         if (value == 0) {
1078                 /* this path (reset toggle+halt) is needed to implement
1079                  * SET_INTERFACE on normal hardware.  but it can't be
1080                  * done from software on the PXA UDC, and the hardware
1081                  * forgets to do it as part of SET_INTERFACE automagic.
1082                  */
1083                 DMSG("only host can clear %s halt\n", _ep->name);
1084                 return -EROFS;
1085         }
1086
1087         local_irq_save(flags);
1088
1089         if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1090                         && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0
1091                            || !list_empty(&ep->queue))) {
1092                 local_irq_restore(flags);
1093                 return -EAGAIN;
1094         }
1095
1096         /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1097         *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF;
1098
1099         /* ep0 needs special care */
1100         if (!ep->desc) {
1101                 start_watchdog(ep->dev);
1102                 ep->dev->req_pending = 0;
1103                 ep->dev->ep0state = EP0_STALL;
1104
1105         /* and bulk/intr endpoints like dropping stalls too */
1106         } else {
1107                 unsigned i;
1108                 for (i = 0; i < 1000; i += 20) {
1109                         if (*ep->reg_udccs & UDCCS_BI_SST)
1110                                 break;
1111                         udelay(20);
1112                 }
1113         }
1114         local_irq_restore(flags);
1115
1116         DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1117         return 0;
1118 }
1119
1120 static int pxa2xx_ep_fifo_status(struct usb_ep *_ep)
1121 {
1122         struct pxa2xx_ep        *ep;
1123
1124         ep = container_of(_ep, struct pxa2xx_ep, ep);
1125         if (!_ep) {
1126                 DMSG("%s, bad ep\n", __FUNCTION__);
1127                 return -ENODEV;
1128         }
1129         /* pxa can't report unclaimed bytes from IN fifos */
1130         if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1131                 return -EOPNOTSUPP;
1132         if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1133                         || (*ep->reg_udccs & UDCCS_BO_RFS) == 0)
1134                 return 0;
1135         else
1136                 return (*ep->reg_ubcr & 0xfff) + 1;
1137 }
1138
1139 static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep)
1140 {
1141         struct pxa2xx_ep        *ep;
1142
1143         ep = container_of(_ep, struct pxa2xx_ep, ep);
1144         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1145                 DMSG("%s, bad ep\n", __FUNCTION__);
1146                 return;
1147         }
1148
1149         /* toggle and halt bits stay unchanged */
1150
1151         /* for OUT, just read and discard the FIFO contents. */
1152         if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1153                 while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0)
1154                         (void) *ep->reg_uddr;
1155                 return;
1156         }
1157
1158         /* most IN status is the same, but ISO can't stall */
1159         *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1160                 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1161                         ? 0 : UDCCS_BI_SST;
1162 }
1163
1164
1165 static struct usb_ep_ops pxa2xx_ep_ops = {
1166         .enable         = pxa2xx_ep_enable,
1167         .disable        = pxa2xx_ep_disable,
1168
1169         .alloc_request  = pxa2xx_ep_alloc_request,
1170         .free_request   = pxa2xx_ep_free_request,
1171
1172         .alloc_buffer   = pxa2xx_ep_alloc_buffer,
1173         .free_buffer    = pxa2xx_ep_free_buffer,
1174
1175         .queue          = pxa2xx_ep_queue,
1176         .dequeue        = pxa2xx_ep_dequeue,
1177
1178         .set_halt       = pxa2xx_ep_set_halt,
1179         .fifo_status    = pxa2xx_ep_fifo_status,
1180         .fifo_flush     = pxa2xx_ep_fifo_flush,
1181 };
1182
1183
1184 /* ---------------------------------------------------------------------------
1185  *      device-scoped parts of the api to the usb controller hardware
1186  * ---------------------------------------------------------------------------
1187  */
1188
1189 static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget)
1190 {
1191         return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff);
1192 }
1193
1194 static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget)
1195 {
1196         /* host may not have enabled remote wakeup */
1197         if ((UDCCS0 & UDCCS0_DRWF) == 0)
1198                 return -EHOSTUNREACH;
1199         udc_set_mask_UDCCR(UDCCR_RSM);
1200         return 0;
1201 }
1202
1203 static void stop_activity(struct pxa2xx_udc *, struct usb_gadget_driver *);
1204 static void udc_enable (struct pxa2xx_udc *);
1205 static void udc_disable(struct pxa2xx_udc *);
1206
1207 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1208  * in active use.
1209  */
1210 static int pullup(struct pxa2xx_udc *udc, int is_active)
1211 {
1212         is_active = is_active && udc->vbus && udc->pullup;
1213         DMSG("%s\n", is_active ? "active" : "inactive");
1214         if (is_active)
1215                 udc_enable(udc);
1216         else {
1217                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1218                         DMSG("disconnect %s\n", udc->driver
1219                                 ? udc->driver->driver.name
1220                                 : "(no driver)");
1221                         stop_activity(udc, udc->driver);
1222                 }
1223                 udc_disable(udc);
1224         }
1225         return 0;
1226 }
1227
1228 /* VBUS reporting logically comes from a transceiver */
1229 static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1230 {
1231         struct pxa2xx_udc       *udc;
1232
1233         udc = container_of(_gadget, struct pxa2xx_udc, gadget);
1234         udc->vbus = is_active = (is_active != 0);
1235         DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
1236         pullup(udc, is_active);
1237         return 0;
1238 }
1239
1240 /* drivers may have software control over D+ pullup */
1241 static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active)
1242 {
1243         struct pxa2xx_udc       *udc;
1244
1245         udc = container_of(_gadget, struct pxa2xx_udc, gadget);
1246
1247         /* not all boards support pullup control */
1248         if (!udc->mach->udc_command)
1249                 return -EOPNOTSUPP;
1250
1251         is_active = (is_active != 0);
1252         udc->pullup = is_active;
1253         pullup(udc, is_active);
1254         return 0;
1255 }
1256
1257 static const struct usb_gadget_ops pxa2xx_udc_ops = {
1258         .get_frame      = pxa2xx_udc_get_frame,
1259         .wakeup         = pxa2xx_udc_wakeup,
1260         .vbus_session   = pxa2xx_udc_vbus_session,
1261         .pullup         = pxa2xx_udc_pullup,
1262
1263         // .vbus_draw ... boards may consume current from VBUS, up to
1264         // 100-500mA based on config.  the 500uA suspend ceiling means
1265         // that exclusively vbus-powered PXA designs violate USB specs.
1266 };
1267
1268 /*-------------------------------------------------------------------------*/
1269
1270 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1271
1272 static const char proc_node_name [] = "driver/udc";
1273
1274 static int
1275 udc_proc_read(char *page, char **start, off_t off, int count,
1276                 int *eof, void *_dev)
1277 {
1278         char                    *buf = page;
1279         struct pxa2xx_udc       *dev = _dev;
1280         char                    *next = buf;
1281         unsigned                size = count;
1282         unsigned long           flags;
1283         int                     i, t;
1284         u32                     tmp;
1285
1286         if (off != 0)
1287                 return 0;
1288
1289         local_irq_save(flags);
1290
1291         /* basic device status */
1292         t = scnprintf(next, size, DRIVER_DESC "\n"
1293                 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1294                 driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1295                 dev->driver ? dev->driver->driver.name : "(none)",
1296                 is_vbus_present() ? "full speed" : "disconnected");
1297         size -= t;
1298         next += t;
1299
1300         /* registers for device and ep0 */
1301         t = scnprintf(next, size,
1302                 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1303                 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
1304         size -= t;
1305         next += t;
1306
1307         tmp = UDCCR;
1308         t = scnprintf(next, size,
1309                 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1310                 (tmp & UDCCR_REM) ? " rem" : "",
1311                 (tmp & UDCCR_RSTIR) ? " rstir" : "",
1312                 (tmp & UDCCR_SRM) ? " srm" : "",
1313                 (tmp & UDCCR_SUSIR) ? " susir" : "",
1314                 (tmp & UDCCR_RESIR) ? " resir" : "",
1315                 (tmp & UDCCR_RSM) ? " rsm" : "",
1316                 (tmp & UDCCR_UDA) ? " uda" : "",
1317                 (tmp & UDCCR_UDE) ? " ude" : "");
1318         size -= t;
1319         next += t;
1320
1321         tmp = UDCCS0;
1322         t = scnprintf(next, size,
1323                 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1324                 (tmp & UDCCS0_SA) ? " sa" : "",
1325                 (tmp & UDCCS0_RNE) ? " rne" : "",
1326                 (tmp & UDCCS0_FST) ? " fst" : "",
1327                 (tmp & UDCCS0_SST) ? " sst" : "",
1328                 (tmp & UDCCS0_DRWF) ? " dwrf" : "",
1329                 (tmp & UDCCS0_FTF) ? " ftf" : "",
1330                 (tmp & UDCCS0_IPR) ? " ipr" : "",
1331                 (tmp & UDCCS0_OPR) ? " opr" : "");
1332         size -= t;
1333         next += t;
1334
1335         if (dev->has_cfr) {
1336                 tmp = UDCCFR;
1337                 t = scnprintf(next, size,
1338                         "udccfr %02X =%s%s\n", tmp,
1339                         (tmp & UDCCFR_AREN) ? " aren" : "",
1340                         (tmp & UDCCFR_ACM) ? " acm" : "");
1341                 size -= t;
1342                 next += t;
1343         }
1344
1345         if (!is_vbus_present() || !dev->driver)
1346                 goto done;
1347
1348         t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1349                 dev->stats.write.bytes, dev->stats.write.ops,
1350                 dev->stats.read.bytes, dev->stats.read.ops,
1351                 dev->stats.irqs);
1352         size -= t;
1353         next += t;
1354
1355         /* dump endpoint queues */
1356         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1357                 struct pxa2xx_ep        *ep = &dev->ep [i];
1358                 struct pxa2xx_request   *req;
1359                 int                     t;
1360
1361                 if (i != 0) {
1362                         const struct usb_endpoint_descriptor    *d;
1363
1364                         d = ep->desc;
1365                         if (!d)
1366                                 continue;
1367                         tmp = *dev->ep [i].reg_udccs;
1368                         t = scnprintf(next, size,
1369                                 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1370                                 ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1371                                 (ep->dma >= 0) ? "dma" : "pio", tmp,
1372                                 ep->pio_irqs, ep->dma_irqs);
1373                         /* TODO translate all five groups of udccs bits! */
1374
1375                 } else /* ep0 should only have one transfer queued */
1376                         t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1377                                 ep->pio_irqs);
1378                 if (t <= 0 || t > size)
1379                         goto done;
1380                 size -= t;
1381                 next += t;
1382
1383                 if (list_empty(&ep->queue)) {
1384                         t = scnprintf(next, size, "\t(nothing queued)\n");
1385                         if (t <= 0 || t > size)
1386                                 goto done;
1387                         size -= t;
1388                         next += t;
1389                         continue;
1390                 }
1391                 list_for_each_entry(req, &ep->queue, queue) {
1392 #ifdef  USE_DMA
1393                         if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1394                                 t = scnprintf(next, size,
1395                                         "\treq %p len %d/%d "
1396                                         "buf %p (dma%d dcmd %08x)\n",
1397                                         &req->req, req->req.actual,
1398                                         req->req.length, req->req.buf,
1399                                         ep->dma, DCMD(ep->dma)
1400                                         // low 13 bits == bytes-to-go
1401                                         );
1402                         else
1403 #endif
1404                                 t = scnprintf(next, size,
1405                                         "\treq %p len %d/%d buf %p\n",
1406                                         &req->req, req->req.actual,
1407                                         req->req.length, req->req.buf);
1408                         if (t <= 0 || t > size)
1409                                 goto done;
1410                         size -= t;
1411                         next += t;
1412                 }
1413         }
1414
1415 done:
1416         local_irq_restore(flags);
1417         *eof = 1;
1418         return count - size;
1419 }
1420
1421 #define create_proc_files() \
1422         create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1423 #define remove_proc_files() \
1424         remove_proc_entry(proc_node_name, NULL)
1425
1426 #else   /* !CONFIG_USB_GADGET_DEBUG_FILES */
1427
1428 #define create_proc_files() do {} while (0)
1429 #define remove_proc_files() do {} while (0)
1430
1431 #endif  /* CONFIG_USB_GADGET_DEBUG_FILES */
1432
1433 /* "function" sysfs attribute */
1434 static ssize_t
1435 show_function (struct device *_dev, struct device_attribute *attr, char *buf)
1436 {
1437         struct pxa2xx_udc       *dev = dev_get_drvdata (_dev);
1438
1439         if (!dev->driver
1440                         || !dev->driver->function
1441                         || strlen (dev->driver->function) > PAGE_SIZE)
1442                 return 0;
1443         return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1444 }
1445 static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1446
1447 /*-------------------------------------------------------------------------*/
1448
1449 /*
1450  *      udc_disable - disable USB device controller
1451  */
1452 static void udc_disable(struct pxa2xx_udc *dev)
1453 {
1454         /* block all irqs */
1455         udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1456         UICR0 = UICR1 = 0xff;
1457         UFNRH = UFNRH_SIM;
1458
1459         /* if hardware supports it, disconnect from usb */
1460         pullup_off();
1461
1462         udc_clear_mask_UDCCR(UDCCR_UDE);
1463
1464 #ifdef  CONFIG_ARCH_PXA
1465         /* Disable clock for USB device */
1466         pxa_set_cken(CKEN11_USB, 0);
1467 #endif
1468
1469         ep0_idle (dev);
1470         dev->gadget.speed = USB_SPEED_UNKNOWN;
1471         LED_CONNECTED_OFF;
1472 }
1473
1474
1475 /*
1476  *      udc_reinit - initialize software state
1477  */
1478 static void udc_reinit(struct pxa2xx_udc *dev)
1479 {
1480         u32     i;
1481
1482         /* device/ep0 records init */
1483         INIT_LIST_HEAD (&dev->gadget.ep_list);
1484         INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1485         dev->ep0state = EP0_IDLE;
1486
1487         /* basic endpoint records init */
1488         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1489                 struct pxa2xx_ep *ep = &dev->ep[i];
1490
1491                 if (i != 0)
1492                         list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1493
1494                 ep->desc = NULL;
1495                 ep->stopped = 0;
1496                 INIT_LIST_HEAD (&ep->queue);
1497                 ep->pio_irqs = ep->dma_irqs = 0;
1498         }
1499
1500         /* the rest was statically initialized, and is read-only */
1501 }
1502
1503 /* until it's enabled, this UDC should be completely invisible
1504  * to any USB host.
1505  */
1506 static void udc_enable (struct pxa2xx_udc *dev)
1507 {
1508         udc_clear_mask_UDCCR(UDCCR_UDE);
1509
1510 #ifdef  CONFIG_ARCH_PXA
1511         /* Enable clock for USB device */
1512         pxa_set_cken(CKEN11_USB, 1);
1513         udelay(5);
1514 #endif
1515
1516         /* try to clear these bits before we enable the udc */
1517         udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1518
1519         ep0_idle(dev);
1520         dev->gadget.speed = USB_SPEED_UNKNOWN;
1521         dev->stats.irqs = 0;
1522
1523         /*
1524          * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1525          * - enable UDC
1526          * - if RESET is already in progress, ack interrupt
1527          * - unmask reset interrupt
1528          */
1529         udc_set_mask_UDCCR(UDCCR_UDE);
1530         if (!(UDCCR & UDCCR_UDA))
1531                 udc_ack_int_UDCCR(UDCCR_RSTIR);
1532
1533         if (dev->has_cfr /* UDC_RES2 is defined */) {
1534                 /* pxa255 (a0+) can avoid a set_config race that could
1535                  * prevent gadget drivers from configuring correctly
1536                  */
1537                 UDCCFR = UDCCFR_ACM | UDCCFR_MB1;
1538         } else {
1539                 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1540                  * which could result in missing packets and interrupts.
1541                  * supposedly one bit per endpoint, controlling whether it
1542                  * double buffers or not; ACM/AREN bits fit into the holes.
1543                  * zero bits (like USIR0_IRx) disable double buffering.
1544                  */
1545                 UDC_RES1 = 0x00;
1546                 UDC_RES2 = 0x00;
1547         }
1548
1549 #ifdef  DISABLE_TEST_MODE
1550         /* "test mode" seems to have become the default in later chip
1551          * revs, preventing double buffering (and invalidating docs).
1552          * this EXPERIMENT enables it for bulk endpoints by tweaking
1553          * undefined/reserved register bits (that other drivers clear).
1554          * Belcarra code comments noted this usage.
1555          */
1556         if (fifo_mode & 1) {    /* IN endpoints */
1557                 UDC_RES1 |= USIR0_IR1|USIR0_IR6;
1558                 UDC_RES2 |= USIR1_IR11;
1559         }
1560         if (fifo_mode & 2) {    /* OUT endpoints */
1561                 UDC_RES1 |= USIR0_IR2|USIR0_IR7;
1562                 UDC_RES2 |= USIR1_IR12;
1563         }
1564 #endif
1565
1566         /* enable suspend/resume and reset irqs */
1567         udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1568
1569         /* enable ep0 irqs */
1570         UICR0 &= ~UICR0_IM0;
1571
1572         /* if hardware supports it, pullup D+ and wait for reset */
1573         pullup_on();
1574 }
1575
1576
1577 /* when a driver is successfully registered, it will receive
1578  * control requests including set_configuration(), which enables
1579  * non-control requests.  then usb traffic follows until a
1580  * disconnect is reported.  then a host may connect again, or
1581  * the driver might get unbound.
1582  */
1583 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1584 {
1585         struct pxa2xx_udc       *dev = the_controller;
1586         int                     retval;
1587
1588         if (!driver
1589                         || driver->speed != USB_SPEED_FULL
1590                         || !driver->bind
1591                         || !driver->unbind
1592                         || !driver->disconnect
1593                         || !driver->setup)
1594                 return -EINVAL;
1595         if (!dev)
1596                 return -ENODEV;
1597         if (dev->driver)
1598                 return -EBUSY;
1599
1600         /* first hook up the driver ... */
1601         dev->driver = driver;
1602         dev->gadget.dev.driver = &driver->driver;
1603         dev->pullup = 1;
1604
1605         device_add (&dev->gadget.dev);
1606         retval = driver->bind(&dev->gadget);
1607         if (retval) {
1608                 DMSG("bind to driver %s --> error %d\n",
1609                                 driver->driver.name, retval);
1610                 device_del (&dev->gadget.dev);
1611
1612                 dev->driver = NULL;
1613                 dev->gadget.dev.driver = NULL;
1614                 return retval;
1615         }
1616         device_create_file(dev->dev, &dev_attr_function);
1617
1618         /* ... then enable host detection and ep0; and we're ready
1619          * for set_configuration as well as eventual disconnect.
1620          */
1621         DMSG("registered gadget driver '%s'\n", driver->driver.name);
1622         pullup(dev, 1);
1623         dump_state(dev);
1624         return 0;
1625 }
1626 EXPORT_SYMBOL(usb_gadget_register_driver);
1627
1628 static void
1629 stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver)
1630 {
1631         int i;
1632
1633         /* don't disconnect drivers more than once */
1634         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1635                 driver = NULL;
1636         dev->gadget.speed = USB_SPEED_UNKNOWN;
1637
1638         /* prevent new request submissions, kill any outstanding requests  */
1639         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1640                 struct pxa2xx_ep *ep = &dev->ep[i];
1641
1642                 ep->stopped = 1;
1643                 nuke(ep, -ESHUTDOWN);
1644         }
1645         del_timer_sync(&dev->timer);
1646
1647         /* report disconnect; the driver is already quiesced */
1648         LED_CONNECTED_OFF;
1649         if (driver)
1650                 driver->disconnect(&dev->gadget);
1651
1652         /* re-init driver-visible data structures */
1653         udc_reinit(dev);
1654 }
1655
1656 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1657 {
1658         struct pxa2xx_udc       *dev = the_controller;
1659
1660         if (!dev)
1661                 return -ENODEV;
1662         if (!driver || driver != dev->driver)
1663                 return -EINVAL;
1664
1665         local_irq_disable();
1666         pullup(dev, 0);
1667         stop_activity(dev, driver);
1668         local_irq_enable();
1669
1670         driver->unbind(&dev->gadget);
1671         dev->driver = NULL;
1672
1673         device_del (&dev->gadget.dev);
1674         device_remove_file(dev->dev, &dev_attr_function);
1675
1676         DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1677         dump_state(dev);
1678         return 0;
1679 }
1680 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1681
1682
1683 /*-------------------------------------------------------------------------*/
1684
1685 #ifdef CONFIG_ARCH_LUBBOCK
1686
1687 /* Lubbock has separate connect and disconnect irqs.  More typical designs
1688  * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1689  */
1690
1691 static irqreturn_t
1692 lubbock_vbus_irq(int irq, void *_dev, struct pt_regs *r)
1693 {
1694         struct pxa2xx_udc       *dev = _dev;
1695         int                     vbus;
1696
1697         dev->stats.irqs++;
1698         HEX_DISPLAY(dev->stats.irqs);
1699         switch (irq) {
1700         case LUBBOCK_USB_IRQ:
1701                 LED_CONNECTED_ON;
1702                 vbus = 1;
1703                 disable_irq(LUBBOCK_USB_IRQ);
1704                 enable_irq(LUBBOCK_USB_DISC_IRQ);
1705                 break;
1706         case LUBBOCK_USB_DISC_IRQ:
1707                 LED_CONNECTED_OFF;
1708                 vbus = 0;
1709                 disable_irq(LUBBOCK_USB_DISC_IRQ);
1710                 enable_irq(LUBBOCK_USB_IRQ);
1711                 break;
1712         default:
1713                 return IRQ_NONE;
1714         }
1715
1716         pxa2xx_udc_vbus_session(&dev->gadget, vbus);
1717         return IRQ_HANDLED;
1718 }
1719
1720 #endif
1721
1722
1723 /*-------------------------------------------------------------------------*/
1724
1725 static inline void clear_ep_state (struct pxa2xx_udc *dev)
1726 {
1727         unsigned i;
1728
1729         /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1730          * fifos, and pending transactions mustn't be continued in any case.
1731          */
1732         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1733                 nuke(&dev->ep[i], -ECONNABORTED);
1734 }
1735
1736 static void udc_watchdog(unsigned long _dev)
1737 {
1738         struct pxa2xx_udc       *dev = (void *)_dev;
1739
1740         local_irq_disable();
1741         if (dev->ep0state == EP0_STALL
1742                         && (UDCCS0 & UDCCS0_FST) == 0
1743                         && (UDCCS0 & UDCCS0_SST) == 0) {
1744                 UDCCS0 = UDCCS0_FST|UDCCS0_FTF;
1745                 DBG(DBG_VERBOSE, "ep0 re-stall\n");
1746                 start_watchdog(dev);
1747         }
1748         local_irq_enable();
1749 }
1750
1751 static void handle_ep0 (struct pxa2xx_udc *dev)
1752 {
1753         u32                     udccs0 = UDCCS0;
1754         struct pxa2xx_ep        *ep = &dev->ep [0];
1755         struct pxa2xx_request   *req;
1756         union {
1757                 struct usb_ctrlrequest  r;
1758                 u8                      raw [8];
1759                 u32                     word [2];
1760         } u;
1761
1762         if (list_empty(&ep->queue))
1763                 req = NULL;
1764         else
1765                 req = list_entry(ep->queue.next, struct pxa2xx_request, queue);
1766
1767         /* clear stall status */
1768         if (udccs0 & UDCCS0_SST) {
1769                 nuke(ep, -EPIPE);
1770                 UDCCS0 = UDCCS0_SST;
1771                 del_timer(&dev->timer);
1772                 ep0_idle(dev);
1773         }
1774
1775         /* previous request unfinished?  non-error iff back-to-back ... */
1776         if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1777                 nuke(ep, 0);
1778                 del_timer(&dev->timer);
1779                 ep0_idle(dev);
1780         }
1781
1782         switch (dev->ep0state) {
1783         case EP0_IDLE:
1784                 /* late-breaking status? */
1785                 udccs0 = UDCCS0;
1786
1787                 /* start control request? */
1788                 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1789                                 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1790                         int i;
1791
1792                         nuke (ep, -EPROTO);
1793
1794                         /* read SETUP packet */
1795                         for (i = 0; i < 8; i++) {
1796                                 if (unlikely(!(UDCCS0 & UDCCS0_RNE))) {
1797 bad_setup:
1798                                         DMSG("SETUP %d!\n", i);
1799                                         goto stall;
1800                                 }
1801                                 u.raw [i] = (u8) UDDR0;
1802                         }
1803                         if (unlikely((UDCCS0 & UDCCS0_RNE) != 0))
1804                                 goto bad_setup;
1805
1806 got_setup:
1807                         DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1808                                 u.r.bRequestType, u.r.bRequest,
1809                                 le16_to_cpu(u.r.wValue),
1810                                 le16_to_cpu(u.r.wIndex),
1811                                 le16_to_cpu(u.r.wLength));
1812
1813                         /* cope with automagic for some standard requests. */
1814                         dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1815                                                 == USB_TYPE_STANDARD;
1816                         dev->req_config = 0;
1817                         dev->req_pending = 1;
1818                         switch (u.r.bRequest) {
1819                         /* hardware restricts gadget drivers here! */
1820                         case USB_REQ_SET_CONFIGURATION:
1821                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1822                                         /* reflect hardware's automagic
1823                                          * up to the gadget driver.
1824                                          */
1825 config_change:
1826                                         dev->req_config = 1;
1827                                         clear_ep_state(dev);
1828                                         /* if !has_cfr, there's no synch
1829                                          * else use AREN (later) not SA|OPR
1830                                          * USIR0_IR0 acts edge sensitive
1831                                          */
1832                                 }
1833                                 break;
1834                         /* ... and here, even more ... */
1835                         case USB_REQ_SET_INTERFACE:
1836                                 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1837                                         /* udc hardware is broken by design:
1838                                          *  - altsetting may only be zero;
1839                                          *  - hw resets all interfaces' eps;
1840                                          *  - ep reset doesn't include halt(?).
1841                                          */
1842                                         DMSG("broken set_interface (%d/%d)\n",
1843                                                 le16_to_cpu(u.r.wIndex),
1844                                                 le16_to_cpu(u.r.wValue));
1845                                         goto config_change;
1846                                 }
1847                                 break;
1848                         /* hardware was supposed to hide this */
1849                         case USB_REQ_SET_ADDRESS:
1850                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1851                                         ep0start(dev, 0, "address");
1852                                         return;
1853                                 }
1854                                 break;
1855                         }
1856
1857                         if (u.r.bRequestType & USB_DIR_IN)
1858                                 dev->ep0state = EP0_IN_DATA_PHASE;
1859                         else
1860                                 dev->ep0state = EP0_OUT_DATA_PHASE;
1861
1862                         i = dev->driver->setup(&dev->gadget, &u.r);
1863                         if (i < 0) {
1864                                 /* hardware automagic preventing STALL... */
1865                                 if (dev->req_config) {
1866                                         /* hardware sometimes neglects to tell
1867                                          * tell us about config change events,
1868                                          * so later ones may fail...
1869                                          */
1870                                         WARN("config change %02x fail %d?\n",
1871                                                 u.r.bRequest, i);
1872                                         return;
1873                                         /* TODO experiment:  if has_cfr,
1874                                          * hardware didn't ACK; maybe we
1875                                          * could actually STALL!
1876                                          */
1877                                 }
1878                                 DBG(DBG_VERBOSE, "protocol STALL, "
1879                                         "%02x err %d\n", UDCCS0, i);
1880 stall:
1881                                 /* the watchdog timer helps deal with cases
1882                                  * where udc seems to clear FST wrongly, and
1883                                  * then NAKs instead of STALLing.
1884                                  */
1885                                 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1886                                 start_watchdog(dev);
1887                                 dev->ep0state = EP0_STALL;
1888
1889                         /* deferred i/o == no response yet */
1890                         } else if (dev->req_pending) {
1891                                 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1892                                                 || dev->req_std || u.r.wLength))
1893                                         ep0start(dev, 0, "defer");
1894                                 else
1895                                         ep0start(dev, UDCCS0_IPR, "defer/IPR");
1896                         }
1897
1898                         /* expect at least one data or status stage irq */
1899                         return;
1900
1901                 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1902                                 == (UDCCS0_OPR|UDCCS0_SA))) {
1903                         unsigned i;
1904
1905                         /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1906                          * still observed on a pxa255 a0.
1907                          */
1908                         DBG(DBG_VERBOSE, "e131\n");
1909                         nuke(ep, -EPROTO);
1910
1911                         /* read SETUP data, but don't trust it too much */
1912                         for (i = 0; i < 8; i++)
1913                                 u.raw [i] = (u8) UDDR0;
1914                         if ((u.r.bRequestType & USB_RECIP_MASK)
1915                                         > USB_RECIP_OTHER)
1916                                 goto stall;
1917                         if (u.word [0] == 0 && u.word [1] == 0)
1918                                 goto stall;
1919                         goto got_setup;
1920                 } else {
1921                         /* some random early IRQ:
1922                          * - we acked FST
1923                          * - IPR cleared
1924                          * - OPR got set, without SA (likely status stage)
1925                          */
1926                         UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR);
1927                 }
1928                 break;
1929         case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1930                 if (udccs0 & UDCCS0_OPR) {
1931                         UDCCS0 = UDCCS0_OPR|UDCCS0_FTF;
1932                         DBG(DBG_VERBOSE, "ep0in premature status\n");
1933                         if (req)
1934                                 done(ep, req, 0);
1935                         ep0_idle(dev);
1936                 } else /* irq was IPR clearing */ {
1937                         if (req) {
1938                                 /* this IN packet might finish the request */
1939                                 (void) write_ep0_fifo(ep, req);
1940                         } /* else IN token before response was written */
1941                 }
1942                 break;
1943         case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1944                 if (udccs0 & UDCCS0_OPR) {
1945                         if (req) {
1946                                 /* this OUT packet might finish the request */
1947                                 if (read_ep0_fifo(ep, req))
1948                                         done(ep, req, 0);
1949                                 /* else more OUT packets expected */
1950                         } /* else OUT token before read was issued */
1951                 } else /* irq was IPR clearing */ {
1952                         DBG(DBG_VERBOSE, "ep0out premature status\n");
1953                         if (req)
1954                                 done(ep, req, 0);
1955                         ep0_idle(dev);
1956                 }
1957                 break;
1958         case EP0_END_XFER:
1959                 if (req)
1960                         done(ep, req, 0);
1961                 /* ack control-IN status (maybe in-zlp was skipped)
1962                  * also appears after some config change events.
1963                  */
1964                 if (udccs0 & UDCCS0_OPR)
1965                         UDCCS0 = UDCCS0_OPR;
1966                 ep0_idle(dev);
1967                 break;
1968         case EP0_STALL:
1969                 UDCCS0 = UDCCS0_FST;
1970                 break;
1971         }
1972         USIR0 = USIR0_IR0;
1973 }
1974
1975 static void handle_ep(struct pxa2xx_ep *ep)
1976 {
1977         struct pxa2xx_request   *req;
1978         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
1979         int                     completed;
1980         u32                     udccs, tmp;
1981
1982         do {
1983                 completed = 0;
1984                 if (likely (!list_empty(&ep->queue)))
1985                         req = list_entry(ep->queue.next,
1986                                         struct pxa2xx_request, queue);
1987                 else
1988                         req = NULL;
1989
1990                 // TODO check FST handling
1991
1992                 udccs = *ep->reg_udccs;
1993                 if (unlikely(is_in)) {  /* irq from TPC, SST, or (ISO) TUR */
1994                         tmp = UDCCS_BI_TUR;
1995                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1996                                 tmp |= UDCCS_BI_SST;
1997                         tmp &= udccs;
1998                         if (likely (tmp))
1999                                 *ep->reg_udccs = tmp;
2000                         if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
2001                                 completed = write_fifo(ep, req);
2002
2003                 } else {        /* irq from RPC (or for ISO, ROF) */
2004                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
2005                                 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
2006                         else
2007                                 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
2008                         tmp &= udccs;
2009                         if (likely(tmp))
2010                                 *ep->reg_udccs = tmp;
2011
2012                         /* fifos can hold packets, ready for reading... */
2013                         if (likely(req)) {
2014 #ifdef USE_OUT_DMA
2015 // TODO didn't yet debug out-dma.  this approach assumes
2016 // the worst about short packets and RPC; it might be better.
2017
2018                                 if (likely(ep->dma >= 0)) {
2019                                         if (!(udccs & UDCCS_BO_RSP)) {
2020                                                 *ep->reg_udccs = UDCCS_BO_RPC;
2021                                                 ep->dma_irqs++;
2022                                                 return;
2023                                         }
2024                                 }
2025 #endif
2026                                 completed = read_fifo(ep, req);
2027                         } else
2028                                 pio_irq_disable (ep->bEndpointAddress);
2029                 }
2030                 ep->pio_irqs++;
2031         } while (completed);
2032 }
2033
2034 /*
2035  *      pxa2xx_udc_irq - interrupt handler
2036  *
2037  * avoid delays in ep0 processing. the control handshaking isn't always
2038  * under software control (pxa250c0 and the pxa255 are better), and delays
2039  * could cause usb protocol errors.
2040  */
2041 static irqreturn_t
2042 pxa2xx_udc_irq(int irq, void *_dev, struct pt_regs *r)
2043 {
2044         struct pxa2xx_udc       *dev = _dev;
2045         int                     handled;
2046
2047         dev->stats.irqs++;
2048         HEX_DISPLAY(dev->stats.irqs);
2049         do {
2050                 u32             udccr = UDCCR;
2051
2052                 handled = 0;
2053
2054                 /* SUSpend Interrupt Request */
2055                 if (unlikely(udccr & UDCCR_SUSIR)) {
2056                         udc_ack_int_UDCCR(UDCCR_SUSIR);
2057                         handled = 1;
2058                         DBG(DBG_VERBOSE, "USB suspend%s\n", is_vbus_present()
2059                                 ? "" : "+disconnect");
2060
2061                         if (!is_vbus_present())
2062                                 stop_activity(dev, dev->driver);
2063                         else if (dev->gadget.speed != USB_SPEED_UNKNOWN
2064                                         && dev->driver
2065                                         && dev->driver->suspend)
2066                                 dev->driver->suspend(&dev->gadget);
2067                         ep0_idle (dev);
2068                 }
2069
2070                 /* RESume Interrupt Request */
2071                 if (unlikely(udccr & UDCCR_RESIR)) {
2072                         udc_ack_int_UDCCR(UDCCR_RESIR);
2073                         handled = 1;
2074                         DBG(DBG_VERBOSE, "USB resume\n");
2075
2076                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
2077                                         && dev->driver
2078                                         && dev->driver->resume
2079                                         && is_vbus_present())
2080                                 dev->driver->resume(&dev->gadget);
2081                 }
2082
2083                 /* ReSeT Interrupt Request - USB reset */
2084                 if (unlikely(udccr & UDCCR_RSTIR)) {
2085                         udc_ack_int_UDCCR(UDCCR_RSTIR);
2086                         handled = 1;
2087
2088                         if ((UDCCR & UDCCR_UDA) == 0) {
2089                                 DBG(DBG_VERBOSE, "USB reset start\n");
2090
2091                                 /* reset driver and endpoints,
2092                                  * in case that's not yet done
2093                                  */
2094                                 stop_activity (dev, dev->driver);
2095
2096                         } else {
2097                                 DBG(DBG_VERBOSE, "USB reset end\n");
2098                                 dev->gadget.speed = USB_SPEED_FULL;
2099                                 LED_CONNECTED_ON;
2100                                 memset(&dev->stats, 0, sizeof dev->stats);
2101                                 /* driver and endpoints are still reset */
2102                         }
2103
2104                 } else {
2105                         u32     usir0 = USIR0 & ~UICR0;
2106                         u32     usir1 = USIR1 & ~UICR1;
2107                         int     i;
2108
2109                         if (unlikely (!usir0 && !usir1))
2110                                 continue;
2111
2112                         DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
2113
2114                         /* control traffic */
2115                         if (usir0 & USIR0_IR0) {
2116                                 dev->ep[0].pio_irqs++;
2117                                 handle_ep0(dev);
2118                                 handled = 1;
2119                         }
2120
2121                         /* endpoint data transfers */
2122                         for (i = 0; i < 8; i++) {
2123                                 u32     tmp = 1 << i;
2124
2125                                 if (i && (usir0 & tmp)) {
2126                                         handle_ep(&dev->ep[i]);
2127                                         USIR0 |= tmp;
2128                                         handled = 1;
2129                                 }
2130                                 if (usir1 & tmp) {
2131                                         handle_ep(&dev->ep[i+8]);
2132                                         USIR1 |= tmp;
2133                                         handled = 1;
2134                                 }
2135                         }
2136                 }
2137
2138                 /* we could also ask for 1 msec SOF (SIR) interrupts */
2139
2140         } while (handled);
2141         return IRQ_HANDLED;
2142 }
2143
2144 /*-------------------------------------------------------------------------*/
2145
2146 static void nop_release (struct device *dev)
2147 {
2148         DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2149 }
2150
2151 /* this uses load-time allocation and initialization (instead of
2152  * doing it at run-time) to save code, eliminate fault paths, and
2153  * be more obviously correct.
2154  */
2155 static struct pxa2xx_udc memory = {
2156         .gadget = {
2157                 .ops            = &pxa2xx_udc_ops,
2158                 .ep0            = &memory.ep[0].ep,
2159                 .name           = driver_name,
2160                 .dev = {
2161                         .bus_id         = "gadget",
2162                         .release        = nop_release,
2163                 },
2164         },
2165
2166         /* control endpoint */
2167         .ep[0] = {
2168                 .ep = {
2169                         .name           = ep0name,
2170                         .ops            = &pxa2xx_ep_ops,
2171                         .maxpacket      = EP0_FIFO_SIZE,
2172                 },
2173                 .dev            = &memory,
2174                 .reg_udccs      = &UDCCS0,
2175                 .reg_uddr       = &UDDR0,
2176         },
2177
2178         /* first group of endpoints */
2179         .ep[1] = {
2180                 .ep = {
2181                         .name           = "ep1in-bulk",
2182                         .ops            = &pxa2xx_ep_ops,
2183                         .maxpacket      = BULK_FIFO_SIZE,
2184                 },
2185                 .dev            = &memory,
2186                 .fifo_size      = BULK_FIFO_SIZE,
2187                 .bEndpointAddress = USB_DIR_IN | 1,
2188                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2189                 .reg_udccs      = &UDCCS1,
2190                 .reg_uddr       = &UDDR1,
2191                 drcmr (25)
2192         },
2193         .ep[2] = {
2194                 .ep = {
2195                         .name           = "ep2out-bulk",
2196                         .ops            = &pxa2xx_ep_ops,
2197                         .maxpacket      = BULK_FIFO_SIZE,
2198                 },
2199                 .dev            = &memory,
2200                 .fifo_size      = BULK_FIFO_SIZE,
2201                 .bEndpointAddress = 2,
2202                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2203                 .reg_udccs      = &UDCCS2,
2204                 .reg_ubcr       = &UBCR2,
2205                 .reg_uddr       = &UDDR2,
2206                 drcmr (26)
2207         },
2208 #ifndef CONFIG_USB_PXA2XX_SMALL
2209         .ep[3] = {
2210                 .ep = {
2211                         .name           = "ep3in-iso",
2212                         .ops            = &pxa2xx_ep_ops,
2213                         .maxpacket      = ISO_FIFO_SIZE,
2214                 },
2215                 .dev            = &memory,
2216                 .fifo_size      = ISO_FIFO_SIZE,
2217                 .bEndpointAddress = USB_DIR_IN | 3,
2218                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2219                 .reg_udccs      = &UDCCS3,
2220                 .reg_uddr       = &UDDR3,
2221                 drcmr (27)
2222         },
2223         .ep[4] = {
2224                 .ep = {
2225                         .name           = "ep4out-iso",
2226                         .ops            = &pxa2xx_ep_ops,
2227                         .maxpacket      = ISO_FIFO_SIZE,
2228                 },
2229                 .dev            = &memory,
2230                 .fifo_size      = ISO_FIFO_SIZE,
2231                 .bEndpointAddress = 4,
2232                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2233                 .reg_udccs      = &UDCCS4,
2234                 .reg_ubcr       = &UBCR4,
2235                 .reg_uddr       = &UDDR4,
2236                 drcmr (28)
2237         },
2238         .ep[5] = {
2239                 .ep = {
2240                         .name           = "ep5in-int",
2241                         .ops            = &pxa2xx_ep_ops,
2242                         .maxpacket      = INT_FIFO_SIZE,
2243                 },
2244                 .dev            = &memory,
2245                 .fifo_size      = INT_FIFO_SIZE,
2246                 .bEndpointAddress = USB_DIR_IN | 5,
2247                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2248                 .reg_udccs      = &UDCCS5,
2249                 .reg_uddr       = &UDDR5,
2250         },
2251
2252         /* second group of endpoints */
2253         .ep[6] = {
2254                 .ep = {
2255                         .name           = "ep6in-bulk",
2256                         .ops            = &pxa2xx_ep_ops,
2257                         .maxpacket      = BULK_FIFO_SIZE,
2258                 },
2259                 .dev            = &memory,
2260                 .fifo_size      = BULK_FIFO_SIZE,
2261                 .bEndpointAddress = USB_DIR_IN | 6,
2262                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2263                 .reg_udccs      = &UDCCS6,
2264                 .reg_uddr       = &UDDR6,
2265                 drcmr (30)
2266         },
2267         .ep[7] = {
2268                 .ep = {
2269                         .name           = "ep7out-bulk",
2270                         .ops            = &pxa2xx_ep_ops,
2271                         .maxpacket      = BULK_FIFO_SIZE,
2272                 },
2273                 .dev            = &memory,
2274                 .fifo_size      = BULK_FIFO_SIZE,
2275                 .bEndpointAddress = 7,
2276                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2277                 .reg_udccs      = &UDCCS7,
2278                 .reg_ubcr       = &UBCR7,
2279                 .reg_uddr       = &UDDR7,
2280                 drcmr (31)
2281         },
2282         .ep[8] = {
2283                 .ep = {
2284                         .name           = "ep8in-iso",
2285                         .ops            = &pxa2xx_ep_ops,
2286                         .maxpacket      = ISO_FIFO_SIZE,
2287                 },
2288                 .dev            = &memory,
2289                 .fifo_size      = ISO_FIFO_SIZE,
2290                 .bEndpointAddress = USB_DIR_IN | 8,
2291                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2292                 .reg_udccs      = &UDCCS8,
2293                 .reg_uddr       = &UDDR8,
2294                 drcmr (32)
2295         },
2296         .ep[9] = {
2297                 .ep = {
2298                         .name           = "ep9out-iso",
2299                         .ops            = &pxa2xx_ep_ops,
2300                         .maxpacket      = ISO_FIFO_SIZE,
2301                 },
2302                 .dev            = &memory,
2303                 .fifo_size      = ISO_FIFO_SIZE,
2304                 .bEndpointAddress = 9,
2305                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2306                 .reg_udccs      = &UDCCS9,
2307                 .reg_ubcr       = &UBCR9,
2308                 .reg_uddr       = &UDDR9,
2309                 drcmr (33)
2310         },
2311         .ep[10] = {
2312                 .ep = {
2313                         .name           = "ep10in-int",
2314                         .ops            = &pxa2xx_ep_ops,
2315                         .maxpacket      = INT_FIFO_SIZE,
2316                 },
2317                 .dev            = &memory,
2318                 .fifo_size      = INT_FIFO_SIZE,
2319                 .bEndpointAddress = USB_DIR_IN | 10,
2320                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2321                 .reg_udccs      = &UDCCS10,
2322                 .reg_uddr       = &UDDR10,
2323         },
2324
2325         /* third group of endpoints */
2326         .ep[11] = {
2327                 .ep = {
2328                         .name           = "ep11in-bulk",
2329                         .ops            = &pxa2xx_ep_ops,
2330                         .maxpacket      = BULK_FIFO_SIZE,
2331                 },
2332                 .dev            = &memory,
2333                 .fifo_size      = BULK_FIFO_SIZE,
2334                 .bEndpointAddress = USB_DIR_IN | 11,
2335                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2336                 .reg_udccs      = &UDCCS11,
2337                 .reg_uddr       = &UDDR11,
2338                 drcmr (35)
2339         },
2340         .ep[12] = {
2341                 .ep = {
2342                         .name           = "ep12out-bulk",
2343                         .ops            = &pxa2xx_ep_ops,
2344                         .maxpacket      = BULK_FIFO_SIZE,
2345                 },
2346                 .dev            = &memory,
2347                 .fifo_size      = BULK_FIFO_SIZE,
2348                 .bEndpointAddress = 12,
2349                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
2350                 .reg_udccs      = &UDCCS12,
2351                 .reg_ubcr       = &UBCR12,
2352                 .reg_uddr       = &UDDR12,
2353                 drcmr (36)
2354         },
2355         .ep[13] = {
2356                 .ep = {
2357                         .name           = "ep13in-iso",
2358                         .ops            = &pxa2xx_ep_ops,
2359                         .maxpacket      = ISO_FIFO_SIZE,
2360                 },
2361                 .dev            = &memory,
2362                 .fifo_size      = ISO_FIFO_SIZE,
2363                 .bEndpointAddress = USB_DIR_IN | 13,
2364                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2365                 .reg_udccs      = &UDCCS13,
2366                 .reg_uddr       = &UDDR13,
2367                 drcmr (37)
2368         },
2369         .ep[14] = {
2370                 .ep = {
2371                         .name           = "ep14out-iso",
2372                         .ops            = &pxa2xx_ep_ops,
2373                         .maxpacket      = ISO_FIFO_SIZE,
2374                 },
2375                 .dev            = &memory,
2376                 .fifo_size      = ISO_FIFO_SIZE,
2377                 .bEndpointAddress = 14,
2378                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
2379                 .reg_udccs      = &UDCCS14,
2380                 .reg_ubcr       = &UBCR14,
2381                 .reg_uddr       = &UDDR14,
2382                 drcmr (38)
2383         },
2384         .ep[15] = {
2385                 .ep = {
2386                         .name           = "ep15in-int",
2387                         .ops            = &pxa2xx_ep_ops,
2388                         .maxpacket      = INT_FIFO_SIZE,
2389                 },
2390                 .dev            = &memory,
2391                 .fifo_size      = INT_FIFO_SIZE,
2392                 .bEndpointAddress = USB_DIR_IN | 15,
2393                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
2394                 .reg_udccs      = &UDCCS15,
2395                 .reg_uddr       = &UDDR15,
2396         },
2397 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2398 };
2399
2400 #define CP15R0_VENDOR_MASK      0xffffe000
2401
2402 #if     defined(CONFIG_ARCH_PXA)
2403 #define CP15R0_XSCALE_VALUE     0x69052000      /* intel/arm/xscale */
2404
2405 #elif   defined(CONFIG_ARCH_IXP4XX)
2406 #define CP15R0_XSCALE_VALUE     0x69054000      /* intel/arm/ixp4xx */
2407
2408 #endif
2409
2410 #define CP15R0_PROD_MASK        0x000003f0
2411 #define PXA25x                  0x00000100      /* and PXA26x */
2412 #define PXA210                  0x00000120
2413
2414 #define CP15R0_REV_MASK         0x0000000f
2415
2416 #define CP15R0_PRODREV_MASK     (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2417
2418 #define PXA255_A0               0x00000106      /* or PXA260_B1 */
2419 #define PXA250_C0               0x00000105      /* or PXA26x_B0 */
2420 #define PXA250_B2               0x00000104
2421 #define PXA250_B1               0x00000103      /* or PXA260_A0 */
2422 #define PXA250_B0               0x00000102
2423 #define PXA250_A1               0x00000101
2424 #define PXA250_A0               0x00000100
2425
2426 #define PXA210_C0               0x00000125
2427 #define PXA210_B2               0x00000124
2428 #define PXA210_B1               0x00000123
2429 #define PXA210_B0               0x00000122
2430 #define IXP425_A0               0x000001c1
2431
2432 /*
2433  *      probe - binds to the platform device
2434  */
2435 static int __init pxa2xx_udc_probe(struct device *_dev)
2436 {
2437         struct pxa2xx_udc *dev = &memory;
2438         int retval, out_dma = 1;
2439         u32 chiprev;
2440
2441         /* insist on Intel/ARM/XScale */
2442         asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2443         if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2444                 printk(KERN_ERR "%s: not XScale!\n", driver_name);
2445                 return -ENODEV;
2446         }
2447
2448         /* trigger chiprev-specific logic */
2449         switch (chiprev & CP15R0_PRODREV_MASK) {
2450 #if     defined(CONFIG_ARCH_PXA)
2451         case PXA255_A0:
2452                 dev->has_cfr = 1;
2453                 break;
2454         case PXA250_A0:
2455         case PXA250_A1:
2456                 /* A0/A1 "not released"; ep 13, 15 unusable */
2457                 /* fall through */
2458         case PXA250_B2: case PXA210_B2:
2459         case PXA250_B1: case PXA210_B1:
2460         case PXA250_B0: case PXA210_B0:
2461                 out_dma = 0;
2462                 /* fall through */
2463         case PXA250_C0: case PXA210_C0:
2464                 break;
2465 #elif   defined(CONFIG_ARCH_IXP4XX)
2466         case IXP425_A0:
2467                 out_dma = 0;
2468                 break;
2469 #endif
2470         default:
2471                 out_dma = 0;
2472                 printk(KERN_ERR "%s: unrecognized processor: %08x\n",
2473                         driver_name, chiprev);
2474                 /* iop3xx, ixp4xx, ... */
2475                 return -ENODEV;
2476         }
2477
2478         pr_debug("%s: IRQ %d%s%s%s\n", driver_name, IRQ_USB,
2479                 dev->has_cfr ? "" : " (!cfr)",
2480                 out_dma ? "" : " (broken dma-out)",
2481                 SIZE_STR DMASTR
2482                 );
2483
2484 #ifdef  USE_DMA
2485 #ifndef USE_OUT_DMA
2486         out_dma = 0;
2487 #endif
2488         /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2489         if (!out_dma) {
2490                 DMSG("disabled OUT dma\n");
2491                 dev->ep[ 2].reg_drcmr = dev->ep[ 4].reg_drcmr = 0;
2492                 dev->ep[ 7].reg_drcmr = dev->ep[ 9].reg_drcmr = 0;
2493                 dev->ep[12].reg_drcmr = dev->ep[14].reg_drcmr = 0;
2494         }
2495 #endif
2496
2497         /* other non-static parts of init */
2498         dev->dev = _dev;
2499         dev->mach = _dev->platform_data;
2500
2501         init_timer(&dev->timer);
2502         dev->timer.function = udc_watchdog;
2503         dev->timer.data = (unsigned long) dev;
2504
2505         device_initialize(&dev->gadget.dev);
2506         dev->gadget.dev.parent = _dev;
2507         dev->gadget.dev.dma_mask = _dev->dma_mask;
2508
2509         the_controller = dev;
2510         dev_set_drvdata(_dev, dev);
2511
2512         udc_disable(dev);
2513         udc_reinit(dev);
2514
2515         dev->vbus = is_vbus_present();
2516
2517         /* irq setup after old hardware state is cleaned up */
2518         retval = request_irq(IRQ_USB, pxa2xx_udc_irq,
2519                         SA_INTERRUPT, driver_name, dev);
2520         if (retval != 0) {
2521                 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2522                         driver_name, IRQ_USB, retval);
2523                 return -EBUSY;
2524         }
2525         dev->got_irq = 1;
2526
2527 #ifdef CONFIG_ARCH_LUBBOCK
2528         if (machine_is_lubbock()) {
2529                 retval = request_irq(LUBBOCK_USB_DISC_IRQ,
2530                                 lubbock_vbus_irq,
2531                                 SA_INTERRUPT | SA_SAMPLE_RANDOM,
2532                                 driver_name, dev);
2533                 if (retval != 0) {
2534                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2535                                 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2536 lubbock_fail0:
2537                         free_irq(IRQ_USB, dev);
2538                         return -EBUSY;
2539                 }
2540                 retval = request_irq(LUBBOCK_USB_IRQ,
2541                                 lubbock_vbus_irq,
2542                                 SA_INTERRUPT | SA_SAMPLE_RANDOM,
2543                                 driver_name, dev);
2544                 if (retval != 0) {
2545                         printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2546                                 driver_name, LUBBOCK_USB_IRQ, retval);
2547                         free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2548                         goto lubbock_fail0;
2549                 }
2550 #ifdef DEBUG
2551                 /* with U-Boot (but not BLOB), hex is off by default */
2552                 HEX_DISPLAY(dev->stats.irqs);
2553                 LUB_DISC_BLNK_LED &= 0xff;
2554 #endif
2555         }
2556 #endif
2557         create_proc_files();
2558
2559         return 0;
2560 }
2561
2562 static void pxa2xx_udc_shutdown(struct device *_dev)
2563 {
2564         pullup_off();
2565 }
2566
2567 static int __exit pxa2xx_udc_remove(struct device *_dev)
2568 {
2569         struct pxa2xx_udc *dev = dev_get_drvdata(_dev);
2570
2571         udc_disable(dev);
2572         remove_proc_files();
2573         usb_gadget_unregister_driver(dev->driver);
2574
2575         if (dev->got_irq) {
2576                 free_irq(IRQ_USB, dev);
2577                 dev->got_irq = 0;
2578         }
2579         if (machine_is_lubbock()) {
2580                 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2581                 free_irq(LUBBOCK_USB_IRQ, dev);
2582         }
2583         dev_set_drvdata(_dev, NULL);
2584         the_controller = NULL;
2585         return 0;
2586 }
2587
2588 /*-------------------------------------------------------------------------*/
2589
2590 #ifdef  CONFIG_PM
2591
2592 /* USB suspend (controlled by the host) and system suspend (controlled
2593  * by the PXA) don't necessarily work well together.  If USB is active,
2594  * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2595  * mode, or any deeper PM saving state.
2596  *
2597  * For now, we punt and forcibly disconnect from the USB host when PXA
2598  * enters any suspend state.  While we're disconnected, we always disable
2599  * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2600  * Boards without software pullup control shouldn't use those states.
2601  * VBUS IRQs should probably be ignored so that the PXA device just acts
2602  * "dead" to USB hosts until system resume.
2603  */
2604 static int pxa2xx_udc_suspend(struct device *dev, pm_message_t state)
2605 {
2606         struct pxa2xx_udc       *udc = dev_get_drvdata(dev);
2607
2608         if (!udc->mach->udc_command)
2609                 WARN("USB host won't detect disconnect!\n");
2610         pullup(udc, 0);
2611
2612         return 0;
2613 }
2614
2615 static int pxa2xx_udc_resume(struct device *dev)
2616 {
2617         struct pxa2xx_udc       *udc = dev_get_drvdata(dev);
2618
2619         pullup(udc, 1);
2620
2621         return 0;
2622 }
2623
2624 #else
2625 #define pxa2xx_udc_suspend      NULL
2626 #define pxa2xx_udc_resume       NULL
2627 #endif
2628
2629 /*-------------------------------------------------------------------------*/
2630
2631 static struct device_driver udc_driver = {
2632         .name           = "pxa2xx-udc",
2633         .owner          = THIS_MODULE,
2634         .bus            = &platform_bus_type,
2635         .probe          = pxa2xx_udc_probe,
2636         .shutdown       = pxa2xx_udc_shutdown,
2637         .remove         = __exit_p(pxa2xx_udc_remove),
2638         .suspend        = pxa2xx_udc_suspend,
2639         .resume         = pxa2xx_udc_resume,
2640 };
2641
2642 static int __init udc_init(void)
2643 {
2644         printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2645         return driver_register(&udc_driver);
2646 }
2647 module_init(udc_init);
2648
2649 static void __exit udc_exit(void)
2650 {
2651         driver_unregister(&udc_driver);
2652 }
2653 module_exit(udc_exit);
2654
2655 MODULE_DESCRIPTION(DRIVER_DESC);
2656 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2657 MODULE_LICENSE("GPL");
2658