Merge branch 'linux-2.6'
[linux-2.6] / drivers / ide / pci / scc_pata.c
1 /*
2  * Support for IDE interfaces on Celleb platform
3  *
4  * (C) Copyright 2006 TOSHIBA CORPORATION
5  *
6  * This code is based on drivers/ide/pci/siimage.c:
7  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
8  * Copyright (C) 2003           Red Hat <alan@redhat.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License along
21  * with this program; if not, write to the Free Software Foundation, Inc.,
22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23  */
24
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/hdreg.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
32
33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA            0x01b4
34
35 #define SCC_PATA_NAME           "scc IDE"
36
37 #define TDVHSEL_MASTER          0x00000001
38 #define TDVHSEL_SLAVE           0x00000004
39
40 #define MODE_JCUSFEN            0x00000080
41
42 #define CCKCTRL_ATARESET        0x00040000
43 #define CCKCTRL_BUFCNT          0x00020000
44 #define CCKCTRL_CRST            0x00010000
45 #define CCKCTRL_OCLKEN          0x00000100
46 #define CCKCTRL_ATACLKOEN       0x00000002
47 #define CCKCTRL_LCLKEN          0x00000001
48
49 #define QCHCD_IOS_SS            0x00000001
50
51 #define QCHSD_STPDIAG           0x00020000
52
53 #define INTMASK_MSK             0xD1000012
54 #define INTSTS_SERROR           0x80000000
55 #define INTSTS_PRERR            0x40000000
56 #define INTSTS_RERR             0x10000000
57 #define INTSTS_ICERR            0x01000000
58 #define INTSTS_BMSINT           0x00000010
59 #define INTSTS_BMHE             0x00000008
60 #define INTSTS_IOIRQS           0x00000004
61 #define INTSTS_INTRQ            0x00000002
62 #define INTSTS_ACTEINT          0x00000001
63
64 #define ECMODE_VALUE 0x01
65
66 static struct scc_ports {
67         unsigned long ctl, dma;
68         unsigned char hwif_id;  /* for removing hwif from system */
69 } scc_ports[MAX_HWIFS];
70
71 /* PIO transfer mode  table */
72 /* JCHST */
73 static unsigned long JCHSTtbl[2][7] = {
74         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},   /* 100MHz */
75         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}    /* 133MHz */
76 };
77
78 /* JCHHT */
79 static unsigned long JCHHTtbl[2][7] = {
80         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},   /* 100MHz */
81         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}    /* 133MHz */
82 };
83
84 /* JCHCT */
85 static unsigned long JCHCTtbl[2][7] = {
86         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},   /* 100MHz */
87         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}    /* 133MHz */
88 };
89
90
91 /* DMA transfer mode  table */
92 /* JCHDCTM/JCHDCTS */
93 static unsigned long JCHDCTxtbl[2][7] = {
94         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},   /* 100MHz */
95         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}    /* 133MHz */
96 };
97
98 /* JCSTWTM/JCSTWTS  */
99 static unsigned long JCSTWTxtbl[2][7] = {
100         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},   /* 100MHz */
101         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
102 };
103
104 /* JCTSS */
105 static unsigned long JCTSStbl[2][7] = {
106         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},   /* 100MHz */
107         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}    /* 133MHz */
108 };
109
110 /* JCENVT */
111 static unsigned long JCENVTtbl[2][7] = {
112         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},   /* 100MHz */
113         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
114 };
115
116 /* JCACTSELS/JCACTSELM */
117 static unsigned long JCACTSELtbl[2][7] = {
118         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},   /* 100MHz */
119         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}    /* 133MHz */
120 };
121
122
123 static u8 scc_ide_inb(unsigned long port)
124 {
125         u32 data = in_be32((void*)port);
126         return (u8)data;
127 }
128
129 static u16 scc_ide_inw(unsigned long port)
130 {
131         u32 data = in_be32((void*)port);
132         return (u16)data;
133 }
134
135 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
136 {
137         u16 *ptr = (u16 *)addr;
138         while (count--) {
139                 *ptr++ = le16_to_cpu(in_be32((void*)port));
140         }
141 }
142
143 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
144 {
145         u16 *ptr = (u16 *)addr;
146         while (count--) {
147                 *ptr++ = le16_to_cpu(in_be32((void*)port));
148                 *ptr++ = le16_to_cpu(in_be32((void*)port));
149         }
150 }
151
152 static void scc_ide_outb(u8 addr, unsigned long port)
153 {
154         out_be32((void*)port, addr);
155 }
156
157 static void scc_ide_outw(u16 addr, unsigned long port)
158 {
159         out_be32((void*)port, addr);
160 }
161
162 static void
163 scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
164 {
165         ide_hwif_t *hwif = HWIF(drive);
166
167         out_be32((void*)port, addr);
168         __asm__ __volatile__("eieio":::"memory");
169         in_be32((void*)(hwif->dma_base + 0x01c));
170         __asm__ __volatile__("eieio":::"memory");
171 }
172
173 static void
174 scc_ide_outsw(unsigned long port, void *addr, u32 count)
175 {
176         u16 *ptr = (u16 *)addr;
177         while (count--) {
178                 out_be32((void*)port, cpu_to_le16(*ptr++));
179         }
180 }
181
182 static void
183 scc_ide_outsl(unsigned long port, void *addr, u32 count)
184 {
185         u16 *ptr = (u16 *)addr;
186         while (count--) {
187                 out_be32((void*)port, cpu_to_le16(*ptr++));
188                 out_be32((void*)port, cpu_to_le16(*ptr++));
189         }
190 }
191
192 /**
193  *      scc_tuneproc    -       tune a drive PIO mode
194  *      @drive: drive to tune
195  *      @mode_wanted: the target operating mode
196  *
197  *      Load the timing settings for this device mode into the
198  *      controller.
199  */
200
201 static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted)
202 {
203         ide_hwif_t *hwif = HWIF(drive);
204         struct scc_ports *ports = ide_get_hwifdata(hwif);
205         unsigned long ctl_base = ports->ctl;
206         unsigned long cckctrl_port = ctl_base + 0xff0;
207         unsigned long piosht_port = ctl_base + 0x000;
208         unsigned long pioct_port = ctl_base + 0x004;
209         unsigned long reg;
210         unsigned char speed = XFER_PIO_0;
211         int offset;
212
213         mode_wanted = ide_get_best_pio_mode(drive, mode_wanted, 4, NULL);
214         switch (mode_wanted) {
215         case 4:
216                 speed = XFER_PIO_4;
217                 break;
218         case 3:
219                 speed = XFER_PIO_3;
220                 break;
221         case 2:
222                 speed = XFER_PIO_2;
223                 break;
224         case 1:
225                 speed = XFER_PIO_1;
226                 break;
227         case 0:
228         default:
229                 speed = XFER_PIO_0;
230                 break;
231         }
232
233         reg = in_be32((void __iomem *)cckctrl_port);
234         if (reg & CCKCTRL_ATACLKOEN) {
235                 offset = 1; /* 133MHz */
236         } else {
237                 offset = 0; /* 100MHz */
238         }
239         reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted];
240         out_be32((void __iomem *)piosht_port, reg);
241         reg = JCHCTtbl[offset][mode_wanted];
242         out_be32((void __iomem *)pioct_port, reg);
243
244         ide_config_drive_speed(drive, speed);
245 }
246
247 /**
248  *      scc_tune_chipset        -       tune a drive DMA mode
249  *      @drive: Drive to set up
250  *      @xferspeed: speed we want to achieve
251  *
252  *      Load the timing settings for this device mode into the
253  *      controller.
254  */
255
256 static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
257 {
258         ide_hwif_t *hwif = HWIF(drive);
259         u8 speed = ide_rate_filter(drive, xferspeed);
260         struct scc_ports *ports = ide_get_hwifdata(hwif);
261         unsigned long ctl_base = ports->ctl;
262         unsigned long cckctrl_port = ctl_base + 0xff0;
263         unsigned long mdmact_port = ctl_base + 0x008;
264         unsigned long mcrcst_port = ctl_base + 0x00c;
265         unsigned long sdmact_port = ctl_base + 0x010;
266         unsigned long scrcst_port = ctl_base + 0x014;
267         unsigned long udenvt_port = ctl_base + 0x018;
268         unsigned long tdvhsel_port   = ctl_base + 0x020;
269         int is_slave = (&hwif->drives[1] == drive);
270         int offset, idx;
271         unsigned long reg;
272         unsigned long jcactsel;
273
274         reg = in_be32((void __iomem *)cckctrl_port);
275         if (reg & CCKCTRL_ATACLKOEN) {
276                 offset = 1; /* 133MHz */
277         } else {
278                 offset = 0; /* 100MHz */
279         }
280
281         switch (speed) {
282         case XFER_UDMA_6:
283                 idx = 6;
284                 break;
285         case XFER_UDMA_5:
286                 idx = 5;
287                 break;
288         case XFER_UDMA_4:
289                 idx = 4;
290                 break;
291         case XFER_UDMA_3:
292                 idx = 3;
293                 break;
294         case XFER_UDMA_2:
295                 idx = 2;
296                 break;
297         case XFER_UDMA_1:
298                 idx = 1;
299                 break;
300         case XFER_UDMA_0:
301                 idx = 0;
302                 break;
303         default:
304                 return 1;
305         }
306
307         jcactsel = JCACTSELtbl[offset][idx];
308         if (is_slave) {
309                 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
310                 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
311                 jcactsel = jcactsel << 2;
312                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
313         } else {
314                 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
315                 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
316                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
317         }
318         reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
319         out_be32((void __iomem *)udenvt_port, reg);
320
321         return ide_config_drive_speed(drive, speed);
322 }
323
324 /**
325  *      scc_config_chipset_for_dma      -       configure for DMA
326  *      @drive: drive to configure
327  *
328  *      Called by scc_config_drive_for_dma().
329  */
330
331 static int scc_config_chipset_for_dma(ide_drive_t *drive)
332 {
333         u8 speed = ide_max_dma_mode(drive);
334
335         if (!speed)
336                 return 0;
337
338         if (scc_tune_chipset(drive, speed))
339                 return 0;
340
341         return ide_dma_enable(drive);
342 }
343
344 /**
345  *      scc_configure_drive_for_dma     -       set up for DMA transfers
346  *      @drive: drive we are going to set up
347  *
348  *      Set up the drive for DMA, tune the controller and drive as
349  *      required.
350  *      If the drive isn't suitable for DMA or we hit other problems
351  *      then we will drop down to PIO and set up PIO appropriately.
352  *      (return 1)
353  */
354
355 static int scc_config_drive_for_dma(ide_drive_t *drive)
356 {
357         if (ide_use_dma(drive) && scc_config_chipset_for_dma(drive))
358                 return 0;
359
360         if (ide_use_fast_pio(drive))
361                 scc_tuneproc(drive, 4);
362
363         return -1;
364 }
365
366 /**
367  *      scc_ide_dma_setup       -       begin a DMA phase
368  *      @drive: target device
369  *
370  *      Build an IDE DMA PRD (IDE speak for scatter gather table)
371  *      and then set up the DMA transfer registers.
372  *
373  *      Returns 0 on success. If a PIO fallback is required then 1
374  *      is returned.
375  */
376
377 static int scc_dma_setup(ide_drive_t *drive)
378 {
379         ide_hwif_t *hwif = drive->hwif;
380         struct request *rq = HWGROUP(drive)->rq;
381         unsigned int reading;
382         u8 dma_stat;
383
384         if (rq_data_dir(rq))
385                 reading = 0;
386         else
387                 reading = 1 << 3;
388
389         /* fall back to pio! */
390         if (!ide_build_dmatable(drive, rq)) {
391                 ide_map_sg(drive, rq);
392                 return 1;
393         }
394
395         /* PRD table */
396         out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
397
398         /* specify r/w */
399         out_be32((void __iomem *)hwif->dma_command, reading);
400
401         /* read dma_status for INTR & ERROR flags */
402         dma_stat = in_be32((void __iomem *)hwif->dma_status);
403
404         /* clear INTR & ERROR flags */
405         out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
406         drive->waiting_for_dma = 1;
407         return 0;
408 }
409
410
411 /**
412  *      scc_ide_dma_end -       Stop DMA
413  *      @drive: IDE drive
414  *
415  *      Check and clear INT Status register.
416  *      Then call __ide_dma_end().
417  */
418
419 static int scc_ide_dma_end(ide_drive_t * drive)
420 {
421         ide_hwif_t *hwif = HWIF(drive);
422         unsigned long intsts_port = hwif->dma_base + 0x014;
423         u32 reg;
424
425         while (1) {
426                 reg = in_be32((void __iomem *)intsts_port);
427
428                 if (reg & INTSTS_SERROR) {
429                         printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
430                         out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
431
432                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
433                         continue;
434                 }
435
436                 if (reg & INTSTS_PRERR) {
437                         u32 maea0, maec0;
438                         unsigned long ctl_base = hwif->config_data;
439
440                         maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
441                         maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
442
443                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
444
445                         out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
446
447                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
448                         continue;
449                 }
450
451                 if (reg & INTSTS_RERR) {
452                         printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
453                         out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
454
455                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
456                         continue;
457                 }
458
459                 if (reg & INTSTS_ICERR) {
460                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
461
462                         printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
463                         out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
464                         continue;
465                 }
466
467                 if (reg & INTSTS_BMSINT) {
468                         printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
469                         out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
470
471                         ide_do_reset(drive);
472                         continue;
473                 }
474
475                 if (reg & INTSTS_BMHE) {
476                         out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
477                         continue;
478                 }
479
480                 if (reg & INTSTS_ACTEINT) {
481                         out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
482                         continue;
483                 }
484
485                 if (reg & INTSTS_IOIRQS) {
486                         out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
487                         continue;
488                 }
489                 break;
490         }
491
492         return __ide_dma_end(drive);
493 }
494
495 /* returns 1 if dma irq issued, 0 otherwise */
496 static int scc_dma_test_irq(ide_drive_t *drive)
497 {
498         ide_hwif_t *hwif        = HWIF(drive);
499         u8 dma_stat             = hwif->INB(hwif->dma_status);
500
501         /* return 1 if INTR asserted */
502         if ((dma_stat & 4) == 4)
503                 return 1;
504
505         /* Workaround for PTERADD: emulate DMA_INTR when
506          * - IDE_STATUS[ERR] = 1
507          * - INT_STATUS[INTRQ] = 1
508          * - DMA_STATUS[IORACTA] = 1
509          */
510         if (in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT &&
511             in_be32((void __iomem *)(hwif->dma_base + 0x014)) & INTSTS_INTRQ &&
512                 dma_stat & 1)
513                 return 1;
514
515         if (!drive->waiting_for_dma)
516                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
517                         drive->name, __FUNCTION__);
518         return 0;
519 }
520
521 /**
522  *      setup_mmio_scc  -       map CTRL/BMID region
523  *      @dev: PCI device we are configuring
524  *      @name: device name
525  *
526  */
527
528 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
529 {
530         unsigned long ctl_base = pci_resource_start(dev, 0);
531         unsigned long dma_base = pci_resource_start(dev, 1);
532         unsigned long ctl_size = pci_resource_len(dev, 0);
533         unsigned long dma_size = pci_resource_len(dev, 1);
534         void *ctl_addr;
535         void *dma_addr;
536         int i;
537
538         for (i = 0; i < MAX_HWIFS; i++) {
539                 if (scc_ports[i].ctl == 0)
540                         break;
541         }
542         if (i >= MAX_HWIFS)
543                 return -ENOMEM;
544
545         if (!request_mem_region(ctl_base, ctl_size, name)) {
546                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
547                 goto fail_0;
548         }
549
550         if (!request_mem_region(dma_base, dma_size, name)) {
551                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
552                 goto fail_1;
553         }
554
555         if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
556                 goto fail_2;
557
558         if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
559                 goto fail_3;
560
561         pci_set_master(dev);
562         scc_ports[i].ctl = (unsigned long)ctl_addr;
563         scc_ports[i].dma = (unsigned long)dma_addr;
564         pci_set_drvdata(dev, (void *) &scc_ports[i]);
565
566         return 1;
567
568  fail_3:
569         iounmap(ctl_addr);
570  fail_2:
571         release_mem_region(dma_base, dma_size);
572  fail_1:
573         release_mem_region(ctl_base, ctl_size);
574  fail_0:
575         return -ENOMEM;
576 }
577
578 /**
579  *      init_setup_scc  -       set up an SCC PATA Controller
580  *      @dev: PCI device
581  *      @d: IDE PCI device
582  *
583  *      Perform the initial set up for this device.
584  */
585
586 static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
587 {
588         unsigned long ctl_base;
589         unsigned long dma_base;
590         unsigned long cckctrl_port;
591         unsigned long intmask_port;
592         unsigned long mode_port;
593         unsigned long ecmode_port;
594         unsigned long dma_status_port;
595         u32 reg = 0;
596         struct scc_ports *ports;
597         int rc;
598
599         rc = setup_mmio_scc(dev, d->name);
600         if (rc < 0) {
601                 return rc;
602         }
603
604         ports = pci_get_drvdata(dev);
605         ctl_base = ports->ctl;
606         dma_base = ports->dma;
607         cckctrl_port = ctl_base + 0xff0;
608         intmask_port = dma_base + 0x010;
609         mode_port = ctl_base + 0x024;
610         ecmode_port = ctl_base + 0xf00;
611         dma_status_port = dma_base + 0x004;
612
613         /* controller initialization */
614         reg = 0;
615         out_be32((void*)cckctrl_port, reg);
616         reg |= CCKCTRL_ATACLKOEN;
617         out_be32((void*)cckctrl_port, reg);
618         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
619         out_be32((void*)cckctrl_port, reg);
620         reg |= CCKCTRL_CRST;
621         out_be32((void*)cckctrl_port, reg);
622
623         for (;;) {
624                 reg = in_be32((void*)cckctrl_port);
625                 if (reg & CCKCTRL_CRST)
626                         break;
627                 udelay(5000);
628         }
629
630         reg |= CCKCTRL_ATARESET;
631         out_be32((void*)cckctrl_port, reg);
632
633         out_be32((void*)ecmode_port, ECMODE_VALUE);
634         out_be32((void*)mode_port, MODE_JCUSFEN);
635         out_be32((void*)intmask_port, INTMASK_MSK);
636
637         return ide_setup_pci_device(dev, d);
638 }
639
640 /**
641  *      init_mmio_iops_scc      -       set up the iops for MMIO
642  *      @hwif: interface to set up
643  *
644  */
645
646 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
647 {
648         struct pci_dev *dev = hwif->pci_dev;
649         struct scc_ports *ports = pci_get_drvdata(dev);
650         unsigned long dma_base = ports->dma;
651
652         ide_set_hwifdata(hwif, ports);
653
654         hwif->INB = scc_ide_inb;
655         hwif->INW = scc_ide_inw;
656         hwif->INSW = scc_ide_insw;
657         hwif->INSL = scc_ide_insl;
658         hwif->OUTB = scc_ide_outb;
659         hwif->OUTBSYNC = scc_ide_outbsync;
660         hwif->OUTW = scc_ide_outw;
661         hwif->OUTSW = scc_ide_outsw;
662         hwif->OUTSL = scc_ide_outsl;
663
664         hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
665         hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
666         hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
667         hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
668         hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
669         hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
670         hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
671         hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
672         hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
673
674         hwif->irq = hwif->pci_dev->irq;
675         hwif->dma_base = dma_base;
676         hwif->config_data = ports->ctl;
677         hwif->mmio = 1;
678 }
679
680 /**
681  *      init_iops_scc   -       set up iops
682  *      @hwif: interface to set up
683  *
684  *      Do the basic setup for the SCC hardware interface
685  *      and then do the MMIO setup.
686  */
687
688 static void __devinit init_iops_scc(ide_hwif_t *hwif)
689 {
690         struct pci_dev *dev =  hwif->pci_dev;
691         hwif->hwif_data = NULL;
692         if (pci_get_drvdata(dev) == NULL)
693                 return;
694         init_mmio_iops_scc(hwif);
695 }
696
697 /**
698  *      init_hwif_scc   -       set up hwif
699  *      @hwif: interface to set up
700  *
701  *      We do the basic set up of the interface structure. The SCC
702  *      requires several custom handlers so we override the default
703  *      ide DMA handlers appropriately.
704  */
705
706 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
707 {
708         struct scc_ports *ports = ide_get_hwifdata(hwif);
709
710         ports->hwif_id = hwif->index;
711
712         hwif->dma_command = hwif->dma_base;
713         hwif->dma_status = hwif->dma_base + 0x04;
714         hwif->dma_prdtable = hwif->dma_base + 0x08;
715
716         /* PTERADD */
717         out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
718
719         hwif->dma_setup = scc_dma_setup;
720         hwif->ide_dma_end = scc_ide_dma_end;
721         hwif->speedproc = scc_tune_chipset;
722         hwif->tuneproc = scc_tuneproc;
723         hwif->ide_dma_check = scc_config_drive_for_dma;
724         hwif->ide_dma_test_irq = scc_dma_test_irq;
725
726         hwif->drives[0].autotune = IDE_TUNE_AUTO;
727         hwif->drives[1].autotune = IDE_TUNE_AUTO;
728
729         if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
730                 hwif->ultra_mask = 0x7f; /* 133MHz */
731         } else {
732                 hwif->ultra_mask = 0x3f; /* 100MHz */
733         }
734         hwif->mwdma_mask = 0x00;
735         hwif->swdma_mask = 0x00;
736         hwif->atapi_dma = 1;
737
738         /* we support 80c cable only. */
739         hwif->udma_four = 1;
740
741         hwif->autodma = 0;
742         if (!noautodma)
743                 hwif->autodma = 1;
744         hwif->drives[0].autodma = hwif->autodma;
745         hwif->drives[1].autodma = hwif->autodma;
746 }
747
748 #define DECLARE_SCC_DEV(name_str)                       \
749   {                                                     \
750       .name             = name_str,                     \
751       .init_setup       = init_setup_scc,               \
752       .init_iops        = init_iops_scc,                \
753       .init_hwif        = init_hwif_scc,                \
754       .channels = 1,                                    \
755       .autodma  = AUTODMA,                              \
756       .bootable = ON_BOARD,                             \
757   }
758
759 static ide_pci_device_t scc_chipsets[] __devinitdata = {
760         /* 0 */ DECLARE_SCC_DEV("sccIDE"),
761 };
762
763 /**
764  *      scc_init_one    -       pci layer discovery entry
765  *      @dev: PCI device
766  *      @id: ident table entry
767  *
768  *      Called by the PCI code when it finds an SCC PATA controller.
769  *      We then use the IDE PCI generic helper to do most of the work.
770  */
771
772 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
773 {
774         ide_pci_device_t *d = &scc_chipsets[id->driver_data];
775         return d->init_setup(dev, d);
776 }
777
778 /**
779  *      scc_remove      -       pci layer remove entry
780  *      @dev: PCI device
781  *
782  *      Called by the PCI code when it removes an SCC PATA controller.
783  */
784
785 static void __devexit scc_remove(struct pci_dev *dev)
786 {
787         struct scc_ports *ports = pci_get_drvdata(dev);
788         ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
789         unsigned long ctl_base = pci_resource_start(dev, 0);
790         unsigned long dma_base = pci_resource_start(dev, 1);
791         unsigned long ctl_size = pci_resource_len(dev, 0);
792         unsigned long dma_size = pci_resource_len(dev, 1);
793
794         if (hwif->dmatable_cpu) {
795                 pci_free_consistent(hwif->pci_dev,
796                                     PRD_ENTRIES * PRD_BYTES,
797                                     hwif->dmatable_cpu,
798                                     hwif->dmatable_dma);
799                 hwif->dmatable_cpu = NULL;
800         }
801
802         ide_unregister(hwif->index);
803
804         hwif->chipset = ide_unknown;
805         iounmap((void*)ports->dma);
806         iounmap((void*)ports->ctl);
807         release_mem_region(dma_base, dma_size);
808         release_mem_region(ctl_base, ctl_size);
809         memset(ports, 0, sizeof(*ports));
810 }
811
812 static struct pci_device_id scc_pci_tbl[] = {
813         { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
814         { 0, },
815 };
816 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
817
818 static struct pci_driver driver = {
819         .name = "SCC IDE",
820         .id_table = scc_pci_tbl,
821         .probe = scc_init_one,
822         .remove = scc_remove,
823 };
824
825 static int scc_ide_init(void)
826 {
827         return ide_pci_register_driver(&driver);
828 }
829
830 module_init(scc_ide_init);
831 /* -- No exit code?
832 static void scc_ide_exit(void)
833 {
834         ide_pci_unregister_driver(&driver);
835 }
836 module_exit(scc_ide_exit);
837  */
838
839
840 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
841 MODULE_LICENSE("GPL");