[PATCH] powerpc: trivial: modify comments to refer to new location of files
[linux-2.6] / arch / ppc / platforms / sbc82xx.c
1 /*
2  * SBC82XX platform support
3  *
4  * Author: Guy Streeter <streeter@redhat.com>
5  *
6  * Derived from: est8260_setup.c by Allen Curtis, ONZ
7  *
8  * Copyright 2004 Red Hat, Inc.
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  */
15
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22
23 #include <asm/mpc8260.h>
24 #include <asm/machdep.h>
25 #include <asm/io.h>
26 #include <asm/todc.h>
27 #include <asm/immap_cpm2.h>
28 #include <asm/pci.h>
29
30 static void (*callback_init_IRQ)(void);
31
32 extern unsigned char __res[sizeof(bd_t)];
33
34 extern void (*late_time_init)(void);
35
36 #ifdef CONFIG_GEN_RTC
37 TODC_ALLOC();
38
39 /*
40  * Timer init happens before mem_init but after paging init, so we cannot
41  * directly use ioremap() at that time.
42  * late_time_init() is call after paging init.
43  */
44
45 static void sbc82xx_time_init(void)
46 {
47         volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
48
49         /* Set up CS11 for RTC chip */
50         mc->memc_br11=0;
51         mc->memc_or11=0xffff0836;
52         mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801;
53
54         TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
55
56         todc_info->nvram_data =
57                 (unsigned int)ioremap(todc_info->nvram_data, 0x2000);
58         BUG_ON(!todc_info->nvram_data);
59         ppc_md.get_rtc_time     = todc_get_rtc_time;
60         ppc_md.set_rtc_time     = todc_set_rtc_time;
61         ppc_md.nvram_read_val   = todc_direct_read_val;
62         ppc_md.nvram_write_val  = todc_direct_write_val;
63         todc_time_init();
64 }
65 #endif /* CONFIG_GEN_RTC */
66
67 static volatile char *sbc82xx_i8259_map;
68 static char sbc82xx_i8259_mask = 0xff;
69 static DEFINE_SPINLOCK(sbc82xx_i8259_lock);
70
71 static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr)
72 {
73         unsigned long flags;
74
75         irq_nr -= NR_SIU_INTS;
76
77         spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
78         sbc82xx_i8259_mask |= 1 << irq_nr;
79         (void) sbc82xx_i8259_map[1];    /* Dummy read */
80         sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
81         sbc82xx_i8259_map[0] = 0x20;    /* OCW2: Non-specific EOI */
82         spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
83 }
84
85 static void sbc82xx_i8259_mask_irq(unsigned int irq_nr)
86 {
87         unsigned long flags;
88
89         irq_nr -= NR_SIU_INTS;
90
91         spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
92         sbc82xx_i8259_mask |= 1 << irq_nr;
93         sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
94         spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
95 }
96
97 static void sbc82xx_i8259_unmask_irq(unsigned int irq_nr)
98 {
99         unsigned long flags;
100
101         irq_nr -= NR_SIU_INTS;
102
103         spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
104         sbc82xx_i8259_mask &= ~(1 << irq_nr);
105         sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
106         spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
107 }
108
109 static void sbc82xx_i8259_end_irq(unsigned int irq)
110 {
111         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
112             && irq_desc[irq].action)
113                 sbc82xx_i8259_unmask_irq(irq);
114 }
115
116
117 struct hw_interrupt_type sbc82xx_i8259_ic = {
118         .typename = " i8259     ",
119         .enable = sbc82xx_i8259_unmask_irq,
120         .disable = sbc82xx_i8259_mask_irq,
121         .ack = sbc82xx_i8259_mask_and_ack_irq,
122         .end = sbc82xx_i8259_end_irq,
123 };
124
125 static irqreturn_t sbc82xx_i8259_demux(int irq, void *dev_id, struct pt_regs *regs)
126 {
127         spin_lock(&sbc82xx_i8259_lock);
128
129         sbc82xx_i8259_map[0] = 0x0c;    /* OCW3: Read IR register on RD# pulse */
130         irq = sbc82xx_i8259_map[0] & 7; /* Read IRR */
131
132         if (irq == 7) {
133                 /* Possible spurious interrupt */
134                 int isr;
135                 sbc82xx_i8259_map[0] = 0x0b;    /* OCW3: Read IS register on RD# pulse */
136                 isr = sbc82xx_i8259_map[0];     /* Read ISR */
137
138                 if (!(isr & 0x80)) {
139                         printk(KERN_INFO "Spurious i8259 interrupt\n");
140                         return IRQ_HANDLED;
141                 }
142         }
143         __do_IRQ(NR_SIU_INTS + irq, regs);
144         return IRQ_HANDLED;
145 }
146
147 static struct irqaction sbc82xx_i8259_irqaction = {
148         .handler = sbc82xx_i8259_demux,
149         .flags = SA_INTERRUPT,
150         .mask = CPU_MASK_NONE,
151         .name = "i8259 demux",
152 };
153
154 void __init sbc82xx_init_IRQ(void)
155 {
156         volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
157         volatile intctl_cpm2_t *ic = &cpm2_immr->im_intctl;
158         int i;
159
160         callback_init_IRQ();
161
162         /* u-boot doesn't always set the board up correctly */
163         mc->memc_br5 = 0;
164         mc->memc_or5 = 0xfff00856;
165         mc->memc_br5 = 0x22000801;
166
167         sbc82xx_i8259_map = ioremap(0x22008000, 2);
168         if (!sbc82xx_i8259_map) {
169                 printk(KERN_CRIT "Mapping i8259 interrupt controller failed\n");
170                 return;
171         }
172         
173         /* Set up the interrupt handlers for the i8259 IRQs */
174         for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) {
175                 irq_desc[i].handler = &sbc82xx_i8259_ic;
176                 irq_desc[i].status |= IRQ_LEVEL;
177         }
178
179         /* make IRQ6 level sensitive */
180         ic->ic_siexr &= ~(1 << (14 - (SIU_INT_IRQ6 - SIU_INT_IRQ1)));
181         irq_desc[SIU_INT_IRQ6].status |= IRQ_LEVEL;
182
183         /* Initialise the i8259 */
184         sbc82xx_i8259_map[0] = 0x1b;    /* ICW1: Level, no cascade, ICW4 */
185         sbc82xx_i8259_map[1] = 0x00;    /* ICW2: vector base */
186                                         /* No ICW3 (no cascade) */
187         sbc82xx_i8259_map[1] = 0x01;    /* ICW4: 8086 mode, normal EOI */
188
189         sbc82xx_i8259_map[0] = 0x0b;    /* OCW3: Read IS register on RD# pulse */
190
191         sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; /* Set interrupt mask */
192
193         /* Request cascade IRQ */
194         if (setup_irq(SIU_INT_IRQ6, &sbc82xx_i8259_irqaction)) {
195                 printk("Installation of i8259 IRQ demultiplexer failed.\n");
196         }
197 }
198
199 static int sbc82xx_pci_map_irq(struct pci_dev *dev, unsigned char idsel,
200                                unsigned char pin)
201 {
202         static char pci_irq_table[][4] = {
203                 /*
204                  * PCI IDSEL/INTPIN->INTLINE
205                  *  A      B      C      D
206                  */
207                 { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 16 - PMC slot */
208                 { SBC82xx_PC_IRQA, SBC82xx_PC_IRQB, -1,  -1  },                 /* IDSEL 17 - CardBus */
209                 { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 18 - PCI-X bridge */
210         };
211
212         const long min_idsel = 16, max_idsel = 18, irqs_per_slot = 4;
213
214         return PCI_IRQ_TABLE_LOOKUP;
215 }
216
217 static void __devinit quirk_sbc8260_cardbus(struct pci_dev *pdev)
218 {
219         uint32_t ctrl;
220
221         if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(17, 0))
222                 return;
223
224         printk(KERN_INFO "Setting up CardBus controller\n");
225
226         /* Set P2CCLK bit in System Control Register */
227         pci_read_config_dword(pdev, 0x80, &ctrl);
228         ctrl |= (1<<27);
229         pci_write_config_dword(pdev, 0x80, ctrl);
230
231         /* Set MFUNC up for PCI IRQ routing via INTA and INTB, and LEDs. */
232         pci_write_config_dword(pdev, 0x8c, 0x00c01d22);
233
234 }
235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, quirk_sbc8260_cardbus);
236
237 void __init
238 m82xx_board_init(void)
239 {
240         /* u-boot may be using one of the FCC Ethernet devices.
241            Use the MAC address to the SCC. */
242         __res[offsetof(bd_t, bi_enetaddr[5])] &= ~3;
243
244         /* Anything special for this platform */
245         callback_init_IRQ       = ppc_md.init_IRQ;
246
247         ppc_md.init_IRQ         = sbc82xx_init_IRQ;
248         ppc_md.pci_map_irq      = sbc82xx_pci_map_irq;
249 #ifdef CONFIG_GEN_RTC
250         ppc_md.time_init        = NULL;
251         ppc_md.get_rtc_time     = NULL;
252         ppc_md.set_rtc_time     = NULL;
253         ppc_md.nvram_read_val   = NULL;
254         ppc_md.nvram_write_val  = NULL;
255         late_time_init          = sbc82xx_time_init;
256 #endif /* CONFIG_GEN_RTC */
257 }