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   1 /*
   2  * arch/powerpc/platforms/pseries/xics.c
   3  *
   4  * Copyright 2000 IBM Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/types.h>
  15 #include <linux/threads.h>
  16 #include <linux/kernel.h>
  17 #include <linux/irq.h>
  18 #include <linux/smp.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/signal.h>
  21 #include <linux/init.h>
  22 #include <linux/gfp.h>
  23 #include <linux/radix-tree.h>
  24 #include <linux/cpu.h>
  25
  26 #include <asm/firmware.h>
  27 #include <asm/prom.h>
  28 #include <asm/io.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/smp.h>
  31 #include <asm/rtas.h>
  32 #include <asm/hvcall.h>
  33 #include <asm/machdep.h>
  34 #include <asm/i8259.h>
  35
  36 #include "xics.h"
  37 #include "plpar_wrappers.h"
  38
  39 #define XICS_IPI                2
  40 #define XICS_IRQ_SPURIOUS       0
  41
  42 /* Want a priority other than 0.  Various HW issues require this. */
  43 #define DEFAULT_PRIORITY        5
  44
  45 /*
  46  * Mark IPIs as higher priority so we can take them inside interrupts that
  47  * arent marked IRQF_DISABLED
  48  */
  49 #define IPI_PRIORITY            4
  50
  51 struct xics_ipl {
  52         union {
  53                 u32 word;
  54                 u8 bytes[4];
  55         } xirr_poll;
  56         union {
  57                 u32 word;
  58                 u8 bytes[4];
  59         } xirr;
  60         u32 dummy;
  61         union {
  62                 u32 word;
  63                 u8 bytes[4];
  64         } qirr;
  65 };
  66
  67 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
  68
  69 static unsigned int default_server = 0xFF;
  70 static unsigned int default_distrib_server = 0;
  71 static unsigned int interrupt_server_size = 8;
  72
  73 static struct irq_host *xics_host;
  74
  75 /*
  76  * XICS only has a single IPI, so encode the messages per CPU
  77  */
  78 struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
  79
  80 /* RTAS service tokens */
  81 static int ibm_get_xive;
  82 static int ibm_set_xive;
  83 static int ibm_int_on;
  84 static int ibm_int_off;
  85
  86
  87 /* Direct HW low level accessors */
  88
  89
  90 static inline unsigned int direct_xirr_info_get(void)
  91 {
  92         int cpu = smp_processor_id();
  93
  94         return in_be32(&xics_per_cpu[cpu]->xirr.word);
  95 }
  96
  97 static inline void direct_xirr_info_set(int value)
  98 {
  99         int cpu = smp_processor_id();
 100
 101         out_be32(&xics_per_cpu[cpu]->xirr.word, value);
 102 }
 103
 104 static inline void direct_cppr_info(u8 value)
 105 {
 106         int cpu = smp_processor_id();
 107
 108         out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
 109 }
 110
 111 static inline void direct_qirr_info(int n_cpu, u8 value)
 112 {
 113         out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
 114 }
 115
 116
 117 /* LPAR low level accessors */
 118
 119
 120 static inline unsigned int lpar_xirr_info_get(void)
 121 {
 122         unsigned long lpar_rc;
 123         unsigned long return_value;
 124
 125         lpar_rc = plpar_xirr(&return_value);
 126         if (lpar_rc != H_SUCCESS)
 127                 panic(" bad return code xirr - rc = %lx \n", lpar_rc);
 128         return (unsigned int)return_value;
 129 }
 130
 131 static inline void lpar_xirr_info_set(int value)
 132 {
 133         unsigned long lpar_rc;
 134         unsigned long val64 = value & 0xffffffff;
 135
 136         lpar_rc = plpar_eoi(val64);
 137         if (lpar_rc != H_SUCCESS)
 138                 panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc,
 139                       val64);
 140 }
 141
 142 static inline void lpar_cppr_info(u8 value)
 143 {
 144         unsigned long lpar_rc;
 145
 146         lpar_rc = plpar_cppr(value);
 147         if (lpar_rc != H_SUCCESS)
 148                 panic("bad return code cppr - rc = %lx\n", lpar_rc);
 149 }
 150
 151 static inline void lpar_qirr_info(int n_cpu , u8 value)
 152 {
 153         unsigned long lpar_rc;
 154
 155         lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
 156         if (lpar_rc != H_SUCCESS)
 157                 panic("bad return code qirr - rc = %lx\n", lpar_rc);
 158 }
 159
 160
 161 /* High level handlers and init code */
 162
 163 static void xics_update_irq_servers(void)
 164 {
 165         int i, j;
 166         struct device_node *np;
 167         u32 ilen;
 168         const u32 *ireg, *isize;
 169         u32 hcpuid;
 170
 171         /* Find the server numbers for the boot cpu. */
 172         np = of_get_cpu_node(boot_cpuid, NULL);
 173         BUG_ON(!np);
 174
 175         ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
 176         if (!ireg) {
 177                 of_node_put(np);
 178                 return;
 179         }
 180
 181         i = ilen / sizeof(int);
 182         hcpuid = get_hard_smp_processor_id(boot_cpuid);
 183
 184         /* Global interrupt distribution server is specified in the last
 185          * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
 186          * entry fom this property for current boot cpu id and use it as
 187          * default distribution server
 188          */
 189         for (j = 0; j < i; j += 2) {
 190                 if (ireg[j] == hcpuid) {
 191                         default_server = hcpuid;
 192                         default_distrib_server = ireg[j+1];
 193
 194                         isize = of_get_property(np,
 195                                         "ibm,interrupt-server#-size", NULL);
 196                         if (isize)
 197                                 interrupt_server_size = *isize;
 198                 }
 199         }
 200
 201         of_node_put(np);
 202 }
 203
 204 #ifdef CONFIG_SMP
 205 static int get_irq_server(unsigned int virq, unsigned int strict_check)
 206 {
 207         int server;
 208         /* For the moment only implement delivery to all cpus or one cpu */
 209         cpumask_t cpumask = irq_desc[virq].affinity;
 210         cpumask_t tmp = CPU_MASK_NONE;
 211
 212         if (! cpu_isset(default_server, cpu_online_map))
 213                 xics_update_irq_servers();
 214
 215         if (!distribute_irqs)
 216                 return default_server;
 217
 218         if (!cpus_equal(cpumask, CPU_MASK_ALL)) {
 219                 cpus_and(tmp, cpu_online_map, cpumask);
 220
 221                 server = first_cpu(tmp);
 222
 223                 if (server < NR_CPUS)
 224                         return get_hard_smp_processor_id(server);
 225
 226                 if (strict_check)
 227                         return -1;
 228         }
 229
 230         if (cpus_equal(cpu_online_map, cpu_present_map))
 231                 return default_distrib_server;
 232
 233         return default_server;
 234 }
 235 #else
 236 static int get_irq_server(unsigned int virq, unsigned int strict_check)
 237 {
 238         return default_server;
 239 }
 240 #endif
 241
 242
 243 static void xics_unmask_irq(unsigned int virq)
 244 {
 245         unsigned int irq;
 246         int call_status;
 247         int server;
 248
 249         pr_debug("xics: unmask virq %d\n", virq);
 250
 251         irq = (unsigned int)irq_map[virq].hwirq;
 252         pr_debug(" -> map to hwirq 0x%x\n", irq);
 253         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 254                 return;
 255
 256         server = get_irq_server(virq, 0);
 257
 258         call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
 259                                 DEFAULT_PRIORITY);
 260         if (call_status != 0) {
 261                 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive "
 262                        "returned %d\n", irq, call_status);
 263                 printk("set_xive %x, server %x\n", ibm_set_xive, server);
 264                 return;
 265         }
 266
 267         /* Now unmask the interrupt (often a no-op) */
 268         call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
 269         if (call_status != 0) {
 270                 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on "
 271                        "returned %d\n", irq, call_status);
 272                 return;
 273         }
 274 }
 275
 276 static void xics_mask_real_irq(unsigned int irq)
 277 {
 278         int call_status;
 279
 280         if (irq == XICS_IPI)
 281                 return;
 282
 283         call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
 284         if (call_status != 0) {
 285                 printk(KERN_ERR "xics_disable_real_irq: irq=%u: "
 286                        "ibm_int_off returned %d\n", irq, call_status);
 287                 return;
 288         }
 289
 290         /* Have to set XIVE to 0xff to be able to remove a slot */
 291         call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
 292                                 default_server, 0xff);
 293         if (call_status != 0) {
 294                 printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)"
 295                        " returned %d\n", irq, call_status);
 296                 return;
 297         }
 298 }
 299
 300 static void xics_mask_irq(unsigned int virq)
 301 {
 302         unsigned int irq;
 303
 304         pr_debug("xics: mask virq %d\n", virq);
 305
 306         irq = (unsigned int)irq_map[virq].hwirq;
 307         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 308                 return;
 309         xics_mask_real_irq(irq);
 310 }
 311
 312 static unsigned int xics_startup(unsigned int virq)
 313 {
 314         unsigned int irq;
 315
 316         /* force a reverse mapping of the interrupt so it gets in the cache */
 317         irq = (unsigned int)irq_map[virq].hwirq;
 318         irq_radix_revmap(xics_host, irq);
 319
 320         /* unmask it */
 321         xics_unmask_irq(virq);
 322         return 0;
 323 }
 324
 325 static void xics_eoi_direct(unsigned int virq)
 326 {
 327         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 328
 329         iosync();
 330         direct_xirr_info_set((0xff << 24) | irq);
 331 }
 332
 333
 334 static void xics_eoi_lpar(unsigned int virq)
 335 {
 336         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 337
 338         iosync();
 339         lpar_xirr_info_set((0xff << 24) | irq);
 340 }
 341
 342 static inline unsigned int xics_remap_irq(unsigned int vec)
 343 {
 344         unsigned int irq;
 345
 346         vec &= 0x00ffffff;
 347
 348         if (vec == XICS_IRQ_SPURIOUS)
 349                 return NO_IRQ;
 350         irq = irq_radix_revmap(xics_host, vec);
 351         if (likely(irq != NO_IRQ))
 352                 return irq;
 353
 354         printk(KERN_ERR "Interrupt %u (real) is invalid,"
 355                " disabling it.\n", vec);
 356         xics_mask_real_irq(vec);
 357         return NO_IRQ;
 358 }
 359
 360 static unsigned int xics_get_irq_direct(void)
 361 {
 362         return xics_remap_irq(direct_xirr_info_get());
 363 }
 364
 365 static unsigned int xics_get_irq_lpar(void)
 366 {
 367         return xics_remap_irq(lpar_xirr_info_get());
 368 }
 369
 370 #ifdef CONFIG_SMP
 371
 372 static irqreturn_t xics_ipi_dispatch(int cpu)
 373 {
 374         WARN_ON(cpu_is_offline(cpu));
 375
 376         while (xics_ipi_message[cpu].value) {
 377                 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
 378                                        &xics_ipi_message[cpu].value)) {
 379                         mb();
 380                         smp_message_recv(PPC_MSG_CALL_FUNCTION);
 381                 }
 382                 if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
 383                                        &xics_ipi_message[cpu].value)) {
 384                         mb();
 385                         smp_message_recv(PPC_MSG_RESCHEDULE);
 386                 }
 387 #if 0
 388                 if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK,
 389                                        &xics_ipi_message[cpu].value)) {
 390                         mb();
 391                         smp_message_recv(PPC_MSG_MIGRATE_TASK);
 392                 }
 393 #endif
 394 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 395                 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
 396                                        &xics_ipi_message[cpu].value)) {
 397                         mb();
 398                         smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
 399                 }
 400 #endif
 401         }
 402         return IRQ_HANDLED;
 403 }
 404
 405 static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
 406 {
 407         int cpu = smp_processor_id();
 408
 409         direct_qirr_info(cpu, 0xff);
 410
 411         return xics_ipi_dispatch(cpu);
 412 }
 413
 414 static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
 415 {
 416         int cpu = smp_processor_id();
 417
 418         lpar_qirr_info(cpu, 0xff);
 419
 420         return xics_ipi_dispatch(cpu);
 421 }
 422
 423 void xics_cause_IPI(int cpu)
 424 {
 425         if (firmware_has_feature(FW_FEATURE_LPAR))
 426                 lpar_qirr_info(cpu, IPI_PRIORITY);
 427         else
 428                 direct_qirr_info(cpu, IPI_PRIORITY);
 429 }
 430
 431 #endif /* CONFIG_SMP */
 432
 433 static void xics_set_cpu_priority(unsigned char cppr)
 434 {
 435         if (firmware_has_feature(FW_FEATURE_LPAR))
 436                 lpar_cppr_info(cppr);
 437         else
 438                 direct_cppr_info(cppr);
 439         iosync();
 440 }
 441
 442 static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
 443 {
 444         unsigned int irq;
 445         int status;
 446         int xics_status[2];
 447         int irq_server;
 448
 449         irq = (unsigned int)irq_map[virq].hwirq;
 450         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 451                 return;
 452
 453         status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 454
 455         if (status) {
 456                 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
 457                        "returns %d\n", irq, status);
 458                 return;
 459         }
 460
 461         /*
 462          * For the moment only implement delivery to all cpus or one cpu.
 463          * Get current irq_server for the given irq
 464          */
 465         irq_server = get_irq_server(virq, 1);
 466         if (irq_server == -1) {
 467                 char cpulist[128];
 468                 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
 469                 printk(KERN_WARNING "xics_set_affinity: No online cpus in "
 470                                 "the mask %s for irq %d\n", cpulist, virq);
 471                 return;
 472         }
 473
 474         status = rtas_call(ibm_set_xive, 3, 1, NULL,
 475                                 irq, irq_server, xics_status[1]);
 476
 477         if (status) {
 478                 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
 479                        "returns %d\n", irq, status);
 480                 return;
 481         }
 482 }
 483
 484 void xics_setup_cpu(void)
 485 {
 486         xics_set_cpu_priority(0xff);
 487
 488         /*
 489          * Put the calling processor into the GIQ.  This is really only
 490          * necessary from a secondary thread as the OF start-cpu interface
 491          * performs this function for us on primary threads.
 492          *
 493          * XXX: undo of teardown on kexec needs this too, as may hotplug
 494          */
 495         rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
 496                 (1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
 497 }
 498
 499
 500 static struct irq_chip xics_pic_direct = {
 501         .typename = " XICS     ",
 502         .startup = xics_startup,
 503         .mask = xics_mask_irq,
 504         .unmask = xics_unmask_irq,
 505         .eoi = xics_eoi_direct,
 506         .set_affinity = xics_set_affinity
 507 };
 508
 509
 510 static struct irq_chip xics_pic_lpar = {
 511         .typename = " XICS     ",
 512         .startup = xics_startup,
 513         .mask = xics_mask_irq,
 514         .unmask = xics_unmask_irq,
 515         .eoi = xics_eoi_lpar,
 516         .set_affinity = xics_set_affinity
 517 };
 518
 519
 520 static int xics_host_match(struct irq_host *h, struct device_node *node)
 521 {
 522         /* IBM machines have interrupt parents of various funky types for things
 523          * like vdevices, events, etc... The trick we use here is to match
 524          * everything here except the legacy 8259 which is compatible "chrp,iic"
 525          */
 526         return !of_device_is_compatible(node, "chrp,iic");
 527 }
 528
 529 static int xics_host_map_direct(struct irq_host *h, unsigned int virq,
 530                                 irq_hw_number_t hw)
 531 {
 532         pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
 533
 534         get_irq_desc(virq)->status |= IRQ_LEVEL;
 535         set_irq_chip_and_handler(virq, &xics_pic_direct, handle_fasteoi_irq);
 536         return 0;
 537 }
 538
 539 static int xics_host_map_lpar(struct irq_host *h, unsigned int virq,
 540                               irq_hw_number_t hw)
 541 {
 542         pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
 543
 544         get_irq_desc(virq)->status |= IRQ_LEVEL;
 545         set_irq_chip_and_handler(virq, &xics_pic_lpar, handle_fasteoi_irq);
 546         return 0;
 547 }
 548
 549 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
 550                            u32 *intspec, unsigned int intsize,
 551                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 552
 553 {
 554         /* Current xics implementation translates everything
 555          * to level. It is not technically right for MSIs but this
 556          * is irrelevant at this point. We might get smarter in the future
 557          */
 558         *out_hwirq = intspec[0];
 559         *out_flags = IRQ_TYPE_LEVEL_LOW;
 560
 561         return 0;
 562 }
 563
 564 static struct irq_host_ops xics_host_direct_ops = {
 565         .match = xics_host_match,
 566         .map = xics_host_map_direct,
 567         .xlate = xics_host_xlate,
 568 };
 569
 570 static struct irq_host_ops xics_host_lpar_ops = {
 571         .match = xics_host_match,
 572         .map = xics_host_map_lpar,
 573         .xlate = xics_host_xlate,
 574 };
 575
 576 static void __init xics_init_host(void)
 577 {
 578         struct irq_host_ops *ops;
 579
 580         if (firmware_has_feature(FW_FEATURE_LPAR))
 581                 ops = &xics_host_lpar_ops;
 582         else
 583                 ops = &xics_host_direct_ops;
 584         xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, ops,
 585                                    XICS_IRQ_SPURIOUS);
 586         BUG_ON(xics_host == NULL);
 587         irq_set_default_host(xics_host);
 588 }
 589
 590 static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
 591                                      unsigned long size)
 592 {
 593 #ifdef CONFIG_SMP
 594         int i;
 595
 596         /* This may look gross but it's good enough for now, we don't quite
 597          * have a hard -> linux processor id matching.
 598          */
 599         for_each_possible_cpu(i) {
 600                 if (!cpu_present(i))
 601                         continue;
 602                 if (hw_id == get_hard_smp_processor_id(i)) {
 603                         xics_per_cpu[i] = ioremap(addr, size);
 604                         return;
 605                 }
 606         }
 607 #else
 608         if (hw_id != 0)
 609                 return;
 610         xics_per_cpu[0] = ioremap(addr, size);
 611 #endif /* CONFIG_SMP */
 612 }
 613
 614 static void __init xics_init_one_node(struct device_node *np,
 615                                       unsigned int *indx)
 616 {
 617         unsigned int ilen;
 618         const u32 *ireg;
 619
 620         /* This code does the theorically broken assumption that the interrupt
 621          * server numbers are the same as the hard CPU numbers.
 622          * This happens to be the case so far but we are playing with fire...
 623          * should be fixed one of these days. -BenH.
 624          */
 625         ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
 626
 627         /* Do that ever happen ? we'll know soon enough... but even good'old
 628          * f80 does have that property ..
 629          */
 630         WARN_ON(ireg == NULL);
 631         if (ireg) {
 632                 /*
 633                  * set node starting index for this node
 634                  */
 635                 *indx = *ireg;
 636         }
 637         ireg = of_get_property(np, "reg", &ilen);
 638         if (!ireg)
 639                 panic("xics_init_IRQ: can't find interrupt reg property");
 640
 641         while (ilen >= (4 * sizeof(u32))) {
 642                 unsigned long addr, size;
 643
 644                 /* XXX Use proper OF parsing code here !!! */
 645                 addr = (unsigned long)*ireg++ << 32;
 646                 ilen -= sizeof(u32);
 647                 addr |= *ireg++;
 648                 ilen -= sizeof(u32);
 649                 size = (unsigned long)*ireg++ << 32;
 650                 ilen -= sizeof(u32);
 651                 size |= *ireg++;
 652                 ilen -= sizeof(u32);
 653                 xics_map_one_cpu(*indx, addr, size);
 654                 (*indx)++;
 655         }
 656 }
 657
 658
 659 static void __init xics_setup_8259_cascade(void)
 660 {
 661         struct device_node *np, *old, *found = NULL;
 662         int cascade, naddr;
 663         const u32 *addrp;
 664         unsigned long intack = 0;
 665
 666         for_each_node_by_type(np, "interrupt-controller")
 667                 if (of_device_is_compatible(np, "chrp,iic")) {
 668                         found = np;
 669                         break;
 670                 }
 671         if (found == NULL) {
 672                 printk(KERN_DEBUG "xics: no ISA interrupt controller\n");
 673                 return;
 674         }
 675         cascade = irq_of_parse_and_map(found, 0);
 676         if (cascade == NO_IRQ) {
 677                 printk(KERN_ERR "xics: failed to map cascade interrupt");
 678                 return;
 679         }
 680         pr_debug("xics: cascade mapped to irq %d\n", cascade);
 681
 682         for (old = of_node_get(found); old != NULL ; old = np) {
 683                 np = of_get_parent(old);
 684                 of_node_put(old);
 685                 if (np == NULL)
 686                         break;
 687                 if (strcmp(np->name, "pci") != 0)
 688                         continue;
 689                 addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
 690                 if (addrp == NULL)
 691                         continue;
 692                 naddr = of_n_addr_cells(np);
 693                 intack = addrp[naddr-1];
 694                 if (naddr > 1)
 695                         intack |= ((unsigned long)addrp[naddr-2]) << 32;
 696         }
 697         if (intack)
 698                 printk(KERN_DEBUG "xics: PCI 8259 intack at 0x%016lx\n", intack);
 699         i8259_init(found, intack);
 700         of_node_put(found);
 701         set_irq_chained_handler(cascade, pseries_8259_cascade);
 702 }
 703
 704 void __init xics_init_IRQ(void)
 705 {
 706         struct device_node *np;
 707         u32 indx = 0;
 708         int found = 0;
 709
 710         ppc64_boot_msg(0x20, "XICS Init");
 711
 712         ibm_get_xive = rtas_token("ibm,get-xive");
 713         ibm_set_xive = rtas_token("ibm,set-xive");
 714         ibm_int_on  = rtas_token("ibm,int-on");
 715         ibm_int_off = rtas_token("ibm,int-off");
 716
 717         for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
 718                 found = 1;
 719                 if (firmware_has_feature(FW_FEATURE_LPAR))
 720                         break;
 721                 xics_init_one_node(np, &indx);
 722         }
 723         if (found == 0)
 724                 return;
 725
 726         xics_init_host();
 727         xics_update_irq_servers();
 728
 729         if (firmware_has_feature(FW_FEATURE_LPAR))
 730                 ppc_md.get_irq = xics_get_irq_lpar;
 731         else
 732                 ppc_md.get_irq = xics_get_irq_direct;
 733
 734         xics_setup_cpu();
 735
 736         xics_setup_8259_cascade();
 737
 738         ppc64_boot_msg(0x21, "XICS Done");
 739 }
 740
 741
 742 #ifdef CONFIG_SMP
 743 void xics_request_IPIs(void)
 744 {
 745         unsigned int ipi;
 746         int rc;
 747
 748         ipi = irq_create_mapping(xics_host, XICS_IPI);
 749         BUG_ON(ipi == NO_IRQ);
 750
 751         /*
 752          * IPIs are marked IRQF_DISABLED as they must run with irqs
 753          * disabled
 754          */
 755         set_irq_handler(ipi, handle_percpu_irq);
 756         if (firmware_has_feature(FW_FEATURE_LPAR))
 757                 rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
 758                                 "IPI", NULL);
 759         else
 760                 rc = request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
 761                                 "IPI", NULL);
 762         BUG_ON(rc);
 763 }
 764 #endif /* CONFIG_SMP */
 765
 766 void xics_teardown_cpu()
 767 {
 768         int cpu = smp_processor_id();
 769
 770         xics_set_cpu_priority(0);
 771
 772         /*
 773          * Clear IPI
 774          */
 775         if (firmware_has_feature(FW_FEATURE_LPAR))
 776                 lpar_qirr_info(cpu, 0xff);
 777         else
 778                 direct_qirr_info(cpu, 0xff);
 779 }
 780
 781 void xics_kexec_teardown_cpu(int secondary)
 782 {
 783         unsigned int ipi;
 784         struct irq_desc *desc;
 785
 786         xics_teardown_cpu();
 787
 788         /*
 789          * we need to EOI the IPI
 790          *
 791          * probably need to check all the other interrupts too
 792          * should we be flagging idle loop instead?
 793          * or creating some task to be scheduled?
 794          */
 795
 796         ipi = irq_find_mapping(xics_host, XICS_IPI);
 797         if (ipi == XICS_IRQ_SPURIOUS)
 798                 return;
 799         desc = get_irq_desc(ipi);
 800         if (desc->chip && desc->chip->eoi)
 801                 desc->chip->eoi(ipi);
 802
 803         /*
 804          * Some machines need to have at least one cpu in the GIQ,
 805          * so leave the master cpu in the group.
 806          */
 807         if (secondary)
 808                 rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
 809                                    (1UL << interrupt_server_size) - 1 -
 810                                    default_distrib_server, 0);
 811 }
 812
 813 #ifdef CONFIG_HOTPLUG_CPU
 814
 815 /* Interrupts are disabled. */
 816 void xics_migrate_irqs_away(void)
 817 {
 818         int status;
 819         int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
 820         unsigned int irq, virq;
 821
 822         /* Reject any interrupt that was queued to us... */
 823         xics_set_cpu_priority(0);
 824
 825         /* remove ourselves from the global interrupt queue */
 826         status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
 827                 (1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
 828         WARN_ON(status < 0);
 829
 830         /* Allow IPIs again... */
 831         xics_set_cpu_priority(DEFAULT_PRIORITY);
 832
 833         for_each_irq(virq) {
 834                 struct irq_desc *desc;
 835                 int xics_status[2];
 836                 unsigned long flags;
 837
 838                 /* We cant set affinity on ISA interrupts */
 839                 if (virq < NUM_ISA_INTERRUPTS)
 840                         continue;
 841                 if (irq_map[virq].host != xics_host)
 842                         continue;
 843                 irq = (unsigned int)irq_map[virq].hwirq;
 844                 /* We need to get IPIs still. */
 845                 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 846                         continue;
 847                 desc = get_irq_desc(virq);
 848
 849                 /* We only need to migrate enabled IRQS */
 850                 if (desc == NULL || desc->chip == NULL
 851                     || desc->action == NULL
 852                     || desc->chip->set_affinity == NULL)
 853                         continue;
 854
 855                 spin_lock_irqsave(&desc->lock, flags);
 856
 857                 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 858                 if (status) {
 859                         printk(KERN_ERR "migrate_irqs_away: irq=%u "
 860                                         "ibm,get-xive returns %d\n",
 861                                         virq, status);
 862                         goto unlock;
 863                 }
 864
 865                 /*
 866                  * We only support delivery to all cpus or to one cpu.
 867                  * The irq has to be migrated only in the single cpu
 868                  * case.
 869                  */
 870                 if (xics_status[0] != hw_cpu)
 871                         goto unlock;
 872
 873                 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
 874                        virq, cpu);
 875
 876                 /* Reset affinity to all cpus */
 877                 irq_desc[virq].affinity = CPU_MASK_ALL;
 878                 desc->chip->set_affinity(virq, CPU_MASK_ALL);
 879 unlock:
 880                 spin_unlock_irqrestore(&desc->lock, flags);
 881         }
 882 }
 883 #endif