git.oblomov.eu Git - linux-2.6/blob - drivers/w1/masters/ds1wm.c

   1 /*
   2  * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
   3  * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
   4  * like hx4700).
   5  *
   6  * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
   7  * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
   8  *
   9  * Use consistent with the GNU GPL is permitted,
  10  * provided that this copyright notice is
  11  * preserved in its entirety in all copies and derived works.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/pm.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/delay.h>
  22 #include <linux/ds1wm.h>
  23
  24 #include <asm/io.h>
  25
  26 #include "../w1.h"
  27 #include "../w1_int.h"
  28
  29
  30 #define DS1WM_CMD       0x00    /* R/W 4 bits command */
  31 #define DS1WM_DATA      0x01    /* R/W 8 bits, transmit/receive buffer */
  32 #define DS1WM_INT       0x02    /* R/W interrupt status */
  33 #define DS1WM_INT_EN    0x03    /* R/W interrupt enable */
  34 #define DS1WM_CLKDIV    0x04    /* R/W 5 bits of divisor and pre-scale */
  35
  36 #define DS1WM_CMD_1W_RESET  (1 << 0)    /* force reset on 1-wire bus */
  37 #define DS1WM_CMD_SRA       (1 << 1)    /* enable Search ROM accelerator mode */
  38 #define DS1WM_CMD_DQ_OUTPUT (1 << 2)    /* write only - forces bus low */
  39 #define DS1WM_CMD_DQ_INPUT  (1 << 3)    /* read only - reflects state of bus */
  40 #define DS1WM_CMD_RST       (1 << 5)    /* software reset */
  41 #define DS1WM_CMD_OD        (1 << 7)    /* overdrive */
  42
  43 #define DS1WM_INT_PD        (1 << 0)    /* presence detect */
  44 #define DS1WM_INT_PDR       (1 << 1)    /* presence detect result */
  45 #define DS1WM_INT_TBE       (1 << 2)    /* tx buffer empty */
  46 #define DS1WM_INT_TSRE      (1 << 3)    /* tx shift register empty */
  47 #define DS1WM_INT_RBF       (1 << 4)    /* rx buffer full */
  48 #define DS1WM_INT_RSRF      (1 << 5)    /* rx shift register full */
  49
  50 #define DS1WM_INTEN_EPD     (1 << 0)    /* enable presence detect int */
  51 #define DS1WM_INTEN_IAS     (1 << 1)    /* INTR active state */
  52 #define DS1WM_INTEN_ETBE    (1 << 2)    /* enable tx buffer empty int */
  53 #define DS1WM_INTEN_ETMT    (1 << 3)    /* enable tx shift register empty int */
  54 #define DS1WM_INTEN_ERBF    (1 << 4)    /* enable rx buffer full int */
  55 #define DS1WM_INTEN_ERSRF   (1 << 5)    /* enable rx shift register full int */
  56 #define DS1WM_INTEN_DQO     (1 << 6)    /* enable direct bus driving ops */
  57
  58
  59 #define DS1WM_TIMEOUT (HZ * 5)
  60
  61 static struct {
  62         unsigned long freq;
  63         unsigned long divisor;
  64 } freq[] = {
  65         { 4000000, 0x8 },
  66         { 5000000, 0x2 },
  67         { 6000000, 0x5 },
  68         { 7000000, 0x3 },
  69         { 8000000, 0xc },
  70         { 10000000, 0x6 },
  71         { 12000000, 0x9 },
  72         { 14000000, 0x7 },
  73         { 16000000, 0x10 },
  74         { 20000000, 0xa },
  75         { 24000000, 0xd },
  76         { 28000000, 0xb },
  77         { 32000000, 0x14 },
  78         { 40000000, 0xe },
  79         { 48000000, 0x11 },
  80         { 56000000, 0xf },
  81         { 64000000, 0x18 },
  82         { 80000000, 0x12 },
  83         { 96000000, 0x15 },
  84         { 112000000, 0x13 },
  85         { 128000000, 0x1c },
  86 };
  87
  88 struct ds1wm_data {
  89         void            __iomem *map;
  90         int             bus_shift; /* # of shifts to calc register offsets */
  91         struct platform_device *pdev;
  92         struct ds1wm_platform_data *pdata;
  93         int             irq;
  94         int             active_high;
  95         struct clk      *clk;
  96         int             slave_present;
  97         void            *reset_complete;
  98         void            *read_complete;
  99         void            *write_complete;
 100         u8              read_byte; /* last byte received */
 101 };
 102
 103 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
 104                                         u8 val)
 105 {
 106         __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
 107 }
 108
 109 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
 110 {
 111         return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
 112 }
 113
 114
 115 static irqreturn_t ds1wm_isr(int isr, void *data)
 116 {
 117         struct ds1wm_data *ds1wm_data = data;
 118         u8 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
 119
 120         ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
 121
 122         if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete)
 123                 complete(ds1wm_data->reset_complete);
 124
 125         if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete)
 126                 complete(ds1wm_data->write_complete);
 127
 128         if (intr & DS1WM_INT_RBF) {
 129                 ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
 130                                                             DS1WM_DATA);
 131                 if (ds1wm_data->read_complete)
 132                         complete(ds1wm_data->read_complete);
 133         }
 134
 135         return IRQ_HANDLED;
 136 }
 137
 138 static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
 139 {
 140         unsigned long timeleft;
 141         DECLARE_COMPLETION_ONSTACK(reset_done);
 142
 143         ds1wm_data->reset_complete = &reset_done;
 144
 145         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
 146                 (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
 147
 148         ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
 149
 150         timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
 151         ds1wm_data->reset_complete = NULL;
 152         if (!timeleft) {
 153                 dev_err(&ds1wm_data->pdev->dev, "reset failed\n");
 154                 return 1;
 155         }
 156
 157         /* Wait for the end of the reset. According to the specs, the time
 158          * from when the interrupt is asserted to the end of the reset is:
 159          *     tRSTH  - tPDH  - tPDL - tPDI
 160          *     625 us - 60 us - 240 us - 100 ns = 324.9 us
 161          *
 162          * We'll wait a bit longer just to be sure.
 163          * Was udelay(500), but if it is going to busywait the cpu that long,
 164          * might as well come back later.
 165          */
 166         msleep(1);
 167
 168         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
 169                 DS1WM_INTEN_ERBF | DS1WM_INTEN_ETMT | DS1WM_INTEN_EPD |
 170                 (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
 171
 172         if (!ds1wm_data->slave_present) {
 173                 dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
 174                 return 1;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
 181 {
 182         DECLARE_COMPLETION_ONSTACK(write_done);
 183         ds1wm_data->write_complete = &write_done;
 184
 185         ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
 186
 187         wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
 188         ds1wm_data->write_complete = NULL;
 189
 190         return 0;
 191 }
 192
 193 static int ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
 194 {
 195         DECLARE_COMPLETION_ONSTACK(read_done);
 196         ds1wm_data->read_complete = &read_done;
 197
 198         ds1wm_write(ds1wm_data, write_data);
 199         wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
 200         ds1wm_data->read_complete = NULL;
 201
 202         return ds1wm_data->read_byte;
 203 }
 204
 205 static int ds1wm_find_divisor(int gclk)
 206 {
 207         int i;
 208
 209         for (i = 0; i < ARRAY_SIZE(freq); i++)
 210                 if (gclk <= freq[i].freq)
 211                         return freq[i].divisor;
 212
 213         return 0;
 214 }
 215
 216 static void ds1wm_up(struct ds1wm_data *ds1wm_data)
 217 {
 218         int gclk, divisor;
 219
 220         if (ds1wm_data->pdata->enable)
 221                 ds1wm_data->pdata->enable(ds1wm_data->pdev);
 222
 223         gclk = clk_get_rate(ds1wm_data->clk);
 224         clk_enable(ds1wm_data->clk);
 225         divisor = ds1wm_find_divisor(gclk);
 226         if (divisor == 0) {
 227                 dev_err(&ds1wm_data->pdev->dev,
 228                         "no suitable divisor for %dHz clock\n", gclk);
 229                 return;
 230         }
 231         ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
 232
 233         /* Let the w1 clock stabilize. */
 234         msleep(1);
 235
 236         ds1wm_reset(ds1wm_data);
 237 }
 238
 239 static void ds1wm_down(struct ds1wm_data *ds1wm_data)
 240 {
 241         ds1wm_reset(ds1wm_data);
 242
 243         /* Disable interrupts. */
 244         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
 245                              ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0);
 246
 247         if (ds1wm_data->pdata->disable)
 248                 ds1wm_data->pdata->disable(ds1wm_data->pdev);
 249
 250         clk_disable(ds1wm_data->clk);
 251 }
 252
 253 /* --------------------------------------------------------------------- */
 254 /* w1 methods */
 255
 256 static u8 ds1wm_read_byte(void *data)
 257 {
 258         struct ds1wm_data *ds1wm_data = data;
 259
 260         return ds1wm_read(ds1wm_data, 0xff);
 261 }
 262
 263 static void ds1wm_write_byte(void *data, u8 byte)
 264 {
 265         struct ds1wm_data *ds1wm_data = data;
 266
 267         ds1wm_write(ds1wm_data, byte);
 268 }
 269
 270 static u8 ds1wm_reset_bus(void *data)
 271 {
 272         struct ds1wm_data *ds1wm_data = data;
 273
 274         ds1wm_reset(ds1wm_data);
 275
 276         return 0;
 277 }
 278
 279 static void ds1wm_search(void *data, struct w1_master *master_dev,
 280                         u8 search_type, w1_slave_found_callback slave_found)
 281 {
 282         struct ds1wm_data *ds1wm_data = data;
 283         int i;
 284         unsigned long long rom_id;
 285
 286         /* XXX We need to iterate for multiple devices per the DS1WM docs.
 287          * See http://www.maxim-ic.com/appnotes.cfm/appnote_number/120. */
 288         if (ds1wm_reset(ds1wm_data))
 289                 return;
 290
 291         ds1wm_write(ds1wm_data, search_type);
 292         ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
 293
 294         for (rom_id = 0, i = 0; i < 16; i++) {
 295
 296                 unsigned char resp, r, d;
 297
 298                 resp = ds1wm_read(ds1wm_data, 0x00);
 299
 300                 r = ((resp & 0x02) >> 1) |
 301                     ((resp & 0x08) >> 2) |
 302                     ((resp & 0x20) >> 3) |
 303                     ((resp & 0x80) >> 4);
 304
 305                 d = ((resp & 0x01) >> 0) |
 306                     ((resp & 0x04) >> 1) |
 307                     ((resp & 0x10) >> 2) |
 308                     ((resp & 0x40) >> 3);
 309
 310                 rom_id |= (unsigned long long) r << (i * 4);
 311
 312         }
 313         dev_dbg(&ds1wm_data->pdev->dev, "found 0x%08llX\n", rom_id);
 314
 315         ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
 316         ds1wm_reset(ds1wm_data);
 317
 318         slave_found(master_dev, rom_id);
 319 }
 320
 321 /* --------------------------------------------------------------------- */
 322
 323 static struct w1_bus_master ds1wm_master = {
 324         .read_byte  = ds1wm_read_byte,
 325         .write_byte = ds1wm_write_byte,
 326         .reset_bus  = ds1wm_reset_bus,
 327         .search     = ds1wm_search,
 328 };
 329
 330 static int ds1wm_probe(struct platform_device *pdev)
 331 {
 332         struct ds1wm_data *ds1wm_data;
 333         struct ds1wm_platform_data *plat;
 334         struct resource *res;
 335         int ret;
 336
 337         if (!pdev)
 338                 return -ENODEV;
 339
 340         ds1wm_data = kzalloc(sizeof(*ds1wm_data), GFP_KERNEL);
 341         if (!ds1wm_data)
 342                 return -ENOMEM;
 343
 344         platform_set_drvdata(pdev, ds1wm_data);
 345
 346         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 347         if (!res) {
 348                 ret = -ENXIO;
 349                 goto err0;
 350         }
 351         ds1wm_data->map = ioremap(res->start, res->end - res->start + 1);
 352         if (!ds1wm_data->map) {
 353                 ret = -ENOMEM;
 354                 goto err0;
 355         }
 356         plat = pdev->dev.platform_data;
 357         ds1wm_data->bus_shift = plat->bus_shift;
 358         ds1wm_data->pdev = pdev;
 359         ds1wm_data->pdata = plat;
 360
 361         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 362         if (!res) {
 363                 ret = -ENXIO;
 364                 goto err1;
 365         }
 366         ds1wm_data->irq = res->start;
 367         ds1wm_data->active_high = plat->active_high;
 368
 369         if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
 370                 set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 371         if (res->flags & IORESOURCE_IRQ_LOWEDGE)
 372                 set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
 373
 374         ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
 375                           "ds1wm", ds1wm_data);
 376         if (ret)
 377                 goto err1;
 378
 379         ds1wm_data->clk = clk_get(&pdev->dev, "ds1wm");
 380         if (IS_ERR(ds1wm_data->clk)) {
 381                 ret = PTR_ERR(ds1wm_data->clk);
 382                 goto err2;
 383         }
 384
 385         ds1wm_up(ds1wm_data);
 386
 387         ds1wm_master.data = (void *)ds1wm_data;
 388
 389         ret = w1_add_master_device(&ds1wm_master);
 390         if (ret)
 391                 goto err3;
 392
 393         return 0;
 394
 395 err3:
 396         ds1wm_down(ds1wm_data);
 397         clk_put(ds1wm_data->clk);
 398 err2:
 399         free_irq(ds1wm_data->irq, ds1wm_data);
 400 err1:
 401         iounmap(ds1wm_data->map);
 402 err0:
 403         kfree(ds1wm_data);
 404
 405         return ret;
 406 }
 407
 408 #ifdef CONFIG_PM
 409 static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
 410 {
 411         struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 412
 413         ds1wm_down(ds1wm_data);
 414
 415         return 0;
 416 }
 417
 418 static int ds1wm_resume(struct platform_device *pdev)
 419 {
 420         struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 421
 422         ds1wm_up(ds1wm_data);
 423
 424         return 0;
 425 }
 426 #else
 427 #define ds1wm_suspend NULL
 428 #define ds1wm_resume NULL
 429 #endif
 430
 431 static int ds1wm_remove(struct platform_device *pdev)
 432 {
 433         struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 434
 435         w1_remove_master_device(&ds1wm_master);
 436         ds1wm_down(ds1wm_data);
 437         clk_put(ds1wm_data->clk);
 438         free_irq(ds1wm_data->irq, ds1wm_data);
 439         iounmap(ds1wm_data->map);
 440         kfree(ds1wm_data);
 441
 442         return 0;
 443 }
 444
 445 static struct platform_driver ds1wm_driver = {
 446         .driver   = {
 447                 .name = "ds1wm",
 448         },
 449         .probe    = ds1wm_probe,
 450         .remove   = ds1wm_remove,
 451         .suspend  = ds1wm_suspend,
 452         .resume   = ds1wm_resume
 453 };
 454
 455 static int __init ds1wm_init(void)
 456 {
 457         printk("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
 458         return platform_driver_register(&ds1wm_driver);
 459 }
 460
 461 static void __exit ds1wm_exit(void)
 462 {
 463         platform_driver_unregister(&ds1wm_driver);
 464 }
 465
 466 module_init(ds1wm_init);
 467 module_exit(ds1wm_exit);
 468
 469 MODULE_LICENSE("GPL");
 470 MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
 471               "Matt Reimer <mreimer@vpop.net>");
 472 MODULE_DESCRIPTION("DS1WM w1 busmaster driver");