2 * rtrap.S: Preparing for return from trap on Sparc V9.
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
10 #include <asm/pstate.h>
11 #include <asm/ptrace.h>
12 #include <asm/spitfire.h>
14 #include <asm/visasm.h>
15 #include <asm/processor.h>
17 #define RTRAP_PSTATE (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
18 #define RTRAP_PSTATE_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
19 #define RTRAP_PSTATE_AG_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
26 ba,a,pt %xcc, __handle_softirq_continue
30 wrpr %g0, RTRAP_PSTATE, %pstate
31 ba,pt %xcc, __handle_preemption_continue
32 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
34 __handle_user_windows:
35 call fault_in_user_windows
36 wrpr %g0, RTRAP_PSTATE, %pstate
37 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
38 /* Redo sched+sig checks */
39 ldx [%g6 + TI_FLAGS], %l0
40 andcc %l0, _TIF_NEED_RESCHED, %g0
45 wrpr %g0, RTRAP_PSTATE, %pstate
46 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
47 ldx [%g6 + TI_FLAGS], %l0
49 1: andcc %l0, _TIF_SIGPENDING, %g0
50 be,pt %xcc, __handle_user_windows_continue
53 add %sp, PTREGS_OFF, %o0
57 wrpr %g0, RTRAP_PSTATE, %pstate
58 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
59 /* Signal delivery can modify pt_regs tstate, so we must
62 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
63 sethi %hi(0xf << 20), %l4
65 ba,pt %xcc, __handle_user_windows_continue
70 wrpr %g0, RTRAP_PSTATE, %pstate
71 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
72 ldub [%g6 + TI_WSAVED], %o2
75 /* Redo userwin+sched+sig checks */
76 call fault_in_user_windows
78 wrpr %g0, RTRAP_PSTATE, %pstate
79 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
80 ldx [%g6 + TI_FLAGS], %l0
81 andcc %l0, _TIF_NEED_RESCHED, %g0
86 wrpr %g0, RTRAP_PSTATE, %pstate
87 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
88 ldx [%g6 + TI_FLAGS], %l0
89 1: andcc %l0, _TIF_SIGPENDING, %g0
91 be,pt %xcc, __handle_perfctrs_continue
92 sethi %hi(TSTATE_PEF), %o0
94 add %sp, PTREGS_OFF, %o0
98 wrpr %g0, RTRAP_PSTATE, %pstate
99 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
100 /* Signal delivery can modify pt_regs tstate, so we must
103 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
104 sethi %hi(0xf << 20), %l4
107 ba,pt %xcc, __handle_perfctrs_continue
109 sethi %hi(TSTATE_PEF), %o0
112 andcc %l5, FPRS_FEF, %g0
113 sethi %hi(TSTATE_PEF), %o0
114 be,a,pn %icc, __handle_userfpu_continue
116 ba,a,pt %xcc, __handle_userfpu_continue
120 add %sp, PTREGS_OFF, %o0
122 call do_notify_resume
123 wrpr %g0, RTRAP_PSTATE, %pstate
124 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
126 /* Signal delivery can modify pt_regs tstate, so we must
129 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
130 sethi %hi(0xf << 20), %l4
132 ba,pt %xcc, __handle_signal_continue
136 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
140 sethi %hi(per_cpu____cpu_data), %l0
141 lduw [%l0 + %lo(per_cpu____cpu_data)], %l1
143 sethi %hi(per_cpu____cpu_data), %l0
144 or %l0, %lo(per_cpu____cpu_data), %l0
145 lduw [%l0 + %g5], %l1
149 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
150 bne,pn %icc, __handle_softirq
151 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
152 __handle_softirq_continue:
154 sethi %hi(0xf << 20), %l4
158 #ifdef CONFIG_TRACE_IRQFLAGS
159 brnz,pn %l4, rtrap_no_irq_enable
161 call trace_hardirqs_on
166 andcc %l1, TSTATE_PRIV, %l3
167 bne,pn %icc, to_kernel
170 /* We must hold IRQs off and atomically test schedule+signal
171 * state, then hold them off all the way back to userspace.
172 * If we are returning to kernel, none of this matters. Note
173 * that we are disabling interrupts via PSTATE_IE, not using
176 * If we do not do this, there is a window where we would do
177 * the tests, later the signal/resched event arrives but we do
178 * not process it since we are still in kernel mode. It would
179 * take until the next local IRQ before the signal/resched
180 * event would be handled.
182 * This also means that if we have to deal with performance
183 * counters or user windows, we have to redo all of these
184 * sched+signal checks with IRQs disabled.
186 to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
188 __handle_preemption_continue:
189 ldx [%g6 + TI_FLAGS], %l0
190 sethi %hi(_TIF_USER_WORK_MASK), %o0
191 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
193 sethi %hi(TSTATE_PEF), %o0
194 be,pt %xcc, user_nowork
196 andcc %l0, _TIF_NEED_RESCHED, %g0
197 bne,pn %xcc, __handle_preemption
198 andcc %l0, _TIF_SIGPENDING, %g0
199 bne,pn %xcc, __handle_signal
200 __handle_signal_continue:
201 ldub [%g6 + TI_WSAVED], %o2
202 brnz,pn %o2, __handle_user_windows
204 __handle_user_windows_continue:
205 ldx [%g6 + TI_FLAGS], %l5
206 andcc %l5, _TIF_PERFCTR, %g0
207 sethi %hi(TSTATE_PEF), %o0
208 bne,pn %xcc, __handle_perfctrs
209 __handle_perfctrs_continue:
212 /* This fpdepth clear is necessary for non-syscall rtraps only */
214 bne,pn %xcc, __handle_userfpu
215 stb %g0, [%g6 + TI_FPDEPTH]
216 __handle_userfpu_continue:
218 rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
219 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
221 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
222 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
223 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
227 /* Must do this before thread reg is clobbered below. */
228 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
230 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
231 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
233 /* Normal globals are restored, go to trap globals. */
234 661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
236 .section .sun4v_2insn_patch, "ax"
238 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
244 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
245 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
247 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
248 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
249 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
250 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
251 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
252 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
253 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
254 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
256 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
260 andn %l1, TSTATE_SYSCALL, %l1
261 wrpr %l1, %g0, %tstate
265 brnz,pn %l3, kern_rtt
266 mov PRIMARY_CONTEXT, %l7
268 661: ldxa [%l7 + %l7] ASI_DMMU, %l0
269 .section .sun4v_1insn_patch, "ax"
271 ldxa [%l7 + %l7] ASI_MMU, %l0
274 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
275 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
278 661: stxa %l0, [%l7] ASI_DMMU
279 .section .sun4v_1insn_patch, "ax"
281 stxa %l0, [%l7] ASI_MMU
284 sethi %hi(KERNBASE), %l7
290 wrpr %l2, %g0, %canrestore
291 wrpr %l1, %g0, %wstate
292 brnz,pt %l2, user_rtt_restore
293 wrpr %g0, %g0, %otherwin
295 ldx [%g6 + TI_FLAGS], %g3
296 wr %g0, ASI_AIUP, %asi
298 andcc %g3, _TIF_32BIT, %g0
300 bne,pt %xcc, user_rtt_fill_32bit
302 ba,a,pt %xcc, user_rtt_fill_64bit
311 wrpr %g2, 0x0, %wstate
313 /* We know %canrestore and %otherwin are both zero. */
315 sethi %hi(sparc64_kern_pri_context), %g2
316 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
317 mov PRIMARY_CONTEXT, %g1
319 661: stxa %g2, [%g1] ASI_DMMU
320 .section .sun4v_1insn_patch, "ax"
322 stxa %g2, [%g1] ASI_MMU
325 sethi %hi(KERNBASE), %g1
328 or %g4, FAULT_CODE_WINFIXUP, %g4
329 stb %g4, [%g6 + TI_FAULT_CODE]
330 stx %g5, [%g6 + TI_FAULT_ADDR]
336 .section .sun4v_1insn_patch, "ax"
341 wrpr %g0, RTRAP_PSTATE, %pstate
344 ldx [%g6 + TI_TASK], %g4
345 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
346 call do_sparc64_fault
347 add %sp, PTREGS_OFF, %o0
351 user_rtt_pre_restore:
357 rdpr %canrestore, %g1
358 wrpr %g1, 0x0, %cleanwin
362 kern_rtt: rdpr %canrestore, %g1
363 brz,pn %g1, kern_rtt_fill
366 stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
371 #ifdef CONFIG_PREEMPT
372 ldsw [%g6 + TI_PRE_COUNT], %l5
373 brnz %l5, kern_fpucheck
374 ldx [%g6 + TI_FLAGS], %l5
375 andcc %l5, _TIF_NEED_RESCHED, %g0
376 be,pt %xcc, kern_fpucheck
379 bne,pn %xcc, kern_fpucheck
380 sethi %hi(PREEMPT_ACTIVE), %l6
381 stw %l6, [%g6 + TI_PRE_COUNT]
385 stw %g0, [%g6 + TI_PRE_COUNT]
387 kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
388 brz,pt %l5, rt_continue
390 add %g6, TI_FPSAVED, %l6
391 ldub [%l6 + %o0], %l2
395 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
397 and %l2, FPRS_DL, %l6
398 andcc %l2, FPRS_FEF, %g0
403 wr %g1, FPRS_FEF, %fprs
405 add %g6, TI_XFSR, %o1
407 add %g6, TI_FPREGS, %o3
409 add %g6, TI_FPREGS+0x40, %o4
412 ldda [%o3 + %o2] ASI_BLK_P, %f0
413 ldda [%o4 + %o2] ASI_BLK_P, %f16
415 1: andcc %l2, FPRS_DU, %g0
420 ldda [%o3 + %o2] ASI_BLK_P, %f32
421 ldda [%o4 + %o2] ASI_BLK_P, %f48
423 ldx [%o1 + %o5], %fsr
424 2: stb %l5, [%g6 + TI_FPDEPTH]
425 ba,pt %xcc, rt_continue
427 5: wr %g0, FPRS_FEF, %fprs
430 add %g6, TI_FPREGS+0x80, %o3
431 add %g6, TI_FPREGS+0xc0, %o4
433 ldda [%o3 + %o2] ASI_BLK_P, %f32
434 ldda [%o4 + %o2] ASI_BLK_P, %f48
436 wr %g0, FPRS_DU, %fprs
437 ba,pt %xcc, rt_continue
438 stb %l5, [%g6 + TI_FPDEPTH]