1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 /*****************************************************************************
11 * Support for the SFE4001 NIC: driver code for the PCA9539 I/O expander that
12 * controls the PHY power rails, and for the MAX6647 temp. sensor used to check
15 #include <linux/delay.h>
20 #include "falcon_hwdefs.h"
23 /**************************************************************************
25 * I2C IO Expander device
27 **************************************************************************/
32 #define P0_INVERT 0x04
33 #define P0_CONFIG 0x06
35 #define P0_EN_1V0X_LBN 0
36 #define P0_EN_1V0X_WIDTH 1
37 #define P0_EN_1V2_LBN 1
38 #define P0_EN_1V2_WIDTH 1
39 #define P0_EN_2V5_LBN 2
40 #define P0_EN_2V5_WIDTH 1
41 #define P0_EN_3V3X_LBN 3
42 #define P0_EN_3V3X_WIDTH 1
43 #define P0_EN_5V_LBN 4
44 #define P0_EN_5V_WIDTH 1
45 #define P0_SHORTEN_JTAG_LBN 5
46 #define P0_SHORTEN_JTAG_WIDTH 1
47 #define P0_X_TRST_LBN 6
48 #define P0_X_TRST_WIDTH 1
49 #define P0_DSP_RESET_LBN 7
50 #define P0_DSP_RESET_WIDTH 1
54 #define P1_INVERT 0x05
55 #define P1_CONFIG 0x07
57 #define P1_AFE_PWD_LBN 0
58 #define P1_AFE_PWD_WIDTH 1
59 #define P1_DSP_PWD25_LBN 1
60 #define P1_DSP_PWD25_WIDTH 1
61 #define P1_RESERVED_LBN 2
62 #define P1_RESERVED_WIDTH 2
63 #define P1_SPARE_LBN 4
64 #define P1_SPARE_WIDTH 4
67 /**************************************************************************
71 **************************************************************************/
98 #define MAX6647_BUSY (1 << 7) /* ADC is converting */
99 #define MAX6647_LHIGH (1 << 6) /* Local high temp. alarm */
100 #define MAX6647_LLOW (1 << 5) /* Local low temp. alarm */
101 #define MAX6647_RHIGH (1 << 4) /* Remote high temp. alarm */
102 #define MAX6647_RLOW (1 << 3) /* Remote low temp. alarm */
103 #define MAX6647_FAULT (1 << 2) /* DXN/DXP short/open circuit */
104 #define MAX6647_EOT (1 << 1) /* Remote junction overtemp. */
105 #define MAX6647_IOT (1 << 0) /* Local junction overtemp. */
107 static const u8 xgphy_max_temperature = 90;
109 void sfe4001_poweroff(struct efx_nic *efx)
111 struct efx_i2c_interface *i2c = &efx->i2c;
115 EFX_INFO(efx, "%s\n", __func__);
117 /* Turn off all power rails */
119 efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1);
121 /* Disable port 1 outputs on IO expander */
123 efx_i2c_write(i2c, PCA9539, P1_CONFIG, &cfg, 1);
125 /* Disable port 0 outputs on IO expander */
127 efx_i2c_write(i2c, PCA9539, P0_CONFIG, &cfg, 1);
129 /* Clear any over-temperature alert */
130 efx_i2c_read(i2c, MAX6647, RSL, &in, 1);
133 /* The P0_EN_3V3X line on SFE4001 boards (from A2 onward) is connected
134 * to the FLASH_CFG_1 input on the DSP. We must keep it high at power-
135 * up to allow writing the flash (done through MDIO from userland).
137 unsigned int sfe4001_phy_flash_cfg;
138 module_param_named(phy_flash_cfg, sfe4001_phy_flash_cfg, uint, 0444);
139 MODULE_PARM_DESC(phy_flash_cfg,
140 "Force PHY to enter flash configuration mode");
142 /* This board uses an I2C expander to provider power to the PHY, which needs to
143 * be turned on before the PHY can be used.
144 * Context: Process context, rtnl lock held
146 int sfe4001_poweron(struct efx_nic *efx)
148 struct efx_i2c_interface *i2c = &efx->i2c;
154 /* 10Xpress has fixed-function LED pins, so there is no board-specific
156 efx->board_info.blink = tenxpress_phy_blink;
158 /* Ensure that XGXS and XAUI SerDes are held in reset */
159 EFX_POPULATE_DWORD_7(reg, XX_PWRDNA_EN, 1,
166 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
169 /* Set DSP over-temperature alert threshold */
170 EFX_INFO(efx, "DSP cut-out at %dC\n", xgphy_max_temperature);
171 rc = efx_i2c_write(i2c, MAX6647, WLHO,
172 &xgphy_max_temperature, 1);
176 /* Read it back and verify */
177 rc = efx_i2c_read(i2c, MAX6647, RLHN, &in, 1);
180 if (in != xgphy_max_temperature) {
185 /* Clear any previous over-temperature alert */
186 rc = efx_i2c_read(i2c, MAX6647, RSL, &in, 1);
190 /* Enable port 0 and port 1 outputs on IO expander */
192 rc = efx_i2c_write(i2c, PCA9539, P0_CONFIG, &cfg, 1);
195 cfg = 0xff & ~(1 << P1_SPARE_LBN);
196 rc = efx_i2c_write(i2c, PCA9539, P1_CONFIG, &cfg, 1);
200 /* Turn all power off then wait 1 sec. This ensures PHY is reset */
201 out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) |
202 (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) |
203 (0 << P0_EN_1V0X_LBN));
204 rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1);
208 schedule_timeout_uninterruptible(HZ);
211 /* Turn on 1.2V, 2.5V, 3.3V and 5V power rails */
212 out = 0xff & ~((1 << P0_EN_1V2_LBN) | (1 << P0_EN_2V5_LBN) |
213 (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN) |
214 (1 << P0_X_TRST_LBN));
215 if (sfe4001_phy_flash_cfg)
216 out |= 1 << P0_EN_3V3X_LBN;
218 rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1);
223 /* Turn on 1V power rail */
224 out &= ~(1 << P0_EN_1V0X_LBN);
225 rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1);
229 EFX_INFO(efx, "waiting for power (attempt %d)...\n", count);
231 schedule_timeout_uninterruptible(HZ);
233 /* Check DSP is powered */
234 rc = efx_i2c_read(i2c, PCA9539, P1_IN, &in, 1);
237 if (in & (1 << P1_AFE_PWD_LBN))
240 /* DSP doesn't look powered in flash config mode */
241 if (sfe4001_phy_flash_cfg)
243 } while (++count < 20);
245 EFX_INFO(efx, "timed out waiting for power\n");
250 EFX_INFO(efx, "PHY is powered on\n");
254 /* Turn off all power rails */
256 efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1);
257 /* Disable port 1 outputs on IO expander */
259 efx_i2c_write(i2c, PCA9539, P1_CONFIG, &out, 1);
261 /* Disable port 0 outputs on IO expander */
263 efx_i2c_write(i2c, PCA9539, P0_CONFIG, &out, 1);