3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
92 static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
103 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
105 /* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109 #define RATETAB_ENT(_rateid, _flags) \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
120 static struct ieee80211_rate __b43_ratetable[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
135 #define b43_a_ratetable (__b43_ratetable + 4)
136 #define b43_a_ratetable_size 8
137 #define b43_b_ratetable (__b43_ratetable + 0)
138 #define b43_b_ratetable_size 4
139 #define b43_g_ratetable (__b43_ratetable + 0)
140 #define b43_g_ratetable_size 12
142 #define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
147 .max_antenna_gain = 0, \
150 static struct ieee80211_channel b43_2ghz_chantable[] = {
168 #define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
173 .max_antenna_gain = 0, \
176 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
234 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
257 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
265 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
273 static struct ieee80211_supported_band b43_band_2GHz = {
274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
281 static void b43_wireless_core_exit(struct b43_wldev *dev);
282 static int b43_wireless_core_init(struct b43_wldev *dev);
283 static void b43_wireless_core_stop(struct b43_wldev *dev);
284 static int b43_wireless_core_start(struct b43_wldev *dev);
286 static int b43_ratelimit(struct b43_wl *wl)
288 if (!wl || !wl->current_dev)
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
297 void b43info(struct b43_wl *wl, const char *fmt, ...)
301 if (!b43_ratelimit(wl))
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
310 void b43err(struct b43_wl *wl, const char *fmt, ...)
314 if (!b43_ratelimit(wl))
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
323 void b43warn(struct b43_wl *wl, const char *fmt, ...)
327 if (!b43_ratelimit(wl))
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
337 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
353 B43_WARN_ON(offset % 4 != 0);
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
364 static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
369 /* "offset" is the WORD offset. */
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
376 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
378 struct b43_wl *wl = dev->wl;
382 spin_lock_irqsave(&wl->shm_lock, flags);
383 if (routing == B43_SHM_SHARED) {
384 B43_WARN_ON(offset & 0x0001);
385 if (offset & 0x0003) {
386 /* Unaligned access */
387 b43_shm_control_word(dev, routing, offset >> 2);
388 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
390 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
391 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
397 b43_shm_control_word(dev, routing, offset);
398 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
400 spin_unlock_irqrestore(&wl->shm_lock, flags);
405 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
407 struct b43_wl *wl = dev->wl;
411 spin_lock_irqsave(&wl->shm_lock, flags);
412 if (routing == B43_SHM_SHARED) {
413 B43_WARN_ON(offset & 0x0001);
414 if (offset & 0x0003) {
415 /* Unaligned access */
416 b43_shm_control_word(dev, routing, offset >> 2);
417 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
423 b43_shm_control_word(dev, routing, offset);
424 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
426 spin_unlock_irqrestore(&wl->shm_lock, flags);
431 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
433 struct b43_wl *wl = dev->wl;
436 spin_lock_irqsave(&wl->shm_lock, flags);
437 if (routing == B43_SHM_SHARED) {
438 B43_WARN_ON(offset & 0x0001);
439 if (offset & 0x0003) {
440 /* Unaligned access */
441 b43_shm_control_word(dev, routing, offset >> 2);
442 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
443 (value >> 16) & 0xffff);
444 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
445 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
450 b43_shm_control_word(dev, routing, offset);
451 b43_write32(dev, B43_MMIO_SHM_DATA, value);
453 spin_unlock_irqrestore(&wl->shm_lock, flags);
456 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
458 struct b43_wl *wl = dev->wl;
461 spin_lock_irqsave(&wl->shm_lock, flags);
462 if (routing == B43_SHM_SHARED) {
463 B43_WARN_ON(offset & 0x0001);
464 if (offset & 0x0003) {
465 /* Unaligned access */
466 b43_shm_control_word(dev, routing, offset >> 2);
467 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
472 b43_shm_control_word(dev, routing, offset);
473 b43_write16(dev, B43_MMIO_SHM_DATA, value);
475 spin_unlock_irqrestore(&wl->shm_lock, flags);
479 u64 b43_hf_read(struct b43_wldev * dev)
483 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
485 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
487 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
492 /* Write HostFlags */
493 void b43_hf_write(struct b43_wldev *dev, u64 value)
497 lo = (value & 0x00000000FFFFULL);
498 mi = (value & 0x0000FFFF0000ULL) >> 16;
499 hi = (value & 0xFFFF00000000ULL) >> 32;
500 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
501 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
502 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
505 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
507 /* We need to be careful. As we read the TSF from multiple
508 * registers, we should take care of register overflows.
509 * In theory, the whole tsf read process should be atomic.
510 * We try to be atomic here, by restaring the read process,
511 * if any of the high registers changed (overflew).
513 if (dev->dev->id.revision >= 3) {
514 u32 low, high, high2;
517 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
518 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
519 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
520 } while (unlikely(high != high2));
528 u16 test1, test2, test3;
531 v3 = b43_read16(dev, B43_MMIO_TSF_3);
532 v2 = b43_read16(dev, B43_MMIO_TSF_2);
533 v1 = b43_read16(dev, B43_MMIO_TSF_1);
534 v0 = b43_read16(dev, B43_MMIO_TSF_0);
536 test3 = b43_read16(dev, B43_MMIO_TSF_3);
537 test2 = b43_read16(dev, B43_MMIO_TSF_2);
538 test1 = b43_read16(dev, B43_MMIO_TSF_1);
539 } while (v3 != test3 || v2 != test2 || v1 != test1);
553 static void b43_time_lock(struct b43_wldev *dev)
557 macctl = b43_read32(dev, B43_MMIO_MACCTL);
558 macctl |= B43_MACCTL_TBTTHOLD;
559 b43_write32(dev, B43_MMIO_MACCTL, macctl);
560 /* Commit the write */
561 b43_read32(dev, B43_MMIO_MACCTL);
564 static void b43_time_unlock(struct b43_wldev *dev)
568 macctl = b43_read32(dev, B43_MMIO_MACCTL);
569 macctl &= ~B43_MACCTL_TBTTHOLD;
570 b43_write32(dev, B43_MMIO_MACCTL, macctl);
571 /* Commit the write */
572 b43_read32(dev, B43_MMIO_MACCTL);
575 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
577 /* Be careful with the in-progress timer.
578 * First zero out the low register, so we have a full
579 * register-overflow duration to complete the operation.
581 if (dev->dev->id.revision >= 3) {
582 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
583 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
585 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
587 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
589 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
591 u16 v0 = (tsf & 0x000000000000FFFFULL);
592 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
593 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
594 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
596 b43_write16(dev, B43_MMIO_TSF_0, 0);
598 b43_write16(dev, B43_MMIO_TSF_3, v3);
600 b43_write16(dev, B43_MMIO_TSF_2, v2);
602 b43_write16(dev, B43_MMIO_TSF_1, v1);
604 b43_write16(dev, B43_MMIO_TSF_0, v0);
608 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
611 b43_tsf_write_locked(dev, tsf);
612 b43_time_unlock(dev);
616 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
618 static const u8 zero_addr[ETH_ALEN] = { 0 };
625 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
629 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
638 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
642 u8 mac_bssid[ETH_ALEN * 2];
646 bssid = dev->wl->bssid;
647 mac = dev->wl->mac_addr;
649 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
651 memcpy(mac_bssid, mac, ETH_ALEN);
652 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
654 /* Write our MAC address and BSSID to template ram */
655 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
656 tmp = (u32) (mac_bssid[i + 0]);
657 tmp |= (u32) (mac_bssid[i + 1]) << 8;
658 tmp |= (u32) (mac_bssid[i + 2]) << 16;
659 tmp |= (u32) (mac_bssid[i + 3]) << 24;
660 b43_ram_write(dev, 0x20 + i, tmp);
664 static void b43_upload_card_macaddress(struct b43_wldev *dev)
666 b43_write_mac_bssid_templates(dev);
667 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
670 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
672 /* slot_time is in usec. */
673 if (dev->phy.type != B43_PHYTYPE_G)
675 b43_write16(dev, 0x684, 510 + slot_time);
676 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
679 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
681 b43_set_slot_time(dev, 9);
685 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
687 b43_set_slot_time(dev, 20);
691 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
692 * Returns the _previously_ enabled IRQ mask.
694 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
698 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
699 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
704 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
705 * Returns the _previously_ enabled IRQ mask.
707 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
711 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
712 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
717 /* Synchronize IRQ top- and bottom-half.
718 * IRQs must be masked before calling this.
719 * This must not be called with the irq_lock held.
721 static void b43_synchronize_irq(struct b43_wldev *dev)
723 synchronize_irq(dev->dev->irq);
724 tasklet_kill(&dev->isr_tasklet);
727 /* DummyTransmission function, as documented on
728 * http://bcm-specs.sipsolutions.net/DummyTransmission
730 void b43_dummy_transmission(struct b43_wldev *dev)
732 struct b43_wl *wl = dev->wl;
733 struct b43_phy *phy = &dev->phy;
734 unsigned int i, max_loop;
747 buffer[0] = 0x000201CC;
752 buffer[0] = 0x000B846E;
759 spin_lock_irq(&wl->irq_lock);
760 write_lock(&wl->tx_lock);
762 for (i = 0; i < 5; i++)
763 b43_ram_write(dev, i * 4, buffer[i]);
766 b43_read32(dev, B43_MMIO_MACCTL);
768 b43_write16(dev, 0x0568, 0x0000);
769 b43_write16(dev, 0x07C0, 0x0000);
770 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
771 b43_write16(dev, 0x050C, value);
772 b43_write16(dev, 0x0508, 0x0000);
773 b43_write16(dev, 0x050A, 0x0000);
774 b43_write16(dev, 0x054C, 0x0000);
775 b43_write16(dev, 0x056A, 0x0014);
776 b43_write16(dev, 0x0568, 0x0826);
777 b43_write16(dev, 0x0500, 0x0000);
778 b43_write16(dev, 0x0502, 0x0030);
780 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
781 b43_radio_write16(dev, 0x0051, 0x0017);
782 for (i = 0x00; i < max_loop; i++) {
783 value = b43_read16(dev, 0x050E);
788 for (i = 0x00; i < 0x0A; i++) {
789 value = b43_read16(dev, 0x050E);
794 for (i = 0x00; i < 0x0A; i++) {
795 value = b43_read16(dev, 0x0690);
796 if (!(value & 0x0100))
800 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
801 b43_radio_write16(dev, 0x0051, 0x0037);
803 write_unlock(&wl->tx_lock);
804 spin_unlock_irq(&wl->irq_lock);
807 static void key_write(struct b43_wldev *dev,
808 u8 index, u8 algorithm, const u8 * key)
815 /* Key index/algo block */
816 kidx = b43_kidx_to_fw(dev, index);
817 value = ((kidx << 4) | algorithm);
818 b43_shm_write16(dev, B43_SHM_SHARED,
819 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
821 /* Write the key to the Key Table Pointer offset */
822 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
823 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
825 value |= (u16) (key[i + 1]) << 8;
826 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
830 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
832 u32 addrtmp[2] = { 0, 0, };
833 u8 per_sta_keys_start = 8;
835 if (b43_new_kidx_api(dev))
836 per_sta_keys_start = 4;
838 B43_WARN_ON(index < per_sta_keys_start);
839 /* We have two default TX keys and possibly two default RX keys.
840 * Physical mac 0 is mapped to physical key 4 or 8, depending
841 * on the firmware version.
842 * So we must adjust the index here.
844 index -= per_sta_keys_start;
847 addrtmp[0] = addr[0];
848 addrtmp[0] |= ((u32) (addr[1]) << 8);
849 addrtmp[0] |= ((u32) (addr[2]) << 16);
850 addrtmp[0] |= ((u32) (addr[3]) << 24);
851 addrtmp[1] = addr[4];
852 addrtmp[1] |= ((u32) (addr[5]) << 8);
855 if (dev->dev->id.revision >= 5) {
856 /* Receive match transmitter address mechanism */
857 b43_shm_write32(dev, B43_SHM_RCMTA,
858 (index * 2) + 0, addrtmp[0]);
859 b43_shm_write16(dev, B43_SHM_RCMTA,
860 (index * 2) + 1, addrtmp[1]);
862 /* RXE (Receive Engine) and
863 * PSM (Programmable State Machine) mechanism
866 /* TODO write to RCM 16, 19, 22 and 25 */
868 b43_shm_write32(dev, B43_SHM_SHARED,
869 B43_SHM_SH_PSM + (index * 6) + 0,
871 b43_shm_write16(dev, B43_SHM_SHARED,
872 B43_SHM_SH_PSM + (index * 6) + 4,
878 static void do_key_write(struct b43_wldev *dev,
879 u8 index, u8 algorithm,
880 const u8 * key, size_t key_len, const u8 * mac_addr)
882 u8 buf[B43_SEC_KEYSIZE] = { 0, };
883 u8 per_sta_keys_start = 8;
885 if (b43_new_kidx_api(dev))
886 per_sta_keys_start = 4;
888 B43_WARN_ON(index >= dev->max_nr_keys);
889 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
891 if (index >= per_sta_keys_start)
892 keymac_write(dev, index, NULL); /* First zero out mac. */
894 memcpy(buf, key, key_len);
895 key_write(dev, index, algorithm, buf);
896 if (index >= per_sta_keys_start)
897 keymac_write(dev, index, mac_addr);
899 dev->key[index].algorithm = algorithm;
902 static int b43_key_write(struct b43_wldev *dev,
903 int index, u8 algorithm,
904 const u8 * key, size_t key_len,
906 struct ieee80211_key_conf *keyconf)
911 if (key_len > B43_SEC_KEYSIZE)
913 for (i = 0; i < dev->max_nr_keys; i++) {
914 /* Check that we don't already have this key. */
915 B43_WARN_ON(dev->key[i].keyconf == keyconf);
918 /* Either pairwise key or address is 00:00:00:00:00:00
919 * for transmit-only keys. Search the index. */
920 if (b43_new_kidx_api(dev))
924 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
925 if (!dev->key[i].keyconf) {
932 b43err(dev->wl, "Out of hardware key memory\n");
936 B43_WARN_ON(index > 3);
938 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
939 if ((index <= 3) && !b43_new_kidx_api(dev)) {
941 B43_WARN_ON(mac_addr);
942 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
944 keyconf->hw_key_idx = index;
945 dev->key[index].keyconf = keyconf;
950 static int b43_key_clear(struct b43_wldev *dev, int index)
952 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
954 do_key_write(dev, index, B43_SEC_ALGO_NONE,
955 NULL, B43_SEC_KEYSIZE, NULL);
956 if ((index <= 3) && !b43_new_kidx_api(dev)) {
957 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
958 NULL, B43_SEC_KEYSIZE, NULL);
960 dev->key[index].keyconf = NULL;
965 static void b43_clear_keys(struct b43_wldev *dev)
969 for (i = 0; i < dev->max_nr_keys; i++)
970 b43_key_clear(dev, i);
973 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
981 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
982 (ps_flags & B43_PS_DISABLED));
983 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
985 if (ps_flags & B43_PS_ENABLED) {
987 } else if (ps_flags & B43_PS_DISABLED) {
990 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
991 // and thus is not an AP and we are associated, set bit 25
993 if (ps_flags & B43_PS_AWAKE) {
995 } else if (ps_flags & B43_PS_ASLEEP) {
998 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
999 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1000 // successful, set bit26
1003 /* FIXME: For now we force awake-on and hwps-off */
1007 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1009 macctl |= B43_MACCTL_HWPS;
1011 macctl &= ~B43_MACCTL_HWPS;
1013 macctl |= B43_MACCTL_AWAKE;
1015 macctl &= ~B43_MACCTL_AWAKE;
1016 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1018 b43_read32(dev, B43_MMIO_MACCTL);
1019 if (awake && dev->dev->id.revision >= 5) {
1020 /* Wait for the microcode to wake up. */
1021 for (i = 0; i < 100; i++) {
1022 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1023 B43_SHM_SH_UCODESTAT);
1024 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1031 /* Turn the Analog ON/OFF */
1032 static void b43_switch_analog(struct b43_wldev *dev, int on)
1034 switch (dev->phy.type) {
1037 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
1040 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1048 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1053 flags |= B43_TMSLOW_PHYCLKEN;
1054 flags |= B43_TMSLOW_PHYRESET;
1055 ssb_device_enable(dev->dev, flags);
1056 msleep(2); /* Wait for the PLL to turn on. */
1058 /* Now take the PHY out of Reset again */
1059 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1060 tmslow |= SSB_TMSLOW_FGC;
1061 tmslow &= ~B43_TMSLOW_PHYRESET;
1062 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1063 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1065 tmslow &= ~SSB_TMSLOW_FGC;
1066 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1067 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1070 /* Turn Analog ON */
1071 b43_switch_analog(dev, 1);
1073 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1074 macctl &= ~B43_MACCTL_GMODE;
1075 if (flags & B43_TMSLOW_GMODE)
1076 macctl |= B43_MACCTL_GMODE;
1077 macctl |= B43_MACCTL_IHR_ENABLED;
1078 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1081 static void handle_irq_transmit_status(struct b43_wldev *dev)
1085 struct b43_txstatus stat;
1088 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1089 if (!(v0 & 0x00000001))
1091 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1093 stat.cookie = (v0 >> 16);
1094 stat.seq = (v1 & 0x0000FFFF);
1095 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1096 tmp = (v0 & 0x0000FFFF);
1097 stat.frame_count = ((tmp & 0xF000) >> 12);
1098 stat.rts_count = ((tmp & 0x0F00) >> 8);
1099 stat.supp_reason = ((tmp & 0x001C) >> 2);
1100 stat.pm_indicated = !!(tmp & 0x0080);
1101 stat.intermediate = !!(tmp & 0x0040);
1102 stat.for_ampdu = !!(tmp & 0x0020);
1103 stat.acked = !!(tmp & 0x0002);
1105 b43_handle_txstatus(dev, &stat);
1109 static void drain_txstatus_queue(struct b43_wldev *dev)
1113 if (dev->dev->id.revision < 5)
1115 /* Read all entries from the microcode TXstatus FIFO
1116 * and throw them away.
1119 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1120 if (!(dummy & 0x00000001))
1122 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1126 static u32 b43_jssi_read(struct b43_wldev *dev)
1130 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1132 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1137 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1139 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1140 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1143 static void b43_generate_noise_sample(struct b43_wldev *dev)
1145 b43_jssi_write(dev, 0x7F7F7F7F);
1146 b43_write32(dev, B43_MMIO_MACCMD,
1147 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1150 static void b43_calculate_link_quality(struct b43_wldev *dev)
1152 /* Top half of Link Quality calculation. */
1154 if (dev->noisecalc.calculation_running)
1156 dev->noisecalc.calculation_running = 1;
1157 dev->noisecalc.nr_samples = 0;
1159 b43_generate_noise_sample(dev);
1162 static void handle_irq_noise(struct b43_wldev *dev)
1164 struct b43_phy *phy = &dev->phy;
1170 /* Bottom half of Link Quality calculation. */
1172 /* Possible race condition: It might be possible that the user
1173 * changed to a different channel in the meantime since we
1174 * started the calculation. We ignore that fact, since it's
1175 * not really that much of a problem. The background noise is
1176 * an estimation only anyway. Slightly wrong results will get damped
1177 * by the averaging of the 8 sample rounds. Additionally the
1178 * value is shortlived. So it will be replaced by the next noise
1179 * calculation round soon. */
1181 B43_WARN_ON(!dev->noisecalc.calculation_running);
1182 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1183 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1184 noise[2] == 0x7F || noise[3] == 0x7F)
1187 /* Get the noise samples. */
1188 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1189 i = dev->noisecalc.nr_samples;
1190 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1191 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1192 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1193 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1194 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1195 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1196 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1197 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1198 dev->noisecalc.nr_samples++;
1199 if (dev->noisecalc.nr_samples == 8) {
1200 /* Calculate the Link Quality by the noise samples. */
1202 for (i = 0; i < 8; i++) {
1203 for (j = 0; j < 4; j++)
1204 average += dev->noisecalc.samples[i][j];
1210 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1211 tmp = (tmp / 128) & 0x1F;
1221 dev->stats.link_noise = average;
1222 dev->noisecalc.calculation_running = 0;
1226 b43_generate_noise_sample(dev);
1229 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1231 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1234 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1235 b43_power_saving_ctl_bits(dev, 0);
1237 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1241 static void handle_irq_atim_end(struct b43_wldev *dev)
1243 if (dev->dfq_valid) {
1244 b43_write32(dev, B43_MMIO_MACCMD,
1245 b43_read32(dev, B43_MMIO_MACCMD)
1246 | B43_MACCMD_DFQ_VALID);
1251 static void handle_irq_pmq(struct b43_wldev *dev)
1258 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1259 if (!(tmp & 0x00000008))
1262 /* 16bit write is odd, but correct. */
1263 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1266 static void b43_write_template_common(struct b43_wldev *dev,
1267 const u8 * data, u16 size,
1269 u16 shm_size_offset, u8 rate)
1272 struct b43_plcp_hdr4 plcp;
1275 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1276 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1277 ram_offset += sizeof(u32);
1278 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1279 * So leave the first two bytes of the next write blank.
1281 tmp = (u32) (data[0]) << 16;
1282 tmp |= (u32) (data[1]) << 24;
1283 b43_ram_write(dev, ram_offset, tmp);
1284 ram_offset += sizeof(u32);
1285 for (i = 2; i < size; i += sizeof(u32)) {
1286 tmp = (u32) (data[i + 0]);
1288 tmp |= (u32) (data[i + 1]) << 8;
1290 tmp |= (u32) (data[i + 2]) << 16;
1292 tmp |= (u32) (data[i + 3]) << 24;
1293 b43_ram_write(dev, ram_offset + i - 2, tmp);
1295 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1296 size + sizeof(struct b43_plcp_hdr6));
1299 /* Check if the use of the antenna that ieee80211 told us to
1300 * use is possible. This will fall back to DEFAULT.
1301 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1302 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1307 if (antenna_nr == 0) {
1308 /* Zero means "use default antenna". That's always OK. */
1312 /* Get the mask of available antennas. */
1314 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1316 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1318 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1319 /* This antenna is not available. Fall back to default. */
1326 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
1328 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
1330 case 0: /* default/diversity */
1331 return B43_ANTENNA_DEFAULT;
1332 case 1: /* Antenna 0 */
1333 return B43_ANTENNA0;
1334 case 2: /* Antenna 1 */
1335 return B43_ANTENNA1;
1336 case 3: /* Antenna 2 */
1337 return B43_ANTENNA2;
1338 case 4: /* Antenna 3 */
1339 return B43_ANTENNA3;
1341 return B43_ANTENNA_DEFAULT;
1345 /* Convert a b43 antenna number value to the PHY TX control value. */
1346 static u16 b43_antenna_to_phyctl(int antenna)
1350 return B43_TXH_PHY_ANT0;
1352 return B43_TXH_PHY_ANT1;
1354 return B43_TXH_PHY_ANT2;
1356 return B43_TXH_PHY_ANT3;
1357 case B43_ANTENNA_AUTO:
1358 return B43_TXH_PHY_ANT01AUTO;
1364 static void b43_write_beacon_template(struct b43_wldev *dev,
1366 u16 shm_size_offset)
1368 unsigned int i, len, variable_len;
1369 const struct ieee80211_mgmt *bcn;
1376 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1377 len = min((size_t) dev->wl->current_beacon->len,
1378 0x200 - sizeof(struct b43_plcp_hdr6));
1379 rate = dev->wl->beacon_txctl.tx_rate->hw_value;
1381 b43_write_template_common(dev, (const u8 *)bcn,
1382 len, ram_offset, shm_size_offset, rate);
1384 /* Write the PHY TX control parameters. */
1385 antenna = b43_antenna_from_ieee80211(dev,
1386 dev->wl->beacon_txctl.antenna_sel_tx);
1387 antenna = b43_antenna_to_phyctl(antenna);
1388 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1389 /* We can't send beacons with short preamble. Would get PHY errors. */
1390 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1391 ctl &= ~B43_TXH_PHY_ANT;
1392 ctl &= ~B43_TXH_PHY_ENC;
1394 if (b43_is_cck_rate(rate))
1395 ctl |= B43_TXH_PHY_ENC_CCK;
1397 ctl |= B43_TXH_PHY_ENC_OFDM;
1398 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1400 /* Find the position of the TIM and the DTIM_period value
1401 * and write them to SHM. */
1402 ie = bcn->u.beacon.variable;
1403 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1404 for (i = 0; i < variable_len - 2; ) {
1405 uint8_t ie_id, ie_len;
1412 /* This is the TIM Information Element */
1414 /* Check whether the ie_len is in the beacon data range. */
1415 if (variable_len < ie_len + 2 + i)
1417 /* A valid TIM is at least 4 bytes long. */
1422 tim_position = sizeof(struct b43_plcp_hdr6);
1423 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1426 dtim_period = ie[i + 3];
1428 b43_shm_write16(dev, B43_SHM_SHARED,
1429 B43_SHM_SH_TIMBPOS, tim_position);
1430 b43_shm_write16(dev, B43_SHM_SHARED,
1431 B43_SHM_SH_DTIMPER, dtim_period);
1437 b43warn(dev->wl, "Did not find a valid TIM IE in "
1438 "the beacon template packet. AP or IBSS operation "
1439 "may be broken.\n");
1441 b43dbg(dev->wl, "Updated beacon template\n");
1444 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1445 u16 shm_offset, u16 size,
1446 struct ieee80211_rate *rate)
1448 struct b43_plcp_hdr4 plcp;
1453 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1454 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1457 /* Write PLCP in two parts and timing for packet transfer */
1458 tmp = le32_to_cpu(plcp.data);
1459 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1460 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1461 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1464 /* Instead of using custom probe response template, this function
1465 * just patches custom beacon template by:
1466 * 1) Changing packet type
1467 * 2) Patching duration field
1470 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1472 struct ieee80211_rate *rate)
1476 u16 src_size, elem_size, src_pos, dest_pos;
1478 struct ieee80211_hdr *hdr;
1481 src_size = dev->wl->current_beacon->len;
1482 src_data = (const u8 *)dev->wl->current_beacon->data;
1484 /* Get the start offset of the variable IEs in the packet. */
1485 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1486 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1488 if (B43_WARN_ON(src_size < ie_start))
1491 dest_data = kmalloc(src_size, GFP_ATOMIC);
1492 if (unlikely(!dest_data))
1495 /* Copy the static data and all Information Elements, except the TIM. */
1496 memcpy(dest_data, src_data, ie_start);
1498 dest_pos = ie_start;
1499 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1500 elem_size = src_data[src_pos + 1] + 2;
1501 if (src_data[src_pos] == 5) {
1502 /* This is the TIM. */
1505 memcpy(dest_data + dest_pos, src_data + src_pos,
1507 dest_pos += elem_size;
1509 *dest_size = dest_pos;
1510 hdr = (struct ieee80211_hdr *)dest_data;
1512 /* Set the frame control. */
1513 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1514 IEEE80211_STYPE_PROBE_RESP);
1515 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1516 dev->wl->vif, *dest_size,
1518 hdr->duration_id = dur;
1523 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1525 u16 shm_size_offset,
1526 struct ieee80211_rate *rate)
1528 const u8 *probe_resp_data;
1531 size = dev->wl->current_beacon->len;
1532 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1533 if (unlikely(!probe_resp_data))
1536 /* Looks like PLCP headers plus packet timings are stored for
1537 * all possible basic rates
1539 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1540 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1541 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1542 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1544 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1545 b43_write_template_common(dev, probe_resp_data,
1546 size, ram_offset, shm_size_offset,
1548 kfree(probe_resp_data);
1551 static void b43_upload_beacon0(struct b43_wldev *dev)
1553 struct b43_wl *wl = dev->wl;
1555 if (wl->beacon0_uploaded)
1557 b43_write_beacon_template(dev, 0x68, 0x18);
1558 /* FIXME: Probe resp upload doesn't really belong here,
1559 * but we don't use that feature anyway. */
1560 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1561 &__b43_ratetable[3]);
1562 wl->beacon0_uploaded = 1;
1565 static void b43_upload_beacon1(struct b43_wldev *dev)
1567 struct b43_wl *wl = dev->wl;
1569 if (wl->beacon1_uploaded)
1571 b43_write_beacon_template(dev, 0x468, 0x1A);
1572 wl->beacon1_uploaded = 1;
1575 static void handle_irq_beacon(struct b43_wldev *dev)
1577 struct b43_wl *wl = dev->wl;
1578 u32 cmd, beacon0_valid, beacon1_valid;
1580 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1583 /* This is the bottom half of the asynchronous beacon update. */
1585 /* Ignore interrupt in the future. */
1586 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1588 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1589 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1590 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1592 /* Schedule interrupt manually, if busy. */
1593 if (beacon0_valid && beacon1_valid) {
1594 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1595 dev->irq_savedstate |= B43_IRQ_BEACON;
1599 if (unlikely(wl->beacon_templates_virgin)) {
1600 /* We never uploaded a beacon before.
1601 * Upload both templates now, but only mark one valid. */
1602 wl->beacon_templates_virgin = 0;
1603 b43_upload_beacon0(dev);
1604 b43_upload_beacon1(dev);
1605 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1606 cmd |= B43_MACCMD_BEACON0_VALID;
1607 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1609 if (!beacon0_valid) {
1610 b43_upload_beacon0(dev);
1611 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1612 cmd |= B43_MACCMD_BEACON0_VALID;
1613 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1614 } else if (!beacon1_valid) {
1615 b43_upload_beacon1(dev);
1616 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1617 cmd |= B43_MACCMD_BEACON1_VALID;
1618 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1623 static void b43_beacon_update_trigger_work(struct work_struct *work)
1625 struct b43_wl *wl = container_of(work, struct b43_wl,
1626 beacon_update_trigger);
1627 struct b43_wldev *dev;
1629 mutex_lock(&wl->mutex);
1630 dev = wl->current_dev;
1631 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1632 spin_lock_irq(&wl->irq_lock);
1633 /* update beacon right away or defer to irq */
1634 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1635 handle_irq_beacon(dev);
1636 /* The handler might have updated the IRQ mask. */
1637 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1638 dev->irq_savedstate);
1640 spin_unlock_irq(&wl->irq_lock);
1642 mutex_unlock(&wl->mutex);
1645 /* Asynchronously update the packet templates in template RAM.
1646 * Locking: Requires wl->irq_lock to be locked. */
1647 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon,
1648 const struct ieee80211_tx_control *txctl)
1650 /* This is the top half of the ansynchronous beacon update.
1651 * The bottom half is the beacon IRQ.
1652 * Beacon update must be asynchronous to avoid sending an
1653 * invalid beacon. This can happen for example, if the firmware
1654 * transmits a beacon while we are updating it. */
1656 if (wl->current_beacon)
1657 dev_kfree_skb_any(wl->current_beacon);
1658 wl->current_beacon = beacon;
1659 memcpy(&wl->beacon_txctl, txctl, sizeof(wl->beacon_txctl));
1660 wl->beacon0_uploaded = 0;
1661 wl->beacon1_uploaded = 0;
1662 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1665 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1670 len = min((u16) ssid_len, (u16) 0x100);
1671 for (i = 0; i < len; i += sizeof(u32)) {
1672 tmp = (u32) (ssid[i + 0]);
1674 tmp |= (u32) (ssid[i + 1]) << 8;
1676 tmp |= (u32) (ssid[i + 2]) << 16;
1678 tmp |= (u32) (ssid[i + 3]) << 24;
1679 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1681 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1684 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1687 if (dev->dev->id.revision >= 3) {
1688 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1689 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1691 b43_write16(dev, 0x606, (beacon_int >> 6));
1692 b43_write16(dev, 0x610, beacon_int);
1694 b43_time_unlock(dev);
1695 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1698 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1703 /* Interrupt handler bottom-half */
1704 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1707 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1708 u32 merged_dma_reason = 0;
1710 unsigned long flags;
1712 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1714 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1716 reason = dev->irq_reason;
1717 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1718 dma_reason[i] = dev->dma_reason[i];
1719 merged_dma_reason |= dma_reason[i];
1722 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1723 b43err(dev->wl, "MAC transmission error\n");
1725 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1726 b43err(dev->wl, "PHY transmission error\n");
1728 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1729 atomic_set(&dev->phy.txerr_cnt,
1730 B43_PHY_TX_BADNESS_LIMIT);
1731 b43err(dev->wl, "Too many PHY TX errors, "
1732 "restarting the controller\n");
1733 b43_controller_restart(dev, "PHY TX errors");
1737 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1738 B43_DMAIRQ_NONFATALMASK))) {
1739 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1740 b43err(dev->wl, "Fatal DMA error: "
1741 "0x%08X, 0x%08X, 0x%08X, "
1742 "0x%08X, 0x%08X, 0x%08X\n",
1743 dma_reason[0], dma_reason[1],
1744 dma_reason[2], dma_reason[3],
1745 dma_reason[4], dma_reason[5]);
1746 b43_controller_restart(dev, "DMA error");
1748 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1751 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1752 b43err(dev->wl, "DMA error: "
1753 "0x%08X, 0x%08X, 0x%08X, "
1754 "0x%08X, 0x%08X, 0x%08X\n",
1755 dma_reason[0], dma_reason[1],
1756 dma_reason[2], dma_reason[3],
1757 dma_reason[4], dma_reason[5]);
1761 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1762 handle_irq_ucode_debug(dev);
1763 if (reason & B43_IRQ_TBTT_INDI)
1764 handle_irq_tbtt_indication(dev);
1765 if (reason & B43_IRQ_ATIM_END)
1766 handle_irq_atim_end(dev);
1767 if (reason & B43_IRQ_BEACON)
1768 handle_irq_beacon(dev);
1769 if (reason & B43_IRQ_PMQ)
1770 handle_irq_pmq(dev);
1771 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1773 if (reason & B43_IRQ_NOISESAMPLE_OK)
1774 handle_irq_noise(dev);
1776 /* Check the DMA reason registers for received data. */
1777 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1778 if (b43_using_pio_transfers(dev))
1779 b43_pio_rx(dev->pio.rx_queue);
1781 b43_dma_rx(dev->dma.rx_ring);
1783 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1784 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1785 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1786 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1787 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1789 if (reason & B43_IRQ_TX_OK)
1790 handle_irq_transmit_status(dev);
1792 b43_interrupt_enable(dev, dev->irq_savedstate);
1794 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1797 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1799 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1801 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1802 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1803 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1804 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1805 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1806 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1809 /* Interrupt handler top-half */
1810 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1812 irqreturn_t ret = IRQ_NONE;
1813 struct b43_wldev *dev = dev_id;
1819 spin_lock(&dev->wl->irq_lock);
1821 if (b43_status(dev) < B43_STAT_STARTED)
1823 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1824 if (reason == 0xffffffff) /* shared IRQ */
1827 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1831 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1833 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1835 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1837 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1839 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1841 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1844 b43_interrupt_ack(dev, reason);
1845 /* disable all IRQs. They are enabled again in the bottom half. */
1846 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1847 /* save the reason code and call our bottom half. */
1848 dev->irq_reason = reason;
1849 tasklet_schedule(&dev->isr_tasklet);
1852 spin_unlock(&dev->wl->irq_lock);
1857 static void do_release_fw(struct b43_firmware_file *fw)
1859 release_firmware(fw->data);
1861 fw->filename = NULL;
1864 static void b43_release_firmware(struct b43_wldev *dev)
1866 do_release_fw(&dev->fw.ucode);
1867 do_release_fw(&dev->fw.pcm);
1868 do_release_fw(&dev->fw.initvals);
1869 do_release_fw(&dev->fw.initvals_band);
1872 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1876 text = "You must go to "
1877 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1878 "and download the latest firmware (version 4).\n";
1885 static int do_request_fw(struct b43_wldev *dev,
1887 struct b43_firmware_file *fw)
1889 char path[sizeof(modparam_fwpostfix) + 32];
1890 const struct firmware *blob;
1891 struct b43_fw_header *hdr;
1896 /* Don't fetch anything. Free possibly cached firmware. */
1901 if (strcmp(fw->filename, name) == 0)
1902 return 0; /* Already have this fw. */
1903 /* Free the cached firmware first. */
1907 snprintf(path, ARRAY_SIZE(path),
1909 modparam_fwpostfix, name);
1910 err = request_firmware(&blob, path, dev->dev->dev);
1912 b43err(dev->wl, "Firmware file \"%s\" not found "
1913 "or load failed.\n", path);
1916 if (blob->size < sizeof(struct b43_fw_header))
1918 hdr = (struct b43_fw_header *)(blob->data);
1919 switch (hdr->type) {
1920 case B43_FW_TYPE_UCODE:
1921 case B43_FW_TYPE_PCM:
1922 size = be32_to_cpu(hdr->size);
1923 if (size != blob->size - sizeof(struct b43_fw_header))
1926 case B43_FW_TYPE_IV:
1935 fw->filename = name;
1940 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1941 release_firmware(blob);
1946 static int b43_request_firmware(struct b43_wldev *dev)
1948 struct b43_firmware *fw = &dev->fw;
1949 const u8 rev = dev->dev->id.revision;
1950 const char *filename;
1955 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1956 if ((rev >= 5) && (rev <= 10))
1957 filename = "ucode5";
1958 else if ((rev >= 11) && (rev <= 12))
1959 filename = "ucode11";
1961 filename = "ucode13";
1964 err = do_request_fw(dev, filename, &fw->ucode);
1969 if ((rev >= 5) && (rev <= 10))
1975 err = do_request_fw(dev, filename, &fw->pcm);
1980 switch (dev->phy.type) {
1982 if ((rev >= 5) && (rev <= 10)) {
1983 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1984 filename = "a0g1initvals5";
1986 filename = "a0g0initvals5";
1988 goto err_no_initvals;
1991 if ((rev >= 5) && (rev <= 10))
1992 filename = "b0g0initvals5";
1994 filename = "lp0initvals13";
1996 goto err_no_initvals;
1999 if ((rev >= 11) && (rev <= 12))
2000 filename = "n0initvals11";
2002 goto err_no_initvals;
2005 goto err_no_initvals;
2007 err = do_request_fw(dev, filename, &fw->initvals);
2011 /* Get bandswitch initvals */
2012 switch (dev->phy.type) {
2014 if ((rev >= 5) && (rev <= 10)) {
2015 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2016 filename = "a0g1bsinitvals5";
2018 filename = "a0g0bsinitvals5";
2019 } else if (rev >= 11)
2022 goto err_no_initvals;
2025 if ((rev >= 5) && (rev <= 10))
2026 filename = "b0g0bsinitvals5";
2030 goto err_no_initvals;
2033 if ((rev >= 11) && (rev <= 12))
2034 filename = "n0bsinitvals11";
2036 goto err_no_initvals;
2039 goto err_no_initvals;
2041 err = do_request_fw(dev, filename, &fw->initvals_band);
2048 b43_print_fw_helptext(dev->wl, 1);
2053 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2058 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2063 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2064 "core rev %u\n", dev->phy.type, rev);
2068 b43_release_firmware(dev);
2072 static int b43_upload_microcode(struct b43_wldev *dev)
2074 const size_t hdr_len = sizeof(struct b43_fw_header);
2076 unsigned int i, len;
2077 u16 fwrev, fwpatch, fwdate, fwtime;
2081 /* Jump the microcode PSM to offset 0 */
2082 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2083 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2084 macctl |= B43_MACCTL_PSM_JMP0;
2085 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2086 /* Zero out all microcode PSM registers and shared memory. */
2087 for (i = 0; i < 64; i++)
2088 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2089 for (i = 0; i < 4096; i += 2)
2090 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2092 /* Upload Microcode. */
2093 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2094 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2095 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2096 for (i = 0; i < len; i++) {
2097 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2101 if (dev->fw.pcm.data) {
2102 /* Upload PCM data. */
2103 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2104 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2105 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2106 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2107 /* No need for autoinc bit in SHM_HW */
2108 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2109 for (i = 0; i < len; i++) {
2110 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2115 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2117 /* Start the microcode PSM */
2118 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2119 macctl &= ~B43_MACCTL_PSM_JMP0;
2120 macctl |= B43_MACCTL_PSM_RUN;
2121 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2123 /* Wait for the microcode to load and respond */
2126 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2127 if (tmp == B43_IRQ_MAC_SUSPENDED)
2131 b43err(dev->wl, "Microcode not responding\n");
2132 b43_print_fw_helptext(dev->wl, 1);
2136 msleep_interruptible(50);
2137 if (signal_pending(current)) {
2142 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2144 /* Get and check the revisions. */
2145 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2146 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2147 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2148 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2150 if (fwrev <= 0x128) {
2151 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2152 "binary drivers older than version 4.x is unsupported. "
2153 "You must upgrade your firmware files.\n");
2154 b43_print_fw_helptext(dev->wl, 1);
2158 b43info(dev->wl, "Loading firmware version %u.%u "
2159 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2161 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2162 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2164 dev->fw.rev = fwrev;
2165 dev->fw.patch = fwpatch;
2167 if (b43_is_old_txhdr_format(dev)) {
2168 b43warn(dev->wl, "You are using an old firmware image. "
2169 "Support for old firmware will be removed in July 2008.\n");
2170 b43_print_fw_helptext(dev->wl, 0);
2176 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2177 macctl &= ~B43_MACCTL_PSM_RUN;
2178 macctl |= B43_MACCTL_PSM_JMP0;
2179 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2184 static int b43_write_initvals(struct b43_wldev *dev,
2185 const struct b43_iv *ivals,
2189 const struct b43_iv *iv;
2194 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2196 for (i = 0; i < count; i++) {
2197 if (array_size < sizeof(iv->offset_size))
2199 array_size -= sizeof(iv->offset_size);
2200 offset = be16_to_cpu(iv->offset_size);
2201 bit32 = !!(offset & B43_IV_32BIT);
2202 offset &= B43_IV_OFFSET_MASK;
2203 if (offset >= 0x1000)
2208 if (array_size < sizeof(iv->data.d32))
2210 array_size -= sizeof(iv->data.d32);
2212 value = get_unaligned_be32(&iv->data.d32);
2213 b43_write32(dev, offset, value);
2215 iv = (const struct b43_iv *)((const uint8_t *)iv +
2221 if (array_size < sizeof(iv->data.d16))
2223 array_size -= sizeof(iv->data.d16);
2225 value = be16_to_cpu(iv->data.d16);
2226 b43_write16(dev, offset, value);
2228 iv = (const struct b43_iv *)((const uint8_t *)iv +
2239 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2240 b43_print_fw_helptext(dev->wl, 1);
2245 static int b43_upload_initvals(struct b43_wldev *dev)
2247 const size_t hdr_len = sizeof(struct b43_fw_header);
2248 const struct b43_fw_header *hdr;
2249 struct b43_firmware *fw = &dev->fw;
2250 const struct b43_iv *ivals;
2254 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2255 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2256 count = be32_to_cpu(hdr->size);
2257 err = b43_write_initvals(dev, ivals, count,
2258 fw->initvals.data->size - hdr_len);
2261 if (fw->initvals_band.data) {
2262 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2263 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2264 count = be32_to_cpu(hdr->size);
2265 err = b43_write_initvals(dev, ivals, count,
2266 fw->initvals_band.data->size - hdr_len);
2275 /* Initialize the GPIOs
2276 * http://bcm-specs.sipsolutions.net/GPIO
2278 static int b43_gpio_init(struct b43_wldev *dev)
2280 struct ssb_bus *bus = dev->dev->bus;
2281 struct ssb_device *gpiodev, *pcidev = NULL;
2284 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2285 & ~B43_MACCTL_GPOUTSMSK);
2287 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2292 if (dev->dev->bus->chip_id == 0x4301) {
2296 if (0 /* FIXME: conditional unknown */ ) {
2297 b43_write16(dev, B43_MMIO_GPIO_MASK,
2298 b43_read16(dev, B43_MMIO_GPIO_MASK)
2303 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2304 b43_write16(dev, B43_MMIO_GPIO_MASK,
2305 b43_read16(dev, B43_MMIO_GPIO_MASK)
2310 if (dev->dev->id.revision >= 2)
2311 mask |= 0x0010; /* FIXME: This is redundant. */
2313 #ifdef CONFIG_SSB_DRIVER_PCICORE
2314 pcidev = bus->pcicore.dev;
2316 gpiodev = bus->chipco.dev ? : pcidev;
2319 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2320 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2326 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2327 static void b43_gpio_cleanup(struct b43_wldev *dev)
2329 struct ssb_bus *bus = dev->dev->bus;
2330 struct ssb_device *gpiodev, *pcidev = NULL;
2332 #ifdef CONFIG_SSB_DRIVER_PCICORE
2333 pcidev = bus->pcicore.dev;
2335 gpiodev = bus->chipco.dev ? : pcidev;
2338 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2341 /* http://bcm-specs.sipsolutions.net/EnableMac */
2342 static void b43_mac_enable(struct b43_wldev *dev)
2344 dev->mac_suspended--;
2345 B43_WARN_ON(dev->mac_suspended < 0);
2346 if (dev->mac_suspended == 0) {
2347 b43_write32(dev, B43_MMIO_MACCTL,
2348 b43_read32(dev, B43_MMIO_MACCTL)
2349 | B43_MACCTL_ENABLED);
2350 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2351 B43_IRQ_MAC_SUSPENDED);
2353 b43_read32(dev, B43_MMIO_MACCTL);
2354 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2355 b43_power_saving_ctl_bits(dev, 0);
2357 /* Re-enable IRQs. */
2358 spin_lock_irq(&dev->wl->irq_lock);
2359 b43_interrupt_enable(dev, dev->irq_savedstate);
2360 spin_unlock_irq(&dev->wl->irq_lock);
2364 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2365 static void b43_mac_suspend(struct b43_wldev *dev)
2371 B43_WARN_ON(dev->mac_suspended < 0);
2373 if (dev->mac_suspended == 0) {
2374 /* Mask IRQs before suspending MAC. Otherwise
2375 * the MAC stays busy and won't suspend. */
2376 spin_lock_irq(&dev->wl->irq_lock);
2377 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2378 spin_unlock_irq(&dev->wl->irq_lock);
2379 b43_synchronize_irq(dev);
2380 dev->irq_savedstate = tmp;
2382 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2383 b43_write32(dev, B43_MMIO_MACCTL,
2384 b43_read32(dev, B43_MMIO_MACCTL)
2385 & ~B43_MACCTL_ENABLED);
2386 /* force pci to flush the write */
2387 b43_read32(dev, B43_MMIO_MACCTL);
2388 for (i = 35; i; i--) {
2389 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2390 if (tmp & B43_IRQ_MAC_SUSPENDED)
2394 /* Hm, it seems this will take some time. Use msleep(). */
2395 for (i = 40; i; i--) {
2396 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2397 if (tmp & B43_IRQ_MAC_SUSPENDED)
2401 b43err(dev->wl, "MAC suspend failed\n");
2404 dev->mac_suspended++;
2407 static void b43_adjust_opmode(struct b43_wldev *dev)
2409 struct b43_wl *wl = dev->wl;
2413 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2414 /* Reset status to STA infrastructure mode. */
2415 ctl &= ~B43_MACCTL_AP;
2416 ctl &= ~B43_MACCTL_KEEP_CTL;
2417 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2418 ctl &= ~B43_MACCTL_KEEP_BAD;
2419 ctl &= ~B43_MACCTL_PROMISC;
2420 ctl &= ~B43_MACCTL_BEACPROMISC;
2421 ctl |= B43_MACCTL_INFRA;
2423 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2424 ctl |= B43_MACCTL_AP;
2425 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2426 ctl &= ~B43_MACCTL_INFRA;
2428 if (wl->filter_flags & FIF_CONTROL)
2429 ctl |= B43_MACCTL_KEEP_CTL;
2430 if (wl->filter_flags & FIF_FCSFAIL)
2431 ctl |= B43_MACCTL_KEEP_BAD;
2432 if (wl->filter_flags & FIF_PLCPFAIL)
2433 ctl |= B43_MACCTL_KEEP_BADPLCP;
2434 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2435 ctl |= B43_MACCTL_PROMISC;
2436 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2437 ctl |= B43_MACCTL_BEACPROMISC;
2439 /* Workaround: On old hardware the HW-MAC-address-filter
2440 * doesn't work properly, so always run promisc in filter
2441 * it in software. */
2442 if (dev->dev->id.revision <= 4)
2443 ctl |= B43_MACCTL_PROMISC;
2445 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2448 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2449 if (dev->dev->bus->chip_id == 0x4306 &&
2450 dev->dev->bus->chip_rev == 3)
2455 b43_write16(dev, 0x612, cfp_pretbtt);
2458 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2464 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2467 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2469 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2470 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2473 static void b43_rate_memory_init(struct b43_wldev *dev)
2475 switch (dev->phy.type) {
2479 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2480 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2481 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2482 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2483 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2484 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2485 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2486 if (dev->phy.type == B43_PHYTYPE_A)
2490 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2491 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2492 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2493 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2500 /* Set the default values for the PHY TX Control Words. */
2501 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2505 ctl |= B43_TXH_PHY_ENC_CCK;
2506 ctl |= B43_TXH_PHY_ANT01AUTO;
2507 ctl |= B43_TXH_PHY_TXPWR;
2509 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2510 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2511 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2514 /* Set the TX-Antenna for management frames sent by firmware. */
2515 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2520 ant = b43_antenna_to_phyctl(antenna);
2523 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2524 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2526 /* For Probe Resposes */
2527 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2528 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2529 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2532 /* This is the opposite of b43_chip_init() */
2533 static void b43_chip_exit(struct b43_wldev *dev)
2535 b43_radio_turn_off(dev, 1);
2536 b43_gpio_cleanup(dev);
2537 /* firmware is released later */
2540 /* Initialize the chip
2541 * http://bcm-specs.sipsolutions.net/ChipInit
2543 static int b43_chip_init(struct b43_wldev *dev)
2545 struct b43_phy *phy = &dev->phy;
2547 u32 value32, macctl;
2550 /* Initialize the MAC control */
2551 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2553 macctl |= B43_MACCTL_GMODE;
2554 macctl |= B43_MACCTL_INFRA;
2555 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2557 err = b43_request_firmware(dev);
2560 err = b43_upload_microcode(dev);
2562 goto out; /* firmware is released later */
2564 err = b43_gpio_init(dev);
2566 goto out; /* firmware is released later */
2568 err = b43_upload_initvals(dev);
2570 goto err_gpio_clean;
2571 b43_radio_turn_on(dev);
2573 b43_write16(dev, 0x03E6, 0x0000);
2574 err = b43_phy_init(dev);
2578 /* Select initial Interference Mitigation. */
2579 tmp = phy->interfmode;
2580 phy->interfmode = B43_INTERFMODE_NONE;
2581 b43_radio_set_interference_mitigation(dev, tmp);
2583 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2584 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2586 if (phy->type == B43_PHYTYPE_B) {
2587 value16 = b43_read16(dev, 0x005E);
2589 b43_write16(dev, 0x005E, value16);
2591 b43_write32(dev, 0x0100, 0x01000000);
2592 if (dev->dev->id.revision < 5)
2593 b43_write32(dev, 0x010C, 0x01000000);
2595 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2596 & ~B43_MACCTL_INFRA);
2597 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2598 | B43_MACCTL_INFRA);
2600 /* Probe Response Timeout value */
2601 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2602 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2604 /* Initially set the wireless operation mode. */
2605 b43_adjust_opmode(dev);
2607 if (dev->dev->id.revision < 3) {
2608 b43_write16(dev, 0x060E, 0x0000);
2609 b43_write16(dev, 0x0610, 0x8000);
2610 b43_write16(dev, 0x0604, 0x0000);
2611 b43_write16(dev, 0x0606, 0x0200);
2613 b43_write32(dev, 0x0188, 0x80000000);
2614 b43_write32(dev, 0x018C, 0x02000000);
2616 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2617 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2618 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2619 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2620 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2621 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2622 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2624 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2625 value32 |= 0x00100000;
2626 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2628 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2629 dev->dev->bus->chipco.fast_pwrup_delay);
2632 b43dbg(dev->wl, "Chip initialized\n");
2637 b43_radio_turn_off(dev, 1);
2639 b43_gpio_cleanup(dev);
2643 static void b43_periodic_every120sec(struct b43_wldev *dev)
2645 struct b43_phy *phy = &dev->phy;
2647 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2650 b43_mac_suspend(dev);
2651 b43_lo_g_measure(dev);
2652 b43_mac_enable(dev);
2653 if (b43_has_hardware_pctl(phy))
2654 b43_lo_g_ctl_mark_all_unused(dev);
2657 static void b43_periodic_every60sec(struct b43_wldev *dev)
2659 struct b43_phy *phy = &dev->phy;
2661 if (phy->type != B43_PHYTYPE_G)
2663 if (!b43_has_hardware_pctl(phy))
2664 b43_lo_g_ctl_mark_all_unused(dev);
2665 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2666 b43_mac_suspend(dev);
2667 b43_calc_nrssi_slope(dev);
2668 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2669 u8 old_chan = phy->channel;
2671 /* VCO Calibration */
2673 b43_radio_selectchannel(dev, 1, 0);
2675 b43_radio_selectchannel(dev, 13, 0);
2676 b43_radio_selectchannel(dev, old_chan, 0);
2678 b43_mac_enable(dev);
2682 static void b43_periodic_every30sec(struct b43_wldev *dev)
2684 /* Update device statistics. */
2685 b43_calculate_link_quality(dev);
2688 static void b43_periodic_every15sec(struct b43_wldev *dev)
2690 struct b43_phy *phy = &dev->phy;
2692 if (phy->type == B43_PHYTYPE_G) {
2693 //TODO: update_aci_moving_average
2694 if (phy->aci_enable && phy->aci_wlan_automatic) {
2695 b43_mac_suspend(dev);
2696 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2697 if (0 /*TODO: bunch of conditions */ ) {
2698 b43_radio_set_interference_mitigation
2699 (dev, B43_INTERFMODE_MANUALWLAN);
2701 } else if (1 /*TODO*/) {
2703 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2704 b43_radio_set_interference_mitigation(dev,
2705 B43_INTERFMODE_NONE);
2709 b43_mac_enable(dev);
2710 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2712 //TODO: implement rev1 workaround
2715 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2716 //TODO for APHY (temperature?)
2718 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2722 static void do_periodic_work(struct b43_wldev *dev)
2726 state = dev->periodic_state;
2728 b43_periodic_every120sec(dev);
2730 b43_periodic_every60sec(dev);
2732 b43_periodic_every30sec(dev);
2733 b43_periodic_every15sec(dev);
2736 /* Periodic work locking policy:
2737 * The whole periodic work handler is protected by
2738 * wl->mutex. If another lock is needed somewhere in the
2739 * pwork callchain, it's aquired in-place, where it's needed.
2741 static void b43_periodic_work_handler(struct work_struct *work)
2743 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2744 periodic_work.work);
2745 struct b43_wl *wl = dev->wl;
2746 unsigned long delay;
2748 mutex_lock(&wl->mutex);
2750 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2752 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2755 do_periodic_work(dev);
2757 dev->periodic_state++;
2759 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2760 delay = msecs_to_jiffies(50);
2762 delay = round_jiffies_relative(HZ * 15);
2763 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2765 mutex_unlock(&wl->mutex);
2768 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2770 struct delayed_work *work = &dev->periodic_work;
2772 dev->periodic_state = 0;
2773 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2774 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2777 /* Check if communication with the device works correctly. */
2778 static int b43_validate_chipaccess(struct b43_wldev *dev)
2782 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2784 /* Check for read/write and endianness problems. */
2785 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2786 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2788 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2789 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2792 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2794 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2795 /* The 32bit register shadows the two 16bit registers
2796 * with update sideeffects. Validate this. */
2797 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2798 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2799 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2801 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2804 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2806 v = b43_read32(dev, B43_MMIO_MACCTL);
2807 v |= B43_MACCTL_GMODE;
2808 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2813 b43err(dev->wl, "Failed to validate the chipaccess\n");
2817 static void b43_security_init(struct b43_wldev *dev)
2819 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2820 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2821 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2822 /* KTP is a word address, but we address SHM bytewise.
2823 * So multiply by two.
2826 if (dev->dev->id.revision >= 5) {
2827 /* Number of RCMTA address slots */
2828 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2830 b43_clear_keys(dev);
2833 static int b43_rng_read(struct hwrng *rng, u32 * data)
2835 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2836 unsigned long flags;
2838 /* Don't take wl->mutex here, as it could deadlock with
2839 * hwrng internal locking. It's not needed to take
2840 * wl->mutex here, anyway. */
2842 spin_lock_irqsave(&wl->irq_lock, flags);
2843 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2844 spin_unlock_irqrestore(&wl->irq_lock, flags);
2846 return (sizeof(u16));
2849 static void b43_rng_exit(struct b43_wl *wl)
2851 if (wl->rng_initialized)
2852 hwrng_unregister(&wl->rng);
2855 static int b43_rng_init(struct b43_wl *wl)
2859 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2860 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2861 wl->rng.name = wl->rng_name;
2862 wl->rng.data_read = b43_rng_read;
2863 wl->rng.priv = (unsigned long)wl;
2864 wl->rng_initialized = 1;
2865 err = hwrng_register(&wl->rng);
2867 wl->rng_initialized = 0;
2868 b43err(wl, "Failed to register the random "
2869 "number generator (%d)\n", err);
2875 static int b43_op_tx(struct ieee80211_hw *hw,
2876 struct sk_buff *skb,
2877 struct ieee80211_tx_control *ctl)
2879 struct b43_wl *wl = hw_to_b43_wl(hw);
2880 struct b43_wldev *dev = wl->current_dev;
2881 unsigned long flags;
2884 if (unlikely(skb->len < 2 + 2 + 6)) {
2885 /* Too short, this can't be a valid frame. */
2888 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
2892 /* Transmissions on seperate queues can run concurrently. */
2893 read_lock_irqsave(&wl->tx_lock, flags);
2896 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2897 if (b43_using_pio_transfers(dev))
2898 err = b43_pio_tx(dev, skb, ctl);
2900 err = b43_dma_tx(dev, skb, ctl);
2903 read_unlock_irqrestore(&wl->tx_lock, flags);
2907 return NETDEV_TX_OK;
2910 /* We can not transmit this packet. Drop it. */
2911 dev_kfree_skb_any(skb);
2912 return NETDEV_TX_OK;
2915 /* Locking: wl->irq_lock */
2916 static void b43_qos_params_upload(struct b43_wldev *dev,
2917 const struct ieee80211_tx_queue_params *p,
2920 u16 params[B43_NR_QOSPARAMS];
2921 int cw_min, cw_max, aifs, bslots, tmp;
2924 const u16 aCWmin = 0x0001;
2925 const u16 aCWmax = 0x03FF;
2927 /* Calculate the default values for the parameters, if needed. */
2928 switch (shm_offset) {
2930 aifs = (p->aifs == -1) ? 2 : p->aifs;
2931 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
2932 cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
2935 aifs = (p->aifs == -1) ? 2 : p->aifs;
2936 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
2937 cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
2939 case B43_QOS_BESTEFFORT:
2940 aifs = (p->aifs == -1) ? 3 : p->aifs;
2941 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2942 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2944 case B43_QOS_BACKGROUND:
2945 aifs = (p->aifs == -1) ? 7 : p->aifs;
2946 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2947 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2957 bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
2959 memset(¶ms, 0, sizeof(params));
2961 params[B43_QOSPARAM_TXOP] = p->txop * 32;
2962 params[B43_QOSPARAM_CWMIN] = cw_min;
2963 params[B43_QOSPARAM_CWMAX] = cw_max;
2964 params[B43_QOSPARAM_CWCUR] = cw_min;
2965 params[B43_QOSPARAM_AIFS] = aifs;
2966 params[B43_QOSPARAM_BSLOTS] = bslots;
2967 params[B43_QOSPARAM_REGGAP] = bslots + aifs;
2969 for (i = 0; i < ARRAY_SIZE(params); i++) {
2970 if (i == B43_QOSPARAM_STATUS) {
2971 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
2972 shm_offset + (i * 2));
2973 /* Mark the parameters as updated. */
2975 b43_shm_write16(dev, B43_SHM_SHARED,
2976 shm_offset + (i * 2),
2979 b43_shm_write16(dev, B43_SHM_SHARED,
2980 shm_offset + (i * 2),
2986 /* Update the QOS parameters in hardware. */
2987 static void b43_qos_update(struct b43_wldev *dev)
2989 struct b43_wl *wl = dev->wl;
2990 struct b43_qos_params *params;
2991 unsigned long flags;
2994 /* Mapping of mac80211 queues to b43 SHM offsets. */
2995 static const u16 qos_shm_offsets[] = {
2996 [0] = B43_QOS_VOICE,
2997 [1] = B43_QOS_VIDEO,
2998 [2] = B43_QOS_BESTEFFORT,
2999 [3] = B43_QOS_BACKGROUND,
3001 BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
3003 b43_mac_suspend(dev);
3004 spin_lock_irqsave(&wl->irq_lock, flags);
3006 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3007 params = &(wl->qos_params[i]);
3008 if (params->need_hw_update) {
3009 b43_qos_params_upload(dev, &(params->p),
3010 qos_shm_offsets[i]);
3011 params->need_hw_update = 0;
3015 spin_unlock_irqrestore(&wl->irq_lock, flags);
3016 b43_mac_enable(dev);
3019 static void b43_qos_clear(struct b43_wl *wl)
3021 struct b43_qos_params *params;
3024 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3025 params = &(wl->qos_params[i]);
3027 memset(&(params->p), 0, sizeof(params->p));
3028 params->p.aifs = -1;
3029 params->need_hw_update = 1;
3033 /* Initialize the core's QOS capabilities */
3034 static void b43_qos_init(struct b43_wldev *dev)
3036 struct b43_wl *wl = dev->wl;
3039 /* Upload the current QOS parameters. */
3040 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
3041 wl->qos_params[i].need_hw_update = 1;
3042 b43_qos_update(dev);
3044 /* Enable QOS support. */
3045 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3046 b43_write16(dev, B43_MMIO_IFSCTL,
3047 b43_read16(dev, B43_MMIO_IFSCTL)
3048 | B43_MMIO_IFSCTL_USE_EDCF);
3051 static void b43_qos_update_work(struct work_struct *work)
3053 struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
3054 struct b43_wldev *dev;
3056 mutex_lock(&wl->mutex);
3057 dev = wl->current_dev;
3058 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
3059 b43_qos_update(dev);
3060 mutex_unlock(&wl->mutex);
3063 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3065 const struct ieee80211_tx_queue_params *params)
3067 struct b43_wl *wl = hw_to_b43_wl(hw);
3068 unsigned long flags;
3069 unsigned int queue = (unsigned int)_queue;
3070 struct b43_qos_params *p;
3072 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3073 /* Queue not available or don't support setting
3074 * params on this queue. Return success to not
3075 * confuse mac80211. */
3079 spin_lock_irqsave(&wl->irq_lock, flags);
3080 p = &(wl->qos_params[queue]);
3081 memcpy(&(p->p), params, sizeof(p->p));
3082 p->need_hw_update = 1;
3083 spin_unlock_irqrestore(&wl->irq_lock, flags);
3085 queue_work(hw->workqueue, &wl->qos_update_work);
3090 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3091 struct ieee80211_tx_queue_stats *stats)
3093 struct b43_wl *wl = hw_to_b43_wl(hw);
3094 struct b43_wldev *dev = wl->current_dev;
3095 unsigned long flags;
3100 spin_lock_irqsave(&wl->irq_lock, flags);
3101 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3102 if (b43_using_pio_transfers(dev))
3103 b43_pio_get_tx_stats(dev, stats);
3105 b43_dma_get_tx_stats(dev, stats);
3108 spin_unlock_irqrestore(&wl->irq_lock, flags);
3113 static int b43_op_get_stats(struct ieee80211_hw *hw,
3114 struct ieee80211_low_level_stats *stats)
3116 struct b43_wl *wl = hw_to_b43_wl(hw);
3117 unsigned long flags;
3119 spin_lock_irqsave(&wl->irq_lock, flags);
3120 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3121 spin_unlock_irqrestore(&wl->irq_lock, flags);
3126 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3128 struct ssb_device *sdev = dev->dev;
3131 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3132 tmslow &= ~B43_TMSLOW_GMODE;
3133 tmslow |= B43_TMSLOW_PHYRESET;
3134 tmslow |= SSB_TMSLOW_FGC;
3135 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3138 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3139 tmslow &= ~SSB_TMSLOW_FGC;
3140 tmslow |= B43_TMSLOW_PHYRESET;
3141 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3145 static const char * band_to_string(enum ieee80211_band band)
3148 case IEEE80211_BAND_5GHZ:
3150 case IEEE80211_BAND_2GHZ:
3159 /* Expects wl->mutex locked */
3160 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3162 struct b43_wldev *up_dev = NULL;
3163 struct b43_wldev *down_dev;
3164 struct b43_wldev *d;
3169 /* Find a device and PHY which supports the band. */
3170 list_for_each_entry(d, &wl->devlist, list) {
3171 switch (chan->band) {
3172 case IEEE80211_BAND_5GHZ:
3173 if (d->phy.supports_5ghz) {
3178 case IEEE80211_BAND_2GHZ:
3179 if (d->phy.supports_2ghz) {
3192 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3193 band_to_string(chan->band));
3196 if ((up_dev == wl->current_dev) &&
3197 (!!wl->current_dev->phy.gmode == !!gmode)) {
3198 /* This device is already running. */
3201 b43dbg(wl, "Switching to %s-GHz band\n",
3202 band_to_string(chan->band));
3203 down_dev = wl->current_dev;
3205 prev_status = b43_status(down_dev);
3206 /* Shutdown the currently running core. */
3207 if (prev_status >= B43_STAT_STARTED)
3208 b43_wireless_core_stop(down_dev);
3209 if (prev_status >= B43_STAT_INITIALIZED)
3210 b43_wireless_core_exit(down_dev);
3212 if (down_dev != up_dev) {
3213 /* We switch to a different core, so we put PHY into
3214 * RESET on the old core. */
3215 b43_put_phy_into_reset(down_dev);
3218 /* Now start the new core. */
3219 up_dev->phy.gmode = gmode;
3220 if (prev_status >= B43_STAT_INITIALIZED) {
3221 err = b43_wireless_core_init(up_dev);
3223 b43err(wl, "Fatal: Could not initialize device for "
3224 "selected %s-GHz band\n",
3225 band_to_string(chan->band));
3229 if (prev_status >= B43_STAT_STARTED) {
3230 err = b43_wireless_core_start(up_dev);
3232 b43err(wl, "Fatal: Coult not start device for "
3233 "selected %s-GHz band\n",
3234 band_to_string(chan->band));
3235 b43_wireless_core_exit(up_dev);
3239 B43_WARN_ON(b43_status(up_dev) != prev_status);
3241 wl->current_dev = up_dev;
3245 /* Whoops, failed to init the new core. No core is operating now. */
3246 wl->current_dev = NULL;
3250 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3252 struct b43_wl *wl = hw_to_b43_wl(hw);
3253 struct b43_wldev *dev;
3254 struct b43_phy *phy;
3255 unsigned long flags;
3260 mutex_lock(&wl->mutex);
3262 /* Switch the band (if necessary). This might change the active core. */
3263 err = b43_switch_band(wl, conf->channel);
3265 goto out_unlock_mutex;
3266 dev = wl->current_dev;
3269 /* Disable IRQs while reconfiguring the device.
3270 * This makes it possible to drop the spinlock throughout
3271 * the reconfiguration process. */
3272 spin_lock_irqsave(&wl->irq_lock, flags);
3273 if (b43_status(dev) < B43_STAT_STARTED) {
3274 spin_unlock_irqrestore(&wl->irq_lock, flags);
3275 goto out_unlock_mutex;
3277 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3278 spin_unlock_irqrestore(&wl->irq_lock, flags);
3279 b43_synchronize_irq(dev);
3281 /* Switch to the requested channel.
3282 * The firmware takes care of races with the TX handler. */
3283 if (conf->channel->hw_value != phy->channel)
3284 b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
3286 /* Enable/Disable ShortSlot timing. */
3287 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3289 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3290 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3291 b43_short_slot_timing_enable(dev);
3293 b43_short_slot_timing_disable(dev);
3296 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3298 /* Adjust the desired TX power level. */
3299 if (conf->power_level != 0) {
3300 if (conf->power_level != phy->power_level) {
3301 phy->power_level = conf->power_level;
3302 b43_phy_xmitpower(dev);
3306 /* Antennas for RX and management frame TX. */
3307 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3308 b43_mgmtframe_txantenna(dev, antenna);
3309 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3310 b43_set_rx_antenna(dev, antenna);
3312 /* Update templates for AP mode. */
3313 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
3314 b43_set_beacon_int(dev, conf->beacon_int);
3316 if (!!conf->radio_enabled != phy->radio_on) {
3317 if (conf->radio_enabled) {
3318 b43_radio_turn_on(dev);
3319 b43info(dev->wl, "Radio turned on by software\n");
3320 if (!dev->radio_hw_enable) {
3321 b43info(dev->wl, "The hardware RF-kill button "
3322 "still turns the radio physically off. "
3323 "Press the button to turn it on.\n");
3326 b43_radio_turn_off(dev, 0);
3327 b43info(dev->wl, "Radio turned off by software\n");
3331 spin_lock_irqsave(&wl->irq_lock, flags);
3332 b43_interrupt_enable(dev, savedirqs);
3334 spin_unlock_irqrestore(&wl->irq_lock, flags);
3336 mutex_unlock(&wl->mutex);
3341 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3342 const u8 *local_addr, const u8 *addr,
3343 struct ieee80211_key_conf *key)
3345 struct b43_wl *wl = hw_to_b43_wl(hw);
3346 struct b43_wldev *dev;
3347 unsigned long flags;
3351 DECLARE_MAC_BUF(mac);
3353 if (modparam_nohwcrypt)
3354 return -ENOSPC; /* User disabled HW-crypto */
3356 mutex_lock(&wl->mutex);
3357 spin_lock_irqsave(&wl->irq_lock, flags);
3359 dev = wl->current_dev;
3361 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3367 if (key->keylen == 5)
3368 algorithm = B43_SEC_ALGO_WEP40;
3370 algorithm = B43_SEC_ALGO_WEP104;
3373 algorithm = B43_SEC_ALGO_TKIP;
3376 algorithm = B43_SEC_ALGO_AES;
3382 index = (u8) (key->keyidx);
3388 if (algorithm == B43_SEC_ALGO_TKIP) {
3389 /* FIXME: No TKIP hardware encryption for now. */
3394 if (is_broadcast_ether_addr(addr)) {
3395 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3396 err = b43_key_write(dev, index, algorithm,
3397 key->key, key->keylen, NULL, key);
3400 * either pairwise key or address is 00:00:00:00:00:00
3401 * for transmit-only keys
3403 err = b43_key_write(dev, -1, algorithm,
3404 key->key, key->keylen, addr, key);
3409 if (algorithm == B43_SEC_ALGO_WEP40 ||
3410 algorithm == B43_SEC_ALGO_WEP104) {
3411 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3414 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3416 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3419 err = b43_key_clear(dev, key->hw_key_idx);
3428 spin_unlock_irqrestore(&wl->irq_lock, flags);
3429 mutex_unlock(&wl->mutex);
3431 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3433 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3434 print_mac(mac, addr));
3439 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3440 unsigned int changed, unsigned int *fflags,
3441 int mc_count, struct dev_addr_list *mc_list)
3443 struct b43_wl *wl = hw_to_b43_wl(hw);
3444 struct b43_wldev *dev = wl->current_dev;
3445 unsigned long flags;
3452 spin_lock_irqsave(&wl->irq_lock, flags);
3453 *fflags &= FIF_PROMISC_IN_BSS |
3459 FIF_BCN_PRBRESP_PROMISC;
3461 changed &= FIF_PROMISC_IN_BSS |
3467 FIF_BCN_PRBRESP_PROMISC;
3469 wl->filter_flags = *fflags;
3471 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3472 b43_adjust_opmode(dev);
3473 spin_unlock_irqrestore(&wl->irq_lock, flags);
3476 static int b43_op_config_interface(struct ieee80211_hw *hw,
3477 struct ieee80211_vif *vif,
3478 struct ieee80211_if_conf *conf)
3480 struct b43_wl *wl = hw_to_b43_wl(hw);
3481 struct b43_wldev *dev = wl->current_dev;
3482 unsigned long flags;
3486 mutex_lock(&wl->mutex);
3487 spin_lock_irqsave(&wl->irq_lock, flags);
3488 B43_WARN_ON(wl->vif != vif);
3490 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3492 memset(wl->bssid, 0, ETH_ALEN);
3493 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3494 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3495 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3496 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3498 b43_update_templates(wl, conf->beacon,
3499 conf->beacon_control);
3502 b43_write_mac_bssid_templates(dev);
3504 spin_unlock_irqrestore(&wl->irq_lock, flags);
3505 mutex_unlock(&wl->mutex);
3510 /* Locking: wl->mutex */
3511 static void b43_wireless_core_stop(struct b43_wldev *dev)
3513 struct b43_wl *wl = dev->wl;
3514 unsigned long flags;
3516 if (b43_status(dev) < B43_STAT_STARTED)
3519 /* Disable and sync interrupts. We must do this before than
3520 * setting the status to INITIALIZED, as the interrupt handler
3521 * won't care about IRQs then. */
3522 spin_lock_irqsave(&wl->irq_lock, flags);
3523 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3524 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3525 spin_unlock_irqrestore(&wl->irq_lock, flags);
3526 b43_synchronize_irq(dev);
3528 write_lock_irqsave(&wl->tx_lock, flags);
3529 b43_set_status(dev, B43_STAT_INITIALIZED);
3530 write_unlock_irqrestore(&wl->tx_lock, flags);
3533 mutex_unlock(&wl->mutex);
3534 /* Must unlock as it would otherwise deadlock. No races here.
3535 * Cancel the possibly running self-rearming periodic work. */
3536 cancel_delayed_work_sync(&dev->periodic_work);
3537 mutex_lock(&wl->mutex);
3539 b43_mac_suspend(dev);
3540 free_irq(dev->dev->irq, dev);
3541 b43dbg(wl, "Wireless interface stopped\n");
3544 /* Locking: wl->mutex */
3545 static int b43_wireless_core_start(struct b43_wldev *dev)
3549 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3551 drain_txstatus_queue(dev);
3552 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3553 IRQF_SHARED, KBUILD_MODNAME, dev);
3555 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3559 /* We are ready to run. */
3560 b43_set_status(dev, B43_STAT_STARTED);
3562 /* Start data flow (TX/RX). */
3563 b43_mac_enable(dev);
3564 b43_interrupt_enable(dev, dev->irq_savedstate);
3565 ieee80211_start_queues(dev->wl->hw);
3567 /* Start maintainance work */
3568 b43_periodic_tasks_setup(dev);
3570 b43dbg(dev->wl, "Wireless interface started\n");
3575 /* Get PHY and RADIO versioning numbers */
3576 static int b43_phy_versioning(struct b43_wldev *dev)
3578 struct b43_phy *phy = &dev->phy;
3586 int unsupported = 0;
3588 /* Get PHY versioning */
3589 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3590 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3591 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3592 phy_rev = (tmp & B43_PHYVER_VERSION);
3599 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3607 #ifdef CONFIG_B43_NPHY
3617 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3618 "(Analog %u, Type %u, Revision %u)\n",
3619 analog_type, phy_type, phy_rev);
3622 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3623 analog_type, phy_type, phy_rev);
3625 /* Get RADIO versioning */
3626 if (dev->dev->bus->chip_id == 0x4317) {
3627 if (dev->dev->bus->chip_rev == 0)
3629 else if (dev->dev->bus->chip_rev == 1)
3634 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3635 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3636 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3637 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3639 radio_manuf = (tmp & 0x00000FFF);
3640 radio_ver = (tmp & 0x0FFFF000) >> 12;
3641 radio_rev = (tmp & 0xF0000000) >> 28;
3642 if (radio_manuf != 0x17F /* Broadcom */)
3646 if (radio_ver != 0x2060)
3650 if (radio_manuf != 0x17F)
3654 if ((radio_ver & 0xFFF0) != 0x2050)
3658 if (radio_ver != 0x2050)
3662 if (radio_ver != 0x2055)
3669 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3670 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3671 radio_manuf, radio_ver, radio_rev);
3674 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3675 radio_manuf, radio_ver, radio_rev);
3677 phy->radio_manuf = radio_manuf;
3678 phy->radio_ver = radio_ver;
3679 phy->radio_rev = radio_rev;
3681 phy->analog = analog_type;
3682 phy->type = phy_type;
3688 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3689 struct b43_phy *phy)
3691 struct b43_txpower_lo_control *lo;
3694 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3695 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3697 phy->aci_enable = 0;
3698 phy->aci_wlan_automatic = 0;
3699 phy->aci_hw_rssi = 0;
3701 phy->radio_off_context.valid = 0;
3703 lo = phy->lo_control;
3705 memset(lo, 0, sizeof(*(phy->lo_control)));
3709 phy->max_lb_gain = 0;
3710 phy->trsw_rx_gain = 0;
3711 phy->txpwr_offset = 0;
3714 phy->nrssislope = 0;
3715 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3716 phy->nrssi[i] = -1000;
3717 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3718 phy->nrssi_lt[i] = i;
3720 phy->lofcal = 0xFFFF;
3721 phy->initval = 0xFFFF;
3723 phy->interfmode = B43_INTERFMODE_NONE;
3724 phy->channel = 0xFF;
3726 phy->hardware_power_control = !!modparam_hwpctl;
3728 /* PHY TX errors counter. */
3729 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3731 /* OFDM-table address caching. */
3732 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3735 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3739 /* Assume the radio is enabled. If it's not enabled, the state will
3740 * immediately get fixed on the first periodic work run. */
3741 dev->radio_hw_enable = 1;
3744 memset(&dev->stats, 0, sizeof(dev->stats));
3746 setup_struct_phy_for_init(dev, &dev->phy);
3748 /* IRQ related flags */
3749 dev->irq_reason = 0;
3750 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3751 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3753 dev->mac_suspended = 1;
3755 /* Noise calculation context */
3756 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3759 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3761 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3764 if (!modparam_btcoex)
3766 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3768 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3771 hf = b43_hf_read(dev);
3772 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3773 hf |= B43_HF_BTCOEXALT;
3775 hf |= B43_HF_BTCOEX;
3776 b43_hf_write(dev, hf);
3779 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3781 if (!modparam_btcoex)
3786 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3788 #ifdef CONFIG_SSB_DRIVER_PCICORE
3789 struct ssb_bus *bus = dev->dev->bus;
3792 if (bus->pcicore.dev &&
3793 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3794 bus->pcicore.dev->id.revision <= 5) {
3795 /* IMCFGLO timeouts workaround. */
3796 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3797 tmp &= ~SSB_IMCFGLO_REQTO;
3798 tmp &= ~SSB_IMCFGLO_SERTO;
3799 switch (bus->bustype) {
3800 case SSB_BUSTYPE_PCI:
3801 case SSB_BUSTYPE_PCMCIA:
3804 case SSB_BUSTYPE_SSB:
3808 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3810 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3813 /* Write the short and long frame retry limit values. */
3814 static void b43_set_retry_limits(struct b43_wldev *dev,
3815 unsigned int short_retry,
3816 unsigned int long_retry)
3818 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3819 * the chip-internal counter. */
3820 short_retry = min(short_retry, (unsigned int)0xF);
3821 long_retry = min(long_retry, (unsigned int)0xF);
3823 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3825 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3829 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3833 /* The time value is in microseconds. */
3834 if (dev->phy.type == B43_PHYTYPE_A)
3838 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle)
3840 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3841 pu_delay = max(pu_delay, (u16)2400);
3843 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3846 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3847 static void b43_set_pretbtt(struct b43_wldev *dev)
3851 /* The time value is in microseconds. */
3852 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) {
3855 if (dev->phy.type == B43_PHYTYPE_A)
3860 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3861 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3864 /* Shutdown a wireless core */
3865 /* Locking: wl->mutex */
3866 static void b43_wireless_core_exit(struct b43_wldev *dev)
3868 struct b43_phy *phy = &dev->phy;
3871 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3872 if (b43_status(dev) != B43_STAT_INITIALIZED)
3874 b43_set_status(dev, B43_STAT_UNINIT);
3876 /* Stop the microcode PSM. */
3877 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3878 macctl &= ~B43_MACCTL_PSM_RUN;
3879 macctl |= B43_MACCTL_PSM_JMP0;
3880 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3882 if (!dev->suspend_in_progress) {
3884 b43_rng_exit(dev->wl);
3889 b43_radio_turn_off(dev, 1);
3890 b43_switch_analog(dev, 0);
3891 if (phy->dyn_tssi_tbl)
3892 kfree(phy->tssi2dbm);
3893 kfree(phy->lo_control);
3894 phy->lo_control = NULL;
3895 if (dev->wl->current_beacon) {
3896 dev_kfree_skb_any(dev->wl->current_beacon);
3897 dev->wl->current_beacon = NULL;
3900 ssb_device_disable(dev->dev, 0);
3901 ssb_bus_may_powerdown(dev->dev->bus);
3904 /* Initialize a wireless core */
3905 static int b43_wireless_core_init(struct b43_wldev *dev)
3907 struct b43_wl *wl = dev->wl;
3908 struct ssb_bus *bus = dev->dev->bus;
3909 struct ssb_sprom *sprom = &bus->sprom;
3910 struct b43_phy *phy = &dev->phy;
3915 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3917 err = ssb_bus_powerup(bus, 0);
3920 if (!ssb_device_is_enabled(dev->dev)) {
3921 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3922 b43_wireless_core_reset(dev, tmp);
3925 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3927 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3928 if (!phy->lo_control) {
3933 setup_struct_wldev_for_init(dev);
3935 err = b43_phy_init_tssi2dbm_table(dev);
3937 goto err_kfree_lo_control;
3939 /* Enable IRQ routing to this device. */
3940 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3942 b43_imcfglo_timeouts_workaround(dev);
3943 b43_bluetooth_coext_disable(dev);
3944 b43_phy_early_init(dev);
3945 err = b43_chip_init(dev);
3947 goto err_kfree_tssitbl;
3948 b43_shm_write16(dev, B43_SHM_SHARED,
3949 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3950 hf = b43_hf_read(dev);
3951 if (phy->type == B43_PHYTYPE_G) {
3955 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3956 hf |= B43_HF_OFDMPABOOST;
3957 } else if (phy->type == B43_PHYTYPE_B) {
3959 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3962 b43_hf_write(dev, hf);
3964 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3965 B43_DEFAULT_LONG_RETRY_LIMIT);
3966 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3967 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3969 /* Disable sending probe responses from firmware.
3970 * Setting the MaxTime to one usec will always trigger
3971 * a timeout, so we never send any probe resp.
3972 * A timeout of zero is infinite. */
3973 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3975 b43_rate_memory_init(dev);
3976 b43_set_phytxctl_defaults(dev);
3978 /* Minimum Contention Window */
3979 if (phy->type == B43_PHYTYPE_B) {
3980 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3982 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3984 /* Maximum Contention Window */
3985 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3987 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
3988 dev->__using_pio_transfers = 1;
3989 err = b43_pio_init(dev);
3991 dev->__using_pio_transfers = 0;
3992 err = b43_dma_init(dev);
3997 b43_set_synth_pu_delay(dev, 1);
3998 b43_bluetooth_coext_enable(dev);
4000 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4001 b43_upload_card_macaddress(dev);
4002 b43_security_init(dev);
4003 if (!dev->suspend_in_progress)
4006 b43_set_status(dev, B43_STAT_INITIALIZED);
4008 if (!dev->suspend_in_progress)
4016 if (phy->dyn_tssi_tbl)
4017 kfree(phy->tssi2dbm);
4018 err_kfree_lo_control:
4019 kfree(phy->lo_control);
4020 phy->lo_control = NULL;
4022 ssb_bus_may_powerdown(bus);
4023 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4027 static int b43_op_add_interface(struct ieee80211_hw *hw,
4028 struct ieee80211_if_init_conf *conf)
4030 struct b43_wl *wl = hw_to_b43_wl(hw);
4031 struct b43_wldev *dev;
4032 unsigned long flags;
4033 int err = -EOPNOTSUPP;
4035 /* TODO: allow WDS/AP devices to coexist */
4037 if (conf->type != IEEE80211_IF_TYPE_AP &&
4038 conf->type != IEEE80211_IF_TYPE_STA &&
4039 conf->type != IEEE80211_IF_TYPE_WDS &&
4040 conf->type != IEEE80211_IF_TYPE_IBSS)
4043 mutex_lock(&wl->mutex);
4045 goto out_mutex_unlock;
4047 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4049 dev = wl->current_dev;
4051 wl->vif = conf->vif;
4052 wl->if_type = conf->type;
4053 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4055 spin_lock_irqsave(&wl->irq_lock, flags);
4056 b43_adjust_opmode(dev);
4057 b43_set_pretbtt(dev);
4058 b43_set_synth_pu_delay(dev, 0);
4059 b43_upload_card_macaddress(dev);
4060 spin_unlock_irqrestore(&wl->irq_lock, flags);
4064 mutex_unlock(&wl->mutex);
4069 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4070 struct ieee80211_if_init_conf *conf)
4072 struct b43_wl *wl = hw_to_b43_wl(hw);
4073 struct b43_wldev *dev = wl->current_dev;
4074 unsigned long flags;
4076 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4078 mutex_lock(&wl->mutex);
4080 B43_WARN_ON(!wl->operating);
4081 B43_WARN_ON(wl->vif != conf->vif);
4086 spin_lock_irqsave(&wl->irq_lock, flags);
4087 b43_adjust_opmode(dev);
4088 memset(wl->mac_addr, 0, ETH_ALEN);
4089 b43_upload_card_macaddress(dev);
4090 spin_unlock_irqrestore(&wl->irq_lock, flags);
4092 mutex_unlock(&wl->mutex);
4095 static int b43_op_start(struct ieee80211_hw *hw)
4097 struct b43_wl *wl = hw_to_b43_wl(hw);
4098 struct b43_wldev *dev = wl->current_dev;
4101 bool do_rfkill_exit = 0;
4103 /* Kill all old instance specific information to make sure
4104 * the card won't use it in the short timeframe between start
4105 * and mac80211 reconfiguring it. */
4106 memset(wl->bssid, 0, ETH_ALEN);
4107 memset(wl->mac_addr, 0, ETH_ALEN);
4108 wl->filter_flags = 0;
4109 wl->radiotap_enabled = 0;
4111 wl->beacon0_uploaded = 0;
4112 wl->beacon1_uploaded = 0;
4113 wl->beacon_templates_virgin = 1;
4115 /* First register RFkill.
4116 * LEDs that are registered later depend on it. */
4117 b43_rfkill_init(dev);
4119 mutex_lock(&wl->mutex);
4121 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4122 err = b43_wireless_core_init(dev);
4125 goto out_mutex_unlock;
4130 if (b43_status(dev) < B43_STAT_STARTED) {
4131 err = b43_wireless_core_start(dev);
4134 b43_wireless_core_exit(dev);
4136 goto out_mutex_unlock;
4141 mutex_unlock(&wl->mutex);
4144 b43_rfkill_exit(dev);
4149 static void b43_op_stop(struct ieee80211_hw *hw)
4151 struct b43_wl *wl = hw_to_b43_wl(hw);
4152 struct b43_wldev *dev = wl->current_dev;
4154 b43_rfkill_exit(dev);
4155 cancel_work_sync(&(wl->qos_update_work));
4156 cancel_work_sync(&(wl->beacon_update_trigger));
4158 mutex_lock(&wl->mutex);
4159 if (b43_status(dev) >= B43_STAT_STARTED)
4160 b43_wireless_core_stop(dev);
4161 b43_wireless_core_exit(dev);
4162 mutex_unlock(&wl->mutex);
4165 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4166 u32 short_retry_limit, u32 long_retry_limit)
4168 struct b43_wl *wl = hw_to_b43_wl(hw);
4169 struct b43_wldev *dev;
4172 mutex_lock(&wl->mutex);
4173 dev = wl->current_dev;
4174 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4178 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4180 mutex_unlock(&wl->mutex);
4185 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
4187 struct b43_wl *wl = hw_to_b43_wl(hw);
4188 struct sk_buff *beacon;
4189 unsigned long flags;
4190 struct ieee80211_tx_control txctl;
4192 /* We could modify the existing beacon and set the aid bit in
4193 * the TIM field, but that would probably require resizing and
4194 * moving of data within the beacon template.
4195 * Simply request a new beacon and let mac80211 do the hard work. */
4196 beacon = ieee80211_beacon_get(hw, wl->vif, &txctl);
4197 if (unlikely(!beacon))
4199 spin_lock_irqsave(&wl->irq_lock, flags);
4200 b43_update_templates(wl, beacon, &txctl);
4201 spin_unlock_irqrestore(&wl->irq_lock, flags);
4206 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
4207 struct sk_buff *beacon,
4208 struct ieee80211_tx_control *ctl)
4210 struct b43_wl *wl = hw_to_b43_wl(hw);
4211 unsigned long flags;
4213 spin_lock_irqsave(&wl->irq_lock, flags);
4214 b43_update_templates(wl, beacon, ctl);
4215 spin_unlock_irqrestore(&wl->irq_lock, flags);
4220 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4221 struct ieee80211_vif *vif,
4222 enum sta_notify_cmd notify_cmd,
4225 struct b43_wl *wl = hw_to_b43_wl(hw);
4227 B43_WARN_ON(!vif || wl->vif != vif);
4230 static const struct ieee80211_ops b43_hw_ops = {
4232 .conf_tx = b43_op_conf_tx,
4233 .add_interface = b43_op_add_interface,
4234 .remove_interface = b43_op_remove_interface,
4235 .config = b43_op_config,
4236 .config_interface = b43_op_config_interface,
4237 .configure_filter = b43_op_configure_filter,
4238 .set_key = b43_op_set_key,
4239 .get_stats = b43_op_get_stats,
4240 .get_tx_stats = b43_op_get_tx_stats,
4241 .start = b43_op_start,
4242 .stop = b43_op_stop,
4243 .set_retry_limit = b43_op_set_retry_limit,
4244 .set_tim = b43_op_beacon_set_tim,
4245 .beacon_update = b43_op_ibss_beacon_update,
4246 .sta_notify = b43_op_sta_notify,
4249 /* Hard-reset the chip. Do not call this directly.
4250 * Use b43_controller_restart()
4252 static void b43_chip_reset(struct work_struct *work)
4254 struct b43_wldev *dev =
4255 container_of(work, struct b43_wldev, restart_work);
4256 struct b43_wl *wl = dev->wl;
4260 mutex_lock(&wl->mutex);
4262 prev_status = b43_status(dev);
4263 /* Bring the device down... */
4264 if (prev_status >= B43_STAT_STARTED)
4265 b43_wireless_core_stop(dev);
4266 if (prev_status >= B43_STAT_INITIALIZED)
4267 b43_wireless_core_exit(dev);
4269 /* ...and up again. */
4270 if (prev_status >= B43_STAT_INITIALIZED) {
4271 err = b43_wireless_core_init(dev);
4275 if (prev_status >= B43_STAT_STARTED) {
4276 err = b43_wireless_core_start(dev);
4278 b43_wireless_core_exit(dev);
4284 wl->current_dev = NULL; /* Failed to init the dev. */
4285 mutex_unlock(&wl->mutex);
4287 b43err(wl, "Controller restart FAILED\n");
4289 b43info(wl, "Controller restarted\n");
4292 static int b43_setup_bands(struct b43_wldev *dev,
4293 bool have_2ghz_phy, bool have_5ghz_phy)
4295 struct ieee80211_hw *hw = dev->wl->hw;
4298 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4299 if (dev->phy.type == B43_PHYTYPE_N) {
4301 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4304 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4307 dev->phy.supports_2ghz = have_2ghz_phy;
4308 dev->phy.supports_5ghz = have_5ghz_phy;
4313 static void b43_wireless_core_detach(struct b43_wldev *dev)
4315 /* We release firmware that late to not be required to re-request
4316 * is all the time when we reinit the core. */
4317 b43_release_firmware(dev);
4320 static int b43_wireless_core_attach(struct b43_wldev *dev)
4322 struct b43_wl *wl = dev->wl;
4323 struct ssb_bus *bus = dev->dev->bus;
4324 struct pci_dev *pdev = bus->host_pci;
4326 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4329 /* Do NOT do any device initialization here.
4330 * Do it in wireless_core_init() instead.
4331 * This function is for gathering basic information about the HW, only.
4332 * Also some structs may be set up here. But most likely you want to have
4333 * that in core_init(), too.
4336 err = ssb_bus_powerup(bus, 0);
4338 b43err(wl, "Bus powerup failed\n");
4341 /* Get the PHY type. */
4342 if (dev->dev->id.revision >= 5) {
4345 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4346 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4347 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4351 dev->phy.gmode = have_2ghz_phy;
4352 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4353 b43_wireless_core_reset(dev, tmp);
4355 err = b43_phy_versioning(dev);
4358 /* Check if this device supports multiband. */
4360 (pdev->device != 0x4312 &&
4361 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4362 /* No multiband support. */
4365 switch (dev->phy.type) {
4377 if (dev->phy.type == B43_PHYTYPE_A) {
4379 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4383 if (1 /* disable A-PHY */) {
4384 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4385 if (dev->phy.type != B43_PHYTYPE_N) {
4391 dev->phy.gmode = have_2ghz_phy;
4392 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4393 b43_wireless_core_reset(dev, tmp);
4395 err = b43_validate_chipaccess(dev);
4398 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4402 /* Now set some default "current_dev" */
4403 if (!wl->current_dev)
4404 wl->current_dev = dev;
4405 INIT_WORK(&dev->restart_work, b43_chip_reset);
4407 b43_radio_turn_off(dev, 1);
4408 b43_switch_analog(dev, 0);
4409 ssb_device_disable(dev->dev, 0);
4410 ssb_bus_may_powerdown(bus);
4416 ssb_bus_may_powerdown(bus);
4420 static void b43_one_core_detach(struct ssb_device *dev)
4422 struct b43_wldev *wldev;
4425 /* Do not cancel ieee80211-workqueue based work here.
4426 * See comment in b43_remove(). */
4428 wldev = ssb_get_drvdata(dev);
4430 b43_debugfs_remove_device(wldev);
4431 b43_wireless_core_detach(wldev);
4432 list_del(&wldev->list);
4434 ssb_set_drvdata(dev, NULL);
4438 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4440 struct b43_wldev *wldev;
4441 struct pci_dev *pdev;
4444 if (!list_empty(&wl->devlist)) {
4445 /* We are not the first core on this chip. */
4446 pdev = dev->bus->host_pci;
4447 /* Only special chips support more than one wireless
4448 * core, although some of the other chips have more than
4449 * one wireless core as well. Check for this and
4453 ((pdev->device != 0x4321) &&
4454 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4455 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4460 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4466 b43_set_status(wldev, B43_STAT_UNINIT);
4467 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4468 tasklet_init(&wldev->isr_tasklet,
4469 (void (*)(unsigned long))b43_interrupt_tasklet,
4470 (unsigned long)wldev);
4471 INIT_LIST_HEAD(&wldev->list);
4473 err = b43_wireless_core_attach(wldev);
4475 goto err_kfree_wldev;
4477 list_add(&wldev->list, &wl->devlist);
4479 ssb_set_drvdata(dev, wldev);
4480 b43_debugfs_add_device(wldev);
4490 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4491 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4492 (pdev->device == _device) && \
4493 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4494 (pdev->subsystem_device == _subdevice) )
4496 static void b43_sprom_fixup(struct ssb_bus *bus)
4498 struct pci_dev *pdev;
4500 /* boardflags workarounds */
4501 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4502 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4503 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4504 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4505 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4506 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4507 if (bus->bustype == SSB_BUSTYPE_PCI) {
4508 pdev = bus->host_pci;
4509 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4510 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4511 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
4512 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4516 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4518 struct ieee80211_hw *hw = wl->hw;
4520 ssb_set_devtypedata(dev, NULL);
4521 ieee80211_free_hw(hw);
4524 static int b43_wireless_init(struct ssb_device *dev)
4526 struct ssb_sprom *sprom = &dev->bus->sprom;
4527 struct ieee80211_hw *hw;
4531 b43_sprom_fixup(dev->bus);
4533 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4535 b43err(NULL, "Could not allocate ieee80211 device\n");
4540 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4541 IEEE80211_HW_RX_INCLUDES_FCS;
4542 hw->max_signal = 100;
4543 hw->max_rssi = -110;
4544 hw->max_noise = -110;
4545 hw->queues = b43_modparam_qos ? 4 : 1;
4546 SET_IEEE80211_DEV(hw, dev->dev);
4547 if (is_valid_ether_addr(sprom->et1mac))
4548 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4550 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4552 /* Get and initialize struct b43_wl */
4553 wl = hw_to_b43_wl(hw);
4554 memset(wl, 0, sizeof(*wl));
4556 spin_lock_init(&wl->irq_lock);
4557 rwlock_init(&wl->tx_lock);
4558 spin_lock_init(&wl->leds_lock);
4559 spin_lock_init(&wl->shm_lock);
4560 mutex_init(&wl->mutex);
4561 INIT_LIST_HEAD(&wl->devlist);
4562 INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
4563 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4565 ssb_set_devtypedata(dev, wl);
4566 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4572 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4578 wl = ssb_get_devtypedata(dev);
4580 /* Probing the first core. Must setup common struct b43_wl */
4582 err = b43_wireless_init(dev);
4585 wl = ssb_get_devtypedata(dev);
4588 err = b43_one_core_attach(dev, wl);
4590 goto err_wireless_exit;
4593 err = ieee80211_register_hw(wl->hw);
4595 goto err_one_core_detach;
4601 err_one_core_detach:
4602 b43_one_core_detach(dev);
4605 b43_wireless_exit(dev, wl);
4609 static void b43_remove(struct ssb_device *dev)
4611 struct b43_wl *wl = ssb_get_devtypedata(dev);
4612 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4614 /* We must cancel any work here before unregistering from ieee80211,
4615 * as the ieee80211 unreg will destroy the workqueue. */
4616 cancel_work_sync(&wldev->restart_work);
4619 if (wl->current_dev == wldev)
4620 ieee80211_unregister_hw(wl->hw);
4622 b43_one_core_detach(dev);
4624 if (list_empty(&wl->devlist)) {
4625 /* Last core on the chip unregistered.
4626 * We can destroy common struct b43_wl.
4628 b43_wireless_exit(dev, wl);
4632 /* Perform a hardware reset. This can be called from any context. */
4633 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4635 /* Must avoid requeueing, if we are in shutdown. */
4636 if (b43_status(dev) < B43_STAT_INITIALIZED)
4638 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4639 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4644 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4646 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4647 struct b43_wl *wl = wldev->wl;
4649 b43dbg(wl, "Suspending...\n");
4651 mutex_lock(&wl->mutex);
4652 wldev->suspend_in_progress = true;
4653 wldev->suspend_init_status = b43_status(wldev);
4654 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4655 b43_wireless_core_stop(wldev);
4656 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4657 b43_wireless_core_exit(wldev);
4658 mutex_unlock(&wl->mutex);
4660 b43dbg(wl, "Device suspended.\n");
4665 static int b43_resume(struct ssb_device *dev)
4667 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4668 struct b43_wl *wl = wldev->wl;
4671 b43dbg(wl, "Resuming...\n");
4673 mutex_lock(&wl->mutex);
4674 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4675 err = b43_wireless_core_init(wldev);
4677 b43err(wl, "Resume failed at core init\n");
4681 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4682 err = b43_wireless_core_start(wldev);
4684 b43_leds_exit(wldev);
4685 b43_rng_exit(wldev->wl);
4686 b43_wireless_core_exit(wldev);
4687 b43err(wl, "Resume failed at core start\n");
4691 b43dbg(wl, "Device resumed.\n");
4693 wldev->suspend_in_progress = false;
4694 mutex_unlock(&wl->mutex);
4698 #else /* CONFIG_PM */
4699 # define b43_suspend NULL
4700 # define b43_resume NULL
4701 #endif /* CONFIG_PM */
4703 static struct ssb_driver b43_ssb_driver = {
4704 .name = KBUILD_MODNAME,
4705 .id_table = b43_ssb_tbl,
4707 .remove = b43_remove,
4708 .suspend = b43_suspend,
4709 .resume = b43_resume,
4712 static void b43_print_driverinfo(void)
4714 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4715 *feat_leds = "", *feat_rfkill = "";
4717 #ifdef CONFIG_B43_PCI_AUTOSELECT
4720 #ifdef CONFIG_B43_PCMCIA
4723 #ifdef CONFIG_B43_NPHY
4726 #ifdef CONFIG_B43_LEDS
4729 #ifdef CONFIG_B43_RFKILL
4732 printk(KERN_INFO "Broadcom 43xx driver loaded "
4733 "[ Features: %s%s%s%s%s, Firmware-ID: "
4734 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4735 feat_pci, feat_pcmcia, feat_nphy,
4736 feat_leds, feat_rfkill);
4739 static int __init b43_init(void)
4744 err = b43_pcmcia_init();
4747 err = ssb_driver_register(&b43_ssb_driver);
4749 goto err_pcmcia_exit;
4750 b43_print_driverinfo();
4761 static void __exit b43_exit(void)
4763 ssb_driver_unregister(&b43_ssb_driver);
4768 module_init(b43_init)
4769 module_exit(b43_exit)