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   1 /*
   2  * cbe_regs.h
   3  *
   4  * This file is intended to hold the various register definitions for CBE
   5  * on-chip system devices (memory controller, IO controller, etc...)
   6  *
   7  * (C) Copyright IBM Corporation 2001,2006
   8  *
   9  * Authors: Maximino Aguilar (maguilar@us.ibm.com)
  10  *          David J. Erb (djerb@us.ibm.com)
  11  *
  12  * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
  13  */
  14
  15 #ifndef CBE_REGS_H
  16 #define CBE_REGS_H
  17
  18 /*
  19  *
  20  * Some HID register definitions
  21  *
  22  */
  23
  24 /* CBE specific HID0 bits */
  25 #define HID0_CBE_THERM_WAKEUP   0x0000020000000000ul
  26 #define HID0_CBE_SYSERR_WAKEUP  0x0000008000000000ul
  27 #define HID0_CBE_THERM_INT_EN   0x0000000400000000ul
  28 #define HID0_CBE_SYSERR_INT_EN  0x0000000200000000ul
  29
  30 #define MAX_CBE         2
  31
  32 /*
  33  *
  34  * Pervasive unit register definitions
  35  *
  36  */
  37
  38 /* Macros for the pm_control register. */
  39 #define CBE_PM_16BIT_CTR(ctr)                   (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
  40 #define CBE_PM_ENABLE_PERF_MON                  0x80000000
  41
  42
  43 union spe_reg {
  44         u64 val;
  45         u8 spe[8];
  46 };
  47
  48 union ppe_spe_reg {
  49         u64 val;
  50         struct {
  51                 u32 ppe;
  52                 u32 spe;
  53         };
  54 };
  55
  56
  57 struct cbe_pmd_regs {
  58         /* Debug Bus Control */
  59         u64     pad_0x0000;                                     /* 0x0000 */
  60
  61         u64     group_control;                                  /* 0x0008 */
  62
  63         u8      pad_0x0010_0x00a8 [0x00a8 - 0x0010];            /* 0x0010 */
  64
  65         u64     debug_bus_control;                              /* 0x00a8 */
  66
  67         u8      pad_0x00b0_0x0100 [0x0100 - 0x00b0];            /* 0x00b0 */
  68
  69         u64     trace_aux_data;                                 /* 0x0100 */
  70         u64     trace_buffer_0_63;                              /* 0x0108 */
  71         u64     trace_buffer_64_127;                            /* 0x0110 */
  72         u64     trace_address;                                  /* 0x0118 */
  73         u64     ext_tr_timer;                                   /* 0x0120 */
  74
  75         u8      pad_0x0128_0x0400 [0x0400 - 0x0128];            /* 0x0128 */
  76
  77         /* Performance Monitor */
  78         u64     pm_status;                                      /* 0x0400 */
  79         u64     pm_control;                                     /* 0x0408 */
  80         u64     pm_interval;                                    /* 0x0410 */
  81         u64     pm_ctr[4];                                      /* 0x0418 */
  82         u64     pm_start_stop;                                  /* 0x0438 */
  83         u64     pm07_control[8];                                /* 0x0440 */
  84
  85         u8      pad_0x0480_0x0800 [0x0800 - 0x0480];            /* 0x0480 */
  86
  87         /* Thermal Sensor Registers */
  88         union   spe_reg ts_ctsr1;                               /* 0x0800 */
  89         u64     ts_ctsr2;                                       /* 0x0808 */
  90         union   spe_reg ts_mtsr1;                               /* 0x0810 */
  91         u64     ts_mtsr2;                                       /* 0x0818 */
  92         union   spe_reg ts_itr1;                                /* 0x0820 */
  93         u64     ts_itr2;                                        /* 0x0828 */
  94         u64     ts_gitr;                                        /* 0x0830 */
  95         u64     ts_isr;                                         /* 0x0838 */
  96         u64     ts_imr;                                         /* 0x0840 */
  97         union   spe_reg tm_cr1;                                 /* 0x0848 */
  98         u64     tm_cr2;                                         /* 0x0850 */
  99         u64     tm_simr;                                        /* 0x0858 */
 100         union   ppe_spe_reg tm_tpr;                             /* 0x0860 */
 101         union   spe_reg tm_str1;                                /* 0x0868 */
 102         u64     tm_str2;                                        /* 0x0870 */
 103         union   ppe_spe_reg tm_tsr;                             /* 0x0878 */
 104
 105         /* Power Management */
 106         u64     pmcr;                                           /* 0x0880 */
 107 #define CBE_PMD_PAUSE_ZERO_CONTROL      0x10000
 108         u64     pmsr;                                           /* 0x0888 */
 109
 110         /* Time Base Register */
 111         u64     tbr;                                            /* 0x0890 */
 112
 113         u8      pad_0x0898_0x0c00 [0x0c00 - 0x0898];            /* 0x0898 */
 114
 115         /* Fault Isolation Registers */
 116         u64     checkstop_fir;                                  /* 0x0c00 */
 117         u64     recoverable_fir;                                /* 0x0c08 */
 118         u64     spec_att_mchk_fir;                              /* 0x0c10 */
 119         u64     fir_mode_reg;                                   /* 0x0c18 */
 120         u64     fir_enable_mask;                                /* 0x0c20 */
 121
 122         u8      pad_0x0c28_0x1000 [0x1000 - 0x0c28];            /* 0x0c28 */
 123 };
 124
 125 extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
 126 extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
 127
 128 /*
 129  * PMU shadow registers
 130  *
 131  * Many of the registers in the performance monitoring unit are write-only,
 132  * so we need to save a copy of what we write to those registers.
 133  *
 134  * The actual data counters are read/write. However, writing to the counters
 135  * only takes effect if the PMU is enabled. Otherwise the value is stored in
 136  * a hardware latch until the next time the PMU is enabled. So we save a copy
 137  * of the counter values if we need to read them back while the PMU is
 138  * disabled. The counter_value_in_latch field is a bitmap indicating which
 139  * counters currently have a value waiting to be written.
 140  */
 141
 142 #define NR_PHYS_CTRS    4
 143 #define NR_CTRS         (NR_PHYS_CTRS * 2)
 144
 145 struct cbe_pmd_shadow_regs {
 146         u32 group_control;
 147         u32 debug_bus_control;
 148         u32 trace_address;
 149         u32 ext_tr_timer;
 150         u32 pm_status;
 151         u32 pm_control;
 152         u32 pm_interval;
 153         u32 pm_start_stop;
 154         u32 pm07_control[NR_CTRS];
 155
 156         u32 pm_ctr[NR_PHYS_CTRS];
 157         u32 counter_value_in_latch;
 158 };
 159
 160 extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
 161 extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
 162
 163 /*
 164  *
 165  * IIC unit register definitions
 166  *
 167  */
 168
 169 struct cbe_iic_pending_bits {
 170         u32 data;
 171         u8 flags;
 172         u8 class;
 173         u8 source;
 174         u8 prio;
 175 };
 176
 177 #define CBE_IIC_IRQ_VALID       0x80
 178 #define CBE_IIC_IRQ_IPI         0x40
 179
 180 struct cbe_iic_thread_regs {
 181         struct cbe_iic_pending_bits pending;
 182         struct cbe_iic_pending_bits pending_destr;
 183         u64 generate;
 184         u64 prio;
 185 };
 186
 187 struct cbe_iic_regs {
 188         u8      pad_0x0000_0x0400[0x0400 - 0x0000];             /* 0x0000 */
 189
 190         /* IIC interrupt registers */
 191         struct  cbe_iic_thread_regs thread[2];                  /* 0x0400 */
 192
 193         u64     iic_ir;                                         /* 0x0440 */
 194         u64     iic_is;                                         /* 0x0448 */
 195 #define CBE_IIC_IS_PMI          0x2
 196
 197         u8      pad_0x0450_0x0500[0x0500 - 0x0450];             /* 0x0450 */
 198
 199         /* IOC FIR */
 200         u64     ioc_fir_reset;                                  /* 0x0500 */
 201         u64     ioc_fir_set;                                    /* 0x0508 */
 202         u64     ioc_checkstop_enable;                           /* 0x0510 */
 203         u64     ioc_fir_error_mask;                             /* 0x0518 */
 204         u64     ioc_syserr_enable;                              /* 0x0520 */
 205         u64     ioc_fir;                                        /* 0x0528 */
 206
 207         u8      pad_0x0530_0x1000[0x1000 - 0x0530];             /* 0x0530 */
 208 };
 209
 210 extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
 211 extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
 212
 213
 214 struct cbe_mic_tm_regs {
 215         u8      pad_0x0000_0x0040[0x0040 - 0x0000];             /* 0x0000 */
 216
 217         u64     mic_ctl_cnfg2;                                  /* 0x0040 */
 218 #define CBE_MIC_ENABLE_AUX_TRC          0x8000000000000000LL
 219 #define CBE_MIC_DISABLE_PWR_SAV_2       0x0200000000000000LL
 220 #define CBE_MIC_DISABLE_AUX_TRC_WRAP    0x0100000000000000LL
 221 #define CBE_MIC_ENABLE_AUX_TRC_INT      0x0080000000000000LL
 222
 223         u64     pad_0x0048;                                     /* 0x0048 */
 224
 225         u64     mic_aux_trc_base;                               /* 0x0050 */
 226         u64     mic_aux_trc_max_addr;                           /* 0x0058 */
 227         u64     mic_aux_trc_cur_addr;                           /* 0x0060 */
 228         u64     mic_aux_trc_grf_addr;                           /* 0x0068 */
 229         u64     mic_aux_trc_grf_data;                           /* 0x0070 */
 230
 231         u64     pad_0x0078;                                     /* 0x0078 */
 232
 233         u64     mic_ctl_cnfg_0;                                 /* 0x0080 */
 234 #define CBE_MIC_DISABLE_PWR_SAV_0       0x8000000000000000LL
 235
 236         u64     pad_0x0088;                                     /* 0x0088 */
 237
 238         u64     slow_fast_timer_0;                              /* 0x0090 */
 239         u64     slow_next_timer_0;                              /* 0x0098 */
 240
 241         u8      pad_0x00a0_0x01c0[0x01c0 - 0x0a0];              /* 0x00a0 */
 242
 243         u64     mic_ctl_cnfg_1;                                 /* 0x01c0 */
 244 #define CBE_MIC_DISABLE_PWR_SAV_1       0x8000000000000000LL
 245         u64     pad_0x01c8;                                     /* 0x01c8 */
 246
 247         u64     slow_fast_timer_1;                              /* 0x01d0 */
 248         u64     slow_next_timer_1;                              /* 0x01d8 */
 249
 250         u8      pad_0x01e0_0x1000[0x1000 - 0x01e0];             /* 0x01e0 */
 251 };
 252
 253 extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
 254 extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
 255
 256 /* Init this module early */
 257 extern void cbe_regs_init(void);
 258
 259
 260 #endif /* CBE_REGS_H */