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   1 /*
   2  * Cell Broadband Engine Performance Monitor
   3  *
   4  * (C) Copyright IBM Corporation 2001,2006
   5  *
   6  * Author:
   7  *    David Erb (djerb@us.ibm.com)
   8  *    Kevin Corry (kevcorry@us.ibm.com)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2, or (at your option)
  13  * any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <linux/types.h>
  26 #include <asm/io.h>
  27 #include <asm/machdep.h>
  28 #include <asm/reg.h>
  29 #include <asm/spu.h>
  30
  31 #include "cbe_regs.h"
  32 #include "interrupt.h"
  33 #include "pmu.h"
  34
  35 /*
  36  * When writing to write-only mmio addresses, save a shadow copy. All of the
  37  * registers are 32-bit, but stored in the upper-half of a 64-bit field in
  38  * pmd_regs.
  39  */
  40
  41 #define WRITE_WO_MMIO(reg, x)                                   \
  42         do {                                                    \
  43                 u32 _x = (x);                                   \
  44                 struct cbe_pmd_regs __iomem *pmd_regs;          \
  45                 struct cbe_pmd_shadow_regs *shadow_regs;        \
  46                 pmd_regs = cbe_get_cpu_pmd_regs(cpu);           \
  47                 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
  48                 out_be64(&(pmd_regs->reg), (((u64)_x) << 32));  \
  49                 shadow_regs->reg = _x;                          \
  50         } while (0)
  51
  52 #define READ_SHADOW_REG(val, reg)                               \
  53         do {                                                    \
  54                 struct cbe_pmd_shadow_regs *shadow_regs;        \
  55                 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
  56                 (val) = shadow_regs->reg;                       \
  57         } while (0)
  58
  59 #define READ_MMIO_UPPER32(val, reg)                             \
  60         do {                                                    \
  61                 struct cbe_pmd_regs __iomem *pmd_regs;          \
  62                 pmd_regs = cbe_get_cpu_pmd_regs(cpu);           \
  63                 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32);   \
  64         } while (0)
  65
  66 /*
  67  * Physical counter registers.
  68  * Each physical counter can act as one 32-bit counter or two 16-bit counters.
  69  */
  70
  71 u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
  72 {
  73         u32 val_in_latch, val = 0;
  74
  75         if (phys_ctr < NR_PHYS_CTRS) {
  76                 READ_SHADOW_REG(val_in_latch, counter_value_in_latch);
  77
  78                 /* Read the latch or the actual counter, whichever is newer. */
  79                 if (val_in_latch & (1 << phys_ctr)) {
  80                         READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
  81                 } else {
  82                         READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
  83                 }
  84         }
  85
  86         return val;
  87 }
  88
  89 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
  90 {
  91         struct cbe_pmd_shadow_regs *shadow_regs;
  92         u32 pm_ctrl;
  93
  94         if (phys_ctr < NR_PHYS_CTRS) {
  95                 /* Writing to a counter only writes to a hardware latch.
  96                  * The new value is not propagated to the actual counter
  97                  * until the performance monitor is enabled.
  98                  */
  99                 WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
 100
 101                 pm_ctrl = cbe_read_pm(cpu, pm_control);
 102                 if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
 103                         /* The counters are already active, so we need to
 104                          * rewrite the pm_control register to "re-enable"
 105                          * the PMU.
 106                          */
 107                         cbe_write_pm(cpu, pm_control, pm_ctrl);
 108                 } else {
 109                         shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
 110                         shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
 111                 }
 112         }
 113 }
 114
 115 /*
 116  * "Logical" counter registers.
 117  * These will read/write 16-bits or 32-bits depending on the
 118  * current size of the counter. Counters 4 - 7 are always 16-bit.
 119  */
 120
 121 u32 cbe_read_ctr(u32 cpu, u32 ctr)
 122 {
 123         u32 val;
 124         u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
 125
 126         val = cbe_read_phys_ctr(cpu, phys_ctr);
 127
 128         if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
 129                 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
 130
 131         return val;
 132 }
 133
 134 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
 135 {
 136         u32 phys_ctr;
 137         u32 phys_val;
 138
 139         phys_ctr = ctr & (NR_PHYS_CTRS - 1);
 140
 141         if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
 142                 phys_val = cbe_read_phys_ctr(cpu, phys_ctr);
 143
 144                 if (ctr < NR_PHYS_CTRS)
 145                         val = (val << 16) | (phys_val & 0xffff);
 146                 else
 147                         val = (val & 0xffff) | (phys_val & 0xffff0000);
 148         }
 149
 150         cbe_write_phys_ctr(cpu, phys_ctr, val);
 151 }
 152
 153 /*
 154  * Counter-control registers.
 155  * Each "logical" counter has a corresponding control register.
 156  */
 157
 158 u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
 159 {
 160         u32 pm07_control = 0;
 161
 162         if (ctr < NR_CTRS)
 163                 READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
 164
 165         return pm07_control;
 166 }
 167
 168 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
 169 {
 170         if (ctr < NR_CTRS)
 171                 WRITE_WO_MMIO(pm07_control[ctr], val);
 172 }
 173
 174 /*
 175  * Other PMU control registers. Most of these are write-only.
 176  */
 177
 178 u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
 179 {
 180         u32 val = 0;
 181
 182         switch (reg) {
 183         case group_control:
 184                 READ_SHADOW_REG(val, group_control);
 185                 break;
 186
 187         case debug_bus_control:
 188                 READ_SHADOW_REG(val, debug_bus_control);
 189                 break;
 190
 191         case trace_address:
 192                 READ_MMIO_UPPER32(val, trace_address);
 193                 break;
 194
 195         case ext_tr_timer:
 196                 READ_SHADOW_REG(val, ext_tr_timer);
 197                 break;
 198
 199         case pm_status:
 200                 READ_MMIO_UPPER32(val, pm_status);
 201                 break;
 202
 203         case pm_control:
 204                 READ_SHADOW_REG(val, pm_control);
 205                 break;
 206
 207         case pm_interval:
 208                 READ_SHADOW_REG(val, pm_interval);
 209                 break;
 210
 211         case pm_start_stop:
 212                 READ_SHADOW_REG(val, pm_start_stop);
 213                 break;
 214         }
 215
 216         return val;
 217 }
 218
 219 void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
 220 {
 221         switch (reg) {
 222         case group_control:
 223                 WRITE_WO_MMIO(group_control, val);
 224                 break;
 225
 226         case debug_bus_control:
 227                 WRITE_WO_MMIO(debug_bus_control, val);
 228                 break;
 229
 230         case trace_address:
 231                 WRITE_WO_MMIO(trace_address, val);
 232                 break;
 233
 234         case ext_tr_timer:
 235                 WRITE_WO_MMIO(ext_tr_timer, val);
 236                 break;
 237
 238         case pm_status:
 239                 WRITE_WO_MMIO(pm_status, val);
 240                 break;
 241
 242         case pm_control:
 243                 WRITE_WO_MMIO(pm_control, val);
 244                 break;
 245
 246         case pm_interval:
 247                 WRITE_WO_MMIO(pm_interval, val);
 248                 break;
 249
 250         case pm_start_stop:
 251                 WRITE_WO_MMIO(pm_start_stop, val);
 252                 break;
 253         }
 254 }
 255
 256 /*
 257  * Get/set the size of a physical counter to either 16 or 32 bits.
 258  */
 259
 260 u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
 261 {
 262         u32 pm_ctrl, size = 0;
 263
 264         if (phys_ctr < NR_PHYS_CTRS) {
 265                 pm_ctrl = cbe_read_pm(cpu, pm_control);
 266                 size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
 267         }
 268
 269         return size;
 270 }
 271
 272 void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
 273 {
 274         u32 pm_ctrl;
 275
 276         if (phys_ctr < NR_PHYS_CTRS) {
 277                 pm_ctrl = cbe_read_pm(cpu, pm_control);
 278                 switch (ctr_size) {
 279                 case 16:
 280                         pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
 281                         break;
 282
 283                 case 32:
 284                         pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
 285                         break;
 286                 }
 287                 cbe_write_pm(cpu, pm_control, pm_ctrl);
 288         }
 289 }
 290
 291 /*
 292  * Enable/disable the entire performance monitoring unit.
 293  * When we enable the PMU, all pending writes to counters get committed.
 294  */
 295
 296 void cbe_enable_pm(u32 cpu)
 297 {
 298         struct cbe_pmd_shadow_regs *shadow_regs;
 299         u32 pm_ctrl;
 300
 301         shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
 302         shadow_regs->counter_value_in_latch = 0;
 303
 304         pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON;
 305         cbe_write_pm(cpu, pm_control, pm_ctrl);
 306 }
 307
 308 void cbe_disable_pm(u32 cpu)
 309 {
 310         u32 pm_ctrl;
 311         pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
 312         cbe_write_pm(cpu, pm_control, pm_ctrl);
 313 }
 314
 315 /*
 316  * Reading from the trace_buffer.
 317  * The trace buffer is two 64-bit registers. Reading from
 318  * the second half automatically increments the trace_address.
 319  */
 320
 321 void cbe_read_trace_buffer(u32 cpu, u64 *buf)
 322 {
 323         struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);
 324
 325         *buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
 326         *buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
 327 }
 328