git.oblomov.eu Git - linux-2.6/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include "drmP.h"
  29 #include "intel_drv.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32
  33 #include "drm_crtc_helper.h"
  34
  35 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  36
  37 typedef struct {
  38     /* given values */
  39     int n;
  40     int m1, m2;
  41     int p1, p2;
  42     /* derived values */
  43     int dot;
  44     int vco;
  45     int m;
  46     int p;
  47 } intel_clock_t;
  48
  49 typedef struct {
  50     int min, max;
  51 } intel_range_t;
  52
  53 typedef struct {
  54     int dot_limit;
  55     int p2_slow, p2_fast;
  56 } intel_p2_t;
  57
  58 #define INTEL_P2_NUM                  2
  59 typedef struct intel_limit intel_limit_t;
  60 struct intel_limit {
  61     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  62     intel_p2_t      p2;
  63     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  64                       int, int, intel_clock_t *);
  65 };
  66
  67 #define I8XX_DOT_MIN              25000
  68 #define I8XX_DOT_MAX             350000
  69 #define I8XX_VCO_MIN             930000
  70 #define I8XX_VCO_MAX            1400000
  71 #define I8XX_N_MIN                    3
  72 #define I8XX_N_MAX                   16
  73 #define I8XX_M_MIN                   96
  74 #define I8XX_M_MAX                  140
  75 #define I8XX_M1_MIN                  18
  76 #define I8XX_M1_MAX                  26
  77 #define I8XX_M2_MIN                   6
  78 #define I8XX_M2_MAX                  16
  79 #define I8XX_P_MIN                    4
  80 #define I8XX_P_MAX                  128
  81 #define I8XX_P1_MIN                   2
  82 #define I8XX_P1_MAX                  33
  83 #define I8XX_P1_LVDS_MIN              1
  84 #define I8XX_P1_LVDS_MAX              6
  85 #define I8XX_P2_SLOW                  4
  86 #define I8XX_P2_FAST                  2
  87 #define I8XX_P2_LVDS_SLOW             14
  88 #define I8XX_P2_LVDS_FAST             14 /* No fast option */
  89 #define I8XX_P2_SLOW_LIMIT       165000
  90
  91 #define I9XX_DOT_MIN              20000
  92 #define I9XX_DOT_MAX             400000
  93 #define I9XX_VCO_MIN            1400000
  94 #define I9XX_VCO_MAX            2800000
  95 #define IGD_VCO_MIN             1700000
  96 #define IGD_VCO_MAX             3500000
  97 #define I9XX_N_MIN                    1
  98 #define I9XX_N_MAX                    6
  99 /* IGD's Ncounter is a ring counter */
 100 #define IGD_N_MIN                     3
 101 #define IGD_N_MAX                     6
 102 #define I9XX_M_MIN                   70
 103 #define I9XX_M_MAX                  120
 104 #define IGD_M_MIN                     2
 105 #define IGD_M_MAX                   256
 106 #define I9XX_M1_MIN                  10
 107 #define I9XX_M1_MAX                  22
 108 #define I9XX_M2_MIN                   5
 109 #define I9XX_M2_MAX                   9
 110 /* IGD M1 is reserved, and must be 0 */
 111 #define IGD_M1_MIN                    0
 112 #define IGD_M1_MAX                    0
 113 #define IGD_M2_MIN                    0
 114 #define IGD_M2_MAX                    254
 115 #define I9XX_P_SDVO_DAC_MIN           5
 116 #define I9XX_P_SDVO_DAC_MAX          80
 117 #define I9XX_P_LVDS_MIN               7
 118 #define I9XX_P_LVDS_MAX              98
 119 #define IGD_P_LVDS_MIN                7
 120 #define IGD_P_LVDS_MAX               112
 121 #define I9XX_P1_MIN                   1
 122 #define I9XX_P1_MAX                   8
 123 #define I9XX_P2_SDVO_DAC_SLOW                10
 124 #define I9XX_P2_SDVO_DAC_FAST                 5
 125 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 126 #define I9XX_P2_LVDS_SLOW                    14
 127 #define I9XX_P2_LVDS_FAST                     7
 128 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 129
 130 #define INTEL_LIMIT_I8XX_DVO_DAC    0
 131 #define INTEL_LIMIT_I8XX_LVDS       1
 132 #define INTEL_LIMIT_I9XX_SDVO_DAC   2
 133 #define INTEL_LIMIT_I9XX_LVDS       3
 134 #define INTEL_LIMIT_G4X_SDVO        4
 135 #define INTEL_LIMIT_G4X_HDMI_DAC   5
 136 #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS   6
 137 #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS   7
 138 #define INTEL_LIMIT_IGD_SDVO_DAC    8
 139 #define INTEL_LIMIT_IGD_LVDS        9
 140 #define INTEL_LIMIT_IGDNG_SDVO_DAC  10
 141 #define INTEL_LIMIT_IGDNG_LVDS      11
 142
 143 /*The parameter is for SDVO on G4x platform*/
 144 #define G4X_DOT_SDVO_MIN           25000
 145 #define G4X_DOT_SDVO_MAX           270000
 146 #define G4X_VCO_MIN                1750000
 147 #define G4X_VCO_MAX                3500000
 148 #define G4X_N_SDVO_MIN             1
 149 #define G4X_N_SDVO_MAX             4
 150 #define G4X_M_SDVO_MIN             104
 151 #define G4X_M_SDVO_MAX             138
 152 #define G4X_M1_SDVO_MIN            17
 153 #define G4X_M1_SDVO_MAX            23
 154 #define G4X_M2_SDVO_MIN            5
 155 #define G4X_M2_SDVO_MAX            11
 156 #define G4X_P_SDVO_MIN             10
 157 #define G4X_P_SDVO_MAX             30
 158 #define G4X_P1_SDVO_MIN            1
 159 #define G4X_P1_SDVO_MAX            3
 160 #define G4X_P2_SDVO_SLOW           10
 161 #define G4X_P2_SDVO_FAST           10
 162 #define G4X_P2_SDVO_LIMIT          270000
 163
 164 /*The parameter is for HDMI_DAC on G4x platform*/
 165 #define G4X_DOT_HDMI_DAC_MIN           22000
 166 #define G4X_DOT_HDMI_DAC_MAX           400000
 167 #define G4X_N_HDMI_DAC_MIN             1
 168 #define G4X_N_HDMI_DAC_MAX             4
 169 #define G4X_M_HDMI_DAC_MIN             104
 170 #define G4X_M_HDMI_DAC_MAX             138
 171 #define G4X_M1_HDMI_DAC_MIN            16
 172 #define G4X_M1_HDMI_DAC_MAX            23
 173 #define G4X_M2_HDMI_DAC_MIN            5
 174 #define G4X_M2_HDMI_DAC_MAX            11
 175 #define G4X_P_HDMI_DAC_MIN             5
 176 #define G4X_P_HDMI_DAC_MAX             80
 177 #define G4X_P1_HDMI_DAC_MIN            1
 178 #define G4X_P1_HDMI_DAC_MAX            8
 179 #define G4X_P2_HDMI_DAC_SLOW           10
 180 #define G4X_P2_HDMI_DAC_FAST           5
 181 #define G4X_P2_HDMI_DAC_LIMIT          165000
 182
 183 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 185 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 187 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 189 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 191 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 193 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 195 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 197 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 200 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 201
 202 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 204 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 206 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 208 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 210 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 212 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 214 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 216 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 219 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 220
 221 /* IGDNG */
 222 /* as we calculate clock using (register_value + 2) for
 223    N/M1/M2, so here the range value for them is (actual_value-2).
 224  */
 225 #define IGDNG_DOT_MIN         25000
 226 #define IGDNG_DOT_MAX         350000
 227 #define IGDNG_VCO_MIN         1760000
 228 #define IGDNG_VCO_MAX         3510000
 229 #define IGDNG_N_MIN           1
 230 #define IGDNG_N_MAX           5
 231 #define IGDNG_M_MIN           79
 232 #define IGDNG_M_MAX           118
 233 #define IGDNG_M1_MIN          12
 234 #define IGDNG_M1_MAX          23
 235 #define IGDNG_M2_MIN          5
 236 #define IGDNG_M2_MAX          9
 237 #define IGDNG_P_SDVO_DAC_MIN  5
 238 #define IGDNG_P_SDVO_DAC_MAX  80
 239 #define IGDNG_P_LVDS_MIN      28
 240 #define IGDNG_P_LVDS_MAX      112
 241 #define IGDNG_P1_MIN          1
 242 #define IGDNG_P1_MAX          8
 243 #define IGDNG_P2_SDVO_DAC_SLOW 10
 244 #define IGDNG_P2_SDVO_DAC_FAST 5
 245 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 246 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 247 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 248
 249 static bool
 250 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 251                     int target, int refclk, intel_clock_t *best_clock);
 252 static bool
 253 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 254                         int target, int refclk, intel_clock_t *best_clock);
 255 static bool
 256 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 257                         int target, int refclk, intel_clock_t *best_clock);
 258
 259 static const intel_limit_t intel_limits[] = {
 260     { /* INTEL_LIMIT_I8XX_DVO_DAC */
 261         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 262         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 263         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 264         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 265         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 266         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 267         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 268         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 269         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 270                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 271         .find_pll = intel_find_best_PLL,
 272     },
 273     { /* INTEL_LIMIT_I8XX_LVDS */
 274         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 275         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 276         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 277         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 278         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 279         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 280         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 281         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 282         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 283                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 284         .find_pll = intel_find_best_PLL,
 285     },
 286     { /* INTEL_LIMIT_I9XX_SDVO_DAC */
 287         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 288         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 289         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 290         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 291         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 292         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 293         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 294         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 295         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 296                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 297         .find_pll = intel_find_best_PLL,
 298     },
 299     { /* INTEL_LIMIT_I9XX_LVDS */
 300         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 301         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 302         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 303         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 304         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 305         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 306         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 307         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 308         /* The single-channel range is 25-112Mhz, and dual-channel
 309          * is 80-224Mhz.  Prefer single channel as much as possible.
 310          */
 311         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 312                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 313         .find_pll = intel_find_best_PLL,
 314     },
 315     /* below parameter and function is for G4X Chipset Family*/
 316     { /* INTEL_LIMIT_G4X_SDVO */
 317         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 318         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 319         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 320         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 321         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 322         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 323         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 324         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 325         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 326                  .p2_slow = G4X_P2_SDVO_SLOW,
 327                  .p2_fast = G4X_P2_SDVO_FAST
 328         },
 329         .find_pll = intel_g4x_find_best_PLL,
 330     },
 331     { /* INTEL_LIMIT_G4X_HDMI_DAC */
 332         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 333         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 334         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 335         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 336         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 337         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 338         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 339         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 340         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 341                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 342                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 343         },
 344         .find_pll = intel_g4x_find_best_PLL,
 345     },
 346     { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
 347         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 348                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 349         .vco = { .min = G4X_VCO_MIN,
 350                  .max = G4X_VCO_MAX },
 351         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 352                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 353         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 354                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 355         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 356                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 357         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 358                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 359         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 360                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 361         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 362                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 363         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 364                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 365                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 366         },
 367         .find_pll = intel_g4x_find_best_PLL,
 368     },
 369     { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
 370         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 371                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 372         .vco = { .min = G4X_VCO_MIN,
 373                  .max = G4X_VCO_MAX },
 374         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 375                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 376         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 377                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 378         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 379                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 380         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 381                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 382         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 383                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 384         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 385                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 386         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 387                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 388                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 389         },
 390         .find_pll = intel_g4x_find_best_PLL,
 391     },
 392     { /* INTEL_LIMIT_IGD_SDVO */
 393         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 394         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 395         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 396         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 397         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 398         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 399         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 400         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 401         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 402                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 403         .find_pll = intel_find_best_PLL,
 404     },
 405     { /* INTEL_LIMIT_IGD_LVDS */
 406         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 407         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 408         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 409         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 410         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 411         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 412         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 413         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 414         /* IGD only supports single-channel mode. */
 415         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 416                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 417         .find_pll = intel_find_best_PLL,
 418     },
 419     { /* INTEL_LIMIT_IGDNG_SDVO_DAC */
 420         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 421         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 422         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 423         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 424         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 425         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 426         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 427         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 428         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 429                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 430                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 431         .find_pll = intel_igdng_find_best_PLL,
 432     },
 433     { /* INTEL_LIMIT_IGDNG_LVDS */
 434         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 435         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 436         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 437         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 438         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 439         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 440         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 441         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 442         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 443                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 444                  .p2_fast = IGDNG_P2_LVDS_FAST },
 445         .find_pll = intel_igdng_find_best_PLL,
 446     },
 447 };
 448
 449 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 450 {
 451         const intel_limit_t *limit;
 452         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 453                 limit = &intel_limits[INTEL_LIMIT_IGDNG_LVDS];
 454         else
 455                 limit = &intel_limits[INTEL_LIMIT_IGDNG_SDVO_DAC];
 456
 457         return limit;
 458 }
 459
 460 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 461 {
 462         struct drm_device *dev = crtc->dev;
 463         struct drm_i915_private *dev_priv = dev->dev_private;
 464         const intel_limit_t *limit;
 465
 466         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 467                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 468                     LVDS_CLKB_POWER_UP)
 469                         /* LVDS with dual channel */
 470                         limit = &intel_limits
 471                                         [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS];
 472                 else
 473                         /* LVDS with dual channel */
 474                         limit = &intel_limits
 475                                         [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS];
 476         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 477                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 478                 limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC];
 479         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 480                 limit = &intel_limits[INTEL_LIMIT_G4X_SDVO];
 481         } else /* The option is for other outputs */
 482                 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 483
 484         return limit;
 485 }
 486
 487 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 488 {
 489         struct drm_device *dev = crtc->dev;
 490         const intel_limit_t *limit;
 491
 492         if (IS_IGDNG(dev))
 493                 limit = intel_igdng_limit(crtc);
 494         else if (IS_G4X(dev)) {
 495                 limit = intel_g4x_limit(crtc);
 496         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 497                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 498                         limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
 499                 else
 500                         limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
 501         } else if (IS_IGD(dev)) {
 502                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 503                         limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
 504                 else
 505                         limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
 506         } else {
 507                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 508                         limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
 509                 else
 510                         limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
 511         }
 512         return limit;
 513 }
 514
 515 /* m1 is reserved as 0 in IGD, n is a ring counter */
 516 static void igd_clock(int refclk, intel_clock_t *clock)
 517 {
 518         clock->m = clock->m2 + 2;
 519         clock->p = clock->p1 * clock->p2;
 520         clock->vco = refclk * clock->m / clock->n;
 521         clock->dot = clock->vco / clock->p;
 522 }
 523
 524 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 525 {
 526         if (IS_IGD(dev)) {
 527                 igd_clock(refclk, clock);
 528                 return;
 529         }
 530         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 531         clock->p = clock->p1 * clock->p2;
 532         clock->vco = refclk * clock->m / (clock->n + 2);
 533         clock->dot = clock->vco / clock->p;
 534 }
 535
 536 /**
 537  * Returns whether any output on the specified pipe is of the specified type
 538  */
 539 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 540 {
 541     struct drm_device *dev = crtc->dev;
 542     struct drm_mode_config *mode_config = &dev->mode_config;
 543     struct drm_connector *l_entry;
 544
 545     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 546             if (l_entry->encoder &&
 547                 l_entry->encoder->crtc == crtc) {
 548                     struct intel_output *intel_output = to_intel_output(l_entry);
 549                     if (intel_output->type == type)
 550                             return true;
 551             }
 552     }
 553     return false;
 554 }
 555
 556 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 557 /**
 558  * Returns whether the given set of divisors are valid for a given refclk with
 559  * the given connectors.
 560  */
 561
 562 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 563 {
 564         const intel_limit_t *limit = intel_limit (crtc);
 565         struct drm_device *dev = crtc->dev;
 566
 567         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 568                 INTELPllInvalid ("p1 out of range\n");
 569         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 570                 INTELPllInvalid ("p out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid ("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid ("m1 out of range\n");
 575         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 576                 INTELPllInvalid ("m1 <= m2\n");
 577         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 578                 INTELPllInvalid ("m out of range\n");
 579         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 580                 INTELPllInvalid ("n out of range\n");
 581         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 582                 INTELPllInvalid ("vco out of range\n");
 583         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 584          * connector, etc., rather than just a single range.
 585          */
 586         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 587                 INTELPllInvalid ("dot out of range\n");
 588
 589         return true;
 590 }
 591
 592 static bool
 593 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 594                     int target, int refclk, intel_clock_t *best_clock)
 595
 596 {
 597         struct drm_device *dev = crtc->dev;
 598         struct drm_i915_private *dev_priv = dev->dev_private;
 599         intel_clock_t clock;
 600         int err = target;
 601
 602         if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 603             (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
 604                 /*
 605                  * For LVDS, if the panel is on, just rely on its current
 606                  * settings for dual-channel.  We haven't figured out how to
 607                  * reliably set up different single/dual channel state, if we
 608                  * even can.
 609                  */
 610                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 611                     LVDS_CLKB_POWER_UP)
 612                         clock.p2 = limit->p2.p2_fast;
 613                 else
 614                         clock.p2 = limit->p2.p2_slow;
 615         } else {
 616                 if (target < limit->p2.dot_limit)
 617                         clock.p2 = limit->p2.p2_slow;
 618                 else
 619                         clock.p2 = limit->p2.p2_fast;
 620         }
 621
 622         memset (best_clock, 0, sizeof (*best_clock));
 623
 624         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 625                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 626                         /* m1 is always 0 in IGD */
 627                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 628                                 break;
 629                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 630                              clock.n++) {
 631                                 for (clock.p1 = limit->p1.min;
 632                                      clock.p1 <= limit->p1.max; clock.p1++) {
 633                                         int this_err;
 634
 635                                         intel_clock(dev, refclk, &clock);
 636
 637                                         if (!intel_PLL_is_valid(crtc, &clock))
 638                                                 continue;
 639
 640                                         this_err = abs(clock.dot - target);
 641                                         if (this_err < err) {
 642                                                 *best_clock = clock;
 643                                                 err = this_err;
 644                                         }
 645                                 }
 646                         }
 647                 }
 648         }
 649
 650         return (err != target);
 651 }
 652
 653 static bool
 654 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 655                         int target, int refclk, intel_clock_t *best_clock)
 656 {
 657         struct drm_device *dev = crtc->dev;
 658         struct drm_i915_private *dev_priv = dev->dev_private;
 659         intel_clock_t clock;
 660         int max_n;
 661         bool found;
 662         /* approximately equals target * 0.00488 */
 663         int err_most = (target >> 8) + (target >> 10);
 664         found = false;
 665
 666         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 667                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 668                     LVDS_CLKB_POWER_UP)
 669                         clock.p2 = limit->p2.p2_fast;
 670                 else
 671                         clock.p2 = limit->p2.p2_slow;
 672         } else {
 673                 if (target < limit->p2.dot_limit)
 674                         clock.p2 = limit->p2.p2_slow;
 675                 else
 676                         clock.p2 = limit->p2.p2_fast;
 677         }
 678
 679         memset(best_clock, 0, sizeof(*best_clock));
 680         max_n = limit->n.max;
 681         /* based on hardware requriment prefer smaller n to precision */
 682         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 683                 /* based on hardware requirment prefere larger m1,m2, p1 */
 684                 for (clock.m1 = limit->m1.max;
 685                      clock.m1 >= limit->m1.min; clock.m1--) {
 686                         for (clock.m2 = limit->m2.max;
 687                              clock.m2 >= limit->m2.min; clock.m2--) {
 688                                 for (clock.p1 = limit->p1.max;
 689                                      clock.p1 >= limit->p1.min; clock.p1--) {
 690                                         int this_err;
 691
 692                                         intel_clock(dev, refclk, &clock);
 693                                         if (!intel_PLL_is_valid(crtc, &clock))
 694                                                 continue;
 695                                         this_err = abs(clock.dot - target) ;
 696                                         if (this_err < err_most) {
 697                                                 *best_clock = clock;
 698                                                 err_most = this_err;
 699                                                 max_n = clock.n;
 700                                                 found = true;
 701                                         }
 702                                 }
 703                         }
 704                 }
 705         }
 706         return found;
 707 }
 708
 709 static bool
 710 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 711                         int target, int refclk, intel_clock_t *best_clock)
 712 {
 713         struct drm_device *dev = crtc->dev;
 714         struct drm_i915_private *dev_priv = dev->dev_private;
 715         intel_clock_t clock;
 716         int max_n;
 717         bool found;
 718         int err_most = 47;
 719         found = false;
 720
 721         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 722                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 723                     LVDS_CLKB_POWER_UP)
 724                         clock.p2 = limit->p2.p2_fast;
 725                 else
 726                         clock.p2 = limit->p2.p2_slow;
 727         } else {
 728                 if (target < limit->p2.dot_limit)
 729                         clock.p2 = limit->p2.p2_slow;
 730                 else
 731                         clock.p2 = limit->p2.p2_fast;
 732         }
 733
 734         memset(best_clock, 0, sizeof(*best_clock));
 735         max_n = limit->n.max;
 736         /* based on hardware requriment prefer smaller n to precision */
 737         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 738                 /* based on hardware requirment prefere larger m1,m2, p1 */
 739                 for (clock.m1 = limit->m1.max;
 740                      clock.m1 >= limit->m1.min; clock.m1--) {
 741                         for (clock.m2 = limit->m2.max;
 742                              clock.m2 >= limit->m2.min; clock.m2--) {
 743                                 for (clock.p1 = limit->p1.max;
 744                                      clock.p1 >= limit->p1.min; clock.p1--) {
 745                                         int this_err;
 746
 747                                         intel_clock(dev, refclk, &clock);
 748                                         if (!intel_PLL_is_valid(crtc, &clock))
 749                                                 continue;
 750                                         this_err = abs((10000 - (target*10000/clock.dot)));
 751                                         if (this_err < err_most) {
 752                                                 *best_clock = clock;
 753                                                 err_most = this_err;
 754                                                 max_n = clock.n;
 755                                                 found = true;
 756                                                 /* found on first matching */
 757                                                 goto out;
 758                                         }
 759                                 }
 760                         }
 761                 }
 762         }
 763 out:
 764         return found;
 765 }
 766
 767 void
 768 intel_wait_for_vblank(struct drm_device *dev)
 769 {
 770         /* Wait for 20ms, i.e. one cycle at 50hz. */
 771         mdelay(20);
 772 }
 773
 774 static int
 775 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 776                     struct drm_framebuffer *old_fb)
 777 {
 778         struct drm_device *dev = crtc->dev;
 779         struct drm_i915_private *dev_priv = dev->dev_private;
 780         struct drm_i915_master_private *master_priv;
 781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 782         struct intel_framebuffer *intel_fb;
 783         struct drm_i915_gem_object *obj_priv;
 784         struct drm_gem_object *obj;
 785         int pipe = intel_crtc->pipe;
 786         unsigned long Start, Offset;
 787         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 788         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 789         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 790         int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
 791         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 792         u32 dspcntr, alignment;
 793         int ret;
 794
 795         /* no fb bound */
 796         if (!crtc->fb) {
 797                 DRM_DEBUG("No FB bound\n");
 798                 return 0;
 799         }
 800
 801         switch (pipe) {
 802         case 0:
 803         case 1:
 804                 break;
 805         default:
 806                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 807                 return -EINVAL;
 808         }
 809
 810         intel_fb = to_intel_framebuffer(crtc->fb);
 811         obj = intel_fb->obj;
 812         obj_priv = obj->driver_private;
 813
 814         switch (obj_priv->tiling_mode) {
 815         case I915_TILING_NONE:
 816                 alignment = 64 * 1024;
 817                 break;
 818         case I915_TILING_X:
 819                 /* pin() will align the object as required by fence */
 820                 alignment = 0;
 821                 break;
 822         case I915_TILING_Y:
 823                 /* FIXME: Is this true? */
 824                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 825                 return -EINVAL;
 826         default:
 827                 BUG();
 828         }
 829
 830         mutex_lock(&dev->struct_mutex);
 831         ret = i915_gem_object_pin(obj, alignment);
 832         if (ret != 0) {
 833                 mutex_unlock(&dev->struct_mutex);
 834                 return ret;
 835         }
 836
 837         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 838         if (ret != 0) {
 839                 i915_gem_object_unpin(obj);
 840                 mutex_unlock(&dev->struct_mutex);
 841                 return ret;
 842         }
 843
 844         /* Pre-i965 needs to install a fence for tiled scan-out */
 845         if (!IS_I965G(dev) &&
 846             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
 847             obj_priv->tiling_mode != I915_TILING_NONE) {
 848                 ret = i915_gem_object_get_fence_reg(obj);
 849                 if (ret != 0) {
 850                         i915_gem_object_unpin(obj);
 851                         mutex_unlock(&dev->struct_mutex);
 852                         return ret;
 853                 }
 854         }
 855
 856         dspcntr = I915_READ(dspcntr_reg);
 857         /* Mask out pixel format bits in case we change it */
 858         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 859         switch (crtc->fb->bits_per_pixel) {
 860         case 8:
 861                 dspcntr |= DISPPLANE_8BPP;
 862                 break;
 863         case 16:
 864                 if (crtc->fb->depth == 15)
 865                         dspcntr |= DISPPLANE_15_16BPP;
 866                 else
 867                         dspcntr |= DISPPLANE_16BPP;
 868                 break;
 869         case 24:
 870         case 32:
 871                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 872                 break;
 873         default:
 874                 DRM_ERROR("Unknown color depth\n");
 875                 i915_gem_object_unpin(obj);
 876                 mutex_unlock(&dev->struct_mutex);
 877                 return -EINVAL;
 878         }
 879         if (IS_I965G(dev)) {
 880                 if (obj_priv->tiling_mode != I915_TILING_NONE)
 881                         dspcntr |= DISPPLANE_TILED;
 882                 else
 883                         dspcntr &= ~DISPPLANE_TILED;
 884         }
 885
 886         I915_WRITE(dspcntr_reg, dspcntr);
 887
 888         Start = obj_priv->gtt_offset;
 889         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 890
 891         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 892         I915_WRITE(dspstride, crtc->fb->pitch);
 893         if (IS_I965G(dev)) {
 894                 I915_WRITE(dspbase, Offset);
 895                 I915_READ(dspbase);
 896                 I915_WRITE(dspsurf, Start);
 897                 I915_READ(dspsurf);
 898                 I915_WRITE(dsptileoff, (y << 16) | x);
 899         } else {
 900                 I915_WRITE(dspbase, Start + Offset);
 901                 I915_READ(dspbase);
 902         }
 903
 904         intel_wait_for_vblank(dev);
 905
 906         if (old_fb) {
 907                 intel_fb = to_intel_framebuffer(old_fb);
 908                 i915_gem_object_unpin(intel_fb->obj);
 909         }
 910         mutex_unlock(&dev->struct_mutex);
 911
 912         if (!dev->primary->master)
 913                 return 0;
 914
 915         master_priv = dev->primary->master->driver_priv;
 916         if (!master_priv->sarea_priv)
 917                 return 0;
 918
 919         if (pipe) {
 920                 master_priv->sarea_priv->pipeB_x = x;
 921                 master_priv->sarea_priv->pipeB_y = y;
 922         } else {
 923                 master_priv->sarea_priv->pipeA_x = x;
 924                 master_priv->sarea_priv->pipeA_y = y;
 925         }
 926
 927         return 0;
 928 }
 929
 930 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
 931 {
 932         struct drm_device *dev = crtc->dev;
 933         struct drm_i915_private *dev_priv = dev->dev_private;
 934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 935         int pipe = intel_crtc->pipe;
 936         int plane = intel_crtc->pipe;
 937         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
 938         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 939         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
 940         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
 941         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
 942         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
 943         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
 944         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
 945         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
 946         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
 947         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
 948         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
 949         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
 950         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
 951         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
 952         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
 953         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
 954         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
 955         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
 956         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
 957         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
 958         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
 959         u32 temp;
 960         int tries = 5, j;
 961
 962         /* XXX: When our outputs are all unaware of DPMS modes other than off
 963          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 964          */
 965         switch (mode) {
 966         case DRM_MODE_DPMS_ON:
 967         case DRM_MODE_DPMS_STANDBY:
 968         case DRM_MODE_DPMS_SUSPEND:
 969                 DRM_DEBUG("crtc %d dpms on\n", pipe);
 970                 /* enable PCH DPLL */
 971                 temp = I915_READ(pch_dpll_reg);
 972                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 973                         I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
 974                         I915_READ(pch_dpll_reg);
 975                 }
 976
 977                 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
 978                 temp = I915_READ(fdi_rx_reg);
 979                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
 980                                 FDI_SEL_PCDCLK |
 981                                 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
 982                 I915_READ(fdi_rx_reg);
 983                 udelay(200);
 984
 985                 /* Enable CPU FDI TX PLL, always on for IGDNG */
 986                 temp = I915_READ(fdi_tx_reg);
 987                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
 988                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
 989                         I915_READ(fdi_tx_reg);
 990                         udelay(100);
 991                 }
 992
 993                 /* Enable CPU pipe */
 994                 temp = I915_READ(pipeconf_reg);
 995                 if ((temp & PIPEACONF_ENABLE) == 0) {
 996                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
 997                         I915_READ(pipeconf_reg);
 998                         udelay(100);
 999                 }
1000
1001                 /* configure and enable CPU plane */
1002                 temp = I915_READ(dspcntr_reg);
1003                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1004                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1005                         /* Flush the plane changes */
1006                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1007                 }
1008
1009                 /* enable CPU FDI TX and PCH FDI RX */
1010                 temp = I915_READ(fdi_tx_reg);
1011                 temp |= FDI_TX_ENABLE;
1012                 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1013                 temp &= ~FDI_LINK_TRAIN_NONE;
1014                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1015                 I915_WRITE(fdi_tx_reg, temp);
1016                 I915_READ(fdi_tx_reg);
1017
1018                 temp = I915_READ(fdi_rx_reg);
1019                 temp &= ~FDI_LINK_TRAIN_NONE;
1020                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1021                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1022                 I915_READ(fdi_rx_reg);
1023
1024                 udelay(150);
1025
1026                 /* Train FDI. */
1027                 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1028                    for train result */
1029                 temp = I915_READ(fdi_rx_imr_reg);
1030                 temp &= ~FDI_RX_SYMBOL_LOCK;
1031                 temp &= ~FDI_RX_BIT_LOCK;
1032                 I915_WRITE(fdi_rx_imr_reg, temp);
1033                 I915_READ(fdi_rx_imr_reg);
1034                 udelay(150);
1035
1036                 temp = I915_READ(fdi_rx_iir_reg);
1037                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1038
1039                 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1040                         for (j = 0; j < tries; j++) {
1041                                 temp = I915_READ(fdi_rx_iir_reg);
1042                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1043                                 if (temp & FDI_RX_BIT_LOCK)
1044                                         break;
1045                                 udelay(200);
1046                         }
1047                         if (j != tries)
1048                                 I915_WRITE(fdi_rx_iir_reg,
1049                                                 temp | FDI_RX_BIT_LOCK);
1050                         else
1051                                 DRM_DEBUG("train 1 fail\n");
1052                 } else {
1053                         I915_WRITE(fdi_rx_iir_reg,
1054                                         temp | FDI_RX_BIT_LOCK);
1055                         DRM_DEBUG("train 1 ok 2!\n");
1056                 }
1057                 temp = I915_READ(fdi_tx_reg);
1058                 temp &= ~FDI_LINK_TRAIN_NONE;
1059                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1060                 I915_WRITE(fdi_tx_reg, temp);
1061
1062                 temp = I915_READ(fdi_rx_reg);
1063                 temp &= ~FDI_LINK_TRAIN_NONE;
1064                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1065                 I915_WRITE(fdi_rx_reg, temp);
1066
1067                 udelay(150);
1068
1069                 temp = I915_READ(fdi_rx_iir_reg);
1070                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1071
1072                 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1073                         for (j = 0; j < tries; j++) {
1074                                 temp = I915_READ(fdi_rx_iir_reg);
1075                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1076                                 if (temp & FDI_RX_SYMBOL_LOCK)
1077                                         break;
1078                                 udelay(200);
1079                         }
1080                         if (j != tries) {
1081                                 I915_WRITE(fdi_rx_iir_reg,
1082                                                 temp | FDI_RX_SYMBOL_LOCK);
1083                                 DRM_DEBUG("train 2 ok 1!\n");
1084                         } else
1085                                 DRM_DEBUG("train 2 fail\n");
1086                 } else {
1087                         I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1088                         DRM_DEBUG("train 2 ok 2!\n");
1089                 }
1090                 DRM_DEBUG("train done\n");
1091
1092                 /* set transcoder timing */
1093                 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1094                 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1095                 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1096
1097                 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1098                 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1099                 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1100
1101                 /* enable PCH transcoder */
1102                 temp = I915_READ(transconf_reg);
1103                 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1104                 I915_READ(transconf_reg);
1105
1106                 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1107                         ;
1108
1109                 /* enable normal */
1110
1111                 temp = I915_READ(fdi_tx_reg);
1112                 temp &= ~FDI_LINK_TRAIN_NONE;
1113                 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1114                                 FDI_TX_ENHANCE_FRAME_ENABLE);
1115                 I915_READ(fdi_tx_reg);
1116
1117                 temp = I915_READ(fdi_rx_reg);
1118                 temp &= ~FDI_LINK_TRAIN_NONE;
1119                 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1120                                 FDI_RX_ENHANCE_FRAME_ENABLE);
1121                 I915_READ(fdi_rx_reg);
1122
1123                 /* wait one idle pattern time */
1124                 udelay(100);
1125
1126                 intel_crtc_load_lut(crtc);
1127
1128         break;
1129         case DRM_MODE_DPMS_OFF:
1130                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1131
1132                 /* Disable the VGA plane that we never use */
1133                 I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
1134
1135                 /* Disable display plane */
1136                 temp = I915_READ(dspcntr_reg);
1137                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1138                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1139                         /* Flush the plane changes */
1140                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1141                         I915_READ(dspbase_reg);
1142                 }
1143
1144                 /* disable cpu pipe, disable after all planes disabled */
1145                 temp = I915_READ(pipeconf_reg);
1146                 if ((temp & PIPEACONF_ENABLE) != 0) {
1147                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1148                         I915_READ(pipeconf_reg);
1149                         /* wait for cpu pipe off, pipe state */
1150                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
1151                                 ;
1152                 } else
1153                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1154
1155                 /* IGDNG-A : disable cpu panel fitter ? */
1156                 temp = I915_READ(pf_ctl_reg);
1157                 if ((temp & PF_ENABLE) != 0) {
1158                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1159                         I915_READ(pf_ctl_reg);
1160                 }
1161
1162                 /* disable CPU FDI tx and PCH FDI rx */
1163                 temp = I915_READ(fdi_tx_reg);
1164                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1165                 I915_READ(fdi_tx_reg);
1166
1167                 temp = I915_READ(fdi_rx_reg);
1168                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1169                 I915_READ(fdi_rx_reg);
1170
1171                 /* still set train pattern 1 */
1172                 temp = I915_READ(fdi_tx_reg);
1173                 temp &= ~FDI_LINK_TRAIN_NONE;
1174                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1175                 I915_WRITE(fdi_tx_reg, temp);
1176
1177                 temp = I915_READ(fdi_rx_reg);
1178                 temp &= ~FDI_LINK_TRAIN_NONE;
1179                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1180                 I915_WRITE(fdi_rx_reg, temp);
1181
1182                 /* disable PCH transcoder */
1183                 temp = I915_READ(transconf_reg);
1184                 if ((temp & TRANS_ENABLE) != 0) {
1185                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1186                         I915_READ(transconf_reg);
1187                         /* wait for PCH transcoder off, transcoder state */
1188                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
1189                                 ;
1190                 }
1191
1192                 /* disable PCH DPLL */
1193                 temp = I915_READ(pch_dpll_reg);
1194                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1195                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1196                         I915_READ(pch_dpll_reg);
1197                 }
1198
1199                 temp = I915_READ(fdi_rx_reg);
1200                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1201                         temp &= ~FDI_SEL_PCDCLK;
1202                         temp &= ~FDI_RX_PLL_ENABLE;
1203                         I915_WRITE(fdi_rx_reg, temp);
1204                         I915_READ(fdi_rx_reg);
1205                 }
1206
1207                 /* Wait for the clocks to turn off. */
1208                 udelay(150);
1209                 break;
1210         }
1211 }
1212
1213 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1214 {
1215         struct drm_device *dev = crtc->dev;
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1218         int pipe = intel_crtc->pipe;
1219         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1220         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1221         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1222         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1223         u32 temp;
1224
1225         /* XXX: When our outputs are all unaware of DPMS modes other than off
1226          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1227          */
1228         switch (mode) {
1229         case DRM_MODE_DPMS_ON:
1230         case DRM_MODE_DPMS_STANDBY:
1231         case DRM_MODE_DPMS_SUSPEND:
1232                 /* Enable the DPLL */
1233                 temp = I915_READ(dpll_reg);
1234                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1235                         I915_WRITE(dpll_reg, temp);
1236                         I915_READ(dpll_reg);
1237                         /* Wait for the clocks to stabilize. */
1238                         udelay(150);
1239                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1240                         I915_READ(dpll_reg);
1241                         /* Wait for the clocks to stabilize. */
1242                         udelay(150);
1243                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1244                         I915_READ(dpll_reg);
1245                         /* Wait for the clocks to stabilize. */
1246                         udelay(150);
1247                 }
1248
1249                 /* Enable the pipe */
1250                 temp = I915_READ(pipeconf_reg);
1251                 if ((temp & PIPEACONF_ENABLE) == 0)
1252                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1253
1254                 /* Enable the plane */
1255                 temp = I915_READ(dspcntr_reg);
1256                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1257                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1258                         /* Flush the plane changes */
1259                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1260                 }
1261
1262                 intel_crtc_load_lut(crtc);
1263
1264                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1265                 //intel_crtc_dpms_video(crtc, true); TODO
1266         break;
1267         case DRM_MODE_DPMS_OFF:
1268                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1269                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1270
1271                 /* Disable the VGA plane that we never use */
1272                 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
1273
1274                 /* Disable display plane */
1275                 temp = I915_READ(dspcntr_reg);
1276                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1277                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1278                         /* Flush the plane changes */
1279                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1280                         I915_READ(dspbase_reg);
1281                 }
1282
1283                 if (!IS_I9XX(dev)) {
1284                         /* Wait for vblank for the disable to take effect */
1285                         intel_wait_for_vblank(dev);
1286                 }
1287
1288                 /* Next, disable display pipes */
1289                 temp = I915_READ(pipeconf_reg);
1290                 if ((temp & PIPEACONF_ENABLE) != 0) {
1291                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1292                         I915_READ(pipeconf_reg);
1293                 }
1294
1295                 /* Wait for vblank for the disable to take effect. */
1296                 intel_wait_for_vblank(dev);
1297
1298                 temp = I915_READ(dpll_reg);
1299                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1300                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1301                         I915_READ(dpll_reg);
1302                 }
1303
1304                 /* Wait for the clocks to turn off. */
1305                 udelay(150);
1306                 break;
1307         }
1308 }
1309
1310 /**
1311  * Sets the power management mode of the pipe and plane.
1312  *
1313  * This code should probably grow support for turning the cursor off and back
1314  * on appropriately at the same time as we're turning the pipe off/on.
1315  */
1316 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1317 {
1318         struct drm_device *dev = crtc->dev;
1319         struct drm_i915_master_private *master_priv;
1320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1321         int pipe = intel_crtc->pipe;
1322         bool enabled;
1323
1324         if (IS_IGDNG(dev))
1325                 igdng_crtc_dpms(crtc, mode);
1326         else
1327                 i9xx_crtc_dpms(crtc, mode);
1328
1329         if (!dev->primary->master)
1330                 return;
1331
1332         master_priv = dev->primary->master->driver_priv;
1333         if (!master_priv->sarea_priv)
1334                 return;
1335
1336         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1337
1338         switch (pipe) {
1339         case 0:
1340                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1341                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1342                 break;
1343         case 1:
1344                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1345                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1346                 break;
1347         default:
1348                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1349                 break;
1350         }
1351
1352         intel_crtc->dpms_mode = mode;
1353 }
1354
1355 static void intel_crtc_prepare (struct drm_crtc *crtc)
1356 {
1357         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1358         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1359 }
1360
1361 static void intel_crtc_commit (struct drm_crtc *crtc)
1362 {
1363         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1364         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1365 }
1366
1367 void intel_encoder_prepare (struct drm_encoder *encoder)
1368 {
1369         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1370         /* lvds has its own version of prepare see intel_lvds_prepare */
1371         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1372 }
1373
1374 void intel_encoder_commit (struct drm_encoder *encoder)
1375 {
1376         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1377         /* lvds has its own version of commit see intel_lvds_commit */
1378         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1379 }
1380
1381 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1382                                   struct drm_display_mode *mode,
1383                                   struct drm_display_mode *adjusted_mode)
1384 {
1385         struct drm_device *dev = crtc->dev;
1386         if (IS_IGDNG(dev)) {
1387                 /* FDI link clock is fixed at 2.7G */
1388                 if (mode->clock * 3 > 27000 * 4)
1389                         return MODE_CLOCK_HIGH;
1390         }
1391         return true;
1392 }
1393
1394
1395 /** Returns the core display clock speed for i830 - i945 */
1396 static int intel_get_core_clock_speed(struct drm_device *dev)
1397 {
1398
1399         /* Core clock values taken from the published datasheets.
1400          * The 830 may go up to 166 Mhz, which we should check.
1401          */
1402         if (IS_I945G(dev))
1403                 return 400000;
1404         else if (IS_I915G(dev))
1405                 return 333000;
1406         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1407                 return 200000;
1408         else if (IS_I915GM(dev)) {
1409                 u16 gcfgc = 0;
1410
1411                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1412
1413                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1414                         return 133000;
1415                 else {
1416                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1417                         case GC_DISPLAY_CLOCK_333_MHZ:
1418                                 return 333000;
1419                         default:
1420                         case GC_DISPLAY_CLOCK_190_200_MHZ:
1421                                 return 190000;
1422                         }
1423                 }
1424         } else if (IS_I865G(dev))
1425                 return 266000;
1426         else if (IS_I855(dev)) {
1427                 u16 hpllcc = 0;
1428                 /* Assume that the hardware is in the high speed state.  This
1429                  * should be the default.
1430                  */
1431                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1432                 case GC_CLOCK_133_200:
1433                 case GC_CLOCK_100_200:
1434                         return 200000;
1435                 case GC_CLOCK_166_250:
1436                         return 250000;
1437                 case GC_CLOCK_100_133:
1438                         return 133000;
1439                 }
1440         } else /* 852, 830 */
1441                 return 133000;
1442
1443         return 0; /* Silence gcc warning */
1444 }
1445
1446
1447 /**
1448  * Return the pipe currently connected to the panel fitter,
1449  * or -1 if the panel fitter is not present or not in use
1450  */
1451 static int intel_panel_fitter_pipe (struct drm_device *dev)
1452 {
1453         struct drm_i915_private *dev_priv = dev->dev_private;
1454         u32  pfit_control;
1455
1456         /* i830 doesn't have a panel fitter */
1457         if (IS_I830(dev))
1458                 return -1;
1459
1460         pfit_control = I915_READ(PFIT_CONTROL);
1461
1462         /* See if the panel fitter is in use */
1463         if ((pfit_control & PFIT_ENABLE) == 0)
1464                 return -1;
1465
1466         /* 965 can place panel fitter on either pipe */
1467         if (IS_I965G(dev))
1468                 return (pfit_control >> 29) & 0x3;
1469
1470         /* older chips can only use pipe 1 */
1471         return 1;
1472 }
1473
1474 struct fdi_m_n {
1475         u32        tu;
1476         u32        gmch_m;
1477         u32        gmch_n;
1478         u32        link_m;
1479         u32        link_n;
1480 };
1481
1482 static void
1483 fdi_reduce_ratio(u32 *num, u32 *den)
1484 {
1485         while (*num > 0xffffff || *den > 0xffffff) {
1486                 *num >>= 1;
1487                 *den >>= 1;
1488         }
1489 }
1490
1491 #define DATA_N 0x800000
1492 #define LINK_N 0x80000
1493
1494 static void
1495 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1496                 int pixel_clock, int link_clock,
1497                 struct fdi_m_n *m_n)
1498 {
1499         u64 temp;
1500
1501         m_n->tu = 64; /* default size */
1502
1503         temp = (u64) DATA_N * pixel_clock;
1504         temp = div_u64(temp, link_clock);
1505         m_n->gmch_m = (temp * bytes_per_pixel) / nlanes;
1506         m_n->gmch_n = DATA_N;
1507         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1508
1509         temp = (u64) LINK_N * pixel_clock;
1510         m_n->link_m = div_u64(temp, link_clock);
1511         m_n->link_n = LINK_N;
1512         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1513 }
1514
1515
1516 static int intel_crtc_mode_set(struct drm_crtc *crtc,
1517                                struct drm_display_mode *mode,
1518                                struct drm_display_mode *adjusted_mode,
1519                                int x, int y,
1520                                struct drm_framebuffer *old_fb)
1521 {
1522         struct drm_device *dev = crtc->dev;
1523         struct drm_i915_private *dev_priv = dev->dev_private;
1524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1525         int pipe = intel_crtc->pipe;
1526         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
1527         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1528         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
1529         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1530         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1531         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1532         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1533         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1534         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1535         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1536         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1537         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
1538         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
1539         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
1540         int refclk, num_outputs = 0;
1541         intel_clock_t clock;
1542         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
1543         bool ok, is_sdvo = false, is_dvo = false;
1544         bool is_crt = false, is_lvds = false, is_tv = false;
1545         struct drm_mode_config *mode_config = &dev->mode_config;
1546         struct drm_connector *connector;
1547         const intel_limit_t *limit;
1548         int ret;
1549         struct fdi_m_n m_n = {0};
1550         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
1551         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
1552         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
1553         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
1554         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
1555         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1556         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1557         int lvds_reg = LVDS;
1558         u32 temp;
1559         int sdvo_pixel_multiply;
1560
1561         drm_vblank_pre_modeset(dev, pipe);
1562
1563         list_for_each_entry(connector, &mode_config->connector_list, head) {
1564                 struct intel_output *intel_output = to_intel_output(connector);
1565
1566                 if (!connector->encoder || connector->encoder->crtc != crtc)
1567                         continue;
1568
1569                 switch (intel_output->type) {
1570                 case INTEL_OUTPUT_LVDS:
1571                         is_lvds = true;
1572                         break;
1573                 case INTEL_OUTPUT_SDVO:
1574                 case INTEL_OUTPUT_HDMI:
1575                         is_sdvo = true;
1576                         if (intel_output->needs_tv_clock)
1577                                 is_tv = true;
1578                         break;
1579                 case INTEL_OUTPUT_DVO:
1580                         is_dvo = true;
1581                         break;
1582                 case INTEL_OUTPUT_TVOUT:
1583                         is_tv = true;
1584                         break;
1585                 case INTEL_OUTPUT_ANALOG:
1586                         is_crt = true;
1587                         break;
1588                 }
1589
1590                 num_outputs++;
1591         }
1592
1593         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
1594                 refclk = dev_priv->lvds_ssc_freq * 1000;
1595                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
1596         } else if (IS_I9XX(dev)) {
1597                 refclk = 96000;
1598                 if (IS_IGDNG(dev))
1599                         refclk = 120000; /* 120Mhz refclk */
1600         } else {
1601                 refclk = 48000;
1602         }
1603
1604         /*
1605          * Returns a set of divisors for the desired target clock with the given
1606          * refclk, or FALSE.  The returned values represent the clock equation:
1607          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
1608          */
1609         limit = intel_limit(crtc);
1610         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
1611         if (!ok) {
1612                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
1613                 drm_vblank_post_modeset(dev, pipe);
1614                 return -EINVAL;
1615         }
1616
1617         /* SDVO TV has fixed PLL values depend on its clock range,
1618            this mirrors vbios setting. */
1619         if (is_sdvo && is_tv) {
1620                 if (adjusted_mode->clock >= 100000
1621                                 && adjusted_mode->clock < 140500) {
1622                         clock.p1 = 2;
1623                         clock.p2 = 10;
1624                         clock.n = 3;
1625                         clock.m1 = 16;
1626                         clock.m2 = 8;
1627                 } else if (adjusted_mode->clock >= 140500
1628                                 && adjusted_mode->clock <= 200000) {
1629                         clock.p1 = 1;
1630                         clock.p2 = 10;
1631                         clock.n = 6;
1632                         clock.m1 = 12;
1633                         clock.m2 = 8;
1634                 }
1635         }
1636
1637         /* FDI link */
1638         if (IS_IGDNG(dev))
1639                 igdng_compute_m_n(3, 4, /* lane num 4 */
1640                                 adjusted_mode->clock,
1641                                 270000, /* lane clock */
1642                                 &m_n);
1643
1644         if (IS_IGD(dev))
1645                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1646         else
1647                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
1648
1649         if (!IS_IGDNG(dev))
1650                 dpll = DPLL_VGA_MODE_DIS;
1651
1652         if (IS_I9XX(dev)) {
1653                 if (is_lvds)
1654                         dpll |= DPLLB_MODE_LVDS;
1655                 else
1656                         dpll |= DPLLB_MODE_DAC_SERIAL;
1657                 if (is_sdvo) {
1658                         dpll |= DPLL_DVO_HIGH_SPEED;
1659                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1660                         if (IS_I945G(dev) || IS_I945GM(dev))
1661                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1662                         else if (IS_IGDNG(dev))
1663                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
1664                 }
1665
1666                 /* compute bitmask from p1 value */
1667                 if (IS_IGD(dev))
1668                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1669                 else {
1670                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1671                         /* also FPA1 */
1672                         if (IS_IGDNG(dev))
1673                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1674                 }
1675                 switch (clock.p2) {
1676                 case 5:
1677                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1678                         break;
1679                 case 7:
1680                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1681                         break;
1682                 case 10:
1683                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1684                         break;
1685                 case 14:
1686                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1687                         break;
1688                 }
1689                 if (IS_I965G(dev) && !IS_IGDNG(dev))
1690                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1691         } else {
1692                 if (is_lvds) {
1693                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1694                 } else {
1695                         if (clock.p1 == 2)
1696                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
1697                         else
1698                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1699                         if (clock.p2 == 4)
1700                                 dpll |= PLL_P2_DIVIDE_BY_4;
1701                 }
1702         }
1703
1704         if (is_sdvo && is_tv)
1705                 dpll |= PLL_REF_INPUT_TVCLKINBC;
1706         else if (is_tv)
1707                 /* XXX: just matching BIOS for now */
1708                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
1709                 dpll |= 3;
1710         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
1711                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1712         else
1713                 dpll |= PLL_REF_INPUT_DREFCLK;
1714
1715         /* setup pipeconf */
1716         pipeconf = I915_READ(pipeconf_reg);
1717
1718         /* Set up the display plane register */
1719         dspcntr = DISPPLANE_GAMMA_ENABLE;
1720
1721         /* IGDNG's plane is forced to pipe, bit 24 is to
1722            enable color space conversion */
1723         if (!IS_IGDNG(dev)) {
1724                 if (pipe == 0)
1725                         dspcntr |= DISPPLANE_SEL_PIPE_A;
1726                 else
1727                         dspcntr |= DISPPLANE_SEL_PIPE_B;
1728         }
1729
1730         if (pipe == 0 && !IS_I965G(dev)) {
1731                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
1732                  * core speed.
1733                  *
1734                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
1735                  * pipe == 0 check?
1736                  */
1737                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
1738                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
1739                 else
1740                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
1741         }
1742
1743         dspcntr |= DISPLAY_PLANE_ENABLE;
1744         pipeconf |= PIPEACONF_ENABLE;
1745         dpll |= DPLL_VCO_ENABLE;
1746
1747
1748         /* Disable the panel fitter if it was on our pipe */
1749         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
1750                 I915_WRITE(PFIT_CONTROL, 0);
1751
1752         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1753         drm_mode_debug_printmodeline(mode);
1754
1755         /* assign to IGDNG registers */
1756         if (IS_IGDNG(dev)) {
1757                 fp_reg = pch_fp_reg;
1758                 dpll_reg = pch_dpll_reg;
1759         }
1760
1761         if (dpll & DPLL_VCO_ENABLE) {
1762                 I915_WRITE(fp_reg, fp);
1763                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
1764                 I915_READ(dpll_reg);
1765                 udelay(150);
1766         }
1767
1768         if (IS_IGDNG(dev)) {
1769                 /* enable PCH clock reference source */
1770                 /* XXX need to change the setting for other outputs */
1771                 u32 temp;
1772                 temp = I915_READ(PCH_DREF_CONTROL);
1773                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
1774                 temp |= DREF_NONSPREAD_CK505_ENABLE;
1775                 temp &= ~DREF_SSC_SOURCE_MASK;
1776                 temp |= DREF_SSC_SOURCE_ENABLE;
1777                 temp &= ~DREF_SSC1_ENABLE;
1778                 /* if no eDP, disable source output to CPU */
1779                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
1780                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
1781                 I915_WRITE(PCH_DREF_CONTROL, temp);
1782         }
1783
1784         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1785          * This is an exception to the general rule that mode_set doesn't turn
1786          * things on.
1787          */
1788         if (is_lvds) {
1789                 u32 lvds;
1790
1791                 if (IS_IGDNG(dev))
1792                         lvds_reg = PCH_LVDS;
1793
1794                 lvds = I915_READ(lvds_reg);
1795                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
1796                 /* Set the B0-B3 data pairs corresponding to whether we're going to
1797                  * set the DPLLs for dual-channel mode or not.
1798                  */
1799                 if (clock.p2 == 7)
1800                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1801                 else
1802                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1803
1804                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1805                  * appropriately here, but we need to look more thoroughly into how
1806                  * panels behave in the two modes.
1807                  */
1808
1809                 I915_WRITE(lvds_reg, lvds);
1810                 I915_READ(lvds_reg);
1811         }
1812
1813         I915_WRITE(fp_reg, fp);
1814         I915_WRITE(dpll_reg, dpll);
1815         I915_READ(dpll_reg);
1816         /* Wait for the clocks to stabilize. */
1817         udelay(150);
1818
1819         if (IS_I965G(dev) && !IS_IGDNG(dev)) {
1820                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1821                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
1822                            ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1823         } else {
1824                 /* write it again -- the BIOS does, after all */
1825                 I915_WRITE(dpll_reg, dpll);
1826         }
1827         I915_READ(dpll_reg);
1828         /* Wait for the clocks to stabilize. */
1829         udelay(150);
1830
1831         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
1832                    ((adjusted_mode->crtc_htotal - 1) << 16));
1833         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
1834                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
1835         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
1836                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
1837         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
1838                    ((adjusted_mode->crtc_vtotal - 1) << 16));
1839         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
1840                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
1841         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
1842                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
1843         /* pipesrc and dspsize control the size that is scaled from, which should
1844          * always be the user's requested size.
1845          */
1846         if (!IS_IGDNG(dev)) {
1847                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
1848                                 (mode->hdisplay - 1));
1849                 I915_WRITE(dsppos_reg, 0);
1850         }
1851         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1852
1853         if (IS_IGDNG(dev)) {
1854                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
1855                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
1856                 I915_WRITE(link_m1_reg, m_n.link_m);
1857                 I915_WRITE(link_n1_reg, m_n.link_n);
1858
1859                  /* enable FDI RX PLL too */
1860                 temp = I915_READ(fdi_rx_reg);
1861                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1862                 udelay(200);
1863         }
1864
1865         I915_WRITE(pipeconf_reg, pipeconf);
1866         I915_READ(pipeconf_reg);
1867
1868         intel_wait_for_vblank(dev);
1869
1870         I915_WRITE(dspcntr_reg, dspcntr);
1871
1872         /* Flush the plane changes */
1873         ret = intel_pipe_set_base(crtc, x, y, old_fb);
1874         drm_vblank_post_modeset(dev, pipe);
1875
1876         return ret;
1877 }
1878
1879 /** Loads the palette/gamma unit for the CRTC with the prepared values */
1880 void intel_crtc_load_lut(struct drm_crtc *crtc)
1881 {
1882         struct drm_device *dev = crtc->dev;
1883         struct drm_i915_private *dev_priv = dev->dev_private;
1884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1885         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
1886         int i;
1887
1888         /* The clocks have to be on to load the palette. */
1889         if (!crtc->enabled)
1890                 return;
1891
1892         /* use legacy palette for IGDNG */
1893         if (IS_IGDNG(dev))
1894                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
1895                                                    LGC_PALETTE_B;
1896
1897         for (i = 0; i < 256; i++) {
1898                 I915_WRITE(palreg + 4 * i,
1899                            (intel_crtc->lut_r[i] << 16) |
1900                            (intel_crtc->lut_g[i] << 8) |
1901                            intel_crtc->lut_b[i]);
1902         }
1903 }
1904
1905 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
1906                                  struct drm_file *file_priv,
1907                                  uint32_t handle,
1908                                  uint32_t width, uint32_t height)
1909 {
1910         struct drm_device *dev = crtc->dev;
1911         struct drm_i915_private *dev_priv = dev->dev_private;
1912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1913         struct drm_gem_object *bo;
1914         struct drm_i915_gem_object *obj_priv;
1915         int pipe = intel_crtc->pipe;
1916         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1917         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1918         uint32_t temp = I915_READ(control);
1919         size_t addr;
1920         int ret;
1921
1922         DRM_DEBUG("\n");
1923
1924         /* if we want to turn off the cursor ignore width and height */
1925         if (!handle) {
1926                 DRM_DEBUG("cursor off\n");
1927                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
1928                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
1929                         temp |= CURSOR_MODE_DISABLE;
1930                 } else {
1931                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
1932                 }
1933                 addr = 0;
1934                 bo = NULL;
1935                 mutex_lock(&dev->struct_mutex);
1936                 goto finish;
1937         }
1938
1939         /* Currently we only support 64x64 cursors */
1940         if (width != 64 || height != 64) {
1941                 DRM_ERROR("we currently only support 64x64 cursors\n");
1942                 return -EINVAL;
1943         }
1944
1945         bo = drm_gem_object_lookup(dev, file_priv, handle);
1946         if (!bo)
1947                 return -ENOENT;
1948
1949         obj_priv = bo->driver_private;
1950
1951         if (bo->size < width * height * 4) {
1952                 DRM_ERROR("buffer is to small\n");
1953                 ret = -ENOMEM;
1954                 goto fail;
1955         }
1956
1957         /* we only need to pin inside GTT if cursor is non-phy */
1958         mutex_lock(&dev->struct_mutex);
1959         if (!dev_priv->cursor_needs_physical) {
1960                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
1961                 if (ret) {
1962                         DRM_ERROR("failed to pin cursor bo\n");
1963                         goto fail_locked;
1964                 }
1965                 addr = obj_priv->gtt_offset;
1966         } else {
1967                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
1968                 if (ret) {
1969                         DRM_ERROR("failed to attach phys object\n");
1970                         goto fail_locked;
1971                 }
1972                 addr = obj_priv->phys_obj->handle->busaddr;
1973         }
1974
1975         if (!IS_I9XX(dev))
1976                 I915_WRITE(CURSIZE, (height << 12) | width);
1977
1978         /* Hooray for CUR*CNTR differences */
1979         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
1980                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
1981                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1982                 temp |= (pipe << 28); /* Connect to correct pipe */
1983         } else {
1984                 temp &= ~(CURSOR_FORMAT_MASK);
1985                 temp |= CURSOR_ENABLE;
1986                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
1987         }
1988
1989  finish:
1990         I915_WRITE(control, temp);
1991         I915_WRITE(base, addr);
1992
1993         if (intel_crtc->cursor_bo) {
1994                 if (dev_priv->cursor_needs_physical) {
1995                         if (intel_crtc->cursor_bo != bo)
1996                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
1997                 } else
1998                         i915_gem_object_unpin(intel_crtc->cursor_bo);
1999                 drm_gem_object_unreference(intel_crtc->cursor_bo);
2000         }
2001         mutex_unlock(&dev->struct_mutex);
2002
2003         intel_crtc->cursor_addr = addr;
2004         intel_crtc->cursor_bo = bo;
2005
2006         return 0;
2007 fail:
2008         mutex_lock(&dev->struct_mutex);
2009 fail_locked:
2010         drm_gem_object_unreference(bo);
2011         mutex_unlock(&dev->struct_mutex);
2012         return ret;
2013 }
2014
2015 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2016 {
2017         struct drm_device *dev = crtc->dev;
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2020         int pipe = intel_crtc->pipe;
2021         uint32_t temp = 0;
2022         uint32_t adder;
2023
2024         if (x < 0) {
2025                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
2026                 x = -x;
2027         }
2028         if (y < 0) {
2029                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
2030                 y = -y;
2031         }
2032
2033         temp |= x << CURSOR_X_SHIFT;
2034         temp |= y << CURSOR_Y_SHIFT;
2035
2036         adder = intel_crtc->cursor_addr;
2037         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2038         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2039
2040         return 0;
2041 }
2042
2043 /** Sets the color ramps on behalf of RandR */
2044 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2045                                  u16 blue, int regno)
2046 {
2047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2048
2049         intel_crtc->lut_r[regno] = red >> 8;
2050         intel_crtc->lut_g[regno] = green >> 8;
2051         intel_crtc->lut_b[regno] = blue >> 8;
2052 }
2053
2054 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2055                                  u16 *blue, uint32_t size)
2056 {
2057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2058         int i;
2059
2060         if (size != 256)
2061                 return;
2062
2063         for (i = 0; i < 256; i++) {
2064                 intel_crtc->lut_r[i] = red[i] >> 8;
2065                 intel_crtc->lut_g[i] = green[i] >> 8;
2066                 intel_crtc->lut_b[i] = blue[i] >> 8;
2067         }
2068
2069         intel_crtc_load_lut(crtc);
2070 }
2071
2072 /**
2073  * Get a pipe with a simple mode set on it for doing load-based monitor
2074  * detection.
2075  *
2076  * It will be up to the load-detect code to adjust the pipe as appropriate for
2077  * its requirements.  The pipe will be connected to no other outputs.
2078  *
2079  * Currently this code will only succeed if there is a pipe with no outputs
2080  * configured for it.  In the future, it could choose to temporarily disable
2081  * some outputs to free up a pipe for its use.
2082  *
2083  * \return crtc, or NULL if no pipes are available.
2084  */
2085
2086 /* VESA 640x480x72Hz mode to set on the pipe */
2087 static struct drm_display_mode load_detect_mode = {
2088         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2089                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2090 };
2091
2092 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2093                                             struct drm_display_mode *mode,
2094                                             int *dpms_mode)
2095 {
2096         struct intel_crtc *intel_crtc;
2097         struct drm_crtc *possible_crtc;
2098         struct drm_crtc *supported_crtc =NULL;
2099         struct drm_encoder *encoder = &intel_output->enc;
2100         struct drm_crtc *crtc = NULL;
2101         struct drm_device *dev = encoder->dev;
2102         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2103         struct drm_crtc_helper_funcs *crtc_funcs;
2104         int i = -1;
2105
2106         /*
2107          * Algorithm gets a little messy:
2108          *   - if the connector already has an assigned crtc, use it (but make
2109          *     sure it's on first)
2110          *   - try to find the first unused crtc that can drive this connector,
2111          *     and use that if we find one
2112          *   - if there are no unused crtcs available, try to use the first
2113          *     one we found that supports the connector
2114          */
2115
2116         /* See if we already have a CRTC for this connector */
2117         if (encoder->crtc) {
2118                 crtc = encoder->crtc;
2119                 /* Make sure the crtc and connector are running */
2120                 intel_crtc = to_intel_crtc(crtc);
2121                 *dpms_mode = intel_crtc->dpms_mode;
2122                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2123                         crtc_funcs = crtc->helper_private;
2124                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2125                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2126                 }
2127                 return crtc;
2128         }
2129
2130         /* Find an unused one (if possible) */
2131         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2132                 i++;
2133                 if (!(encoder->possible_crtcs & (1 << i)))
2134                         continue;
2135                 if (!possible_crtc->enabled) {
2136                         crtc = possible_crtc;
2137                         break;
2138                 }
2139                 if (!supported_crtc)
2140                         supported_crtc = possible_crtc;
2141         }
2142
2143         /*
2144          * If we didn't find an unused CRTC, don't use any.
2145          */
2146         if (!crtc) {
2147                 return NULL;
2148         }
2149
2150         encoder->crtc = crtc;
2151         intel_output->base.encoder = encoder;
2152         intel_output->load_detect_temp = true;
2153
2154         intel_crtc = to_intel_crtc(crtc);
2155         *dpms_mode = intel_crtc->dpms_mode;
2156
2157         if (!crtc->enabled) {
2158                 if (!mode)
2159                         mode = &load_detect_mode;
2160                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
2161         } else {
2162                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2163                         crtc_funcs = crtc->helper_private;
2164                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2165                 }
2166
2167                 /* Add this connector to the crtc */
2168                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
2169                 encoder_funcs->commit(encoder);
2170         }
2171         /* let the connector get through one full cycle before testing */
2172         intel_wait_for_vblank(dev);
2173
2174         return crtc;
2175 }
2176
2177 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
2178 {
2179         struct drm_encoder *encoder = &intel_output->enc;
2180         struct drm_device *dev = encoder->dev;
2181         struct drm_crtc *crtc = encoder->crtc;
2182         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2183         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2184
2185         if (intel_output->load_detect_temp) {
2186                 encoder->crtc = NULL;
2187                 intel_output->base.encoder = NULL;
2188                 intel_output->load_detect_temp = false;
2189                 crtc->enabled = drm_helper_crtc_in_use(crtc);
2190                 drm_helper_disable_unused_functions(dev);
2191         }
2192
2193         /* Switch crtc and output back off if necessary */
2194         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
2195                 if (encoder->crtc == crtc)
2196                         encoder_funcs->dpms(encoder, dpms_mode);
2197                 crtc_funcs->dpms(crtc, dpms_mode);
2198         }
2199 }
2200
2201 /* Returns the clock of the currently programmed mode of the given pipe. */
2202 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
2203 {
2204         struct drm_i915_private *dev_priv = dev->dev_private;
2205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2206         int pipe = intel_crtc->pipe;
2207         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
2208         u32 fp;
2209         intel_clock_t clock;
2210
2211         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2212                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
2213         else
2214                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
2215
2216         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
2217         if (IS_IGD(dev)) {
2218                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2219                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2220         } else {
2221                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2222                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2223         }
2224
2225         if (IS_I9XX(dev)) {
2226                 if (IS_IGD(dev))
2227                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2228                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
2229                 else
2230                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2231                                DPLL_FPA01_P1_POST_DIV_SHIFT);
2232
2233                 switch (dpll & DPLL_MODE_MASK) {
2234                 case DPLLB_MODE_DAC_SERIAL:
2235                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
2236                                 5 : 10;
2237                         break;
2238                 case DPLLB_MODE_LVDS:
2239                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
2240                                 7 : 14;
2241                         break;
2242                 default:
2243                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
2244                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
2245                         return 0;
2246                 }
2247
2248                 /* XXX: Handle the 100Mhz refclk */
2249                 intel_clock(dev, 96000, &clock);
2250         } else {
2251                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2252
2253                 if (is_lvds) {
2254                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2255                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
2256                         clock.p2 = 14;
2257
2258                         if ((dpll & PLL_REF_INPUT_MASK) ==
2259                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
2260                                 /* XXX: might not be 66MHz */
2261                                 intel_clock(dev, 66000, &clock);
2262                         } else
2263                                 intel_clock(dev, 48000, &clock);
2264                 } else {
2265                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
2266                                 clock.p1 = 2;
2267                         else {
2268                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2269                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
2270                         }
2271                         if (dpll & PLL_P2_DIVIDE_BY_4)
2272                                 clock.p2 = 4;
2273                         else
2274                                 clock.p2 = 2;
2275
2276                         intel_clock(dev, 48000, &clock);
2277                 }
2278         }
2279
2280         /* XXX: It would be nice to validate the clocks, but we can't reuse
2281          * i830PllIsValid() because it relies on the xf86_config connector
2282          * configuration being accurate, which it isn't necessarily.
2283          */
2284
2285         return clock.dot;
2286 }
2287
2288 /** Returns the currently programmed mode of the given pipe. */
2289 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
2290                                              struct drm_crtc *crtc)
2291 {
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294         int pipe = intel_crtc->pipe;
2295         struct drm_display_mode *mode;
2296         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
2297         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
2298         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
2299         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
2300
2301         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
2302         if (!mode)
2303                 return NULL;
2304
2305         mode->clock = intel_crtc_clock_get(dev, crtc);
2306         mode->hdisplay = (htot & 0xffff) + 1;
2307         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
2308         mode->hsync_start = (hsync & 0xffff) + 1;
2309         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
2310         mode->vdisplay = (vtot & 0xffff) + 1;
2311         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
2312         mode->vsync_start = (vsync & 0xffff) + 1;
2313         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
2314
2315         drm_mode_set_name(mode);
2316         drm_mode_set_crtcinfo(mode, 0);
2317
2318         return mode;
2319 }
2320
2321 static void intel_crtc_destroy(struct drm_crtc *crtc)
2322 {
2323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324
2325         if (intel_crtc->mode_set.mode)
2326                 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
2327         drm_crtc_cleanup(crtc);
2328         kfree(intel_crtc);
2329 }
2330
2331 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
2332         .dpms = intel_crtc_dpms,
2333         .mode_fixup = intel_crtc_mode_fixup,
2334         .mode_set = intel_crtc_mode_set,
2335         .mode_set_base = intel_pipe_set_base,
2336         .prepare = intel_crtc_prepare,
2337         .commit = intel_crtc_commit,
2338 };
2339
2340 static const struct drm_crtc_funcs intel_crtc_funcs = {
2341         .cursor_set = intel_crtc_cursor_set,
2342         .cursor_move = intel_crtc_cursor_move,
2343         .gamma_set = intel_crtc_gamma_set,
2344         .set_config = drm_crtc_helper_set_config,
2345         .destroy = intel_crtc_destroy,
2346 };
2347
2348
2349 static void intel_crtc_init(struct drm_device *dev, int pipe)
2350 {
2351         struct intel_crtc *intel_crtc;
2352         int i;
2353
2354         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2355         if (intel_crtc == NULL)
2356                 return;
2357
2358         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2359
2360         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
2361         intel_crtc->pipe = pipe;
2362         for (i = 0; i < 256; i++) {
2363                 intel_crtc->lut_r[i] = i;
2364                 intel_crtc->lut_g[i] = i;
2365                 intel_crtc->lut_b[i] = i;
2366         }
2367
2368         intel_crtc->cursor_addr = 0;
2369         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
2370         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2371
2372         intel_crtc->mode_set.crtc = &intel_crtc->base;
2373         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
2374         intel_crtc->mode_set.num_connectors = 0;
2375
2376         if (i915_fbpercrtc) {
2377
2378
2379
2380         }
2381 }
2382
2383 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
2384                                 struct drm_file *file_priv)
2385 {
2386         drm_i915_private_t *dev_priv = dev->dev_private;
2387         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
2388         struct drm_crtc *crtc = NULL;
2389         int pipe = -1;
2390
2391         if (!dev_priv) {
2392                 DRM_ERROR("called with no initialization\n");
2393                 return -EINVAL;
2394         }
2395
2396         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2397                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2398                 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
2399                         pipe = intel_crtc->pipe;
2400                         break;
2401                 }
2402         }
2403
2404         if (pipe == -1) {
2405                 DRM_ERROR("no such CRTC id\n");
2406                 return -EINVAL;
2407         }
2408
2409         pipe_from_crtc_id->pipe = pipe;
2410
2411        return 0;
2412 }
2413
2414 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
2415 {
2416         struct drm_crtc *crtc = NULL;
2417
2418         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2419                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2420                 if (intel_crtc->pipe == pipe)
2421                         break;
2422         }
2423         return crtc;
2424 }
2425
2426 static int intel_connector_clones(struct drm_device *dev, int type_mask)
2427 {
2428         int index_mask = 0;
2429         struct drm_connector *connector;
2430         int entry = 0;
2431
2432         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2433                 struct intel_output *intel_output = to_intel_output(connector);
2434                 if (type_mask & (1 << intel_output->type))
2435                         index_mask |= (1 << entry);
2436                 entry++;
2437         }
2438         return index_mask;
2439 }
2440
2441
2442 static void intel_setup_outputs(struct drm_device *dev)
2443 {
2444         struct drm_i915_private *dev_priv = dev->dev_private;
2445         struct drm_connector *connector;
2446
2447         intel_crt_init(dev);
2448
2449         /* Set up integrated LVDS */
2450         if (IS_MOBILE(dev) && !IS_I830(dev))
2451                 intel_lvds_init(dev);
2452
2453         if (IS_IGDNG(dev)) {
2454                 int found;
2455
2456                 if (I915_READ(HDMIB) & PORT_DETECTED) {
2457                         /* check SDVOB */
2458                         /* found = intel_sdvo_init(dev, HDMIB); */
2459                         found = 0;
2460                         if (!found)
2461                                 intel_hdmi_init(dev, HDMIB);
2462                 }
2463
2464                 if (I915_READ(HDMIC) & PORT_DETECTED)
2465                         intel_hdmi_init(dev, HDMIC);
2466
2467                 if (I915_READ(HDMID) & PORT_DETECTED)
2468                         intel_hdmi_init(dev, HDMID);
2469
2470         } else if (IS_I9XX(dev)) {
2471                 int found;
2472                 u32 reg;
2473
2474                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
2475                         found = intel_sdvo_init(dev, SDVOB);
2476                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2477                                 intel_hdmi_init(dev, SDVOB);
2478                 }
2479
2480                 /* Before G4X SDVOC doesn't have its own detect register */
2481                 if (IS_G4X(dev))
2482                         reg = SDVOC;
2483                 else
2484                         reg = SDVOB;
2485
2486                 if (I915_READ(reg) & SDVO_DETECTED) {
2487                         found = intel_sdvo_init(dev, SDVOC);
2488                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2489                                 intel_hdmi_init(dev, SDVOC);
2490                 }
2491         } else
2492                 intel_dvo_init(dev);
2493
2494         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
2495                 intel_tv_init(dev);
2496
2497         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2498                 struct intel_output *intel_output = to_intel_output(connector);
2499                 struct drm_encoder *encoder = &intel_output->enc;
2500                 int crtc_mask = 0, clone_mask = 0;
2501
2502                 /* valid crtcs */
2503                 switch(intel_output->type) {
2504                 case INTEL_OUTPUT_HDMI:
2505                         crtc_mask = ((1 << 0)|
2506                                      (1 << 1));
2507                         clone_mask = ((1 << INTEL_OUTPUT_HDMI));
2508                         break;
2509                 case INTEL_OUTPUT_DVO:
2510                 case INTEL_OUTPUT_SDVO:
2511                         crtc_mask = ((1 << 0)|
2512                                      (1 << 1));
2513                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
2514                                       (1 << INTEL_OUTPUT_DVO) |
2515                                       (1 << INTEL_OUTPUT_SDVO));
2516                         break;
2517                 case INTEL_OUTPUT_ANALOG:
2518                         crtc_mask = ((1 << 0)|
2519                                      (1 << 1));
2520                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
2521                                       (1 << INTEL_OUTPUT_DVO) |
2522                                       (1 << INTEL_OUTPUT_SDVO));
2523                         break;
2524                 case INTEL_OUTPUT_LVDS:
2525                         crtc_mask = (1 << 1);
2526                         clone_mask = (1 << INTEL_OUTPUT_LVDS);
2527                         break;
2528                 case INTEL_OUTPUT_TVOUT:
2529                         crtc_mask = ((1 << 0) |
2530                                      (1 << 1));
2531                         clone_mask = (1 << INTEL_OUTPUT_TVOUT);
2532                         break;
2533                 }
2534                 encoder->possible_crtcs = crtc_mask;
2535                 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
2536         }
2537 }
2538
2539 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
2540 {
2541         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2542         struct drm_device *dev = fb->dev;
2543
2544         if (fb->fbdev)
2545                 intelfb_remove(dev, fb);
2546
2547         drm_framebuffer_cleanup(fb);
2548         mutex_lock(&dev->struct_mutex);
2549         drm_gem_object_unreference(intel_fb->obj);
2550         mutex_unlock(&dev->struct_mutex);
2551
2552         kfree(intel_fb);
2553 }
2554
2555 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
2556                                                 struct drm_file *file_priv,
2557                                                 unsigned int *handle)
2558 {
2559         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2560         struct drm_gem_object *object = intel_fb->obj;
2561
2562         return drm_gem_handle_create(file_priv, object, handle);
2563 }
2564
2565 static const struct drm_framebuffer_funcs intel_fb_funcs = {
2566         .destroy = intel_user_framebuffer_destroy,
2567         .create_handle = intel_user_framebuffer_create_handle,
2568 };
2569
2570 int intel_framebuffer_create(struct drm_device *dev,
2571                              struct drm_mode_fb_cmd *mode_cmd,
2572                              struct drm_framebuffer **fb,
2573                              struct drm_gem_object *obj)
2574 {
2575         struct intel_framebuffer *intel_fb;
2576         int ret;
2577
2578         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2579         if (!intel_fb)
2580                 return -ENOMEM;
2581
2582         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
2583         if (ret) {
2584                 DRM_ERROR("framebuffer init failed %d\n", ret);
2585                 return ret;
2586         }
2587
2588         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
2589
2590         intel_fb->obj = obj;
2591
2592         *fb = &intel_fb->base;
2593
2594         return 0;
2595 }
2596
2597
2598 static struct drm_framebuffer *
2599 intel_user_framebuffer_create(struct drm_device *dev,
2600                               struct drm_file *filp,
2601                               struct drm_mode_fb_cmd *mode_cmd)
2602 {
2603         struct drm_gem_object *obj;
2604         struct drm_framebuffer *fb;
2605         int ret;
2606
2607         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
2608         if (!obj)
2609                 return NULL;
2610
2611         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
2612         if (ret) {
2613                 mutex_lock(&dev->struct_mutex);
2614                 drm_gem_object_unreference(obj);
2615                 mutex_unlock(&dev->struct_mutex);
2616                 return NULL;
2617         }
2618
2619         return fb;
2620 }
2621
2622 static const struct drm_mode_config_funcs intel_mode_funcs = {
2623         .fb_create = intel_user_framebuffer_create,
2624         .fb_changed = intelfb_probe,
2625 };
2626
2627 void intel_modeset_init(struct drm_device *dev)
2628 {
2629         int num_pipe;
2630         int i;
2631
2632         drm_mode_config_init(dev);
2633
2634         dev->mode_config.min_width = 0;
2635         dev->mode_config.min_height = 0;
2636
2637         dev->mode_config.funcs = (void *)&intel_mode_funcs;
2638
2639         if (IS_I965G(dev)) {
2640                 dev->mode_config.max_width = 8192;
2641                 dev->mode_config.max_height = 8192;
2642         } else {
2643                 dev->mode_config.max_width = 2048;
2644                 dev->mode_config.max_height = 2048;
2645         }
2646
2647         /* set memory base */
2648         if (IS_I9XX(dev))
2649                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
2650         else
2651                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
2652
2653         if (IS_MOBILE(dev) || IS_I9XX(dev))
2654                 num_pipe = 2;
2655         else
2656                 num_pipe = 1;
2657         DRM_DEBUG("%d display pipe%s available.\n",
2658                   num_pipe, num_pipe > 1 ? "s" : "");
2659
2660         for (i = 0; i < num_pipe; i++) {
2661                 intel_crtc_init(dev, i);
2662         }
2663
2664         intel_setup_outputs(dev);
2665 }
2666
2667 void intel_modeset_cleanup(struct drm_device *dev)
2668 {
2669         drm_mode_config_cleanup(dev);
2670 }
2671
2672
2673 /* current intel driver doesn't take advantage of encoders
2674    always give back the encoder for the connector
2675 */
2676 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
2677 {
2678         struct intel_output *intel_output = to_intel_output(connector);
2679
2680         return &intel_output->enc;
2681 }