git.oblomov.eu Git - linux-2.6/blob - drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/string.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/tty.h>
  24 #include <linux/serial_core.h>
  25 #include <linux/8250_pci.h>
  26 #include <linux/bitops.h>
  27
  28 #include <asm/byteorder.h>
  29 #include <asm/io.h>
  30
  31 #include "8250.h"
  32
  33 #undef SERIAL_DEBUG_PCI
  34
  35 /*
  36  * init function returns:
  37  *  > 0 - number of ports
  38  *  = 0 - use board->num_ports
  39  *  < 0 - error
  40  */
  41 struct pci_serial_quirk {
  42         u32     vendor;
  43         u32     device;
  44         u32     subvendor;
  45         u32     subdevice;
  46         int     (*init)(struct pci_dev *dev);
  47         int     (*setup)(struct serial_private *, struct pciserial_board *,
  48                          struct uart_port *, int);
  49         void    (*exit)(struct pci_dev *dev);
  50 };
  51
  52 #define PCI_NUM_BAR_RESOURCES   6
  53
  54 struct serial_private {
  55         struct pci_dev          *dev;
  56         unsigned int            nr;
  57         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  58         struct pci_serial_quirk *quirk;
  59         int                     line[0];
  60 };
  61
  62 static void moan_device(const char *str, struct pci_dev *dev)
  63 {
  64         printk(KERN_WARNING "%s: %s\n"
  65                KERN_WARNING "Please send the output of lspci -vv, this\n"
  66                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  67                KERN_WARNING "manufacturer and name of serial board or\n"
  68                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  69                pci_name(dev), str, dev->vendor, dev->device,
  70                dev->subsystem_vendor, dev->subsystem_device);
  71 }
  72
  73 static int
  74 setup_port(struct serial_private *priv, struct uart_port *port,
  75            int bar, int offset, int regshift)
  76 {
  77         struct pci_dev *dev = priv->dev;
  78         unsigned long base, len;
  79
  80         if (bar >= PCI_NUM_BAR_RESOURCES)
  81                 return -EINVAL;
  82
  83         base = pci_resource_start(dev, bar);
  84
  85         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  86                 len =  pci_resource_len(dev, bar);
  87
  88                 if (!priv->remapped_bar[bar])
  89                         priv->remapped_bar[bar] = ioremap(base, len);
  90                 if (!priv->remapped_bar[bar])
  91                         return -ENOMEM;
  92
  93                 port->iotype = UPIO_MEM;
  94                 port->iobase = 0;
  95                 port->mapbase = base + offset;
  96                 port->membase = priv->remapped_bar[bar] + offset;
  97                 port->regshift = regshift;
  98         } else {
  99                 port->iotype = UPIO_PORT;
 100                 port->iobase = base + offset;
 101                 port->mapbase = 0;
 102                 port->membase = NULL;
 103                 port->regshift = 0;
 104         }
 105         return 0;
 106 }
 107
 108 /*
 109  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 110  */
 111 static int addidata_apci7800_setup(struct serial_private *priv,
 112                                 struct pciserial_board *board,
 113                                 struct uart_port *port, int idx)
 114 {
 115         unsigned int bar = 0, offset = board->first_offset;
 116         bar = FL_GET_BASE(board->flags);
 117
 118         if (idx < 2) {
 119                 offset += idx * board->uart_offset;
 120         } else if ((idx >= 2) && (idx < 4)) {
 121                 bar += 1;
 122                 offset += ((idx - 2) * board->uart_offset);
 123         } else if ((idx >= 4) && (idx < 6)) {
 124                 bar += 2;
 125                 offset += ((idx - 4) * board->uart_offset);
 126         } else if (idx >= 6) {
 127                 bar += 3;
 128                 offset += ((idx - 6) * board->uart_offset);
 129         }
 130
 131         return setup_port(priv, port, bar, offset, board->reg_shift);
 132 }
 133
 134 /*
 135  * AFAVLAB uses a different mixture of BARs and offsets
 136  * Not that ugly ;) -- HW
 137  */
 138 static int
 139 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 140               struct uart_port *port, int idx)
 141 {
 142         unsigned int bar, offset = board->first_offset;
 143
 144         bar = FL_GET_BASE(board->flags);
 145         if (idx < 4)
 146                 bar += idx;
 147         else {
 148                 bar = 4;
 149                 offset += (idx - 4) * board->uart_offset;
 150         }
 151
 152         return setup_port(priv, port, bar, offset, board->reg_shift);
 153 }
 154
 155 /*
 156  * HP's Remote Management Console.  The Diva chip came in several
 157  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 158  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 159  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 160  * one Diva chip, but it has been expanded to 5 UARTs.
 161  */
 162 static int pci_hp_diva_init(struct pci_dev *dev)
 163 {
 164         int rc = 0;
 165
 166         switch (dev->subsystem_device) {
 167         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 168         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 169         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 170         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 171                 rc = 3;
 172                 break;
 173         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 174                 rc = 2;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 177                 rc = 4;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 180         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 181                 rc = 1;
 182                 break;
 183         }
 184
 185         return rc;
 186 }
 187
 188 /*
 189  * HP's Diva chip puts the 4th/5th serial port further out, and
 190  * some serial ports are supposed to be hidden on certain models.
 191  */
 192 static int
 193 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 194               struct uart_port *port, int idx)
 195 {
 196         unsigned int offset = board->first_offset;
 197         unsigned int bar = FL_GET_BASE(board->flags);
 198
 199         switch (priv->dev->subsystem_device) {
 200         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 201                 if (idx == 3)
 202                         idx++;
 203                 break;
 204         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 205                 if (idx > 0)
 206                         idx++;
 207                 if (idx > 2)
 208                         idx++;
 209                 break;
 210         }
 211         if (idx > 2)
 212                 offset = 0x18;
 213
 214         offset += idx * board->uart_offset;
 215
 216         return setup_port(priv, port, bar, offset, board->reg_shift);
 217 }
 218
 219 /*
 220  * Added for EKF Intel i960 serial boards
 221  */
 222 static int pci_inteli960ni_init(struct pci_dev *dev)
 223 {
 224         unsigned long oldval;
 225
 226         if (!(dev->subsystem_device & 0x1000))
 227                 return -ENODEV;
 228
 229         /* is firmware started? */
 230         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 231         if (oldval == 0x00001000L) { /* RESET value */
 232                 printk(KERN_DEBUG "Local i960 firmware missing");
 233                 return -ENODEV;
 234         }
 235         return 0;
 236 }
 237
 238 /*
 239  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 240  * that the card interrupt be explicitly enabled or disabled.  This
 241  * seems to be mainly needed on card using the PLX which also use I/O
 242  * mapped memory.
 243  */
 244 static int pci_plx9050_init(struct pci_dev *dev)
 245 {
 246         u8 irq_config;
 247         void __iomem *p;
 248
 249         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 250                 moan_device("no memory in bar 0", dev);
 251                 return 0;
 252         }
 253
 254         irq_config = 0x41;
 255         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 256             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
 257                 irq_config = 0x43;
 258         }
 259         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 260             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 261                 /*
 262                  * As the megawolf cards have the int pins active
 263                  * high, and have 2 UART chips, both ints must be
 264                  * enabled on the 9050. Also, the UARTS are set in
 265                  * 16450 mode by default, so we have to enable the
 266                  * 16C950 'enhanced' mode so that we can use the
 267                  * deep FIFOs
 268                  */
 269                 irq_config = 0x5b;
 270         }
 271
 272         /*
 273          * enable/disable interrupts
 274          */
 275         p = ioremap(pci_resource_start(dev, 0), 0x80);
 276         if (p == NULL)
 277                 return -ENOMEM;
 278         writel(irq_config, p + 0x4c);
 279
 280         /*
 281          * Read the register back to ensure that it took effect.
 282          */
 283         readl(p + 0x4c);
 284         iounmap(p);
 285
 286         return 0;
 287 }
 288
 289 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 290 {
 291         u8 __iomem *p;
 292
 293         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 294                 return;
 295
 296         /*
 297          * disable interrupts
 298          */
 299         p = ioremap(pci_resource_start(dev, 0), 0x80);
 300         if (p != NULL) {
 301                 writel(0, p + 0x4c);
 302
 303                 /*
 304                  * Read the register back to ensure that it took effect.
 305                  */
 306                 readl(p + 0x4c);
 307                 iounmap(p);
 308         }
 309 }
 310
 311 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 312 static int
 313 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 314                 struct uart_port *port, int idx)
 315 {
 316         unsigned int bar, offset = board->first_offset;
 317
 318         bar = 0;
 319
 320         if (idx < 4) {
 321                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 322                 offset += idx * board->uart_offset;
 323         } else if (idx < 8) {
 324                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 325                 offset += idx * board->uart_offset + 0xC00;
 326         } else /* we have only 8 ports on PMC-OCTALPRO */
 327                 return 1;
 328
 329         return setup_port(priv, port, bar, offset, board->reg_shift);
 330 }
 331
 332 /*
 333 * This does initialization for PMC OCTALPRO cards:
 334 * maps the device memory, resets the UARTs (needed, bc
 335 * if the module is removed and inserted again, the card
 336 * is in the sleep mode) and enables global interrupt.
 337 */
 338
 339 /* global control register offset for SBS PMC-OctalPro */
 340 #define OCT_REG_CR_OFF          0x500
 341
 342 static int sbs_init(struct pci_dev *dev)
 343 {
 344         u8 __iomem *p;
 345
 346         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 347
 348         if (p == NULL)
 349                 return -ENOMEM;
 350         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 351         writeb(0x10,p + OCT_REG_CR_OFF);
 352         udelay(50);
 353         writeb(0x0,p + OCT_REG_CR_OFF);
 354
 355         /* Set bit-2 (INTENABLE) of Control Register */
 356         writeb(0x4, p + OCT_REG_CR_OFF);
 357         iounmap(p);
 358
 359         return 0;
 360 }
 361
 362 /*
 363  * Disables the global interrupt of PMC-OctalPro
 364  */
 365
 366 static void __devexit sbs_exit(struct pci_dev *dev)
 367 {
 368         u8 __iomem *p;
 369
 370         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 371         if (p != NULL) {
 372                 writeb(0, p + OCT_REG_CR_OFF);
 373         }
 374         iounmap(p);
 375 }
 376
 377 /*
 378  * SIIG serial cards have an PCI interface chip which also controls
 379  * the UART clocking frequency. Each UART can be clocked independently
 380  * (except cards equiped with 4 UARTs) and initial clocking settings
 381  * are stored in the EEPROM chip. It can cause problems because this
 382  * version of serial driver doesn't support differently clocked UART's
 383  * on single PCI card. To prevent this, initialization functions set
 384  * high frequency clocking for all UART's on given card. It is safe (I
 385  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 386  * with other OSes (like M$ DOS).
 387  *
 388  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 389  *
 390  * There is two family of SIIG serial cards with different PCI
 391  * interface chip and different configuration methods:
 392  *     - 10x cards have control registers in IO and/or memory space;
 393  *     - 20x cards have control registers in standard PCI configuration space.
 394  *
 395  * Note: all 10x cards have PCI device ids 0x10..
 396  *       all 20x cards have PCI device ids 0x20..
 397  *
 398  * There are also Quartet Serial cards which use Oxford Semiconductor
 399  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 400  *
 401  * Note: some SIIG cards are probed by the parport_serial object.
 402  */
 403
 404 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 405 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 406
 407 static int pci_siig10x_init(struct pci_dev *dev)
 408 {
 409         u16 data;
 410         void __iomem *p;
 411
 412         switch (dev->device & 0xfff8) {
 413         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 414                 data = 0xffdf;
 415                 break;
 416         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 417                 data = 0xf7ff;
 418                 break;
 419         default:                        /* 1S1P, 4S */
 420                 data = 0xfffb;
 421                 break;
 422         }
 423
 424         p = ioremap(pci_resource_start(dev, 0), 0x80);
 425         if (p == NULL)
 426                 return -ENOMEM;
 427
 428         writew(readw(p + 0x28) & data, p + 0x28);
 429         readw(p + 0x28);
 430         iounmap(p);
 431         return 0;
 432 }
 433
 434 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 435 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 436
 437 static int pci_siig20x_init(struct pci_dev *dev)
 438 {
 439         u8 data;
 440
 441         /* Change clock frequency for the first UART. */
 442         pci_read_config_byte(dev, 0x6f, &data);
 443         pci_write_config_byte(dev, 0x6f, data & 0xef);
 444
 445         /* If this card has 2 UART, we have to do the same with second UART. */
 446         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 447             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 448                 pci_read_config_byte(dev, 0x73, &data);
 449                 pci_write_config_byte(dev, 0x73, data & 0xef);
 450         }
 451         return 0;
 452 }
 453
 454 static int pci_siig_init(struct pci_dev *dev)
 455 {
 456         unsigned int type = dev->device & 0xff00;
 457
 458         if (type == 0x1000)
 459                 return pci_siig10x_init(dev);
 460         else if (type == 0x2000)
 461                 return pci_siig20x_init(dev);
 462
 463         moan_device("Unknown SIIG card", dev);
 464         return -ENODEV;
 465 }
 466
 467 static int pci_siig_setup(struct serial_private *priv,
 468                           struct pciserial_board *board,
 469                           struct uart_port *port, int idx)
 470 {
 471         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 472
 473         if (idx > 3) {
 474                 bar = 4;
 475                 offset = (idx - 4) * 8;
 476         }
 477
 478         return setup_port(priv, port, bar, offset, 0);
 479 }
 480
 481 /*
 482  * Timedia has an explosion of boards, and to avoid the PCI table from
 483  * growing *huge*, we use this function to collapse some 70 entries
 484  * in the PCI table into one, for sanity's and compactness's sake.
 485  */
 486 static const unsigned short timedia_single_port[] = {
 487         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 488 };
 489
 490 static const unsigned short timedia_dual_port[] = {
 491         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 492         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 493         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 494         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 495         0xD079, 0
 496 };
 497
 498 static const unsigned short timedia_quad_port[] = {
 499         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 500         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 501         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 502         0xB157, 0
 503 };
 504
 505 static const unsigned short timedia_eight_port[] = {
 506         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 507         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 508 };
 509
 510 static const struct timedia_struct {
 511         int num;
 512         const unsigned short *ids;
 513 } timedia_data[] = {
 514         { 1, timedia_single_port },
 515         { 2, timedia_dual_port },
 516         { 4, timedia_quad_port },
 517         { 8, timedia_eight_port }
 518 };
 519
 520 static int pci_timedia_init(struct pci_dev *dev)
 521 {
 522         const unsigned short *ids;
 523         int i, j;
 524
 525         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 526                 ids = timedia_data[i].ids;
 527                 for (j = 0; ids[j]; j++)
 528                         if (dev->subsystem_device == ids[j])
 529                                 return timedia_data[i].num;
 530         }
 531         return 0;
 532 }
 533
 534 /*
 535  * Timedia/SUNIX uses a mixture of BARs and offsets
 536  * Ugh, this is ugly as all hell --- TYT
 537  */
 538 static int
 539 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 540                   struct uart_port *port, int idx)
 541 {
 542         unsigned int bar = 0, offset = board->first_offset;
 543
 544         switch (idx) {
 545         case 0:
 546                 bar = 0;
 547                 break;
 548         case 1:
 549                 offset = board->uart_offset;
 550                 bar = 0;
 551                 break;
 552         case 2:
 553                 bar = 1;
 554                 break;
 555         case 3:
 556                 offset = board->uart_offset;
 557                 /* FALLTHROUGH */
 558         case 4: /* BAR 2 */
 559         case 5: /* BAR 3 */
 560         case 6: /* BAR 4 */
 561         case 7: /* BAR 5 */
 562                 bar = idx - 2;
 563         }
 564
 565         return setup_port(priv, port, bar, offset, board->reg_shift);
 566 }
 567
 568 /*
 569  * Some Titan cards are also a little weird
 570  */
 571 static int
 572 titan_400l_800l_setup(struct serial_private *priv,
 573                       struct pciserial_board *board,
 574                       struct uart_port *port, int idx)
 575 {
 576         unsigned int bar, offset = board->first_offset;
 577
 578         switch (idx) {
 579         case 0:
 580                 bar = 1;
 581                 break;
 582         case 1:
 583                 bar = 2;
 584                 break;
 585         default:
 586                 bar = 4;
 587                 offset = (idx - 2) * board->uart_offset;
 588         }
 589
 590         return setup_port(priv, port, bar, offset, board->reg_shift);
 591 }
 592
 593 static int pci_xircom_init(struct pci_dev *dev)
 594 {
 595         msleep(100);
 596         return 0;
 597 }
 598
 599 static int pci_netmos_init(struct pci_dev *dev)
 600 {
 601         /* subdevice 0x00PS means <P> parallel, <S> serial */
 602         unsigned int num_serial = dev->subsystem_device & 0xf;
 603
 604         if (num_serial == 0)
 605                 return -ENODEV;
 606         return num_serial;
 607 }
 608
 609 /*
 610  * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
 611  *
 612  * These chips are available with optionally one parallel port and up to
 613  * two serial ports. Unfortunately they all have the same product id.
 614  *
 615  * Basic configuration is done over a region of 32 I/O ports. The base
 616  * ioport is called INTA or INTC, depending on docs/other drivers.
 617  *
 618  * The region of the 32 I/O ports is configured in POSIO0R...
 619  */
 620
 621 /* registers */
 622 #define ITE_887x_MISCR          0x9c
 623 #define ITE_887x_INTCBAR        0x78
 624 #define ITE_887x_UARTBAR        0x7c
 625 #define ITE_887x_PS0BAR         0x10
 626 #define ITE_887x_POSIO0         0x60
 627
 628 /* I/O space size */
 629 #define ITE_887x_IOSIZE         32
 630 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 631 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 632 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 633 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 634 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 635 #define ITE_887x_POSIO_SPEED            (3 << 29)
 636 /* enable IO_Space bit */
 637 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 638
 639 static int pci_ite887x_init(struct pci_dev *dev)
 640 {
 641         /* inta_addr are the configuration addresses of the ITE */
 642         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 643                                                         0x200, 0x280, 0 };
 644         int ret, i, type;
 645         struct resource *iobase = NULL;
 646         u32 miscr, uartbar, ioport;
 647
 648         /* search for the base-ioport */
 649         i = 0;
 650         while (inta_addr[i] && iobase == NULL) {
 651                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 652                                                                 "ite887x");
 653                 if (iobase != NULL) {
 654                         /* write POSIO0R - speed | size | ioport */
 655                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 656                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 657                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 658                         /* write INTCBAR - ioport */
 659                         pci_write_config_dword(dev, ITE_887x_INTCBAR, inta_addr[i]);
 660                         ret = inb(inta_addr[i]);
 661                         if (ret != 0xff) {
 662                                 /* ioport connected */
 663                                 break;
 664                         }
 665                         release_region(iobase->start, ITE_887x_IOSIZE);
 666                         iobase = NULL;
 667                 }
 668                 i++;
 669         }
 670
 671         if (!inta_addr[i]) {
 672                 printk(KERN_ERR "ite887x: could not find iobase\n");
 673                 return -ENODEV;
 674         }
 675
 676         /* start of undocumented type checking (see parport_pc.c) */
 677         type = inb(iobase->start + 0x18) & 0x0f;
 678
 679         switch (type) {
 680         case 0x2:       /* ITE8871 (1P) */
 681         case 0xa:       /* ITE8875 (1P) */
 682                 ret = 0;
 683                 break;
 684         case 0xe:       /* ITE8872 (2S1P) */
 685                 ret = 2;
 686                 break;
 687         case 0x6:       /* ITE8873 (1S) */
 688                 ret = 1;
 689                 break;
 690         case 0x8:       /* ITE8874 (2S) */
 691                 ret = 2;
 692                 break;
 693         default:
 694                 moan_device("Unknown ITE887x", dev);
 695                 ret = -ENODEV;
 696         }
 697
 698         /* configure all serial ports */
 699         for (i = 0; i < ret; i++) {
 700                 /* read the I/O port from the device */
 701                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 702                                                                 &ioport);
 703                 ioport &= 0x0000FF00;   /* the actual base address */
 704                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 705                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 706                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 707
 708                 /* write the ioport to the UARTBAR */
 709                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 710                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 711                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 712                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 713
 714                 /* get current config */
 715                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 716                 /* disable interrupts (UARTx_Routing[3:0]) */
 717                 miscr &= ~(0xf << (12 - 4 * i));
 718                 /* activate the UART (UARTx_En) */
 719                 miscr |= 1 << (23 - i);
 720                 /* write new config with activated UART */
 721                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 722         }
 723
 724         if (ret <= 0) {
 725                 /* the device has no UARTs if we get here */
 726                 release_region(iobase->start, ITE_887x_IOSIZE);
 727         }
 728
 729         return ret;
 730 }
 731
 732 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 733 {
 734         u32 ioport;
 735         /* the ioport is bit 0-15 in POSIO0R */
 736         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 737         ioport &= 0xffff;
 738         release_region(ioport, ITE_887x_IOSIZE);
 739 }
 740
 741 static int
 742 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 743                   struct uart_port *port, int idx)
 744 {
 745         unsigned int bar, offset = board->first_offset, maxnr;
 746
 747         bar = FL_GET_BASE(board->flags);
 748         if (board->flags & FL_BASE_BARS)
 749                 bar += idx;
 750         else
 751                 offset += idx * board->uart_offset;
 752
 753         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 754                 (board->reg_shift + 3);
 755
 756         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 757                 return 1;
 758
 759         return setup_port(priv, port, bar, offset, board->reg_shift);
 760 }
 761
 762 /* This should be in linux/pci_ids.h */
 763 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 764 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 765 #define PCI_DEVICE_ID_OCTPRO            0x0001
 766 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 767 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 768 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 769 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 770
 771 /*
 772  * Master list of serial port init/setup/exit quirks.
 773  * This does not describe the general nature of the port.
 774  * (ie, baud base, number and location of ports, etc)
 775  *
 776  * This list is ordered alphabetically by vendor then device.
 777  * Specific entries must come before more generic entries.
 778  */
 779 static struct pci_serial_quirk pci_serial_quirks[] = {
 780         /*
 781         * ADDI-DATA GmbH communication cards <info@addi-data.com>
 782         */
 783         {
 784                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
 785                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
 786                 .subvendor      = PCI_ANY_ID,
 787                 .subdevice      = PCI_ANY_ID,
 788                 .setup          = addidata_apci7800_setup,
 789         },
 790         /*
 791          * AFAVLAB cards - these may be called via parport_serial
 792          *  It is not clear whether this applies to all products.
 793          */
 794         {
 795                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 796                 .device         = PCI_ANY_ID,
 797                 .subvendor      = PCI_ANY_ID,
 798                 .subdevice      = PCI_ANY_ID,
 799                 .setup          = afavlab_setup,
 800         },
 801         /*
 802          * HP Diva
 803          */
 804         {
 805                 .vendor         = PCI_VENDOR_ID_HP,
 806                 .device         = PCI_DEVICE_ID_HP_DIVA,
 807                 .subvendor      = PCI_ANY_ID,
 808                 .subdevice      = PCI_ANY_ID,
 809                 .init           = pci_hp_diva_init,
 810                 .setup          = pci_hp_diva_setup,
 811         },
 812         /*
 813          * Intel
 814          */
 815         {
 816                 .vendor         = PCI_VENDOR_ID_INTEL,
 817                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 818                 .subvendor      = 0xe4bf,
 819                 .subdevice      = PCI_ANY_ID,
 820                 .init           = pci_inteli960ni_init,
 821                 .setup          = pci_default_setup,
 822         },
 823         /*
 824          * ITE
 825          */
 826         {
 827                 .vendor         = PCI_VENDOR_ID_ITE,
 828                 .device         = PCI_DEVICE_ID_ITE_8872,
 829                 .subvendor      = PCI_ANY_ID,
 830                 .subdevice      = PCI_ANY_ID,
 831                 .init           = pci_ite887x_init,
 832                 .setup          = pci_default_setup,
 833                 .exit           = __devexit_p(pci_ite887x_exit),
 834         },
 835         /*
 836          * Panacom
 837          */
 838         {
 839                 .vendor         = PCI_VENDOR_ID_PANACOM,
 840                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 841                 .subvendor      = PCI_ANY_ID,
 842                 .subdevice      = PCI_ANY_ID,
 843                 .init           = pci_plx9050_init,
 844                 .setup          = pci_default_setup,
 845                 .exit           = __devexit_p(pci_plx9050_exit),
 846         },
 847         {
 848                 .vendor         = PCI_VENDOR_ID_PANACOM,
 849                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 850                 .subvendor      = PCI_ANY_ID,
 851                 .subdevice      = PCI_ANY_ID,
 852                 .init           = pci_plx9050_init,
 853                 .setup          = pci_default_setup,
 854                 .exit           = __devexit_p(pci_plx9050_exit),
 855         },
 856         /*
 857          * PLX
 858          */
 859         {
 860                 .vendor         = PCI_VENDOR_ID_PLX,
 861                 .device         = PCI_DEVICE_ID_PLX_9030,
 862                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
 863                 .subdevice      = PCI_ANY_ID,
 864                 .setup          = pci_default_setup,
 865         },
 866         {
 867                 .vendor         = PCI_VENDOR_ID_PLX,
 868                 .device         = PCI_DEVICE_ID_PLX_9050,
 869                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
 870                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
 871                 .init           = pci_plx9050_init,
 872                 .setup          = pci_default_setup,
 873                 .exit           = __devexit_p(pci_plx9050_exit),
 874         },
 875         {
 876                 .vendor         = PCI_VENDOR_ID_PLX,
 877                 .device         = PCI_DEVICE_ID_PLX_9050,
 878                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 879                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 880                 .init           = pci_plx9050_init,
 881                 .setup          = pci_default_setup,
 882                 .exit           = __devexit_p(pci_plx9050_exit),
 883         },
 884         {
 885                 .vendor         = PCI_VENDOR_ID_PLX,
 886                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 887                 .subvendor      = PCI_VENDOR_ID_PLX,
 888                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 889                 .init           = pci_plx9050_init,
 890                 .setup          = pci_default_setup,
 891                 .exit           = __devexit_p(pci_plx9050_exit),
 892         },
 893         /*
 894          * SBS Technologies, Inc., PMC-OCTALPRO 232
 895          */
 896         {
 897                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 898                 .device         = PCI_DEVICE_ID_OCTPRO,
 899                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 900                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 901                 .init           = sbs_init,
 902                 .setup          = sbs_setup,
 903                 .exit           = __devexit_p(sbs_exit),
 904         },
 905         /*
 906          * SBS Technologies, Inc., PMC-OCTALPRO 422
 907          */
 908         {
 909                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 910                 .device         = PCI_DEVICE_ID_OCTPRO,
 911                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 912                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 913                 .init           = sbs_init,
 914                 .setup          = sbs_setup,
 915                 .exit           = __devexit_p(sbs_exit),
 916         },
 917         /*
 918          * SBS Technologies, Inc., P-Octal 232
 919          */
 920         {
 921                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 922                 .device         = PCI_DEVICE_ID_OCTPRO,
 923                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 924                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 925                 .init           = sbs_init,
 926                 .setup          = sbs_setup,
 927                 .exit           = __devexit_p(sbs_exit),
 928         },
 929         /*
 930          * SBS Technologies, Inc., P-Octal 422
 931          */
 932         {
 933                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 934                 .device         = PCI_DEVICE_ID_OCTPRO,
 935                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 936                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 937                 .init           = sbs_init,
 938                 .setup          = sbs_setup,
 939                 .exit           = __devexit_p(sbs_exit),
 940         },
 941         /*
 942          * SIIG cards - these may be called via parport_serial
 943          */
 944         {
 945                 .vendor         = PCI_VENDOR_ID_SIIG,
 946                 .device         = PCI_ANY_ID,
 947                 .subvendor      = PCI_ANY_ID,
 948                 .subdevice      = PCI_ANY_ID,
 949                 .init           = pci_siig_init,
 950                 .setup          = pci_siig_setup,
 951         },
 952         /*
 953          * Titan cards
 954          */
 955         {
 956                 .vendor         = PCI_VENDOR_ID_TITAN,
 957                 .device         = PCI_DEVICE_ID_TITAN_400L,
 958                 .subvendor      = PCI_ANY_ID,
 959                 .subdevice      = PCI_ANY_ID,
 960                 .setup          = titan_400l_800l_setup,
 961         },
 962         {
 963                 .vendor         = PCI_VENDOR_ID_TITAN,
 964                 .device         = PCI_DEVICE_ID_TITAN_800L,
 965                 .subvendor      = PCI_ANY_ID,
 966                 .subdevice      = PCI_ANY_ID,
 967                 .setup          = titan_400l_800l_setup,
 968         },
 969         /*
 970          * Timedia cards
 971          */
 972         {
 973                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 974                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 975                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 976                 .subdevice      = PCI_ANY_ID,
 977                 .init           = pci_timedia_init,
 978                 .setup          = pci_timedia_setup,
 979         },
 980         {
 981                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 982                 .device         = PCI_ANY_ID,
 983                 .subvendor      = PCI_ANY_ID,
 984                 .subdevice      = PCI_ANY_ID,
 985                 .setup          = pci_timedia_setup,
 986         },
 987         /*
 988          * Xircom cards
 989          */
 990         {
 991                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 992                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 993                 .subvendor      = PCI_ANY_ID,
 994                 .subdevice      = PCI_ANY_ID,
 995                 .init           = pci_xircom_init,
 996                 .setup          = pci_default_setup,
 997         },
 998         /*
 999          * Netmos cards - these may be called via parport_serial
1000          */
1001         {
1002                 .vendor         = PCI_VENDOR_ID_NETMOS,
1003                 .device         = PCI_ANY_ID,
1004                 .subvendor      = PCI_ANY_ID,
1005                 .subdevice      = PCI_ANY_ID,
1006                 .init           = pci_netmos_init,
1007                 .setup          = pci_default_setup,
1008         },
1009         /*
1010          * Default "match everything" terminator entry
1011          */
1012         {
1013                 .vendor         = PCI_ANY_ID,
1014                 .device         = PCI_ANY_ID,
1015                 .subvendor      = PCI_ANY_ID,
1016                 .subdevice      = PCI_ANY_ID,
1017                 .setup          = pci_default_setup,
1018         }
1019 };
1020
1021 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1022 {
1023         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1024 }
1025
1026 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1027 {
1028         struct pci_serial_quirk *quirk;
1029
1030         for (quirk = pci_serial_quirks; ; quirk++)
1031                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1032                     quirk_id_matches(quirk->device, dev->device) &&
1033                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1034                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1035                         break;
1036         return quirk;
1037 }
1038
1039 static inline int get_pci_irq(struct pci_dev *dev,
1040                                 struct pciserial_board *board)
1041 {
1042         if (board->flags & FL_NOIRQ)
1043                 return 0;
1044         else
1045                 return dev->irq;
1046 }
1047
1048 /*
1049  * This is the configuration table for all of the PCI serial boards
1050  * which we support.  It is directly indexed by the pci_board_num_t enum
1051  * value, which is encoded in the pci_device_id PCI probe table's
1052  * driver_data member.
1053  *
1054  * The makeup of these names are:
1055  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1056  *
1057  *  bn          = PCI BAR number
1058  *  bt          = Index using PCI BARs
1059  *  n           = number of serial ports
1060  *  baud        = baud rate
1061  *  offsetinhex = offset for each sequential port (in hex)
1062  *
1063  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1064  *
1065  * Please note: in theory if n = 1, _bt infix should make no difference.
1066  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1067  */
1068 enum pci_board_num_t {
1069         pbn_default = 0,
1070
1071         pbn_b0_1_115200,
1072         pbn_b0_2_115200,
1073         pbn_b0_4_115200,
1074         pbn_b0_5_115200,
1075         pbn_b0_8_115200,
1076
1077         pbn_b0_1_921600,
1078         pbn_b0_2_921600,
1079         pbn_b0_4_921600,
1080
1081         pbn_b0_2_1130000,
1082
1083         pbn_b0_4_1152000,
1084
1085         pbn_b0_2_1843200,
1086         pbn_b0_4_1843200,
1087
1088         pbn_b0_2_1843200_200,
1089         pbn_b0_4_1843200_200,
1090         pbn_b0_8_1843200_200,
1091
1092         pbn_b0_bt_1_115200,
1093         pbn_b0_bt_2_115200,
1094         pbn_b0_bt_8_115200,
1095
1096         pbn_b0_bt_1_460800,
1097         pbn_b0_bt_2_460800,
1098         pbn_b0_bt_4_460800,
1099
1100         pbn_b0_bt_1_921600,
1101         pbn_b0_bt_2_921600,
1102         pbn_b0_bt_4_921600,
1103         pbn_b0_bt_8_921600,
1104
1105         pbn_b1_1_115200,
1106         pbn_b1_2_115200,
1107         pbn_b1_4_115200,
1108         pbn_b1_8_115200,
1109
1110         pbn_b1_1_921600,
1111         pbn_b1_2_921600,
1112         pbn_b1_4_921600,
1113         pbn_b1_8_921600,
1114
1115         pbn_b1_2_1250000,
1116
1117         pbn_b1_bt_1_115200,
1118         pbn_b1_bt_2_921600,
1119
1120         pbn_b1_1_1382400,
1121         pbn_b1_2_1382400,
1122         pbn_b1_4_1382400,
1123         pbn_b1_8_1382400,
1124
1125         pbn_b2_1_115200,
1126         pbn_b2_2_115200,
1127         pbn_b2_4_115200,
1128         pbn_b2_8_115200,
1129
1130         pbn_b2_1_460800,
1131         pbn_b2_4_460800,
1132         pbn_b2_8_460800,
1133         pbn_b2_16_460800,
1134
1135         pbn_b2_1_921600,
1136         pbn_b2_4_921600,
1137         pbn_b2_8_921600,
1138
1139         pbn_b2_bt_1_115200,
1140         pbn_b2_bt_2_115200,
1141         pbn_b2_bt_4_115200,
1142
1143         pbn_b2_bt_2_921600,
1144         pbn_b2_bt_4_921600,
1145
1146         pbn_b3_2_115200,
1147         pbn_b3_4_115200,
1148         pbn_b3_8_115200,
1149
1150         /*
1151          * Board-specific versions.
1152          */
1153         pbn_panacom,
1154         pbn_panacom2,
1155         pbn_panacom4,
1156         pbn_exsys_4055,
1157         pbn_plx_romulus,
1158         pbn_oxsemi,
1159         pbn_intel_i960,
1160         pbn_sgi_ioc3,
1161         pbn_computone_4,
1162         pbn_computone_6,
1163         pbn_computone_8,
1164         pbn_sbsxrsio,
1165         pbn_exar_XR17C152,
1166         pbn_exar_XR17C154,
1167         pbn_exar_XR17C158,
1168         pbn_pasemi_1682M,
1169 };
1170
1171 /*
1172  * uart_offset - the space between channels
1173  * reg_shift   - describes how the UART registers are mapped
1174  *               to PCI memory by the card.
1175  * For example IER register on SBS, Inc. PMC-OctPro is located at
1176  * offset 0x10 from the UART base, while UART_IER is defined as 1
1177  * in include/linux/serial_reg.h,
1178  * see first lines of serial_in() and serial_out() in 8250.c
1179 */
1180
1181 static struct pciserial_board pci_boards[] __devinitdata = {
1182         [pbn_default] = {
1183                 .flags          = FL_BASE0,
1184                 .num_ports      = 1,
1185                 .base_baud      = 115200,
1186                 .uart_offset    = 8,
1187         },
1188         [pbn_b0_1_115200] = {
1189                 .flags          = FL_BASE0,
1190                 .num_ports      = 1,
1191                 .base_baud      = 115200,
1192                 .uart_offset    = 8,
1193         },
1194         [pbn_b0_2_115200] = {
1195                 .flags          = FL_BASE0,
1196                 .num_ports      = 2,
1197                 .base_baud      = 115200,
1198                 .uart_offset    = 8,
1199         },
1200         [pbn_b0_4_115200] = {
1201                 .flags          = FL_BASE0,
1202                 .num_ports      = 4,
1203                 .base_baud      = 115200,
1204                 .uart_offset    = 8,
1205         },
1206         [pbn_b0_5_115200] = {
1207                 .flags          = FL_BASE0,
1208                 .num_ports      = 5,
1209                 .base_baud      = 115200,
1210                 .uart_offset    = 8,
1211         },
1212         [pbn_b0_8_115200] = {
1213                 .flags          = FL_BASE0,
1214                 .num_ports      = 8,
1215                 .base_baud      = 115200,
1216                 .uart_offset    = 8,
1217         },
1218         [pbn_b0_8_115200] = {
1219                 .flags          = FL_BASE0,
1220                 .num_ports      = 8,
1221                 .base_baud      = 115200,
1222                 .uart_offset    = 8,
1223         },
1224
1225         [pbn_b0_1_921600] = {
1226                 .flags          = FL_BASE0,
1227                 .num_ports      = 1,
1228                 .base_baud      = 921600,
1229                 .uart_offset    = 8,
1230         },
1231         [pbn_b0_2_921600] = {
1232                 .flags          = FL_BASE0,
1233                 .num_ports      = 2,
1234                 .base_baud      = 921600,
1235                 .uart_offset    = 8,
1236         },
1237         [pbn_b0_4_921600] = {
1238                 .flags          = FL_BASE0,
1239                 .num_ports      = 4,
1240                 .base_baud      = 921600,
1241                 .uart_offset    = 8,
1242         },
1243
1244         [pbn_b0_2_1130000] = {
1245                 .flags          = FL_BASE0,
1246                 .num_ports      = 2,
1247                 .base_baud      = 1130000,
1248                 .uart_offset    = 8,
1249         },
1250
1251         [pbn_b0_4_1152000] = {
1252                 .flags          = FL_BASE0,
1253                 .num_ports      = 4,
1254                 .base_baud      = 1152000,
1255                 .uart_offset    = 8,
1256         },
1257
1258         [pbn_b0_2_1843200] = {
1259                 .flags          = FL_BASE0,
1260                 .num_ports      = 2,
1261                 .base_baud      = 1843200,
1262                 .uart_offset    = 8,
1263         },
1264         [pbn_b0_4_1843200] = {
1265                 .flags          = FL_BASE0,
1266                 .num_ports      = 4,
1267                 .base_baud      = 1843200,
1268                 .uart_offset    = 8,
1269         },
1270
1271         [pbn_b0_2_1843200_200] = {
1272                 .flags          = FL_BASE0,
1273                 .num_ports      = 2,
1274                 .base_baud      = 1843200,
1275                 .uart_offset    = 0x200,
1276         },
1277         [pbn_b0_4_1843200_200] = {
1278                 .flags          = FL_BASE0,
1279                 .num_ports      = 4,
1280                 .base_baud      = 1843200,
1281                 .uart_offset    = 0x200,
1282         },
1283         [pbn_b0_8_1843200_200] = {
1284                 .flags          = FL_BASE0,
1285                 .num_ports      = 8,
1286                 .base_baud      = 1843200,
1287                 .uart_offset    = 0x200,
1288         },
1289
1290         [pbn_b0_bt_1_115200] = {
1291                 .flags          = FL_BASE0|FL_BASE_BARS,
1292                 .num_ports      = 1,
1293                 .base_baud      = 115200,
1294                 .uart_offset    = 8,
1295         },
1296         [pbn_b0_bt_2_115200] = {
1297                 .flags          = FL_BASE0|FL_BASE_BARS,
1298                 .num_ports      = 2,
1299                 .base_baud      = 115200,
1300                 .uart_offset    = 8,
1301         },
1302         [pbn_b0_bt_8_115200] = {
1303                 .flags          = FL_BASE0|FL_BASE_BARS,
1304                 .num_ports      = 8,
1305                 .base_baud      = 115200,
1306                 .uart_offset    = 8,
1307         },
1308
1309         [pbn_b0_bt_1_460800] = {
1310                 .flags          = FL_BASE0|FL_BASE_BARS,
1311                 .num_ports      = 1,
1312                 .base_baud      = 460800,
1313                 .uart_offset    = 8,
1314         },
1315         [pbn_b0_bt_2_460800] = {
1316                 .flags          = FL_BASE0|FL_BASE_BARS,
1317                 .num_ports      = 2,
1318                 .base_baud      = 460800,
1319                 .uart_offset    = 8,
1320         },
1321         [pbn_b0_bt_4_460800] = {
1322                 .flags          = FL_BASE0|FL_BASE_BARS,
1323                 .num_ports      = 4,
1324                 .base_baud      = 460800,
1325                 .uart_offset    = 8,
1326         },
1327
1328         [pbn_b0_bt_1_921600] = {
1329                 .flags          = FL_BASE0|FL_BASE_BARS,
1330                 .num_ports      = 1,
1331                 .base_baud      = 921600,
1332                 .uart_offset    = 8,
1333         },
1334         [pbn_b0_bt_2_921600] = {
1335                 .flags          = FL_BASE0|FL_BASE_BARS,
1336                 .num_ports      = 2,
1337                 .base_baud      = 921600,
1338                 .uart_offset    = 8,
1339         },
1340         [pbn_b0_bt_4_921600] = {
1341                 .flags          = FL_BASE0|FL_BASE_BARS,
1342                 .num_ports      = 4,
1343                 .base_baud      = 921600,
1344                 .uart_offset    = 8,
1345         },
1346         [pbn_b0_bt_8_921600] = {
1347                 .flags          = FL_BASE0|FL_BASE_BARS,
1348                 .num_ports      = 8,
1349                 .base_baud      = 921600,
1350                 .uart_offset    = 8,
1351         },
1352
1353         [pbn_b1_1_115200] = {
1354                 .flags          = FL_BASE1,
1355                 .num_ports      = 1,
1356                 .base_baud      = 115200,
1357                 .uart_offset    = 8,
1358         },
1359         [pbn_b1_2_115200] = {
1360                 .flags          = FL_BASE1,
1361                 .num_ports      = 2,
1362                 .base_baud      = 115200,
1363                 .uart_offset    = 8,
1364         },
1365         [pbn_b1_4_115200] = {
1366                 .flags          = FL_BASE1,
1367                 .num_ports      = 4,
1368                 .base_baud      = 115200,
1369                 .uart_offset    = 8,
1370         },
1371         [pbn_b1_8_115200] = {
1372                 .flags          = FL_BASE1,
1373                 .num_ports      = 8,
1374                 .base_baud      = 115200,
1375                 .uart_offset    = 8,
1376         },
1377
1378         [pbn_b1_1_921600] = {
1379                 .flags          = FL_BASE1,
1380                 .num_ports      = 1,
1381                 .base_baud      = 921600,
1382                 .uart_offset    = 8,
1383         },
1384         [pbn_b1_2_921600] = {
1385                 .flags          = FL_BASE1,
1386                 .num_ports      = 2,
1387                 .base_baud      = 921600,
1388                 .uart_offset    = 8,
1389         },
1390         [pbn_b1_4_921600] = {
1391                 .flags          = FL_BASE1,
1392                 .num_ports      = 4,
1393                 .base_baud      = 921600,
1394                 .uart_offset    = 8,
1395         },
1396         [pbn_b1_8_921600] = {
1397                 .flags          = FL_BASE1,
1398                 .num_ports      = 8,
1399                 .base_baud      = 921600,
1400                 .uart_offset    = 8,
1401         },
1402         [pbn_b1_2_1250000] = {
1403                 .flags          = FL_BASE1,
1404                 .num_ports      = 2,
1405                 .base_baud      = 1250000,
1406                 .uart_offset    = 8,
1407         },
1408
1409         [pbn_b1_bt_1_115200] = {
1410                 .flags          = FL_BASE1|FL_BASE_BARS,
1411                 .num_ports      = 1,
1412                 .base_baud      = 115200,
1413                 .uart_offset    = 8,
1414         },
1415
1416         [pbn_b1_bt_2_921600] = {
1417                 .flags          = FL_BASE1|FL_BASE_BARS,
1418                 .num_ports      = 2,
1419                 .base_baud      = 921600,
1420                 .uart_offset    = 8,
1421         },
1422
1423         [pbn_b1_1_1382400] = {
1424                 .flags          = FL_BASE1,
1425                 .num_ports      = 1,
1426                 .base_baud      = 1382400,
1427                 .uart_offset    = 8,
1428         },
1429         [pbn_b1_2_1382400] = {
1430                 .flags          = FL_BASE1,
1431                 .num_ports      = 2,
1432                 .base_baud      = 1382400,
1433                 .uart_offset    = 8,
1434         },
1435         [pbn_b1_4_1382400] = {
1436                 .flags          = FL_BASE1,
1437                 .num_ports      = 4,
1438                 .base_baud      = 1382400,
1439                 .uart_offset    = 8,
1440         },
1441         [pbn_b1_8_1382400] = {
1442                 .flags          = FL_BASE1,
1443                 .num_ports      = 8,
1444                 .base_baud      = 1382400,
1445                 .uart_offset    = 8,
1446         },
1447
1448         [pbn_b2_1_115200] = {
1449                 .flags          = FL_BASE2,
1450                 .num_ports      = 1,
1451                 .base_baud      = 115200,
1452                 .uart_offset    = 8,
1453         },
1454         [pbn_b2_2_115200] = {
1455                 .flags          = FL_BASE2,
1456                 .num_ports      = 2,
1457                 .base_baud      = 115200,
1458                 .uart_offset    = 8,
1459         },
1460         [pbn_b2_4_115200] = {
1461                 .flags          = FL_BASE2,
1462                 .num_ports      = 4,
1463                 .base_baud      = 115200,
1464                 .uart_offset    = 8,
1465         },
1466         [pbn_b2_8_115200] = {
1467                 .flags          = FL_BASE2,
1468                 .num_ports      = 8,
1469                 .base_baud      = 115200,
1470                 .uart_offset    = 8,
1471         },
1472
1473         [pbn_b2_1_460800] = {
1474                 .flags          = FL_BASE2,
1475                 .num_ports      = 1,
1476                 .base_baud      = 460800,
1477                 .uart_offset    = 8,
1478         },
1479         [pbn_b2_4_460800] = {
1480                 .flags          = FL_BASE2,
1481                 .num_ports      = 4,
1482                 .base_baud      = 460800,
1483                 .uart_offset    = 8,
1484         },
1485         [pbn_b2_8_460800] = {
1486                 .flags          = FL_BASE2,
1487                 .num_ports      = 8,
1488                 .base_baud      = 460800,
1489                 .uart_offset    = 8,
1490         },
1491         [pbn_b2_16_460800] = {
1492                 .flags          = FL_BASE2,
1493                 .num_ports      = 16,
1494                 .base_baud      = 460800,
1495                 .uart_offset    = 8,
1496          },
1497
1498         [pbn_b2_1_921600] = {
1499                 .flags          = FL_BASE2,
1500                 .num_ports      = 1,
1501                 .base_baud      = 921600,
1502                 .uart_offset    = 8,
1503         },
1504         [pbn_b2_4_921600] = {
1505                 .flags          = FL_BASE2,
1506                 .num_ports      = 4,
1507                 .base_baud      = 921600,
1508                 .uart_offset    = 8,
1509         },
1510         [pbn_b2_8_921600] = {
1511                 .flags          = FL_BASE2,
1512                 .num_ports      = 8,
1513                 .base_baud      = 921600,
1514                 .uart_offset    = 8,
1515         },
1516
1517         [pbn_b2_bt_1_115200] = {
1518                 .flags          = FL_BASE2|FL_BASE_BARS,
1519                 .num_ports      = 1,
1520                 .base_baud      = 115200,
1521                 .uart_offset    = 8,
1522         },
1523         [pbn_b2_bt_2_115200] = {
1524                 .flags          = FL_BASE2|FL_BASE_BARS,
1525                 .num_ports      = 2,
1526                 .base_baud      = 115200,
1527                 .uart_offset    = 8,
1528         },
1529         [pbn_b2_bt_4_115200] = {
1530                 .flags          = FL_BASE2|FL_BASE_BARS,
1531                 .num_ports      = 4,
1532                 .base_baud      = 115200,
1533                 .uart_offset    = 8,
1534         },
1535
1536         [pbn_b2_bt_2_921600] = {
1537                 .flags          = FL_BASE2|FL_BASE_BARS,
1538                 .num_ports      = 2,
1539                 .base_baud      = 921600,
1540                 .uart_offset    = 8,
1541         },
1542         [pbn_b2_bt_4_921600] = {
1543                 .flags          = FL_BASE2|FL_BASE_BARS,
1544                 .num_ports      = 4,
1545                 .base_baud      = 921600,
1546                 .uart_offset    = 8,
1547         },
1548
1549         [pbn_b3_2_115200] = {
1550                 .flags          = FL_BASE3,
1551                 .num_ports      = 2,
1552                 .base_baud      = 115200,
1553                 .uart_offset    = 8,
1554         },
1555         [pbn_b3_4_115200] = {
1556                 .flags          = FL_BASE3,
1557                 .num_ports      = 4,
1558                 .base_baud      = 115200,
1559                 .uart_offset    = 8,
1560         },
1561         [pbn_b3_8_115200] = {
1562                 .flags          = FL_BASE3,
1563                 .num_ports      = 8,
1564                 .base_baud      = 115200,
1565                 .uart_offset    = 8,
1566         },
1567
1568         /*
1569          * Entries following this are board-specific.
1570          */
1571
1572         /*
1573          * Panacom - IOMEM
1574          */
1575         [pbn_panacom] = {
1576                 .flags          = FL_BASE2,
1577                 .num_ports      = 2,
1578                 .base_baud      = 921600,
1579                 .uart_offset    = 0x400,
1580                 .reg_shift      = 7,
1581         },
1582         [pbn_panacom2] = {
1583                 .flags          = FL_BASE2|FL_BASE_BARS,
1584                 .num_ports      = 2,
1585                 .base_baud      = 921600,
1586                 .uart_offset    = 0x400,
1587                 .reg_shift      = 7,
1588         },
1589         [pbn_panacom4] = {
1590                 .flags          = FL_BASE2|FL_BASE_BARS,
1591                 .num_ports      = 4,
1592                 .base_baud      = 921600,
1593                 .uart_offset    = 0x400,
1594                 .reg_shift      = 7,
1595         },
1596
1597         [pbn_exsys_4055] = {
1598                 .flags          = FL_BASE2,
1599                 .num_ports      = 4,
1600                 .base_baud      = 115200,
1601                 .uart_offset    = 8,
1602         },
1603
1604         /* I think this entry is broken - the first_offset looks wrong --rmk */
1605         [pbn_plx_romulus] = {
1606                 .flags          = FL_BASE2,
1607                 .num_ports      = 4,
1608                 .base_baud      = 921600,
1609                 .uart_offset    = 8 << 2,
1610                 .reg_shift      = 2,
1611                 .first_offset   = 0x03,
1612         },
1613
1614         /*
1615          * This board uses the size of PCI Base region 0 to
1616          * signal now many ports are available
1617          */
1618         [pbn_oxsemi] = {
1619                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1620                 .num_ports      = 32,
1621                 .base_baud      = 115200,
1622                 .uart_offset    = 8,
1623         },
1624
1625         /*
1626          * EKF addition for i960 Boards form EKF with serial port.
1627          * Max 256 ports.
1628          */
1629         [pbn_intel_i960] = {
1630                 .flags          = FL_BASE0,
1631                 .num_ports      = 32,
1632                 .base_baud      = 921600,
1633                 .uart_offset    = 8 << 2,
1634                 .reg_shift      = 2,
1635                 .first_offset   = 0x10000,
1636         },
1637         [pbn_sgi_ioc3] = {
1638                 .flags          = FL_BASE0|FL_NOIRQ,
1639                 .num_ports      = 1,
1640                 .base_baud      = 458333,
1641                 .uart_offset    = 8,
1642                 .reg_shift      = 0,
1643                 .first_offset   = 0x20178,
1644         },
1645
1646         /*
1647          * Computone - uses IOMEM.
1648          */
1649         [pbn_computone_4] = {
1650                 .flags          = FL_BASE0,
1651                 .num_ports      = 4,
1652                 .base_baud      = 921600,
1653                 .uart_offset    = 0x40,
1654                 .reg_shift      = 2,
1655                 .first_offset   = 0x200,
1656         },
1657         [pbn_computone_6] = {
1658                 .flags          = FL_BASE0,
1659                 .num_ports      = 6,
1660                 .base_baud      = 921600,
1661                 .uart_offset    = 0x40,
1662                 .reg_shift      = 2,
1663                 .first_offset   = 0x200,
1664         },
1665         [pbn_computone_8] = {
1666                 .flags          = FL_BASE0,
1667                 .num_ports      = 8,
1668                 .base_baud      = 921600,
1669                 .uart_offset    = 0x40,
1670                 .reg_shift      = 2,
1671                 .first_offset   = 0x200,
1672         },
1673         [pbn_sbsxrsio] = {
1674                 .flags          = FL_BASE0,
1675                 .num_ports      = 8,
1676                 .base_baud      = 460800,
1677                 .uart_offset    = 256,
1678                 .reg_shift      = 4,
1679         },
1680         /*
1681          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1682          *  Only basic 16550A support.
1683          *  XR17C15[24] are not tested, but they should work.
1684          */
1685         [pbn_exar_XR17C152] = {
1686                 .flags          = FL_BASE0,
1687                 .num_ports      = 2,
1688                 .base_baud      = 921600,
1689                 .uart_offset    = 0x200,
1690         },
1691         [pbn_exar_XR17C154] = {
1692                 .flags          = FL_BASE0,
1693                 .num_ports      = 4,
1694                 .base_baud      = 921600,
1695                 .uart_offset    = 0x200,
1696         },
1697         [pbn_exar_XR17C158] = {
1698                 .flags          = FL_BASE0,
1699                 .num_ports      = 8,
1700                 .base_baud      = 921600,
1701                 .uart_offset    = 0x200,
1702         },
1703         /*
1704          * PA Semi PWRficient PA6T-1682M on-chip UART
1705          */
1706         [pbn_pasemi_1682M] = {
1707                 .flags          = FL_BASE0,
1708                 .num_ports      = 1,
1709                 .base_baud      = 8333333,
1710         },
1711 };
1712
1713 static const struct pci_device_id softmodem_blacklist[] = {
1714         { PCI_VDEVICE ( AL, 0x5457 ), }, /* ALi Corporation M5457 AC'97 Modem */
1715 };
1716
1717 /*
1718  * Given a complete unknown PCI device, try to use some heuristics to
1719  * guess what the configuration might be, based on the pitiful PCI
1720  * serial specs.  Returns 0 on success, 1 on failure.
1721  */
1722 static int __devinit
1723 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1724 {
1725         const struct pci_device_id *blacklist;
1726         int num_iomem, num_port, first_port = -1, i;
1727
1728         /*
1729          * If it is not a communications device or the programming
1730          * interface is greater than 6, give up.
1731          *
1732          * (Should we try to make guesses for multiport serial devices
1733          * later?)
1734          */
1735         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1736              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1737             (dev->class & 0xff) > 6)
1738                 return -ENODEV;
1739
1740         /*
1741          * Do not access blacklisted devices that are known not to
1742          * feature serial ports.
1743          */
1744         for (blacklist = softmodem_blacklist;
1745              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1746              blacklist++) {
1747                 if (dev->vendor == blacklist->vendor &&
1748                     dev->device == blacklist->device)
1749                         return -ENODEV;
1750         }
1751
1752         num_iomem = num_port = 0;
1753         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1754                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1755                         num_port++;
1756                         if (first_port == -1)
1757                                 first_port = i;
1758                 }
1759                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1760                         num_iomem++;
1761         }
1762
1763         /*
1764          * If there is 1 or 0 iomem regions, and exactly one port,
1765          * use it.  We guess the number of ports based on the IO
1766          * region size.
1767          */
1768         if (num_iomem <= 1 && num_port == 1) {
1769                 board->flags = first_port;
1770                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1771                 return 0;
1772         }
1773
1774         /*
1775          * Now guess if we've got a board which indexes by BARs.
1776          * Each IO BAR should be 8 bytes, and they should follow
1777          * consecutively.
1778          */
1779         first_port = -1;
1780         num_port = 0;
1781         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1782                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1783                     pci_resource_len(dev, i) == 8 &&
1784                     (first_port == -1 || (first_port + num_port) == i)) {
1785                         num_port++;
1786                         if (first_port == -1)
1787                                 first_port = i;
1788                 }
1789         }
1790
1791         if (num_port > 1) {
1792                 board->flags = first_port | FL_BASE_BARS;
1793                 board->num_ports = num_port;
1794                 return 0;
1795         }
1796
1797         return -ENODEV;
1798 }
1799
1800 static inline int
1801 serial_pci_matches(struct pciserial_board *board,
1802                    struct pciserial_board *guessed)
1803 {
1804         return
1805             board->num_ports == guessed->num_ports &&
1806             board->base_baud == guessed->base_baud &&
1807             board->uart_offset == guessed->uart_offset &&
1808             board->reg_shift == guessed->reg_shift &&
1809             board->first_offset == guessed->first_offset;
1810 }
1811
1812 struct serial_private *
1813 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1814 {
1815         struct uart_port serial_port;
1816         struct serial_private *priv;
1817         struct pci_serial_quirk *quirk;
1818         int rc, nr_ports, i;
1819
1820         nr_ports = board->num_ports;
1821
1822         /*
1823          * Find an init and setup quirks.
1824          */
1825         quirk = find_quirk(dev);
1826
1827         /*
1828          * Run the new-style initialization function.
1829          * The initialization function returns:
1830          *  <0  - error
1831          *   0  - use board->num_ports
1832          *  >0  - number of ports
1833          */
1834         if (quirk->init) {
1835                 rc = quirk->init(dev);
1836                 if (rc < 0) {
1837                         priv = ERR_PTR(rc);
1838                         goto err_out;
1839                 }
1840                 if (rc)
1841                         nr_ports = rc;
1842         }
1843
1844         priv = kzalloc(sizeof(struct serial_private) +
1845                        sizeof(unsigned int) * nr_ports,
1846                        GFP_KERNEL);
1847         if (!priv) {
1848                 priv = ERR_PTR(-ENOMEM);
1849                 goto err_deinit;
1850         }
1851
1852         priv->dev = dev;
1853         priv->quirk = quirk;
1854
1855         memset(&serial_port, 0, sizeof(struct uart_port));
1856         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1857         serial_port.uartclk = board->base_baud * 16;
1858         serial_port.irq = get_pci_irq(dev, board);
1859         serial_port.dev = &dev->dev;
1860
1861         for (i = 0; i < nr_ports; i++) {
1862                 if (quirk->setup(priv, board, &serial_port, i))
1863                         break;
1864
1865 #ifdef SERIAL_DEBUG_PCI
1866                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1867                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1868 #endif
1869
1870                 priv->line[i] = serial8250_register_port(&serial_port);
1871                 if (priv->line[i] < 0) {
1872                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1873                         break;
1874                 }
1875         }
1876
1877         priv->nr = i;
1878
1879         return priv;
1880
1881  err_deinit:
1882         if (quirk->exit)
1883                 quirk->exit(dev);
1884  err_out:
1885         return priv;
1886 }
1887 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1888
1889 void pciserial_remove_ports(struct serial_private *priv)
1890 {
1891         struct pci_serial_quirk *quirk;
1892         int i;
1893
1894         for (i = 0; i < priv->nr; i++)
1895                 serial8250_unregister_port(priv->line[i]);
1896
1897         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1898                 if (priv->remapped_bar[i])
1899                         iounmap(priv->remapped_bar[i]);
1900                 priv->remapped_bar[i] = NULL;
1901         }
1902
1903         /*
1904          * Find the exit quirks.
1905          */
1906         quirk = find_quirk(priv->dev);
1907         if (quirk->exit)
1908                 quirk->exit(priv->dev);
1909
1910         kfree(priv);
1911 }
1912 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1913
1914 void pciserial_suspend_ports(struct serial_private *priv)
1915 {
1916         int i;
1917
1918         for (i = 0; i < priv->nr; i++)
1919                 if (priv->line[i] >= 0)
1920                         serial8250_suspend_port(priv->line[i]);
1921 }
1922 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1923
1924 void pciserial_resume_ports(struct serial_private *priv)
1925 {
1926         int i;
1927
1928         /*
1929          * Ensure that the board is correctly configured.
1930          */
1931         if (priv->quirk->init)
1932                 priv->quirk->init(priv->dev);
1933
1934         for (i = 0; i < priv->nr; i++)
1935                 if (priv->line[i] >= 0)
1936                         serial8250_resume_port(priv->line[i]);
1937 }
1938 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1939
1940 /*
1941  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1942  * to the arrangement of serial ports on a PCI card.
1943  */
1944 static int __devinit
1945 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1946 {
1947         struct serial_private *priv;
1948         struct pciserial_board *board, tmp;
1949         int rc;
1950
1951         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1952                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1953                         ent->driver_data);
1954                 return -EINVAL;
1955         }
1956
1957         board = &pci_boards[ent->driver_data];
1958
1959         rc = pci_enable_device(dev);
1960         if (rc)
1961                 return rc;
1962
1963         if (ent->driver_data == pbn_default) {
1964                 /*
1965                  * Use a copy of the pci_board entry for this;
1966                  * avoid changing entries in the table.
1967                  */
1968                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1969                 board = &tmp;
1970
1971                 /*
1972                  * We matched one of our class entries.  Try to
1973                  * determine the parameters of this board.
1974                  */
1975                 rc = serial_pci_guess_board(dev, board);
1976                 if (rc)
1977                         goto disable;
1978         } else {
1979                 /*
1980                  * We matched an explicit entry.  If we are able to
1981                  * detect this boards settings with our heuristic,
1982                  * then we no longer need this entry.
1983                  */
1984                 memcpy(&tmp, &pci_boards[pbn_default],
1985                        sizeof(struct pciserial_board));
1986                 rc = serial_pci_guess_board(dev, &tmp);
1987                 if (rc == 0 && serial_pci_matches(board, &tmp))
1988                         moan_device("Redundant entry in serial pci_table.",
1989                                     dev);
1990         }
1991
1992         priv = pciserial_init_ports(dev, board);
1993         if (!IS_ERR(priv)) {
1994                 pci_set_drvdata(dev, priv);
1995                 return 0;
1996         }
1997
1998         rc = PTR_ERR(priv);
1999
2000  disable:
2001         pci_disable_device(dev);
2002         return rc;
2003 }
2004
2005 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2006 {
2007         struct serial_private *priv = pci_get_drvdata(dev);
2008
2009         pci_set_drvdata(dev, NULL);
2010
2011         pciserial_remove_ports(priv);
2012
2013         pci_disable_device(dev);
2014 }
2015
2016 #ifdef CONFIG_PM
2017 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2018 {
2019         struct serial_private *priv = pci_get_drvdata(dev);
2020
2021         if (priv)
2022                 pciserial_suspend_ports(priv);
2023
2024         pci_save_state(dev);
2025         pci_set_power_state(dev, pci_choose_state(dev, state));
2026         return 0;
2027 }
2028
2029 static int pciserial_resume_one(struct pci_dev *dev)
2030 {
2031         int err;
2032         struct serial_private *priv = pci_get_drvdata(dev);
2033
2034         pci_set_power_state(dev, PCI_D0);
2035         pci_restore_state(dev);
2036
2037         if (priv) {
2038                 /*
2039                  * The device may have been disabled.  Re-enable it.
2040                  */
2041                 err = pci_enable_device(dev);
2042                 if (err)
2043                         return err;
2044
2045                 pciserial_resume_ports(priv);
2046         }
2047         return 0;
2048 }
2049 #endif
2050
2051 static struct pci_device_id serial_pci_tbl[] = {
2052         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2053                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2054                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2055                 pbn_b1_8_1382400 },
2056         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2057                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2058                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2059                 pbn_b1_4_1382400 },
2060         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2061                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2062                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2063                 pbn_b1_2_1382400 },
2064         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2065                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2066                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2067                 pbn_b1_8_1382400 },
2068         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2069                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2070                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2071                 pbn_b1_4_1382400 },
2072         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2073                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2074                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2075                 pbn_b1_2_1382400 },
2076         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2077                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2078                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2079                 pbn_b1_8_921600 },
2080         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2081                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2082                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2083                 pbn_b1_8_921600 },
2084         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2085                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2086                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2087                 pbn_b1_4_921600 },
2088         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2089                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2090                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2091                 pbn_b1_4_921600 },
2092         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2093                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2094                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2095                 pbn_b1_2_921600 },
2096         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2097                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2098                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2099                 pbn_b1_8_921600 },
2100         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2101                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2102                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2103                 pbn_b1_8_921600 },
2104         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2105                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2106                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2107                 pbn_b1_4_921600 },
2108         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2109                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2110                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2111                 pbn_b1_2_1250000 },
2112         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2113                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2114                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2115                 pbn_b0_2_1843200 },
2116         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2117                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2118                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2119                 pbn_b0_4_1843200 },
2120         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2121                 PCI_VENDOR_ID_AFAVLAB,
2122                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2123                 pbn_b0_4_1152000 },
2124         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2125                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2126                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2127                 pbn_b0_2_1843200_200 },
2128         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2129                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2130                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2131                 pbn_b0_4_1843200_200 },
2132         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2133                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2134                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2135                 pbn_b0_8_1843200_200 },
2136         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2137                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2138                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2139                 pbn_b0_2_1843200_200 },
2140         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2141                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2142                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2143                 pbn_b0_4_1843200_200 },
2144         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2145                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2146                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2147                 pbn_b0_8_1843200_200 },
2148         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2149                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2150                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2151                 pbn_b0_2_1843200_200 },
2152         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2153                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2154                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2155                 pbn_b0_4_1843200_200 },
2156         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2157                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2158                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2159                 pbn_b0_8_1843200_200 },
2160         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2161                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2162                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2163                 pbn_b0_2_1843200_200 },
2164         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2165                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2166                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2167                 pbn_b0_4_1843200_200 },
2168         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2169                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2170                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2171                 pbn_b0_8_1843200_200 },
2172
2173         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2175                 pbn_b2_bt_1_115200 },
2176         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2178                 pbn_b2_bt_2_115200 },
2179         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2181                 pbn_b2_bt_4_115200 },
2182         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2184                 pbn_b2_bt_2_115200 },
2185         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2186                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2187                 pbn_b2_bt_4_115200 },
2188         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2190                 pbn_b2_8_115200 },
2191         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2192                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2193                 pbn_b2_8_115200 },
2194
2195         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2196                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2197                 pbn_b2_bt_2_115200 },
2198         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2199                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2200                 pbn_b2_bt_2_921600 },
2201         /*
2202          * VScom SPCOM800, from sl@s.pl
2203          */
2204         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2206                 pbn_b2_8_921600 },
2207         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2209                 pbn_b2_4_921600 },
2210         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2211                 PCI_SUBVENDOR_ID_KEYSPAN,
2212                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2213                 pbn_panacom },
2214         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2215                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2216                 pbn_panacom4 },
2217         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2219                 pbn_panacom2 },
2220         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2221                 PCI_VENDOR_ID_ESDGMBH,
2222                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2223                 pbn_b2_4_115200 },
2224         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2225                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2226                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2227                 pbn_b2_4_460800 },
2228         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2229                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2230                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2231                 pbn_b2_8_460800 },
2232         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2233                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2234                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2235                 pbn_b2_16_460800 },
2236         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2237                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2238                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2239                 pbn_b2_16_460800 },
2240         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2241                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2242                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2243                 pbn_b2_4_460800 },
2244         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2245                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2246                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2247                 pbn_b2_8_460800 },
2248         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2249                 PCI_SUBVENDOR_ID_EXSYS,
2250                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2251                 pbn_exsys_4055 },
2252         /*
2253          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2254          * (Exoray@isys.ca)
2255          */
2256         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2257                 0x10b5, 0x106a, 0, 0,
2258                 pbn_plx_romulus },
2259         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2261                 pbn_b1_4_115200 },
2262         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2264                 pbn_b1_2_115200 },
2265         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2266                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2267                 pbn_b1_8_115200 },
2268         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2270                 pbn_b1_8_115200 },
2271         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2272                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2273                 pbn_b0_4_921600 },
2274         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2275                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2276                 pbn_b0_4_1152000 },
2277
2278                 /*
2279                  * The below card is a little controversial since it is the
2280                  * subject of a PCI vendor/device ID clash.  (See
2281                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2282                  * For now just used the hex ID 0x950a.
2283                  */
2284         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2285                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2286                 pbn_b0_2_1130000 },
2287         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2288                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2289                 pbn_b0_4_115200 },
2290         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2291                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2292                 pbn_b0_bt_2_921600 },
2293
2294         /*
2295          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2296          * from skokodyn@yahoo.com
2297          */
2298         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2299                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2300                 pbn_sbsxrsio },
2301         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2302                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2303                 pbn_sbsxrsio },
2304         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2305                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2306                 pbn_sbsxrsio },
2307         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2308                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2309                 pbn_sbsxrsio },
2310
2311         /*
2312          * Digitan DS560-558, from jimd@esoft.com
2313          */
2314         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2315                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2316                 pbn_b1_1_115200 },
2317
2318         /*
2319          * Titan Electronic cards
2320          *  The 400L and 800L have a custom setup quirk.
2321          */
2322         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2324                 pbn_b0_1_921600 },
2325         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2327                 pbn_b0_2_921600 },
2328         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2329                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2330                 pbn_b0_4_921600 },
2331         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2333                 pbn_b0_4_921600 },
2334         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2336                 pbn_b1_1_921600 },
2337         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2339                 pbn_b1_bt_2_921600 },
2340         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2342                 pbn_b0_bt_4_921600 },
2343         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2345                 pbn_b0_bt_8_921600 },
2346
2347         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2348                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2349                 pbn_b2_1_460800 },
2350         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2351                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2352                 pbn_b2_1_460800 },
2353         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2354                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2355                 pbn_b2_1_460800 },
2356         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2357                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2358                 pbn_b2_bt_2_921600 },
2359         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2360                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2361                 pbn_b2_bt_2_921600 },
2362         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2363                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2364                 pbn_b2_bt_2_921600 },
2365         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2366                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2367                 pbn_b2_bt_4_921600 },
2368         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2369                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2370                 pbn_b2_bt_4_921600 },
2371         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2372                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2373                 pbn_b2_bt_4_921600 },
2374         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2375                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2376                 pbn_b0_1_921600 },
2377         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2378                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2379                 pbn_b0_1_921600 },
2380         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2381                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2382                 pbn_b0_1_921600 },
2383         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2384                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2385                 pbn_b0_bt_2_921600 },
2386         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2387                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2388                 pbn_b0_bt_2_921600 },
2389         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2390                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2391                 pbn_b0_bt_2_921600 },
2392         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2394                 pbn_b0_bt_4_921600 },
2395         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2397                 pbn_b0_bt_4_921600 },
2398         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2400                 pbn_b0_bt_4_921600 },
2401         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2403                 pbn_b0_bt_8_921600 },
2404         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2406                 pbn_b0_bt_8_921600 },
2407         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2409                 pbn_b0_bt_8_921600 },
2410
2411         /*
2412          * Computone devices submitted by Doug McNash dmcnash@computone.com
2413          */
2414         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2415                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2416                 0, 0, pbn_computone_4 },
2417         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2418                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2419                 0, 0, pbn_computone_8 },
2420         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2421                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2422                 0, 0, pbn_computone_6 },
2423
2424         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2425                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2426                 pbn_oxsemi },
2427         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2428                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2429                 pbn_b0_bt_1_921600 },
2430
2431         /*
2432          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2433          */
2434         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2436                 pbn_b0_bt_8_115200 },
2437         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2439                 pbn_b0_bt_8_115200 },
2440
2441         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2442                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2443                 pbn_b0_bt_2_115200 },
2444         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2445                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2446                 pbn_b0_bt_2_115200 },
2447         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2448                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2449                 pbn_b0_bt_2_115200 },
2450         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2451                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2452                 pbn_b0_bt_4_460800 },
2453         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2454                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2455                 pbn_b0_bt_4_460800 },
2456         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2457                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2458                 pbn_b0_bt_2_460800 },
2459         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2460                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2461                 pbn_b0_bt_2_460800 },
2462         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2463                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2464                 pbn_b0_bt_2_460800 },
2465         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2466                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2467                 pbn_b0_bt_1_115200 },
2468         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2469                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2470                 pbn_b0_bt_1_460800 },
2471
2472         /*
2473          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2474          * Cards are identified by their subsystem vendor IDs, which
2475          * (in hex) match the model number.
2476          *
2477          * Note that JC140x are RS422/485 cards which require ox950
2478          * ACR = 0x10, and as such are not currently fully supported.
2479          */
2480         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2481                 0x1204, 0x0004, 0, 0,
2482                 pbn_b0_4_921600 },
2483         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2484                 0x1208, 0x0004, 0, 0,
2485                 pbn_b0_4_921600 },
2486 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2487                 0x1402, 0x0002, 0, 0,
2488                 pbn_b0_2_921600 }, */
2489 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2490                 0x1404, 0x0004, 0, 0,
2491                 pbn_b0_4_921600 }, */
2492         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2493                 0x1208, 0x0004, 0, 0,
2494                 pbn_b0_4_921600 },
2495
2496         /*
2497          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2498          */
2499         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2501                 pbn_b1_1_1382400 },
2502
2503         /*
2504          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2505          */
2506         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2507                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2508                 pbn_b1_1_1382400 },
2509
2510         /*
2511          * RAStel 2 port modem, gerg@moreton.com.au
2512          */
2513         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2514                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2515                 pbn_b2_bt_2_115200 },
2516
2517         /*
2518          * EKF addition for i960 Boards form EKF with serial port
2519          */
2520         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2521                 0xE4BF, PCI_ANY_ID, 0, 0,
2522                 pbn_intel_i960 },
2523
2524         /*
2525          * Xircom Cardbus/Ethernet combos
2526          */
2527         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2528                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2529                 pbn_b0_1_115200 },
2530         /*
2531          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2532          */
2533         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2535                 pbn_b0_1_115200 },
2536
2537         /*
2538          * Untested PCI modems, sent in from various folks...
2539          */
2540
2541         /*
2542          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2543          */
2544         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2545                 0x1048, 0x1500, 0, 0,
2546                 pbn_b1_1_115200 },
2547
2548         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2549                 0xFF00, 0, 0, 0,
2550                 pbn_sgi_ioc3 },
2551
2552         /*
2553          * HP Diva card
2554          */
2555         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2556                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2557                 pbn_b1_1_115200 },
2558         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2559                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2560                 pbn_b0_5_115200 },
2561         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2562                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2563                 pbn_b2_1_115200 },
2564
2565         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2566                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2567                 pbn_b3_2_115200 },
2568         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2569                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2570                 pbn_b3_4_115200 },
2571         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2572                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2573                 pbn_b3_8_115200 },
2574
2575         /*
2576          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2577          */
2578         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2579                 PCI_ANY_ID, PCI_ANY_ID,
2580                 0,
2581                 0, pbn_exar_XR17C152 },
2582         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2583                 PCI_ANY_ID, PCI_ANY_ID,
2584                 0,
2585                 0, pbn_exar_XR17C154 },
2586         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2587                 PCI_ANY_ID, PCI_ANY_ID,
2588                 0,
2589                 0, pbn_exar_XR17C158 },
2590
2591         /*
2592          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2593          */
2594         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2595                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2596                 pbn_b0_1_115200 },
2597         /*
2598          * ITE
2599          */
2600         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2601                 PCI_ANY_ID, PCI_ANY_ID,
2602                 0, 0,
2603                 pbn_b1_bt_1_115200 },
2604
2605         /*
2606          * IntaShield IS-200
2607          */
2608         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2609                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
2610                 pbn_b2_2_115200 },
2611
2612         /*
2613          * Perle PCI-RAS cards
2614          */
2615         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2616                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2617                 0, 0, pbn_b2_4_921600 },
2618         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2619                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2620                 0, 0, pbn_b2_8_921600 },
2621
2622         /*
2623          * Mainpine series cards: Fairly standard layout but fools
2624          * parts of the autodetect in some cases and uses otherwise
2625          * unmatched communications subclasses in the PCI Express case
2626          */
2627
2628         {       /* RockForceDUO */
2629                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2630                 PCI_VENDOR_ID_MAINPINE, 0x0200,
2631                 0, 0, pbn_b0_2_115200 },
2632         {       /* RockForceQUATRO */
2633                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2634                 PCI_VENDOR_ID_MAINPINE, 0x0300,
2635                 0, 0, pbn_b0_4_115200 },
2636         {       /* RockForceDUO+ */
2637                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2638                 PCI_VENDOR_ID_MAINPINE, 0x0400,
2639                 0, 0, pbn_b0_2_115200 },
2640         {       /* RockForceQUATRO+ */
2641                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2642                 PCI_VENDOR_ID_MAINPINE, 0x0500,
2643                 0, 0, pbn_b0_4_115200 },
2644         {       /* RockForce+ */
2645                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2646                 PCI_VENDOR_ID_MAINPINE, 0x0600,
2647                 0, 0, pbn_b0_2_115200 },
2648         {       /* RockForce+ */
2649                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2650                 PCI_VENDOR_ID_MAINPINE, 0x0700,
2651                 0, 0, pbn_b0_4_115200 },
2652         {       /* RockForceOCTO+ */
2653                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2654                 PCI_VENDOR_ID_MAINPINE, 0x0800,
2655                 0, 0, pbn_b0_8_115200 },
2656         {       /* RockForceDUO+ */
2657                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2658                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2659                 0, 0, pbn_b0_2_115200 },
2660         {       /* RockForceQUARTRO+ */
2661                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2662                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2663                 0, 0, pbn_b0_4_115200 },
2664         {       /* RockForceOCTO+ */
2665                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2666                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2667                 0, 0, pbn_b0_8_115200 },
2668         {       /* RockForceD1 */
2669                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2670                 PCI_VENDOR_ID_MAINPINE, 0x2000,
2671                 0, 0, pbn_b0_1_115200 },
2672         {       /* RockForceF1 */
2673                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2674                 PCI_VENDOR_ID_MAINPINE, 0x2100,
2675                 0, 0, pbn_b0_1_115200 },
2676         {       /* RockForceD2 */
2677                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2678                 PCI_VENDOR_ID_MAINPINE, 0x2200,
2679                 0, 0, pbn_b0_2_115200 },
2680         {       /* RockForceF2 */
2681                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2682                 PCI_VENDOR_ID_MAINPINE, 0x2300,
2683                 0, 0, pbn_b0_2_115200 },
2684         {       /* RockForceD4 */
2685                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2686                 PCI_VENDOR_ID_MAINPINE, 0x2400,
2687                 0, 0, pbn_b0_4_115200 },
2688         {       /* RockForceF4 */
2689                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2690                 PCI_VENDOR_ID_MAINPINE, 0x2500,
2691                 0, 0, pbn_b0_4_115200 },
2692         {       /* RockForceD8 */
2693                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2694                 PCI_VENDOR_ID_MAINPINE, 0x2600,
2695                 0, 0, pbn_b0_8_115200 },
2696         {       /* RockForceF8 */
2697                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2698                 PCI_VENDOR_ID_MAINPINE, 0x2700,
2699                 0, 0, pbn_b0_8_115200 },
2700         {       /* IQ Express D1 */
2701                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2702                 PCI_VENDOR_ID_MAINPINE, 0x3000,
2703                 0, 0, pbn_b0_1_115200 },
2704         {       /* IQ Express F1 */
2705                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2706                 PCI_VENDOR_ID_MAINPINE, 0x3100,
2707                 0, 0, pbn_b0_1_115200 },
2708         {       /* IQ Express D2 */
2709                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2710                 PCI_VENDOR_ID_MAINPINE, 0x3200,
2711                 0, 0, pbn_b0_2_115200 },
2712         {       /* IQ Express F2 */
2713                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2714                 PCI_VENDOR_ID_MAINPINE, 0x3300,
2715                 0, 0, pbn_b0_2_115200 },
2716         {       /* IQ Express D4 */
2717                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2718                 PCI_VENDOR_ID_MAINPINE, 0x3400,
2719                 0, 0, pbn_b0_4_115200 },
2720         {       /* IQ Express F4 */
2721                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2722                 PCI_VENDOR_ID_MAINPINE, 0x3500,
2723                 0, 0, pbn_b0_4_115200 },
2724         {       /* IQ Express D8 */
2725                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2726                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
2727                 0, 0, pbn_b0_8_115200 },
2728         {       /* IQ Express F8 */
2729                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2730                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
2731                 0, 0, pbn_b0_8_115200 },
2732
2733
2734         /*
2735          * PA Semi PA6T-1682M on-chip UART
2736          */
2737         {       PCI_VENDOR_ID_PASEMI, 0xa004,
2738                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2739                 pbn_pasemi_1682M },
2740
2741         /*
2742         * ADDI-DATA GmbH communication cards <info@addi-data.com>
2743         */
2744         {       PCI_VENDOR_ID_ADDIDATA,
2745                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
2746                 PCI_ANY_ID,
2747                 PCI_ANY_ID,
2748                 0,
2749                 0,
2750                 pbn_b0_4_115200 },
2751
2752         {       PCI_VENDOR_ID_ADDIDATA,
2753                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
2754                 PCI_ANY_ID,
2755                 PCI_ANY_ID,
2756                 0,
2757                 0,
2758                 pbn_b0_2_115200 },
2759
2760         {       PCI_VENDOR_ID_ADDIDATA,
2761                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
2762                 PCI_ANY_ID,
2763                 PCI_ANY_ID,
2764                 0,
2765                 0,
2766                 pbn_b0_1_115200 },
2767
2768         {       PCI_VENDOR_ID_ADDIDATA_OLD,
2769                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
2770                 PCI_ANY_ID,
2771                 PCI_ANY_ID,
2772                 0,
2773                 0,
2774                 pbn_b1_8_115200 },
2775
2776         {       PCI_VENDOR_ID_ADDIDATA,
2777                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
2778                 PCI_ANY_ID,
2779                 PCI_ANY_ID,
2780                 0,
2781                 0,
2782                 pbn_b0_4_115200 },
2783
2784         {       PCI_VENDOR_ID_ADDIDATA,
2785                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
2786                 PCI_ANY_ID,
2787                 PCI_ANY_ID,
2788                 0,
2789                 0,
2790                 pbn_b0_2_115200 },
2791
2792         {       PCI_VENDOR_ID_ADDIDATA,
2793                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
2794                 PCI_ANY_ID,
2795                 PCI_ANY_ID,
2796                 0,
2797                 0,
2798                 pbn_b0_1_115200 },
2799
2800         {       PCI_VENDOR_ID_ADDIDATA,
2801                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
2802                 PCI_ANY_ID,
2803                 PCI_ANY_ID,
2804                 0,
2805                 0,
2806                 pbn_b0_4_115200 },
2807
2808         {       PCI_VENDOR_ID_ADDIDATA,
2809                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
2810                 PCI_ANY_ID,
2811                 PCI_ANY_ID,
2812                 0,
2813                 0,
2814                 pbn_b0_2_115200 },
2815
2816         {       PCI_VENDOR_ID_ADDIDATA,
2817                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
2818                 PCI_ANY_ID,
2819                 PCI_ANY_ID,
2820                 0,
2821                 0,
2822                 pbn_b0_1_115200 },
2823
2824         {       PCI_VENDOR_ID_ADDIDATA,
2825                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
2826                 PCI_ANY_ID,
2827                 PCI_ANY_ID,
2828                 0,
2829                 0,
2830                 pbn_b0_8_115200 },
2831
2832         /*
2833          * These entries match devices with class COMMUNICATION_SERIAL,
2834          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2835          */
2836         {       PCI_ANY_ID, PCI_ANY_ID,
2837                 PCI_ANY_ID, PCI_ANY_ID,
2838                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2839                 0xffff00, pbn_default },
2840         {       PCI_ANY_ID, PCI_ANY_ID,
2841                 PCI_ANY_ID, PCI_ANY_ID,
2842                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2843                 0xffff00, pbn_default },
2844         {       PCI_ANY_ID, PCI_ANY_ID,
2845                 PCI_ANY_ID, PCI_ANY_ID,
2846                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2847                 0xffff00, pbn_default },
2848         { 0, }
2849 };
2850
2851 static struct pci_driver serial_pci_driver = {
2852         .name           = "serial",
2853         .probe          = pciserial_init_one,
2854         .remove         = __devexit_p(pciserial_remove_one),
2855 #ifdef CONFIG_PM
2856         .suspend        = pciserial_suspend_one,
2857         .resume         = pciserial_resume_one,
2858 #endif
2859         .id_table       = serial_pci_tbl,
2860 };
2861
2862 static int __init serial8250_pci_init(void)
2863 {
2864         return pci_register_driver(&serial_pci_driver);
2865 }
2866
2867 static void __exit serial8250_pci_exit(void)
2868 {
2869         pci_unregister_driver(&serial_pci_driver);
2870 }
2871
2872 module_init(serial8250_pci_init);
2873 module_exit(serial8250_pci_exit);
2874
2875 MODULE_LICENSE("GPL");
2876 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2877 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);