2 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/platform_device.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/mtd/plat-ram.h>
24 #include <asm/mach/arch.h>
25 #include <asm/mach-types.h>
26 #include <mach/common.h>
27 #include <mach/hardware.h>
28 #include <mach/iomux.h>
29 #include <asm/mach/time.h>
30 #include <mach/imx-uart.h>
31 #include <mach/board-pcm038.h>
32 #include <mach/mxc_nand.h>
37 * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
41 static struct platdata_mtd_ram pcm038_sram_data = {
45 static struct resource pcm038_sram_resource = {
46 .start = CS1_BASE_ADDR,
47 .end = CS1_BASE_ADDR + 512 * 1024 - 1,
48 .flags = IORESOURCE_MEM,
51 static struct platform_device pcm038_sram_mtd_device = {
55 .platform_data = &pcm038_sram_data,
58 .resource = &pcm038_sram_resource,
62 * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
65 static struct physmap_flash_data pcm038_flash_data = {
69 static struct resource pcm038_flash_resource = {
72 .flags = IORESOURCE_MEM,
75 static struct platform_device pcm038_nor_mtd_device = {
76 .name = "physmap-flash",
79 .platform_data = &pcm038_flash_data,
82 .resource = &pcm038_flash_resource,
85 static int mxc_uart0_pins[] = {
92 static int uart_mxc_port0_init(struct platform_device *pdev)
94 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
95 ARRAY_SIZE(mxc_uart0_pins), "UART0");
98 static int uart_mxc_port0_exit(struct platform_device *pdev)
100 mxc_gpio_release_multiple_pins(mxc_uart0_pins,
101 ARRAY_SIZE(mxc_uart0_pins));
105 static int mxc_uart1_pins[] = {
112 static int uart_mxc_port1_init(struct platform_device *pdev)
114 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
115 ARRAY_SIZE(mxc_uart1_pins), "UART1");
118 static int uart_mxc_port1_exit(struct platform_device *pdev)
120 mxc_gpio_release_multiple_pins(mxc_uart1_pins,
121 ARRAY_SIZE(mxc_uart1_pins));
125 static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
130 static int uart_mxc_port2_init(struct platform_device *pdev)
132 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
133 ARRAY_SIZE(mxc_uart2_pins), "UART2");
136 static int uart_mxc_port2_exit(struct platform_device *pdev)
138 mxc_gpio_release_multiple_pins(mxc_uart2_pins,
139 ARRAY_SIZE(mxc_uart2_pins));
143 static struct imxuart_platform_data uart_pdata[] = {
145 .init = uart_mxc_port0_init,
146 .exit = uart_mxc_port0_exit,
147 .flags = IMXUART_HAVE_RTSCTS,
149 .init = uart_mxc_port1_init,
150 .exit = uart_mxc_port1_exit,
151 .flags = IMXUART_HAVE_RTSCTS,
153 .init = uart_mxc_port2_init,
154 .exit = uart_mxc_port2_exit,
155 .flags = IMXUART_HAVE_RTSCTS,
159 static int mxc_fec_pins[] = {
171 PD11_AOUT_FEC_TX_CLK,
174 PD14_AOUT_FEC_RX_CLK,
180 static void gpio_fec_active(void)
182 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
183 ARRAY_SIZE(mxc_fec_pins), "FEC");
186 static void gpio_fec_inactive(void)
188 mxc_gpio_release_multiple_pins(mxc_fec_pins,
189 ARRAY_SIZE(mxc_fec_pins));
192 static struct mxc_nand_platform_data pcm038_nand_board_info = {
197 static struct platform_device *platform_devices[] __initdata = {
198 &pcm038_nor_mtd_device,
199 &mxc_w1_master_device,
200 &pcm038_sram_mtd_device,
203 /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
204 * setup other stuffs to access the sram. */
205 static void __init pcm038_init_sram(void)
207 __raw_writel(0x0000d843, CSCR_U(1));
208 __raw_writel(0x22252521, CSCR_L(1));
209 __raw_writel(0x22220a00, CSCR_A(1));
212 static void __init pcm038_init(void)
217 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
218 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
219 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
221 mxc_gpio_mode(PE16_AF_OWIRE);
222 mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
224 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
226 #ifdef CONFIG_MACH_PCM970_BASEBOARD
227 pcm970_baseboard_init();
231 static void __init pcm038_timer_init(void)
233 mx27_clocks_init(26000000);
236 struct sys_timer pcm038_timer = {
237 .init = pcm038_timer_init,
240 MACHINE_START(PCM038, "phyCORE-i.MX27")
241 .phys_io = AIPI_BASE_ADDR,
242 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
243 .boot_params = PHYS_OFFSET + 0x100,
244 .map_io = mxc_map_io,
245 .init_irq = mxc_init_irq,
246 .init_machine = pcm038_init,
247 .timer = &pcm038_timer,