git.oblomov.eu Git - linux-2.6/blob - sound/pci/intel8x0.c

   1 /*
   2  *   ALSA driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
   5  *
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11  *
  12  *   This program is free software; you can redistribute it and/or modify
  13  *   it under the terms of the GNU General Public License as published by
  14  *   the Free Software Foundation; either version 2 of the License, or
  15  *   (at your option) any later version.
  16  *
  17  *   This program is distributed in the hope that it will be useful,
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *   GNU General Public License for more details.
  21  *
  22  *   You should have received a copy of the GNU General Public License
  23  *   along with this program; if not, write to the Free Software
  24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25
  26  *
  27  */
  28
  29 #include <asm/io.h>
  30 #include <linux/delay.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/init.h>
  33 #include <linux/pci.h>
  34 #include <linux/slab.h>
  35 #include <linux/moduleparam.h>
  36 #include <sound/core.h>
  37 #include <sound/pcm.h>
  38 #include <sound/ac97_codec.h>
  39 #include <sound/info.h>
  40 #include <sound/initval.h>
  41 /* for 440MX workaround */
  42 #include <asm/pgtable.h>
  43 #include <asm/cacheflush.h>
  44
  45 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  46 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  47 MODULE_LICENSE("GPL");
  48 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  49                 "{Intel,82901AB-ICH0},"
  50                 "{Intel,82801BA-ICH2},"
  51                 "{Intel,82801CA-ICH3},"
  52                 "{Intel,82801DB-ICH4},"
  53                 "{Intel,ICH5},"
  54                 "{Intel,ICH6},"
  55                 "{Intel,ICH7},"
  56                 "{Intel,6300ESB},"
  57                 "{Intel,ESB2},"
  58                 "{Intel,MX440},"
  59                 "{SiS,SI7012},"
  60                 "{NVidia,nForce Audio},"
  61                 "{NVidia,nForce2 Audio},"
  62                 "{NVidia,nForce3 Audio},"
  63                 "{NVidia,MCP04},"
  64                 "{NVidia,MCP501},"
  65                 "{NVidia,CK804},"
  66                 "{NVidia,CK8},"
  67                 "{NVidia,CK8S},"
  68                 "{AMD,AMD768},"
  69                 "{AMD,AMD8111},"
  70                 "{ALI,M5455}}");
  71
  72 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  73 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  74 static int ac97_clock;
  75 static char *ac97_quirk;
  76 static int buggy_semaphore;
  77 static int buggy_irq = -1; /* auto-check */
  78 static int xbox;
  79 static int spdif_aclink = -1;
  80
  81 module_param(index, int, 0444);
  82 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  83 module_param(id, charp, 0444);
  84 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  85 module_param(ac97_clock, int, 0444);
  86 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
  87 module_param(ac97_quirk, charp, 0444);
  88 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  89 module_param(buggy_semaphore, bool, 0444);
  90 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  91 module_param(buggy_irq, bool, 0444);
  92 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  93 module_param(xbox, bool, 0444);
  94 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  95 module_param(spdif_aclink, int, 0444);
  96 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  97
  98 /* just for backward compatibility */
  99 static int enable;
 100 module_param(enable, bool, 0444);
 101 static int joystick;
 102 module_param(joystick, int, 0444);
 103
 104 /*
 105  *  Direct registers
 106  */
 107 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 108
 109 #define ICHREG(x) ICH_REG_##x
 110
 111 #define DEFINE_REGSET(name,base) \
 112 enum { \
 113         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 114         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 115         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 116         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 117         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 118         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 119         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 120 };
 121
 122 /* busmaster blocks */
 123 DEFINE_REGSET(OFF, 0);          /* offset */
 124 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 125 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 126 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 127
 128 /* ICH4 busmaster blocks */
 129 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 130 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 131 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 132
 133 /* values for each busmaster block */
 134
 135 /* LVI */
 136 #define ICH_REG_LVI_MASK                0x1f
 137
 138 /* SR */
 139 #define ICH_FIFOE                       0x10    /* FIFO error */
 140 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 141 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 142 #define ICH_CELV                        0x02    /* current equals last valid */
 143 #define ICH_DCH                         0x01    /* DMA controller halted */
 144
 145 /* PIV */
 146 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 147
 148 /* CR */
 149 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 150 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 151 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 152 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 153 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 154
 155
 156 /* global block */
 157 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 158 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 159 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 160 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 161 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 162 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 163 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 164 #define   ICH_PCM_246_MASK      0x00300000      /* chan mask (not all chips) */
 165 #define   ICH_PCM_8             0x00300000      /* 8 channels (not all chips) */
 166 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 167 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 168 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 169 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 170 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 171 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 172 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 173 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 174 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 175 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 176 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 177 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 178 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 179 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 180 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 181 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 182 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 183 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 184 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 185 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 186 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 187 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 188 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 189 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 190 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
 191 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
 192 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 193 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 194 #define   ICH_RCS               0x00008000      /* read completion status */
 195 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 196 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 197 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 198 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 199 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 200 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 201 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 202 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 203 #define   ICH_POINT             0x00000040      /* playback interrupt */
 204 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 205 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 206 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 207 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 208 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 209 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 210 #define   ICH_CAS               0x01            /* codec access semaphore */
 211 #define ICH_REG_SDM             0x80
 212 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 213 #define   ICH_DI2L_SHIFT        6
 214 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 215 #define   ICH_DI1L_SHIFT        4
 216 #define   ICH_SE                0x00000008      /* steer enable */
 217 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 218
 219 #define ICH_MAX_FRAGS           32              /* max hw frags */
 220
 221
 222 /*
 223  * registers for Ali5455
 224  */
 225
 226 /* ALi 5455 busmaster blocks */
 227 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 228 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 229 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 230 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 231 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 232 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 233 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 234 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 235 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 236 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 237 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 238
 239 enum {
 240         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 241         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 242         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 243         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 244         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 245         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 246         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 247         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 248         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 249         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 250         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 251         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 252         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 253         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 254         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 255         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 256         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 257         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 258         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 259         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 260         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 261 };
 262
 263 #define ALI_CAS_SEM_BUSY        0x80000000
 264 #define ALI_CPR_ADDR_SECONDARY  0x100
 265 #define ALI_CPR_ADDR_READ       0x80
 266 #define ALI_CSPSR_CODEC_READY   0x08
 267 #define ALI_CSPSR_READ_OK       0x02
 268 #define ALI_CSPSR_WRITE_OK      0x01
 269
 270 /* interrupts for the whole chip by interrupt status register finish */
 271
 272 #define ALI_INT_MICIN2          (1<<26)
 273 #define ALI_INT_PCMIN2          (1<<25)
 274 #define ALI_INT_I2SIN           (1<<24)
 275 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 276 #define ALI_INT_SPDIFIN         (1<<22)
 277 #define ALI_INT_LFEOUT          (1<<21)
 278 #define ALI_INT_CENTEROUT       (1<<20)
 279 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 280 #define ALI_INT_MICIN           (1<<18)
 281 #define ALI_INT_PCMOUT          (1<<17)
 282 #define ALI_INT_PCMIN           (1<<16)
 283 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 284 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 285 #define ALI_INT_GPIO            (1<<1)
 286 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
 287                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 288
 289 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 290 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 291 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 292 #define ICH_ALI_SC_IN_BITS      (3<<18)
 293 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 294 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 295 #define ICH_ALI_SC_PCM_4        (1<<8)
 296 #define ICH_ALI_SC_PCM_6        (2<<8)
 297 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 298
 299 #define ICH_ALI_SS_SEC_ID       (3<<5)
 300 #define ICH_ALI_SS_PRI_ID       (3<<3)
 301
 302 #define ICH_ALI_IF_AC97SP       (1<<21)
 303 #define ICH_ALI_IF_MC           (1<<20)
 304 #define ICH_ALI_IF_PI           (1<<19)
 305 #define ICH_ALI_IF_MC2          (1<<18)
 306 #define ICH_ALI_IF_PI2          (1<<17)
 307 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 308 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 309 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 310 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 311 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 312 #define ICH_ALI_IF_PO           (1<<1)
 313
 314 /*
 315  *
 316  */
 317
 318 enum {
 319         ICHD_PCMIN,
 320         ICHD_PCMOUT,
 321         ICHD_MIC,
 322         ICHD_MIC2,
 323         ICHD_PCM2IN,
 324         ICHD_SPBAR,
 325         ICHD_LAST = ICHD_SPBAR
 326 };
 327 enum {
 328         NVD_PCMIN,
 329         NVD_PCMOUT,
 330         NVD_MIC,
 331         NVD_SPBAR,
 332         NVD_LAST = NVD_SPBAR
 333 };
 334 enum {
 335         ALID_PCMIN,
 336         ALID_PCMOUT,
 337         ALID_MIC,
 338         ALID_AC97SPDIFOUT,
 339         ALID_SPDIFIN,
 340         ALID_SPDIFOUT,
 341         ALID_LAST = ALID_SPDIFOUT
 342 };
 343
 344 #define get_ichdev(substream) (substream->runtime->private_data)
 345
 346 struct ichdev {
 347         unsigned int ichd;                      /* ich device number */
 348         unsigned long reg_offset;               /* offset to bmaddr */
 349         u32 *bdbar;                             /* CPU address (32bit) */
 350         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 351         struct snd_pcm_substream *substream;
 352         unsigned int physbuf;                   /* physical address (32bit) */
 353         unsigned int size;
 354         unsigned int fragsize;
 355         unsigned int fragsize1;
 356         unsigned int position;
 357         unsigned int pos_shift;
 358         int frags;
 359         int lvi;
 360         int lvi_frag;
 361         int civ;
 362         int ack;
 363         int ack_reload;
 364         unsigned int ack_bit;
 365         unsigned int roff_sr;
 366         unsigned int roff_picb;
 367         unsigned int int_sta_mask;              /* interrupt status mask */
 368         unsigned int ali_slot;                  /* ALI DMA slot */
 369         struct ac97_pcm *pcm;
 370         int pcm_open_flag;
 371         unsigned int page_attr_changed: 1;
 372         unsigned int suspended: 1;
 373 };
 374
 375 struct intel8x0 {
 376         unsigned int device_type;
 377
 378         int irq;
 379
 380         void __iomem *addr;
 381         void __iomem *bmaddr;
 382
 383         struct pci_dev *pci;
 384         struct snd_card *card;
 385
 386         int pcm_devs;
 387         struct snd_pcm *pcm[6];
 388         struct ichdev ichd[6];
 389
 390         unsigned multi4: 1,
 391                  multi6: 1,
 392                  multi8 :1,
 393                  dra: 1,
 394                  smp20bit: 1;
 395         unsigned in_ac97_init: 1,
 396                  in_sdin_init: 1;
 397         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 398         unsigned fix_nocache: 1;        /* workaround for 440MX */
 399         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 400         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 401         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 402
 403         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 404         unsigned int sdm_saved; /* SDM reg value */
 405
 406         struct snd_ac97_bus *ac97_bus;
 407         struct snd_ac97 *ac97[3];
 408         unsigned int ac97_sdin[3];
 409         unsigned int max_codecs, ncodecs;
 410         unsigned int *codec_bit;
 411         unsigned int codec_isr_bits;
 412         unsigned int codec_ready_bits;
 413
 414         spinlock_t reg_lock;
 415
 416         u32 bdbars_count;
 417         struct snd_dma_buffer bdbars;
 418         u32 int_sta_reg;                /* interrupt status register */
 419         u32 int_sta_mask;               /* interrupt status mask */
 420 };
 421
 422 static struct pci_device_id snd_intel8x0_ids[] = {
 423         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 424         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 425         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 426         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 427         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
 428         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
 429         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
 430         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
 431         { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
 432         { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
 433         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 434         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
 435         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
 436         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
 437         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
 438         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
 439         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
 440         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
 441         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
 442         { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP51 */
 443         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 444         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 445         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 446         { 0, }
 447 };
 448
 449 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 450
 451 /*
 452  *  Lowlevel I/O - busmaster
 453  */
 454
 455 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
 456 {
 457         return ioread8(chip->bmaddr + offset);
 458 }
 459
 460 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
 461 {
 462         return ioread16(chip->bmaddr + offset);
 463 }
 464
 465 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
 466 {
 467         return ioread32(chip->bmaddr + offset);
 468 }
 469
 470 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
 471 {
 472         iowrite8(val, chip->bmaddr + offset);
 473 }
 474
 475 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
 476 {
 477         iowrite16(val, chip->bmaddr + offset);
 478 }
 479
 480 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
 481 {
 482         iowrite32(val, chip->bmaddr + offset);
 483 }
 484
 485 /*
 486  *  Lowlevel I/O - AC'97 registers
 487  */
 488
 489 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
 490 {
 491         return ioread16(chip->addr + offset);
 492 }
 493
 494 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
 495 {
 496         iowrite16(val, chip->addr + offset);
 497 }
 498
 499 /*
 500  *  Basic I/O
 501  */
 502
 503 /*
 504  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 505  */
 506
 507 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
 508 {
 509         int time;
 510
 511         if (codec > 2)
 512                 return -EIO;
 513         if (chip->in_sdin_init) {
 514                 /* we don't know the ready bit assignment at the moment */
 515                 /* so we check any */
 516                 codec = chip->codec_isr_bits;
 517         } else {
 518                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
 519         }
 520
 521         /* codec ready ? */
 522         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 523                 return -EIO;
 524
 525         if (chip->buggy_semaphore)
 526                 return 0; /* just ignore ... */
 527
 528         /* Anyone holding a semaphore for 1 msec should be shot... */
 529         time = 100;
 530         do {
 531                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 532                         return 0;
 533                 udelay(10);
 534         } while (time--);
 535
 536         /* access to some forbidden (non existant) ac97 registers will not
 537          * reset the semaphore. So even if you don't get the semaphore, still
 538          * continue the access. We don't need the semaphore anyway. */
 539         snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 540                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 541         iagetword(chip, 0);     /* clear semaphore flag */
 542         /* I don't care about the semaphore */
 543         return -EBUSY;
 544 }
 545
 546 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
 547                                      unsigned short reg,
 548                                      unsigned short val)
 549 {
 550         struct intel8x0 *chip = ac97->private_data;
 551
 552         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 553                 if (! chip->in_ac97_init)
 554                         snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 555         }
 556         iaputword(chip, reg + ac97->num * 0x80, val);
 557 }
 558
 559 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
 560                                               unsigned short reg)
 561 {
 562         struct intel8x0 *chip = ac97->private_data;
 563         unsigned short res;
 564         unsigned int tmp;
 565
 566         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 567                 if (! chip->in_ac97_init)
 568                         snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 569                 res = 0xffff;
 570         } else {
 571                 res = iagetword(chip, reg + ac97->num * 0x80);
 572                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 573                         /* reset RCS and preserve other R/WC bits */
 574                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 575                                   ~(chip->codec_ready_bits | ICH_GSCI));
 576                         if (! chip->in_ac97_init)
 577                                 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 578                         res = 0xffff;
 579                 }
 580         }
 581         return res;
 582 }
 583
 584 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
 585                                                    unsigned int codec)
 586 {
 587         unsigned int tmp;
 588
 589         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 590                 iagetword(chip, codec * 0x80);
 591                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 592                         /* reset RCS and preserve other R/WC bits */
 593                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 594                                   ~(chip->codec_ready_bits | ICH_GSCI));
 595                 }
 596         }
 597 }
 598
 599 /*
 600  * access to AC97 for Ali5455
 601  */
 602 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
 603 {
 604         int count = 0;
 605         for (count = 0; count < 0x7f; count++) {
 606                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 607                 if (val & mask)
 608                         return 0;
 609         }
 610         if (! chip->in_ac97_init)
 611                 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
 612         return -EBUSY;
 613 }
 614
 615 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
 616 {
 617         int time = 100;
 618         if (chip->buggy_semaphore)
 619                 return 0; /* just ignore ... */
 620         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 621                 udelay(1);
 622         if (! time && ! chip->in_ac97_init)
 623                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
 624         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 625 }
 626
 627 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 628 {
 629         struct intel8x0 *chip = ac97->private_data;
 630         unsigned short data = 0xffff;
 631
 632         if (snd_intel8x0_ali_codec_semaphore(chip))
 633                 goto __err;
 634         reg |= ALI_CPR_ADDR_READ;
 635         if (ac97->num)
 636                 reg |= ALI_CPR_ADDR_SECONDARY;
 637         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 638         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 639                 goto __err;
 640         data = igetword(chip, ICHREG(ALI_SPR));
 641  __err:
 642         return data;
 643 }
 644
 645 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 646                                          unsigned short val)
 647 {
 648         struct intel8x0 *chip = ac97->private_data;
 649
 650         if (snd_intel8x0_ali_codec_semaphore(chip))
 651                 return;
 652         iputword(chip, ICHREG(ALI_CPR), val);
 653         if (ac97->num)
 654                 reg |= ALI_CPR_ADDR_SECONDARY;
 655         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 656         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 657 }
 658
 659
 660 /*
 661  * DMA I/O
 662  */
 663 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
 664 {
 665         int idx;
 666         u32 *bdbar = ichdev->bdbar;
 667         unsigned long port = ichdev->reg_offset;
 668
 669         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 670         if (ichdev->size == ichdev->fragsize) {
 671                 ichdev->ack_reload = ichdev->ack = 2;
 672                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 673                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 674                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 675                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 676                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 677                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 678                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 679                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 680                 }
 681                 ichdev->frags = 2;
 682         } else {
 683                 ichdev->ack_reload = ichdev->ack = 1;
 684                 ichdev->fragsize1 = ichdev->fragsize;
 685                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 686                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
 687                                                      (((idx >> 1) * ichdev->fragsize) %
 688                                                       ichdev->size));
 689                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 690                                                      ichdev->fragsize >> ichdev->pos_shift);
 691 #if 0
 692                         printk("bdbar[%i] = 0x%x [0x%x]\n",
 693                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 694 #endif
 695                 }
 696                 ichdev->frags = ichdev->size / ichdev->fragsize;
 697         }
 698         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 699         ichdev->civ = 0;
 700         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 701         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 702         ichdev->position = 0;
 703 #if 0
 704         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 705                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 706 #endif
 707         /* clear interrupts */
 708         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 709 }
 710
 711 #ifdef __i386__
 712 /*
 713  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
 714  * which aborts PCI busmaster for audio transfer.  A workaround is to set
 715  * the pages as non-cached.  For details, see the errata in
 716  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
 717  */
 718 static void fill_nocache(void *buf, int size, int nocache)
 719 {
 720         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 721         if (nocache)
 722                 set_pages_uc(virt_to_page(buf), size);
 723         else
 724                 set_pages_wb(virt_to_page(buf), size);
 725 }
 726 #else
 727 #define fill_nocache(buf, size, nocache) do { ; } while (0)
 728 #endif
 729
 730 /*
 731  *  Interrupt handler
 732  */
 733
 734 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
 735 {
 736         unsigned long port = ichdev->reg_offset;
 737         unsigned long flags;
 738         int status, civ, i, step;
 739         int ack = 0;
 740
 741         spin_lock_irqsave(&chip->reg_lock, flags);
 742         status = igetbyte(chip, port + ichdev->roff_sr);
 743         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 744         if (!(status & ICH_BCIS)) {
 745                 step = 0;
 746         } else if (civ == ichdev->civ) {
 747                 // snd_printd("civ same %d\n", civ);
 748                 step = 1;
 749                 ichdev->civ++;
 750                 ichdev->civ &= ICH_REG_LVI_MASK;
 751         } else {
 752                 step = civ - ichdev->civ;
 753                 if (step < 0)
 754                         step += ICH_REG_LVI_MASK + 1;
 755                 // if (step != 1)
 756                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 757                 ichdev->civ = civ;
 758         }
 759
 760         ichdev->position += step * ichdev->fragsize1;
 761         if (! chip->in_measurement)
 762                 ichdev->position %= ichdev->size;
 763         ichdev->lvi += step;
 764         ichdev->lvi &= ICH_REG_LVI_MASK;
 765         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 766         for (i = 0; i < step; i++) {
 767                 ichdev->lvi_frag++;
 768                 ichdev->lvi_frag %= ichdev->frags;
 769                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 770 #if 0
 771         printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
 772                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
 773                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
 774                inl(port + 4), inb(port + ICH_REG_OFF_CR));
 775 #endif
 776                 if (--ichdev->ack == 0) {
 777                         ichdev->ack = ichdev->ack_reload;
 778                         ack = 1;
 779                 }
 780         }
 781         spin_unlock_irqrestore(&chip->reg_lock, flags);
 782         if (ack && ichdev->substream) {
 783                 snd_pcm_period_elapsed(ichdev->substream);
 784         }
 785         iputbyte(chip, port + ichdev->roff_sr,
 786                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 787 }
 788
 789 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
 790 {
 791         struct intel8x0 *chip = dev_id;
 792         struct ichdev *ichdev;
 793         unsigned int status;
 794         unsigned int i;
 795
 796         status = igetdword(chip, chip->int_sta_reg);
 797         if (status == 0xffffffff)       /* we are not yet resumed */
 798                 return IRQ_NONE;
 799
 800         if ((status & chip->int_sta_mask) == 0) {
 801                 if (status) {
 802                         /* ack */
 803                         iputdword(chip, chip->int_sta_reg, status);
 804                         if (! chip->buggy_irq)
 805                                 status = 0;
 806                 }
 807                 return IRQ_RETVAL(status);
 808         }
 809
 810         for (i = 0; i < chip->bdbars_count; i++) {
 811                 ichdev = &chip->ichd[i];
 812                 if (status & ichdev->int_sta_mask)
 813                         snd_intel8x0_update(chip, ichdev);
 814         }
 815
 816         /* ack them */
 817         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 818
 819         return IRQ_HANDLED;
 820 }
 821
 822 /*
 823  *  PCM part
 824  */
 825
 826 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 827 {
 828         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 829         struct ichdev *ichdev = get_ichdev(substream);
 830         unsigned char val = 0;
 831         unsigned long port = ichdev->reg_offset;
 832
 833         switch (cmd) {
 834         case SNDRV_PCM_TRIGGER_RESUME:
 835                 ichdev->suspended = 0;
 836                 /* fallthru */
 837         case SNDRV_PCM_TRIGGER_START:
 838                 val = ICH_IOCE | ICH_STARTBM;
 839                 break;
 840         case SNDRV_PCM_TRIGGER_SUSPEND:
 841                 ichdev->suspended = 1;
 842                 /* fallthru */
 843         case SNDRV_PCM_TRIGGER_STOP:
 844                 val = 0;
 845                 break;
 846         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 847                 val = ICH_IOCE;
 848                 break;
 849         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 850                 val = ICH_IOCE | ICH_STARTBM;
 851                 break;
 852         default:
 853                 return -EINVAL;
 854         }
 855         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 856         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 857                 /* wait until DMA stopped */
 858                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 859                 /* reset whole DMA things */
 860                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 861         }
 862         return 0;
 863 }
 864
 865 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
 866 {
 867         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 868         struct ichdev *ichdev = get_ichdev(substream);
 869         unsigned long port = ichdev->reg_offset;
 870         static int fiforeg[] = {
 871                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
 872         };
 873         unsigned int val, fifo;
 874
 875         val = igetdword(chip, ICHREG(ALI_DMACR));
 876         switch (cmd) {
 877         case SNDRV_PCM_TRIGGER_RESUME:
 878                 ichdev->suspended = 0;
 879                 /* fallthru */
 880         case SNDRV_PCM_TRIGGER_START:
 881         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 882                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 883                         /* clear FIFO for synchronization of channels */
 884                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 885                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 886                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 887                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 888                 }
 889                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 890                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 891                 /* start DMA */
 892                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
 893                 break;
 894         case SNDRV_PCM_TRIGGER_SUSPEND:
 895                 ichdev->suspended = 1;
 896                 /* fallthru */
 897         case SNDRV_PCM_TRIGGER_STOP:
 898         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 899                 /* pause */
 900                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
 901                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 902                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 903                         ;
 904                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 905                         break;
 906                 /* reset whole DMA things */
 907                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 908                 /* clear interrupts */
 909                 iputbyte(chip, port + ICH_REG_OFF_SR,
 910                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 911                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 912                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 913                 break;
 914         default:
 915                 return -EINVAL;
 916         }
 917         return 0;
 918 }
 919
 920 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
 921                                   struct snd_pcm_hw_params *hw_params)
 922 {
 923         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 924         struct ichdev *ichdev = get_ichdev(substream);
 925         struct snd_pcm_runtime *runtime = substream->runtime;
 926         int dbl = params_rate(hw_params) > 48000;
 927         int err;
 928
 929         if (chip->fix_nocache && ichdev->page_attr_changed) {
 930                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
 931                 ichdev->page_attr_changed = 0;
 932         }
 933         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 934         if (err < 0)
 935                 return err;
 936         if (chip->fix_nocache) {
 937                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
 938                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
 939                         ichdev->page_attr_changed = 1;
 940                 }
 941         }
 942         if (ichdev->pcm_open_flag) {
 943                 snd_ac97_pcm_close(ichdev->pcm);
 944                 ichdev->pcm_open_flag = 0;
 945         }
 946         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 947                                 params_channels(hw_params),
 948                                 ichdev->pcm->r[dbl].slots);
 949         if (err >= 0) {
 950                 ichdev->pcm_open_flag = 1;
 951                 /* Force SPDIF setting */
 952                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 953                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
 954                                           params_rate(hw_params));
 955         }
 956         return err;
 957 }
 958
 959 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
 960 {
 961         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 962         struct ichdev *ichdev = get_ichdev(substream);
 963
 964         if (ichdev->pcm_open_flag) {
 965                 snd_ac97_pcm_close(ichdev->pcm);
 966                 ichdev->pcm_open_flag = 0;
 967         }
 968         if (chip->fix_nocache && ichdev->page_attr_changed) {
 969                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
 970                 ichdev->page_attr_changed = 0;
 971         }
 972         return snd_pcm_lib_free_pages(substream);
 973 }
 974
 975 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
 976                                        struct snd_pcm_runtime *runtime)
 977 {
 978         unsigned int cnt;
 979         int dbl = runtime->rate > 48000;
 980
 981         spin_lock_irq(&chip->reg_lock);
 982         switch (chip->device_type) {
 983         case DEVICE_ALI:
 984                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 985                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 986                 if (runtime->channels == 4 || dbl)
 987                         cnt |= ICH_ALI_SC_PCM_4;
 988                 else if (runtime->channels == 6)
 989                         cnt |= ICH_ALI_SC_PCM_6;
 990                 iputdword(chip, ICHREG(ALI_SCR), cnt);
 991                 break;
 992         case DEVICE_SIS:
 993                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 994                 cnt &= ~ICH_SIS_PCM_246_MASK;
 995                 if (runtime->channels == 4 || dbl)
 996                         cnt |= ICH_SIS_PCM_4;
 997                 else if (runtime->channels == 6)
 998                         cnt |= ICH_SIS_PCM_6;
 999                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1000                 break;
1001         default:
1002                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1003                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1004                 if (runtime->channels == 4 || dbl)
1005                         cnt |= ICH_PCM_4;
1006                 else if (runtime->channels == 6)
1007                         cnt |= ICH_PCM_6;
1008                 else if (runtime->channels == 8)
1009                         cnt |= ICH_PCM_8;
1010                 if (chip->device_type == DEVICE_NFORCE) {
1011                         /* reset to 2ch once to keep the 6 channel data in alignment,
1012                          * to start from Front Left always
1013                          */
1014                         if (cnt & ICH_PCM_246_MASK) {
1015                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1016                                 spin_unlock_irq(&chip->reg_lock);
1017                                 msleep(50); /* grrr... */
1018                                 spin_lock_irq(&chip->reg_lock);
1019                         }
1020                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1021                         if (runtime->sample_bits > 16)
1022                                 cnt |= ICH_PCM_20BIT;
1023                 }
1024                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1025                 break;
1026         }
1027         spin_unlock_irq(&chip->reg_lock);
1028 }
1029
1030 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1031 {
1032         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1033         struct snd_pcm_runtime *runtime = substream->runtime;
1034         struct ichdev *ichdev = get_ichdev(substream);
1035
1036         ichdev->physbuf = runtime->dma_addr;
1037         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1038         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1039         if (ichdev->ichd == ICHD_PCMOUT) {
1040                 snd_intel8x0_setup_pcm_out(chip, runtime);
1041                 if (chip->device_type == DEVICE_INTEL_ICH4)
1042                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1043         }
1044         snd_intel8x0_setup_periods(chip, ichdev);
1045         return 0;
1046 }
1047
1048 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1049 {
1050         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1051         struct ichdev *ichdev = get_ichdev(substream);
1052         size_t ptr1, ptr;
1053         int civ, timeout = 100;
1054         unsigned int position;
1055
1056         spin_lock(&chip->reg_lock);
1057         do {
1058                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1059                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1060                 position = ichdev->position;
1061                 if (ptr1 == 0) {
1062                         udelay(10);
1063                         continue;
1064                 }
1065                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1066                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1067                         break;
1068         } while (timeout--);
1069         ptr1 <<= ichdev->pos_shift;
1070         ptr = ichdev->fragsize1 - ptr1;
1071         ptr += position;
1072         spin_unlock(&chip->reg_lock);
1073         if (ptr >= ichdev->size)
1074                 return 0;
1075         return bytes_to_frames(substream->runtime, ptr);
1076 }
1077
1078 static struct snd_pcm_hardware snd_intel8x0_stream =
1079 {
1080         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1081                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1082                                  SNDRV_PCM_INFO_MMAP_VALID |
1083                                  SNDRV_PCM_INFO_PAUSE |
1084                                  SNDRV_PCM_INFO_RESUME),
1085         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1086         .rates =                SNDRV_PCM_RATE_48000,
1087         .rate_min =             48000,
1088         .rate_max =             48000,
1089         .channels_min =         2,
1090         .channels_max =         2,
1091         .buffer_bytes_max =     128 * 1024,
1092         .period_bytes_min =     32,
1093         .period_bytes_max =     128 * 1024,
1094         .periods_min =          1,
1095         .periods_max =          1024,
1096         .fifo_size =            0,
1097 };
1098
1099 static unsigned int channels4[] = {
1100         2, 4,
1101 };
1102
1103 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1104         .count = ARRAY_SIZE(channels4),
1105         .list = channels4,
1106         .mask = 0,
1107 };
1108
1109 static unsigned int channels6[] = {
1110         2, 4, 6,
1111 };
1112
1113 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1114         .count = ARRAY_SIZE(channels6),
1115         .list = channels6,
1116         .mask = 0,
1117 };
1118
1119 static unsigned int channels8[] = {
1120         2, 4, 6, 8,
1121 };
1122
1123 static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1124         .count = ARRAY_SIZE(channels8),
1125         .list = channels8,
1126         .mask = 0,
1127 };
1128
1129 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1130 {
1131         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1132         struct snd_pcm_runtime *runtime = substream->runtime;
1133         int err;
1134
1135         ichdev->substream = substream;
1136         runtime->hw = snd_intel8x0_stream;
1137         runtime->hw.rates = ichdev->pcm->rates;
1138         snd_pcm_limit_hw_rates(runtime);
1139         if (chip->device_type == DEVICE_SIS) {
1140                 runtime->hw.buffer_bytes_max = 64*1024;
1141                 runtime->hw.period_bytes_max = 64*1024;
1142         }
1143         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1144                 return err;
1145         runtime->private_data = ichdev;
1146         return 0;
1147 }
1148
1149 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1150 {
1151         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1152         struct snd_pcm_runtime *runtime = substream->runtime;
1153         int err;
1154
1155         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1156         if (err < 0)
1157                 return err;
1158
1159         if (chip->multi8) {
1160                 runtime->hw.channels_max = 8;
1161                 snd_pcm_hw_constraint_list(runtime, 0,
1162                                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1163                                                 &hw_constraints_channels8);
1164         } else if (chip->multi6) {
1165                 runtime->hw.channels_max = 6;
1166                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1167                                            &hw_constraints_channels6);
1168         } else if (chip->multi4) {
1169                 runtime->hw.channels_max = 4;
1170                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1171                                            &hw_constraints_channels4);
1172         }
1173         if (chip->dra) {
1174                 snd_ac97_pcm_double_rate_rules(runtime);
1175         }
1176         if (chip->smp20bit) {
1177                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1178                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1179         }
1180         return 0;
1181 }
1182
1183 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1184 {
1185         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1186
1187         chip->ichd[ICHD_PCMOUT].substream = NULL;
1188         return 0;
1189 }
1190
1191 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1192 {
1193         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1194
1195         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1196 }
1197
1198 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1199 {
1200         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1201
1202         chip->ichd[ICHD_PCMIN].substream = NULL;
1203         return 0;
1204 }
1205
1206 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1207 {
1208         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1209
1210         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1211 }
1212
1213 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1214 {
1215         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1216
1217         chip->ichd[ICHD_MIC].substream = NULL;
1218         return 0;
1219 }
1220
1221 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1222 {
1223         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1224
1225         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1226 }
1227
1228 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1229 {
1230         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1231
1232         chip->ichd[ICHD_MIC2].substream = NULL;
1233         return 0;
1234 }
1235
1236 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1237 {
1238         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1239
1240         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1241 }
1242
1243 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1244 {
1245         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1246
1247         chip->ichd[ICHD_PCM2IN].substream = NULL;
1248         return 0;
1249 }
1250
1251 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1252 {
1253         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1254         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1255
1256         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1257 }
1258
1259 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1260 {
1261         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1262         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1263
1264         chip->ichd[idx].substream = NULL;
1265         return 0;
1266 }
1267
1268 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1269 {
1270         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1271         unsigned int val;
1272
1273         spin_lock_irq(&chip->reg_lock);
1274         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1275         val |= ICH_ALI_IF_AC97SP;
1276         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1277         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1278         spin_unlock_irq(&chip->reg_lock);
1279
1280         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1281 }
1282
1283 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1284 {
1285         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1286         unsigned int val;
1287
1288         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1289         spin_lock_irq(&chip->reg_lock);
1290         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1291         val &= ~ICH_ALI_IF_AC97SP;
1292         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1293         spin_unlock_irq(&chip->reg_lock);
1294
1295         return 0;
1296 }
1297
1298 #if 0 // NYI
1299 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1300 {
1301         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1302
1303         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1304 }
1305
1306 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1307 {
1308         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1309
1310         chip->ichd[ALID_SPDIFIN].substream = NULL;
1311         return 0;
1312 }
1313
1314 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1315 {
1316         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1317
1318         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1319 }
1320
1321 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1322 {
1323         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1324
1325         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1326         return 0;
1327 }
1328 #endif
1329
1330 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1331         .open =         snd_intel8x0_playback_open,
1332         .close =        snd_intel8x0_playback_close,
1333         .ioctl =        snd_pcm_lib_ioctl,
1334         .hw_params =    snd_intel8x0_hw_params,
1335         .hw_free =      snd_intel8x0_hw_free,
1336         .prepare =      snd_intel8x0_pcm_prepare,
1337         .trigger =      snd_intel8x0_pcm_trigger,
1338         .pointer =      snd_intel8x0_pcm_pointer,
1339 };
1340
1341 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1342         .open =         snd_intel8x0_capture_open,
1343         .close =        snd_intel8x0_capture_close,
1344         .ioctl =        snd_pcm_lib_ioctl,
1345         .hw_params =    snd_intel8x0_hw_params,
1346         .hw_free =      snd_intel8x0_hw_free,
1347         .prepare =      snd_intel8x0_pcm_prepare,
1348         .trigger =      snd_intel8x0_pcm_trigger,
1349         .pointer =      snd_intel8x0_pcm_pointer,
1350 };
1351
1352 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1353         .open =         snd_intel8x0_mic_open,
1354         .close =        snd_intel8x0_mic_close,
1355         .ioctl =        snd_pcm_lib_ioctl,
1356         .hw_params =    snd_intel8x0_hw_params,
1357         .hw_free =      snd_intel8x0_hw_free,
1358         .prepare =      snd_intel8x0_pcm_prepare,
1359         .trigger =      snd_intel8x0_pcm_trigger,
1360         .pointer =      snd_intel8x0_pcm_pointer,
1361 };
1362
1363 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1364         .open =         snd_intel8x0_mic2_open,
1365         .close =        snd_intel8x0_mic2_close,
1366         .ioctl =        snd_pcm_lib_ioctl,
1367         .hw_params =    snd_intel8x0_hw_params,
1368         .hw_free =      snd_intel8x0_hw_free,
1369         .prepare =      snd_intel8x0_pcm_prepare,
1370         .trigger =      snd_intel8x0_pcm_trigger,
1371         .pointer =      snd_intel8x0_pcm_pointer,
1372 };
1373
1374 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1375         .open =         snd_intel8x0_capture2_open,
1376         .close =        snd_intel8x0_capture2_close,
1377         .ioctl =        snd_pcm_lib_ioctl,
1378         .hw_params =    snd_intel8x0_hw_params,
1379         .hw_free =      snd_intel8x0_hw_free,
1380         .prepare =      snd_intel8x0_pcm_prepare,
1381         .trigger =      snd_intel8x0_pcm_trigger,
1382         .pointer =      snd_intel8x0_pcm_pointer,
1383 };
1384
1385 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1386         .open =         snd_intel8x0_spdif_open,
1387         .close =        snd_intel8x0_spdif_close,
1388         .ioctl =        snd_pcm_lib_ioctl,
1389         .hw_params =    snd_intel8x0_hw_params,
1390         .hw_free =      snd_intel8x0_hw_free,
1391         .prepare =      snd_intel8x0_pcm_prepare,
1392         .trigger =      snd_intel8x0_pcm_trigger,
1393         .pointer =      snd_intel8x0_pcm_pointer,
1394 };
1395
1396 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1397         .open =         snd_intel8x0_playback_open,
1398         .close =        snd_intel8x0_playback_close,
1399         .ioctl =        snd_pcm_lib_ioctl,
1400         .hw_params =    snd_intel8x0_hw_params,
1401         .hw_free =      snd_intel8x0_hw_free,
1402         .prepare =      snd_intel8x0_pcm_prepare,
1403         .trigger =      snd_intel8x0_ali_trigger,
1404         .pointer =      snd_intel8x0_pcm_pointer,
1405 };
1406
1407 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1408         .open =         snd_intel8x0_capture_open,
1409         .close =        snd_intel8x0_capture_close,
1410         .ioctl =        snd_pcm_lib_ioctl,
1411         .hw_params =    snd_intel8x0_hw_params,
1412         .hw_free =      snd_intel8x0_hw_free,
1413         .prepare =      snd_intel8x0_pcm_prepare,
1414         .trigger =      snd_intel8x0_ali_trigger,
1415         .pointer =      snd_intel8x0_pcm_pointer,
1416 };
1417
1418 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1419         .open =         snd_intel8x0_mic_open,
1420         .close =        snd_intel8x0_mic_close,
1421         .ioctl =        snd_pcm_lib_ioctl,
1422         .hw_params =    snd_intel8x0_hw_params,
1423         .hw_free =      snd_intel8x0_hw_free,
1424         .prepare =      snd_intel8x0_pcm_prepare,
1425         .trigger =      snd_intel8x0_ali_trigger,
1426         .pointer =      snd_intel8x0_pcm_pointer,
1427 };
1428
1429 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1430         .open =         snd_intel8x0_ali_ac97spdifout_open,
1431         .close =        snd_intel8x0_ali_ac97spdifout_close,
1432         .ioctl =        snd_pcm_lib_ioctl,
1433         .hw_params =    snd_intel8x0_hw_params,
1434         .hw_free =      snd_intel8x0_hw_free,
1435         .prepare =      snd_intel8x0_pcm_prepare,
1436         .trigger =      snd_intel8x0_ali_trigger,
1437         .pointer =      snd_intel8x0_pcm_pointer,
1438 };
1439
1440 #if 0 // NYI
1441 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1442         .open =         snd_intel8x0_ali_spdifin_open,
1443         .close =        snd_intel8x0_ali_spdifin_close,
1444         .ioctl =        snd_pcm_lib_ioctl,
1445         .hw_params =    snd_intel8x0_hw_params,
1446         .hw_free =      snd_intel8x0_hw_free,
1447         .prepare =      snd_intel8x0_pcm_prepare,
1448         .trigger =      snd_intel8x0_pcm_trigger,
1449         .pointer =      snd_intel8x0_pcm_pointer,
1450 };
1451
1452 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1453         .open =         snd_intel8x0_ali_spdifout_open,
1454         .close =        snd_intel8x0_ali_spdifout_close,
1455         .ioctl =        snd_pcm_lib_ioctl,
1456         .hw_params =    snd_intel8x0_hw_params,
1457         .hw_free =      snd_intel8x0_hw_free,
1458         .prepare =      snd_intel8x0_pcm_prepare,
1459         .trigger =      snd_intel8x0_pcm_trigger,
1460         .pointer =      snd_intel8x0_pcm_pointer,
1461 };
1462 #endif // NYI
1463
1464 struct ich_pcm_table {
1465         char *suffix;
1466         struct snd_pcm_ops *playback_ops;
1467         struct snd_pcm_ops *capture_ops;
1468         size_t prealloc_size;
1469         size_t prealloc_max_size;
1470         int ac97_idx;
1471 };
1472
1473 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1474                                        struct ich_pcm_table *rec)
1475 {
1476         struct snd_pcm *pcm;
1477         int err;
1478         char name[32];
1479
1480         if (rec->suffix)
1481                 sprintf(name, "Intel ICH - %s", rec->suffix);
1482         else
1483                 strcpy(name, "Intel ICH");
1484         err = snd_pcm_new(chip->card, name, device,
1485                           rec->playback_ops ? 1 : 0,
1486                           rec->capture_ops ? 1 : 0, &pcm);
1487         if (err < 0)
1488                 return err;
1489
1490         if (rec->playback_ops)
1491                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1492         if (rec->capture_ops)
1493                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1494
1495         pcm->private_data = chip;
1496         pcm->info_flags = 0;
1497         if (rec->suffix)
1498                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1499         else
1500                 strcpy(pcm->name, chip->card->shortname);
1501         chip->pcm[device] = pcm;
1502
1503         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1504                                               snd_dma_pci_data(chip->pci),
1505                                               rec->prealloc_size, rec->prealloc_max_size);
1506
1507         return 0;
1508 }
1509
1510 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1511         {
1512                 .playback_ops = &snd_intel8x0_playback_ops,
1513                 .capture_ops = &snd_intel8x0_capture_ops,
1514                 .prealloc_size = 64 * 1024,
1515                 .prealloc_max_size = 128 * 1024,
1516         },
1517         {
1518                 .suffix = "MIC ADC",
1519                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1520                 .prealloc_size = 0,
1521                 .prealloc_max_size = 128 * 1024,
1522                 .ac97_idx = ICHD_MIC,
1523         },
1524         {
1525                 .suffix = "MIC2 ADC",
1526                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1527                 .prealloc_size = 0,
1528                 .prealloc_max_size = 128 * 1024,
1529                 .ac97_idx = ICHD_MIC2,
1530         },
1531         {
1532                 .suffix = "ADC2",
1533                 .capture_ops = &snd_intel8x0_capture2_ops,
1534                 .prealloc_size = 0,
1535                 .prealloc_max_size = 128 * 1024,
1536                 .ac97_idx = ICHD_PCM2IN,
1537         },
1538         {
1539                 .suffix = "IEC958",
1540                 .playback_ops = &snd_intel8x0_spdif_ops,
1541                 .prealloc_size = 64 * 1024,
1542                 .prealloc_max_size = 128 * 1024,
1543                 .ac97_idx = ICHD_SPBAR,
1544         },
1545 };
1546
1547 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1548         {
1549                 .playback_ops = &snd_intel8x0_playback_ops,
1550                 .capture_ops = &snd_intel8x0_capture_ops,
1551                 .prealloc_size = 64 * 1024,
1552                 .prealloc_max_size = 128 * 1024,
1553         },
1554         {
1555                 .suffix = "MIC ADC",
1556                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1557                 .prealloc_size = 0,
1558                 .prealloc_max_size = 128 * 1024,
1559                 .ac97_idx = NVD_MIC,
1560         },
1561         {
1562                 .suffix = "IEC958",
1563                 .playback_ops = &snd_intel8x0_spdif_ops,
1564                 .prealloc_size = 64 * 1024,
1565                 .prealloc_max_size = 128 * 1024,
1566                 .ac97_idx = NVD_SPBAR,
1567         },
1568 };
1569
1570 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1571         {
1572                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1573                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1574                 .prealloc_size = 64 * 1024,
1575                 .prealloc_max_size = 128 * 1024,
1576         },
1577         {
1578                 .suffix = "MIC ADC",
1579                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1580                 .prealloc_size = 0,
1581                 .prealloc_max_size = 128 * 1024,
1582                 .ac97_idx = ALID_MIC,
1583         },
1584         {
1585                 .suffix = "IEC958",
1586                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1587                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1588                 .prealloc_size = 64 * 1024,
1589                 .prealloc_max_size = 128 * 1024,
1590                 .ac97_idx = ALID_AC97SPDIFOUT,
1591         },
1592 #if 0 // NYI
1593         {
1594                 .suffix = "HW IEC958",
1595                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1596                 .prealloc_size = 64 * 1024,
1597                 .prealloc_max_size = 128 * 1024,
1598         },
1599 #endif
1600 };
1601
1602 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1603 {
1604         int i, tblsize, device, err;
1605         struct ich_pcm_table *tbl, *rec;
1606
1607         switch (chip->device_type) {
1608         case DEVICE_INTEL_ICH4:
1609                 tbl = intel_pcms;
1610                 tblsize = ARRAY_SIZE(intel_pcms);
1611                 if (spdif_aclink)
1612                         tblsize--;
1613                 break;
1614         case DEVICE_NFORCE:
1615                 tbl = nforce_pcms;
1616                 tblsize = ARRAY_SIZE(nforce_pcms);
1617                 if (spdif_aclink)
1618                         tblsize--;
1619                 break;
1620         case DEVICE_ALI:
1621                 tbl = ali_pcms;
1622                 tblsize = ARRAY_SIZE(ali_pcms);
1623                 break;
1624         default:
1625                 tbl = intel_pcms;
1626                 tblsize = 2;
1627                 break;
1628         }
1629
1630         device = 0;
1631         for (i = 0; i < tblsize; i++) {
1632                 rec = tbl + i;
1633                 if (i > 0 && rec->ac97_idx) {
1634                         /* activate PCM only when associated AC'97 codec */
1635                         if (! chip->ichd[rec->ac97_idx].pcm)
1636                                 continue;
1637                 }
1638                 err = snd_intel8x0_pcm1(chip, device, rec);
1639                 if (err < 0)
1640                         return err;
1641                 device++;
1642         }
1643
1644         chip->pcm_devs = device;
1645         return 0;
1646 }
1647
1648
1649 /*
1650  *  Mixer part
1651  */
1652
1653 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1654 {
1655         struct intel8x0 *chip = bus->private_data;
1656         chip->ac97_bus = NULL;
1657 }
1658
1659 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1660 {
1661         struct intel8x0 *chip = ac97->private_data;
1662         chip->ac97[ac97->num] = NULL;
1663 }
1664
1665 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1666         /* front PCM */
1667         {
1668                 .exclusive = 1,
1669                 .r = {  {
1670                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1671                                          (1 << AC97_SLOT_PCM_RIGHT) |
1672                                          (1 << AC97_SLOT_PCM_CENTER) |
1673                                          (1 << AC97_SLOT_PCM_SLEFT) |
1674                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1675                                          (1 << AC97_SLOT_LFE)
1676                         },
1677                         {
1678                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1679                                          (1 << AC97_SLOT_PCM_RIGHT) |
1680                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1681                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1682                         }
1683                 }
1684         },
1685         /* PCM IN #1 */
1686         {
1687                 .stream = 1,
1688                 .exclusive = 1,
1689                 .r = {  {
1690                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1691                                          (1 << AC97_SLOT_PCM_RIGHT)
1692                         }
1693                 }
1694         },
1695         /* MIC IN #1 */
1696         {
1697                 .stream = 1,
1698                 .exclusive = 1,
1699                 .r = {  {
1700                                 .slots = (1 << AC97_SLOT_MIC)
1701                         }
1702                 }
1703         },
1704         /* S/PDIF PCM */
1705         {
1706                 .exclusive = 1,
1707                 .spdif = 1,
1708                 .r = {  {
1709                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1710                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1711                         }
1712                 }
1713         },
1714         /* PCM IN #2 */
1715         {
1716                 .stream = 1,
1717                 .exclusive = 1,
1718                 .r = {  {
1719                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1720                                          (1 << AC97_SLOT_PCM_RIGHT)
1721                         }
1722                 }
1723         },
1724         /* MIC IN #2 */
1725         {
1726                 .stream = 1,
1727                 .exclusive = 1,
1728                 .r = {  {
1729                                 .slots = (1 << AC97_SLOT_MIC)
1730                         }
1731                 }
1732         },
1733 };
1734
1735 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1736         {
1737                 .subvendor = 0x0e11,
1738                 .subdevice = 0x000e,
1739                 .name = "Compaq Deskpro EN",    /* AD1885 */
1740                 .type = AC97_TUNE_HP_ONLY
1741         },
1742         {
1743                 .subvendor = 0x0e11,
1744                 .subdevice = 0x008a,
1745                 .name = "Compaq Evo W4000",     /* AD1885 */
1746                 .type = AC97_TUNE_HP_ONLY
1747         },
1748         {
1749                 .subvendor = 0x0e11,
1750                 .subdevice = 0x00b8,
1751                 .name = "Compaq Evo D510C",
1752                 .type = AC97_TUNE_HP_ONLY
1753         },
1754         {
1755                 .subvendor = 0x0e11,
1756                 .subdevice = 0x0860,
1757                 .name = "HP/Compaq nx7010",
1758                 .type = AC97_TUNE_MUTE_LED
1759         },
1760         {
1761                 .subvendor = 0x1014,
1762                 .subdevice = 0x1f00,
1763                 .name = "MS-9128",
1764                 .type = AC97_TUNE_ALC_JACK
1765         },
1766         {
1767                 .subvendor = 0x1014,
1768                 .subdevice = 0x0267,
1769                 .name = "IBM NetVista A30p",    /* AD1981B */
1770                 .type = AC97_TUNE_HP_ONLY
1771         },
1772         {
1773                 .subvendor = 0x1025,
1774                 .subdevice = 0x0082,
1775                 .name = "Acer Travelmate 2310",
1776                 .type = AC97_TUNE_HP_ONLY
1777         },
1778         {
1779                 .subvendor = 0x1025,
1780                 .subdevice = 0x0083,
1781                 .name = "Acer Aspire 3003LCi",
1782                 .type = AC97_TUNE_HP_ONLY
1783         },
1784         {
1785                 .subvendor = 0x1028,
1786                 .subdevice = 0x00d8,
1787                 .name = "Dell Precision 530",   /* AD1885 */
1788                 .type = AC97_TUNE_HP_ONLY
1789         },
1790         {
1791                 .subvendor = 0x1028,
1792                 .subdevice = 0x010d,
1793                 .name = "Dell", /* which model?  AD1885 */
1794                 .type = AC97_TUNE_HP_ONLY
1795         },
1796         {
1797                 .subvendor = 0x1028,
1798                 .subdevice = 0x0126,
1799                 .name = "Dell Optiplex GX260",  /* AD1981A */
1800                 .type = AC97_TUNE_HP_ONLY
1801         },
1802         {
1803                 .subvendor = 0x1028,
1804                 .subdevice = 0x012c,
1805                 .name = "Dell Precision 650",   /* AD1981A */
1806                 .type = AC97_TUNE_HP_ONLY
1807         },
1808         {
1809                 .subvendor = 0x1028,
1810                 .subdevice = 0x012d,
1811                 .name = "Dell Precision 450",   /* AD1981B*/
1812                 .type = AC97_TUNE_HP_ONLY
1813         },
1814         {
1815                 .subvendor = 0x1028,
1816                 .subdevice = 0x0147,
1817                 .name = "Dell", /* which model?  AD1981B*/
1818                 .type = AC97_TUNE_HP_ONLY
1819         },
1820         {
1821                 .subvendor = 0x1028,
1822                 .subdevice = 0x0151,
1823                 .name = "Dell Optiplex GX270",  /* AD1981B */
1824                 .type = AC97_TUNE_HP_ONLY
1825         },
1826         {
1827                 .subvendor = 0x1028,
1828                 .subdevice = 0x014e,
1829                 .name = "Dell D800", /* STAC9750/51 */
1830                 .type = AC97_TUNE_HP_ONLY
1831         },
1832         {
1833                 .subvendor = 0x1028,
1834                 .subdevice = 0x0163,
1835                 .name = "Dell Unknown", /* STAC9750/51 */
1836                 .type = AC97_TUNE_HP_ONLY
1837         },
1838         {
1839                 .subvendor = 0x1028,
1840                 .subdevice = 0x0186,
1841                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1842                 .type = AC97_TUNE_HP_MUTE_LED
1843         },
1844         {
1845                 .subvendor = 0x1028,
1846                 .subdevice = 0x0188,
1847                 .name = "Dell Inspiron 6000",
1848                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1849         },
1850         {
1851                 .subvendor = 0x1028,
1852                 .subdevice = 0x0191,
1853                 .name = "Dell Inspiron 8600",
1854                 .type = AC97_TUNE_HP_ONLY
1855         },
1856         {
1857                 .subvendor = 0x103c,
1858                 .subdevice = 0x006d,
1859                 .name = "HP zv5000",
1860                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1861         },
1862         {       /* FIXME: which codec? */
1863                 .subvendor = 0x103c,
1864                 .subdevice = 0x00c3,
1865                 .name = "HP xw6000",
1866                 .type = AC97_TUNE_HP_ONLY
1867         },
1868         {
1869                 .subvendor = 0x103c,
1870                 .subdevice = 0x088c,
1871                 .name = "HP nc8000",
1872                 .type = AC97_TUNE_HP_MUTE_LED
1873         },
1874         {
1875                 .subvendor = 0x103c,
1876                 .subdevice = 0x0890,
1877                 .name = "HP nc6000",
1878                 .type = AC97_TUNE_MUTE_LED
1879         },
1880         {
1881                 .subvendor = 0x103c,
1882                 .subdevice = 0x0934,
1883                 .name = "HP nx8220",
1884                 .type = AC97_TUNE_MUTE_LED
1885         },
1886         {
1887                 .subvendor = 0x103c,
1888                 .subdevice = 0x129d,
1889                 .name = "HP xw8000",
1890                 .type = AC97_TUNE_HP_ONLY
1891         },
1892         {
1893                 .subvendor = 0x103c,
1894                 .subdevice = 0x0938,
1895                 .name = "HP nc4200",
1896                 .type = AC97_TUNE_HP_MUTE_LED
1897         },
1898         {
1899                 .subvendor = 0x103c,
1900                 .subdevice = 0x099c,
1901                 .name = "HP nx6110/nc6120",
1902                 .type = AC97_TUNE_HP_MUTE_LED
1903         },
1904         {
1905                 .subvendor = 0x103c,
1906                 .subdevice = 0x0944,
1907                 .name = "HP nc6220",
1908                 .type = AC97_TUNE_HP_MUTE_LED
1909         },
1910         {
1911                 .subvendor = 0x103c,
1912                 .subdevice = 0x0934,
1913                 .name = "HP nc8220",
1914                 .type = AC97_TUNE_HP_MUTE_LED
1915         },
1916         {
1917                 .subvendor = 0x103c,
1918                 .subdevice = 0x12f1,
1919                 .name = "HP xw8200",    /* AD1981B*/
1920                 .type = AC97_TUNE_HP_ONLY
1921         },
1922         {
1923                 .subvendor = 0x103c,
1924                 .subdevice = 0x12f2,
1925                 .name = "HP xw6200",
1926                 .type = AC97_TUNE_HP_ONLY
1927         },
1928         {
1929                 .subvendor = 0x103c,
1930                 .subdevice = 0x3008,
1931                 .name = "HP xw4200",    /* AD1981B*/
1932                 .type = AC97_TUNE_HP_ONLY
1933         },
1934         {
1935                 .subvendor = 0x104d,
1936                 .subdevice = 0x8197,
1937                 .name = "Sony S1XP",
1938                 .type = AC97_TUNE_INV_EAPD
1939         },
1940         {
1941                 .subvendor = 0x1043,
1942                 .subdevice = 0x80f3,
1943                 .name = "ASUS ICH5/AD1985",
1944                 .type = AC97_TUNE_AD_SHARING
1945         },
1946         {
1947                 .subvendor = 0x10cf,
1948                 .subdevice = 0x11c3,
1949                 .name = "Fujitsu-Siemens E4010",
1950                 .type = AC97_TUNE_HP_ONLY
1951         },
1952         {
1953                 .subvendor = 0x10cf,
1954                 .subdevice = 0x1225,
1955                 .name = "Fujitsu-Siemens T3010",
1956                 .type = AC97_TUNE_HP_ONLY
1957         },
1958         {
1959                 .subvendor = 0x10cf,
1960                 .subdevice = 0x1253,
1961                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1962                 .type = AC97_TUNE_HP_ONLY
1963         },
1964         {
1965                 .subvendor = 0x10cf,
1966                 .subdevice = 0x127d,
1967                 .name = "Fujitsu Lifebook P7010",
1968                 .type = AC97_TUNE_HP_ONLY
1969         },
1970         {
1971                 .subvendor = 0x10cf,
1972                 .subdevice = 0x127e,
1973                 .name = "Fujitsu Lifebook C1211D",
1974                 .type = AC97_TUNE_HP_ONLY
1975         },
1976         {
1977                 .subvendor = 0x10cf,
1978                 .subdevice = 0x12ec,
1979                 .name = "Fujitsu-Siemens 4010",
1980                 .type = AC97_TUNE_HP_ONLY
1981         },
1982         {
1983                 .subvendor = 0x10cf,
1984                 .subdevice = 0x12f2,
1985                 .name = "Fujitsu-Siemens Celsius H320",
1986                 .type = AC97_TUNE_SWAP_HP
1987         },
1988         {
1989                 .subvendor = 0x10f1,
1990                 .subdevice = 0x2665,
1991                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1992                 .type = AC97_TUNE_HP_ONLY
1993         },
1994         {
1995                 .subvendor = 0x10f1,
1996                 .subdevice = 0x2885,
1997                 .name = "AMD64 Mobo",   /* ALC650 */
1998                 .type = AC97_TUNE_HP_ONLY
1999         },
2000         {
2001                 .subvendor = 0x10f1,
2002                 .subdevice = 0x2895,
2003                 .name = "Tyan Thunder K8WE",
2004                 .type = AC97_TUNE_HP_ONLY
2005         },
2006         {
2007                 .subvendor = 0x10f7,
2008                 .subdevice = 0x834c,
2009                 .name = "Panasonic CF-R4",
2010                 .type = AC97_TUNE_HP_ONLY,
2011         },
2012         {
2013                 .subvendor = 0x110a,
2014                 .subdevice = 0x0056,
2015                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
2016                 .type = AC97_TUNE_HP_ONLY
2017         },
2018         {
2019                 .subvendor = 0x11d4,
2020                 .subdevice = 0x5375,
2021                 .name = "ADI AD1985 (discrete)",
2022                 .type = AC97_TUNE_HP_ONLY
2023         },
2024         {
2025                 .subvendor = 0x1462,
2026                 .subdevice = 0x5470,
2027                 .name = "MSI P4 ATX 645 Ultra",
2028                 .type = AC97_TUNE_HP_ONLY
2029         },
2030         {
2031                 .subvendor = 0x1734,
2032                 .subdevice = 0x0088,
2033                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
2034                 .type = AC97_TUNE_HP_ONLY
2035         },
2036         {
2037                 .subvendor = 0x8086,
2038                 .subdevice = 0x2000,
2039                 .mask = 0xfff0,
2040                 .name = "Intel ICH5/AD1985",
2041                 .type = AC97_TUNE_AD_SHARING
2042         },
2043         {
2044                 .subvendor = 0x8086,
2045                 .subdevice = 0x4000,
2046                 .mask = 0xfff0,
2047                 .name = "Intel ICH5/AD1985",
2048                 .type = AC97_TUNE_AD_SHARING
2049         },
2050         {
2051                 .subvendor = 0x8086,
2052                 .subdevice = 0x4856,
2053                 .name = "Intel D845WN (82801BA)",
2054                 .type = AC97_TUNE_SWAP_HP
2055         },
2056         {
2057                 .subvendor = 0x8086,
2058                 .subdevice = 0x4d44,
2059                 .name = "Intel D850EMV2",       /* AD1885 */
2060                 .type = AC97_TUNE_HP_ONLY
2061         },
2062         {
2063                 .subvendor = 0x8086,
2064                 .subdevice = 0x4d56,
2065                 .name = "Intel ICH/AD1885",
2066                 .type = AC97_TUNE_HP_ONLY
2067         },
2068         {
2069                 .subvendor = 0x8086,
2070                 .subdevice = 0x6000,
2071                 .mask = 0xfff0,
2072                 .name = "Intel ICH5/AD1985",
2073                 .type = AC97_TUNE_AD_SHARING
2074         },
2075         {
2076                 .subvendor = 0x8086,
2077                 .subdevice = 0xe000,
2078                 .mask = 0xfff0,
2079                 .name = "Intel ICH5/AD1985",
2080                 .type = AC97_TUNE_AD_SHARING
2081         },
2082 #if 0 /* FIXME: this seems wrong on most boards */
2083         {
2084                 .subvendor = 0x8086,
2085                 .subdevice = 0xa000,
2086                 .mask = 0xfff0,
2087                 .name = "Intel ICH5/AD1985",
2088                 .type = AC97_TUNE_HP_ONLY
2089         },
2090 #endif
2091         { } /* terminator */
2092 };
2093
2094 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2095                                         const char *quirk_override)
2096 {
2097         struct snd_ac97_bus *pbus;
2098         struct snd_ac97_template ac97;
2099         int err;
2100         unsigned int i, codecs;
2101         unsigned int glob_sta = 0;
2102         struct snd_ac97_bus_ops *ops;
2103         static struct snd_ac97_bus_ops standard_bus_ops = {
2104                 .write = snd_intel8x0_codec_write,
2105                 .read = snd_intel8x0_codec_read,
2106         };
2107         static struct snd_ac97_bus_ops ali_bus_ops = {
2108                 .write = snd_intel8x0_ali_codec_write,
2109                 .read = snd_intel8x0_ali_codec_read,
2110         };
2111
2112         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2113         if (!spdif_aclink) {
2114                 switch (chip->device_type) {
2115                 case DEVICE_NFORCE:
2116                         chip->spdif_idx = NVD_SPBAR;
2117                         break;
2118                 case DEVICE_ALI:
2119                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2120                         break;
2121                 case DEVICE_INTEL_ICH4:
2122                         chip->spdif_idx = ICHD_SPBAR;
2123                         break;
2124                 };
2125         }
2126
2127         chip->in_ac97_init = 1;
2128
2129         memset(&ac97, 0, sizeof(ac97));
2130         ac97.private_data = chip;
2131         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2132         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2133         if (chip->xbox)
2134                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2135         if (chip->device_type != DEVICE_ALI) {
2136                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2137                 ops = &standard_bus_ops;
2138                 chip->in_sdin_init = 1;
2139                 codecs = 0;
2140                 for (i = 0; i < chip->max_codecs; i++) {
2141                         if (! (glob_sta & chip->codec_bit[i]))
2142                                 continue;
2143                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2144                                 snd_intel8x0_codec_read_test(chip, codecs);
2145                                 chip->ac97_sdin[codecs] =
2146                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2147                                 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2148                                         chip->ac97_sdin[codecs] = 0;
2149                         } else
2150                                 chip->ac97_sdin[codecs] = i;
2151                         codecs++;
2152                 }
2153                 chip->in_sdin_init = 0;
2154                 if (! codecs)
2155                         codecs = 1;
2156         } else {
2157                 ops = &ali_bus_ops;
2158                 codecs = 1;
2159                 /* detect the secondary codec */
2160                 for (i = 0; i < 100; i++) {
2161                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2162                         if (reg & 0x40) {
2163                                 codecs = 2;
2164                                 break;
2165                         }
2166                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2167                         udelay(1);
2168                 }
2169         }
2170         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2171                 goto __err;
2172         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2173         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2174                 pbus->clock = ac97_clock;
2175         /* FIXME: my test board doesn't work well with VRA... */
2176         if (chip->device_type == DEVICE_ALI)
2177                 pbus->no_vra = 1;
2178         else
2179                 pbus->dra = 1;
2180         chip->ac97_bus = pbus;
2181         chip->ncodecs = codecs;
2182
2183         ac97.pci = chip->pci;
2184         for (i = 0; i < codecs; i++) {
2185                 ac97.num = i;
2186                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2187                         if (err != -EACCES)
2188                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2189                         if (i == 0)
2190                                 goto __err;
2191                 }
2192         }
2193         /* tune up the primary codec */
2194         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2195         /* enable separate SDINs for ICH4 */
2196         if (chip->device_type == DEVICE_INTEL_ICH4)
2197                 pbus->isdin = 1;
2198         /* find the available PCM streams */
2199         i = ARRAY_SIZE(ac97_pcm_defs);
2200         if (chip->device_type != DEVICE_INTEL_ICH4)
2201                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2202         if (chip->spdif_idx < 0)
2203                 i--;            /* do not allocate S/PDIF */
2204         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2205         if (err < 0)
2206                 goto __err;
2207         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2208         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2209         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2210         if (chip->spdif_idx >= 0)
2211                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2212         if (chip->device_type == DEVICE_INTEL_ICH4) {
2213                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2214                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2215         }
2216         /* enable separate SDINs for ICH4 */
2217         if (chip->device_type == DEVICE_INTEL_ICH4) {
2218                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2219                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2220                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2221                 if (pcm) {
2222                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2223                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2224                         for (i = 1; i < 4; i++) {
2225                                 if (pcm->r[0].codec[i]) {
2226                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2227                                         break;
2228                                 }
2229                         }
2230                 } else {
2231                         tmp &= ~ICH_SE; /* steer disable */
2232                 }
2233                 iputbyte(chip, ICHREG(SDM), tmp);
2234         }
2235         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2236                 chip->multi4 = 1;
2237                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2238                         chip->multi6 = 1;
2239                         if (chip->ac97[0]->flags & AC97_HAS_8CH)
2240                                 chip->multi8 = 1;
2241                 }
2242         }
2243         if (pbus->pcms[0].r[1].rslots[0]) {
2244                 chip->dra = 1;
2245         }
2246         if (chip->device_type == DEVICE_INTEL_ICH4) {
2247                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2248                         chip->smp20bit = 1;
2249         }
2250         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2251                 /* 48kHz only */
2252                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2253         }
2254         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2255                 /* use slot 10/11 for SPDIF */
2256                 u32 val;
2257                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2258                 val |= ICH_PCM_SPDIF_1011;
2259                 iputdword(chip, ICHREG(GLOB_CNT), val);
2260                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2261         }
2262         chip->in_ac97_init = 0;
2263         return 0;
2264
2265  __err:
2266         /* clear the cold-reset bit for the next chance */
2267         if (chip->device_type != DEVICE_ALI)
2268                 iputdword(chip, ICHREG(GLOB_CNT),
2269                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2270         return err;
2271 }
2272
2273
2274 /*
2275  *
2276  */
2277
2278 static void do_ali_reset(struct intel8x0 *chip)
2279 {
2280         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2281         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2282         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2283         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2284         iputdword(chip, ICHREG(ALI_INTERFACECR),
2285                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2286         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2287         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2288 }
2289
2290 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2291 {
2292         unsigned long end_time;
2293         unsigned int cnt, status, nstatus;
2294
2295         /* put logic to right state */
2296         /* first clear status bits */
2297         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2298         if (chip->device_type == DEVICE_NFORCE)
2299                 status |= ICH_NVSPINT;
2300         cnt = igetdword(chip, ICHREG(GLOB_STA));
2301         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2302
2303         /* ACLink on, 2 channels */
2304         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2305         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2306 #ifdef CONFIG_SND_AC97_POWER_SAVE
2307         /* do cold reset - the full ac97 powerdown may leave the controller
2308          * in a warm state but actually it cannot communicate with the codec.
2309          */
2310         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2311         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2312         udelay(10);
2313         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2314         msleep(1);
2315 #else
2316         /* finish cold or do warm reset */
2317         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2318         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2319         end_time = (jiffies + (HZ / 4)) + 1;
2320         do {
2321                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2322                         goto __ok;
2323                 schedule_timeout_uninterruptible(1);
2324         } while (time_after_eq(end_time, jiffies));
2325         snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2326                    igetdword(chip, ICHREG(GLOB_CNT)));
2327         return -EIO;
2328
2329       __ok:
2330 #endif
2331         if (probing) {
2332                 /* wait for any codec ready status.
2333                  * Once it becomes ready it should remain ready
2334                  * as long as we do not disable the ac97 link.
2335                  */
2336                 end_time = jiffies + HZ;
2337                 do {
2338                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2339                                 chip->codec_isr_bits;
2340                         if (status)
2341                                 break;
2342                         schedule_timeout_uninterruptible(1);
2343                 } while (time_after_eq(end_time, jiffies));
2344                 if (! status) {
2345                         /* no codec is found */
2346                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2347                                    igetdword(chip, ICHREG(GLOB_STA)));
2348                         return -EIO;
2349                 }
2350
2351                 /* wait for other codecs ready status. */
2352                 end_time = jiffies + HZ / 4;
2353                 while (status != chip->codec_isr_bits &&
2354                        time_after_eq(end_time, jiffies)) {
2355                         schedule_timeout_uninterruptible(1);
2356                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2357                                 chip->codec_isr_bits;
2358                 }
2359
2360         } else {
2361                 /* resume phase */
2362                 int i;
2363                 status = 0;
2364                 for (i = 0; i < chip->ncodecs; i++)
2365                         if (chip->ac97[i])
2366                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2367                 /* wait until all the probed codecs are ready */
2368                 end_time = jiffies + HZ;
2369                 do {
2370                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2371                                 chip->codec_isr_bits;
2372                         if (status == nstatus)
2373                                 break;
2374                         schedule_timeout_uninterruptible(1);
2375                 } while (time_after_eq(end_time, jiffies));
2376         }
2377
2378         if (chip->device_type == DEVICE_SIS) {
2379                 /* unmute the output on SIS7012 */
2380                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2381         }
2382         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2383                 /* enable SPDIF interrupt */
2384                 unsigned int val;
2385                 pci_read_config_dword(chip->pci, 0x4c, &val);
2386                 val |= 0x1000000;
2387                 pci_write_config_dword(chip->pci, 0x4c, val);
2388         }
2389         return 0;
2390 }
2391
2392 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2393 {
2394         u32 reg;
2395         int i = 0;
2396
2397         reg = igetdword(chip, ICHREG(ALI_SCR));
2398         if ((reg & 2) == 0)     /* Cold required */
2399                 reg |= 2;
2400         else
2401                 reg |= 1;       /* Warm */
2402         reg &= ~0x80000000;     /* ACLink on */
2403         iputdword(chip, ICHREG(ALI_SCR), reg);
2404
2405         for (i = 0; i < HZ / 2; i++) {
2406                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2407                         goto __ok;
2408                 schedule_timeout_uninterruptible(1);
2409         }
2410         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2411         if (probing)
2412                 return -EIO;
2413
2414  __ok:
2415         for (i = 0; i < HZ / 2; i++) {
2416                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2417                 if (reg & 0x80) /* primary codec */
2418                         break;
2419                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2420                 schedule_timeout_uninterruptible(1);
2421         }
2422
2423         do_ali_reset(chip);
2424         return 0;
2425 }
2426
2427 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2428 {
2429         unsigned int i, timeout;
2430         int err;
2431
2432         if (chip->device_type != DEVICE_ALI) {
2433                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2434                         return err;
2435                 iagetword(chip, 0);     /* clear semaphore flag */
2436         } else {
2437                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2438                         return err;
2439         }
2440
2441         /* disable interrupts */
2442         for (i = 0; i < chip->bdbars_count; i++)
2443                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2444         /* reset channels */
2445         for (i = 0; i < chip->bdbars_count; i++)
2446                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2447         for (i = 0; i < chip->bdbars_count; i++) {
2448                 timeout = 100000;
2449                 while (--timeout != 0) {
2450                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2451                                 break;
2452                 }
2453                 if (timeout == 0)
2454                         printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2455         }
2456         /* initialize Buffer Descriptor Lists */
2457         for (i = 0; i < chip->bdbars_count; i++)
2458                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2459                           chip->ichd[i].bdbar_addr);
2460         return 0;
2461 }
2462
2463 static int snd_intel8x0_free(struct intel8x0 *chip)
2464 {
2465         unsigned int i;
2466
2467         if (chip->irq < 0)
2468                 goto __hw_end;
2469         /* disable interrupts */
2470         for (i = 0; i < chip->bdbars_count; i++)
2471                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2472         /* reset channels */
2473         for (i = 0; i < chip->bdbars_count; i++)
2474                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2475         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2476                 /* stop the spdif interrupt */
2477                 unsigned int val;
2478                 pci_read_config_dword(chip->pci, 0x4c, &val);
2479                 val &= ~0x1000000;
2480                 pci_write_config_dword(chip->pci, 0x4c, val);
2481         }
2482         /* --- */
2483
2484       __hw_end:
2485         if (chip->irq >= 0)
2486                 free_irq(chip->irq, chip);
2487         if (chip->bdbars.area) {
2488                 if (chip->fix_nocache)
2489                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2490                 snd_dma_free_pages(&chip->bdbars);
2491         }
2492         if (chip->addr)
2493                 pci_iounmap(chip->pci, chip->addr);
2494         if (chip->bmaddr)
2495                 pci_iounmap(chip->pci, chip->bmaddr);
2496         pci_release_regions(chip->pci);
2497         pci_disable_device(chip->pci);
2498         kfree(chip);
2499         return 0;
2500 }
2501
2502 #ifdef CONFIG_PM
2503 /*
2504  * power management
2505  */
2506 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2507 {
2508         struct snd_card *card = pci_get_drvdata(pci);
2509         struct intel8x0 *chip = card->private_data;
2510         int i;
2511
2512         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2513         for (i = 0; i < chip->pcm_devs; i++)
2514                 snd_pcm_suspend_all(chip->pcm[i]);
2515         /* clear nocache */
2516         if (chip->fix_nocache) {
2517                 for (i = 0; i < chip->bdbars_count; i++) {
2518                         struct ichdev *ichdev = &chip->ichd[i];
2519                         if (ichdev->substream && ichdev->page_attr_changed) {
2520                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2521                                 if (runtime->dma_area)
2522                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2523                         }
2524                 }
2525         }
2526         for (i = 0; i < chip->ncodecs; i++)
2527                 snd_ac97_suspend(chip->ac97[i]);
2528         if (chip->device_type == DEVICE_INTEL_ICH4)
2529                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2530
2531         if (chip->irq >= 0) {
2532                 free_irq(chip->irq, chip);
2533                 chip->irq = -1;
2534         }
2535         pci_disable_device(pci);
2536         pci_save_state(pci);
2537         /* The call below may disable built-in speaker on some laptops
2538          * after S2RAM.  So, don't touch it.
2539          */
2540         /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2541         return 0;
2542 }
2543
2544 static int intel8x0_resume(struct pci_dev *pci)
2545 {
2546         struct snd_card *card = pci_get_drvdata(pci);
2547         struct intel8x0 *chip = card->private_data;
2548         int i;
2549
2550         pci_set_power_state(pci, PCI_D0);
2551         pci_restore_state(pci);
2552         if (pci_enable_device(pci) < 0) {
2553                 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2554                        "disabling device\n");
2555                 snd_card_disconnect(card);
2556                 return -EIO;
2557         }
2558         pci_set_master(pci);
2559         snd_intel8x0_chip_init(chip, 0);
2560         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2561                         IRQF_SHARED, card->shortname, chip)) {
2562                 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2563                        "disabling device\n", pci->irq);
2564                 snd_card_disconnect(card);
2565                 return -EIO;
2566         }
2567         chip->irq = pci->irq;
2568         synchronize_irq(chip->irq);
2569
2570         /* re-initialize mixer stuff */
2571         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2572                 /* enable separate SDINs for ICH4 */
2573                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2574                 /* use slot 10/11 for SPDIF */
2575                 iputdword(chip, ICHREG(GLOB_CNT),
2576                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2577                           ICH_PCM_SPDIF_1011);
2578         }
2579
2580         /* refill nocache */
2581         if (chip->fix_nocache)
2582                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2583
2584         for (i = 0; i < chip->ncodecs; i++)
2585                 snd_ac97_resume(chip->ac97[i]);
2586
2587         /* refill nocache */
2588         if (chip->fix_nocache) {
2589                 for (i = 0; i < chip->bdbars_count; i++) {
2590                         struct ichdev *ichdev = &chip->ichd[i];
2591                         if (ichdev->substream && ichdev->page_attr_changed) {
2592                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2593                                 if (runtime->dma_area)
2594                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2595                         }
2596                 }
2597         }
2598
2599         /* resume status */
2600         for (i = 0; i < chip->bdbars_count; i++) {
2601                 struct ichdev *ichdev = &chip->ichd[i];
2602                 unsigned long port = ichdev->reg_offset;
2603                 if (! ichdev->substream || ! ichdev->suspended)
2604                         continue;
2605                 if (ichdev->ichd == ICHD_PCMOUT)
2606                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2607                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2608                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2609                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2610                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2611         }
2612
2613         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2614         return 0;
2615 }
2616 #endif /* CONFIG_PM */
2617
2618 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2619
2620 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2621 {
2622         struct snd_pcm_substream *subs;
2623         struct ichdev *ichdev;
2624         unsigned long port;
2625         unsigned long pos, t;
2626         struct timeval start_time, stop_time;
2627
2628         if (chip->ac97_bus->clock != 48000)
2629                 return; /* specified in module option */
2630
2631         subs = chip->pcm[0]->streams[0].substream;
2632         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2633                 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2634                 return;
2635         }
2636         ichdev = &chip->ichd[ICHD_PCMOUT];
2637         ichdev->physbuf = subs->dma_buffer.addr;
2638         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2639         ichdev->substream = NULL; /* don't process interrupts */
2640
2641         /* set rate */
2642         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2643                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2644                 return;
2645         }
2646         snd_intel8x0_setup_periods(chip, ichdev);
2647         port = ichdev->reg_offset;
2648         spin_lock_irq(&chip->reg_lock);
2649         chip->in_measurement = 1;
2650         /* trigger */
2651         if (chip->device_type != DEVICE_ALI)
2652                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2653         else {
2654                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2655                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2656         }
2657         do_gettimeofday(&start_time);
2658         spin_unlock_irq(&chip->reg_lock);
2659         msleep(50);
2660         spin_lock_irq(&chip->reg_lock);
2661         /* check the position */
2662         pos = ichdev->fragsize1;
2663         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2664         pos += ichdev->position;
2665         chip->in_measurement = 0;
2666         do_gettimeofday(&stop_time);
2667         /* stop */
2668         if (chip->device_type == DEVICE_ALI) {
2669                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2670                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2671                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2672                         ;
2673         } else {
2674                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2675                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2676                         ;
2677         }
2678         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2679         spin_unlock_irq(&chip->reg_lock);
2680
2681         t = stop_time.tv_sec - start_time.tv_sec;
2682         t *= 1000000;
2683         t += stop_time.tv_usec - start_time.tv_usec;
2684         printk(KERN_INFO "%s: measured %lu usecs\n", __func__, t);
2685         if (t == 0) {
2686                 snd_printk(KERN_ERR "?? calculation error..\n");
2687                 return;
2688         }
2689         pos = (pos / 4) * 1000;
2690         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2691         if (pos < 40000 || pos >= 60000)
2692                 /* abnormal value. hw problem? */
2693                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2694         else if (pos < 47500 || pos > 48500)
2695                 /* not 48000Hz, tuning the clock.. */
2696                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2697         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2698         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2699 }
2700
2701 static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2702         SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2703         SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2704         SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2705         SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2706         { }     /* terminator */
2707 };
2708
2709 static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2710 {
2711         struct pci_dev *pci = chip->pci;
2712         const struct snd_pci_quirk *wl;
2713
2714         wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2715         if (!wl)
2716                 return 0;
2717         printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2718                pci->subsystem_vendor, pci->subsystem_device, wl->value);
2719         chip->ac97_bus->clock = wl->value;
2720         return 1;
2721 }
2722
2723 #ifdef CONFIG_PROC_FS
2724 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2725                                    struct snd_info_buffer *buffer)
2726 {
2727         struct intel8x0 *chip = entry->private_data;
2728         unsigned int tmp;
2729
2730         snd_iprintf(buffer, "Intel8x0\n\n");
2731         if (chip->device_type == DEVICE_ALI)
2732                 return;
2733         tmp = igetdword(chip, ICHREG(GLOB_STA));
2734         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2735         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2736         if (chip->device_type == DEVICE_INTEL_ICH4)
2737                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2738         snd_iprintf(buffer, "AC'97 codecs ready    :");
2739         if (tmp & chip->codec_isr_bits) {
2740                 int i;
2741                 static const char *codecs[3] = {
2742                         "primary", "secondary", "tertiary"
2743                 };
2744                 for (i = 0; i < chip->max_codecs; i++)
2745                         if (tmp & chip->codec_bit[i])
2746                                 snd_iprintf(buffer, " %s", codecs[i]);
2747         } else
2748                 snd_iprintf(buffer, " none");
2749         snd_iprintf(buffer, "\n");
2750         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2751             chip->device_type == DEVICE_SIS)
2752                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2753                         chip->ac97_sdin[0],
2754                         chip->ac97_sdin[1],
2755                         chip->ac97_sdin[2]);
2756 }
2757
2758 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2759 {
2760         struct snd_info_entry *entry;
2761
2762         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2763                 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2764 }
2765 #else
2766 #define snd_intel8x0_proc_init(x)
2767 #endif
2768
2769 static int snd_intel8x0_dev_free(struct snd_device *device)
2770 {
2771         struct intel8x0 *chip = device->device_data;
2772         return snd_intel8x0_free(chip);
2773 }
2774
2775 struct ich_reg_info {
2776         unsigned int int_sta_mask;
2777         unsigned int offset;
2778 };
2779
2780 static unsigned int ich_codec_bits[3] = {
2781         ICH_PCR, ICH_SCR, ICH_TCR
2782 };
2783 static unsigned int sis_codec_bits[3] = {
2784         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2785 };
2786
2787 static int __devinit snd_intel8x0_create(struct snd_card *card,
2788                                          struct pci_dev *pci,
2789                                          unsigned long device_type,
2790                                          struct intel8x0 ** r_intel8x0)
2791 {
2792         struct intel8x0 *chip;
2793         int err;
2794         unsigned int i;
2795         unsigned int int_sta_masks;
2796         struct ichdev *ichdev;
2797         static struct snd_device_ops ops = {
2798                 .dev_free =     snd_intel8x0_dev_free,
2799         };
2800
2801         static unsigned int bdbars[] = {
2802                 3, /* DEVICE_INTEL */
2803                 6, /* DEVICE_INTEL_ICH4 */
2804                 3, /* DEVICE_SIS */
2805                 6, /* DEVICE_ALI */
2806                 4, /* DEVICE_NFORCE */
2807         };
2808         static struct ich_reg_info intel_regs[6] = {
2809                 { ICH_PIINT, 0 },
2810                 { ICH_POINT, 0x10 },
2811                 { ICH_MCINT, 0x20 },
2812                 { ICH_M2INT, 0x40 },
2813                 { ICH_P2INT, 0x50 },
2814                 { ICH_SPINT, 0x60 },
2815         };
2816         static struct ich_reg_info nforce_regs[4] = {
2817                 { ICH_PIINT, 0 },
2818                 { ICH_POINT, 0x10 },
2819                 { ICH_MCINT, 0x20 },
2820                 { ICH_NVSPINT, 0x70 },
2821         };
2822         static struct ich_reg_info ali_regs[6] = {
2823                 { ALI_INT_PCMIN, 0x40 },
2824                 { ALI_INT_PCMOUT, 0x50 },
2825                 { ALI_INT_MICIN, 0x60 },
2826                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2827                 { ALI_INT_SPDIFIN, 0xa0 },
2828                 { ALI_INT_SPDIFOUT, 0xb0 },
2829         };
2830         struct ich_reg_info *tbl;
2831
2832         *r_intel8x0 = NULL;
2833
2834         if ((err = pci_enable_device(pci)) < 0)
2835                 return err;
2836
2837         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2838         if (chip == NULL) {
2839                 pci_disable_device(pci);
2840                 return -ENOMEM;
2841         }
2842         spin_lock_init(&chip->reg_lock);
2843         chip->device_type = device_type;
2844         chip->card = card;
2845         chip->pci = pci;
2846         chip->irq = -1;
2847
2848         /* module parameters */
2849         chip->buggy_irq = buggy_irq;
2850         chip->buggy_semaphore = buggy_semaphore;
2851         if (xbox)
2852                 chip->xbox = 1;
2853
2854         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2855             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2856                 chip->fix_nocache = 1; /* enable workaround */
2857
2858         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2859                 kfree(chip);
2860                 pci_disable_device(pci);
2861                 return err;
2862         }
2863
2864         if (device_type == DEVICE_ALI) {
2865                 /* ALI5455 has no ac97 region */
2866                 chip->bmaddr = pci_iomap(pci, 0, 0);
2867                 goto port_inited;
2868         }
2869
2870         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2871                 chip->addr = pci_iomap(pci, 2, 0);
2872         else
2873                 chip->addr = pci_iomap(pci, 0, 0);
2874         if (!chip->addr) {
2875                 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2876                 snd_intel8x0_free(chip);
2877                 return -EIO;
2878         }
2879         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2880                 chip->bmaddr = pci_iomap(pci, 3, 0);
2881         else
2882                 chip->bmaddr = pci_iomap(pci, 1, 0);
2883         if (!chip->bmaddr) {
2884                 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2885                 snd_intel8x0_free(chip);
2886                 return -EIO;
2887         }
2888
2889  port_inited:
2890         chip->bdbars_count = bdbars[device_type];
2891
2892         /* initialize offsets */
2893         switch (device_type) {
2894         case DEVICE_NFORCE:
2895                 tbl = nforce_regs;
2896                 break;
2897         case DEVICE_ALI:
2898                 tbl = ali_regs;
2899                 break;
2900         default:
2901                 tbl = intel_regs;
2902                 break;
2903         }
2904         for (i = 0; i < chip->bdbars_count; i++) {
2905                 ichdev = &chip->ichd[i];
2906                 ichdev->ichd = i;
2907                 ichdev->reg_offset = tbl[i].offset;
2908                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2909                 if (device_type == DEVICE_SIS) {
2910                         /* SiS 7012 swaps the registers */
2911                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2912                         ichdev->roff_picb = ICH_REG_OFF_SR;
2913                 } else {
2914                         ichdev->roff_sr = ICH_REG_OFF_SR;
2915                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2916                 }
2917                 if (device_type == DEVICE_ALI)
2918                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2919                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2920                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2921         }
2922
2923         /* allocate buffer descriptor lists */
2924         /* the start of each lists must be aligned to 8 bytes */
2925         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2926                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2927                                 &chip->bdbars) < 0) {
2928                 snd_intel8x0_free(chip);
2929                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2930                 return -ENOMEM;
2931         }
2932         /* tables must be aligned to 8 bytes here, but the kernel pages
2933            are much bigger, so we don't care (on i386) */
2934         /* workaround for 440MX */
2935         if (chip->fix_nocache)
2936                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2937         int_sta_masks = 0;
2938         for (i = 0; i < chip->bdbars_count; i++) {
2939                 ichdev = &chip->ichd[i];
2940                 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2941                         (i * ICH_MAX_FRAGS * 2);
2942                 ichdev->bdbar_addr = chip->bdbars.addr +
2943                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2944                 int_sta_masks |= ichdev->int_sta_mask;
2945         }
2946         chip->int_sta_reg = device_type == DEVICE_ALI ?
2947                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2948         chip->int_sta_mask = int_sta_masks;
2949
2950         pci_set_master(pci);
2951
2952         switch(chip->device_type) {
2953         case DEVICE_INTEL_ICH4:
2954                 /* ICH4 can have three codecs */
2955                 chip->max_codecs = 3;
2956                 chip->codec_bit = ich_codec_bits;
2957                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2958                 break;
2959         case DEVICE_SIS:
2960                 /* recent SIS7012 can have three codecs */
2961                 chip->max_codecs = 3;
2962                 chip->codec_bit = sis_codec_bits;
2963                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
2964                 break;
2965         default:
2966                 /* others up to two codecs */
2967                 chip->max_codecs = 2;
2968                 chip->codec_bit = ich_codec_bits;
2969                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
2970                 break;
2971         }
2972         for (i = 0; i < chip->max_codecs; i++)
2973                 chip->codec_isr_bits |= chip->codec_bit[i];
2974
2975         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2976                 snd_intel8x0_free(chip);
2977                 return err;
2978         }
2979
2980         /* request irq after initializaing int_sta_mask, etc */
2981         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2982                         IRQF_SHARED, card->shortname, chip)) {
2983                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2984                 snd_intel8x0_free(chip);
2985                 return -EBUSY;
2986         }
2987         chip->irq = pci->irq;
2988
2989         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2990                 snd_intel8x0_free(chip);
2991                 return err;
2992         }
2993
2994         snd_card_set_dev(card, &pci->dev);
2995
2996         *r_intel8x0 = chip;
2997         return 0;
2998 }
2999
3000 static struct shortname_table {
3001         unsigned int id;
3002         const char *s;
3003 } shortnames[] __devinitdata = {
3004         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3005         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3006         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3007         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3008         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3009         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3010         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3011         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3012         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3013         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3014         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3015         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3016         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3017         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3018         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3019         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3020         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3021         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3022         { 0x003a, "NVidia MCP04" },
3023         { 0x746d, "AMD AMD8111" },
3024         { 0x7445, "AMD AMD768" },
3025         { 0x5455, "ALi M5455" },
3026         { 0, NULL },
3027 };
3028
3029 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3030         SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3031         { } /* end */
3032 };
3033
3034 /* look up white/black list for SPDIF over ac-link */
3035 static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3036 {
3037         const struct snd_pci_quirk *w;
3038
3039         w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3040         if (w) {
3041                 if (w->value)
3042                         snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3043                                     "AC-Link for %s\n", w->name);
3044                 else
3045                         snd_printdd(KERN_INFO "intel8x0: Using integrated "
3046                                     "SPDIF DMA for %s\n", w->name);
3047                 return w->value;
3048         }
3049         return 0;
3050 }
3051
3052 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3053                                         const struct pci_device_id *pci_id)
3054 {
3055         struct snd_card *card;
3056         struct intel8x0 *chip;
3057         int err;
3058         struct shortname_table *name;
3059
3060         card = snd_card_new(index, id, THIS_MODULE, 0);
3061         if (card == NULL)
3062                 return -ENOMEM;
3063
3064         if (spdif_aclink < 0)
3065                 spdif_aclink = check_default_spdif_aclink(pci);
3066
3067         strcpy(card->driver, "ICH");
3068         if (!spdif_aclink) {
3069                 switch (pci_id->driver_data) {
3070                 case DEVICE_NFORCE:
3071                         strcpy(card->driver, "NFORCE");
3072                         break;
3073                 case DEVICE_INTEL_ICH4:
3074                         strcpy(card->driver, "ICH4");
3075                 }
3076         }
3077
3078         strcpy(card->shortname, "Intel ICH");
3079         for (name = shortnames; name->id; name++) {
3080                 if (pci->device == name->id) {
3081                         strcpy(card->shortname, name->s);
3082                         break;
3083                 }
3084         }
3085
3086         if (buggy_irq < 0) {
3087                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3088                  * Needs to return IRQ_HANDLED for unknown irqs.
3089                  */
3090                 if (pci_id->driver_data == DEVICE_NFORCE)
3091                         buggy_irq = 1;
3092                 else
3093                         buggy_irq = 0;
3094         }
3095
3096         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3097                                        &chip)) < 0) {
3098                 snd_card_free(card);
3099                 return err;
3100         }
3101         card->private_data = chip;
3102
3103         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3104                 snd_card_free(card);
3105                 return err;
3106         }
3107         if ((err = snd_intel8x0_pcm(chip)) < 0) {
3108                 snd_card_free(card);
3109                 return err;
3110         }
3111
3112         snd_intel8x0_proc_init(chip);
3113
3114         snprintf(card->longname, sizeof(card->longname),
3115                  "%s with %s at irq %i", card->shortname,
3116                  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3117
3118         if (ac97_clock == 0 || ac97_clock == 1) {
3119                 if (ac97_clock == 0) {
3120                         if (intel8x0_in_clock_list(chip) == 0)
3121                                 intel8x0_measure_ac97_clock(chip);
3122                 } else {
3123                         intel8x0_measure_ac97_clock(chip);
3124                 }
3125         }
3126
3127         if ((err = snd_card_register(card)) < 0) {
3128                 snd_card_free(card);
3129                 return err;
3130         }
3131         pci_set_drvdata(pci, card);
3132         return 0;
3133 }
3134
3135 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3136 {
3137         snd_card_free(pci_get_drvdata(pci));
3138         pci_set_drvdata(pci, NULL);
3139 }
3140
3141 static struct pci_driver driver = {
3142         .name = "Intel ICH",
3143         .id_table = snd_intel8x0_ids,
3144         .probe = snd_intel8x0_probe,
3145         .remove = __devexit_p(snd_intel8x0_remove),
3146 #ifdef CONFIG_PM
3147         .suspend = intel8x0_suspend,
3148         .resume = intel8x0_resume,
3149 #endif
3150 };
3151
3152
3153 static int __init alsa_card_intel8x0_init(void)
3154 {
3155         return pci_register_driver(&driver);
3156 }
3157
3158 static void __exit alsa_card_intel8x0_exit(void)
3159 {
3160         pci_unregister_driver(&driver);
3161 }
3162
3163 module_init(alsa_card_intel8x0_init)
3164 module_exit(alsa_card_intel8x0_exit)