2 * Device driver for the PMU on 68K-based Apple PowerBooks
4 * The VIA (versatile interface adapter) interfaces to the PMU,
5 * a 6805 microprocessor core whose primary function is to control
6 * battery charging and system power on the PowerBooks.
7 * The PMU also controls the ADB (Apple Desktop Bus) which connects
8 * to the keyboard and mouse, as well as the non-volatile RAM
9 * and the RTC (real time clock) chip.
11 * Adapted for 68K PMU by Joshua M. Thompson
13 * Based largely on the PowerMac PMU code by Paul Mackerras and
16 * Also based on the PMU driver from MkLinux by Apple Computer, Inc.
17 * and the Open Software Foundation, Inc.
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/miscdevice.h>
26 #include <linux/blkdev.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
32 #include <linux/adb.h>
33 #include <linux/pmu.h>
34 #include <linux/cuda.h>
36 #include <asm/macintosh.h>
37 #include <asm/macints.h>
38 #include <asm/machw.h>
39 #include <asm/mac_via.h>
41 #include <asm/pgtable.h>
42 #include <asm/system.h>
44 #include <asm/uaccess.h>
46 /* Misc minor number allocated for /dev/pmu */
49 /* VIA registers - spaced 0x200 bytes apart */
50 #define RS 0x200 /* skip between registers */
51 #define B 0 /* B-side data */
52 #define A RS /* A-side data */
53 #define DIRB (2*RS) /* B-side direction (1=output) */
54 #define DIRA (3*RS) /* A-side direction (1=output) */
55 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
56 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
57 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
58 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
59 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
60 #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */
61 #define SR (10*RS) /* Shift register */
62 #define ACR (11*RS) /* Auxiliary control register */
63 #define PCR (12*RS) /* Peripheral control register */
64 #define IFR (13*RS) /* Interrupt flag register */
65 #define IER (14*RS) /* Interrupt enable register */
66 #define ANH (15*RS) /* A-side data, no handshake */
68 /* Bits in B data register: both active low */
69 #define TACK 0x02 /* Transfer acknowledge (input) */
70 #define TREQ 0x04 /* Transfer request (output) */
73 #define SR_CTRL 0x1c /* Shift register control bits */
74 #define SR_EXT 0x0c /* Shift on external clock */
75 #define SR_OUT 0x10 /* Shift out if 1 */
77 /* Bits in IFR and IER */
78 #define SR_INT 0x04 /* Shift register full/empty */
79 #define CB1_INT 0x10 /* transition on CB1 input */
81 static enum pmu_state {
89 static struct adb_request *current_req;
90 static struct adb_request *last_req;
91 static struct adb_request *req_awaiting_reply;
92 static unsigned char interrupt_data[32];
93 static unsigned char *reply_ptr;
94 static int data_index;
96 static int adb_int_pending;
97 static int pmu_adb_flags;
98 static int adb_dev_map;
99 static struct adb_request bright_req_1, bright_req_2, bright_req_3;
100 static int pmu_kind = PMU_UNKNOWN;
101 static int pmu_fully_inited;
105 static int pmu_probe(void);
106 static int pmu_init(void);
107 static void pmu_start(void);
108 static irqreturn_t pmu_interrupt(int irq, void *arg);
109 static int pmu_send_request(struct adb_request *req, int sync);
110 static int pmu_autopoll(int devs);
112 static int pmu_reset_bus(void);
114 static void pmu_start(void);
115 static void send_byte(int x);
116 static void recv_byte(void);
117 static void pmu_done(struct adb_request *req);
118 static void pmu_handle_data(unsigned char *data, int len);
119 static void set_volume(int level);
120 static void pmu_enable_backlight(int on);
121 static void pmu_set_brightness(int level);
123 struct adb_driver via_pmu_driver = {
134 * This table indicates for each PMU opcode:
135 * - the number of data bytes to be sent with the command, or -1
136 * if a length byte should be sent,
137 * - the number of response bytes which the PMU will return, or
138 * -1 if it will send a length byte.
140 static s8 pmu_data_len[256][2] = {
141 /* 0 1 2 3 4 5 6 7 */
142 /*00*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
143 /*08*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
144 /*10*/ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
145 /*18*/ { 0, 1},{ 0, 1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{ 0, 0},
146 /*20*/ {-1, 0},{ 0, 0},{ 2, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},
147 /*28*/ { 0,-1},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{ 0,-1},
148 /*30*/ { 4, 0},{20, 0},{-1, 0},{ 3, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
149 /*38*/ { 0, 4},{ 0,20},{ 2,-1},{ 2, 1},{ 3,-1},{-1,-1},{-1,-1},{ 4, 0},
150 /*40*/ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
151 /*48*/ { 0, 1},{ 0, 1},{-1,-1},{ 1, 0},{ 1, 0},{-1,-1},{-1,-1},{-1,-1},
152 /*50*/ { 1, 0},{ 0, 0},{ 2, 0},{ 2, 0},{-1, 0},{ 1, 0},{ 3, 0},{ 1, 0},
153 /*58*/ { 0, 1},{ 1, 0},{ 0, 2},{ 0, 2},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},
154 /*60*/ { 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
155 /*68*/ { 0, 3},{ 0, 3},{ 0, 2},{ 0, 8},{ 0,-1},{ 0,-1},{-1,-1},{-1,-1},
156 /*70*/ { 1, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
157 /*78*/ { 0,-1},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},{ 5, 1},{ 4, 1},{ 4, 1},
158 /*80*/ { 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
159 /*88*/ { 0, 5},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
160 /*90*/ { 1, 0},{ 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
161 /*98*/ { 0, 1},{ 0, 1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
162 /*a0*/ { 2, 0},{ 2, 0},{ 2, 0},{ 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},
163 /*a8*/ { 1, 1},{ 1, 0},{ 3, 0},{ 2, 0},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
164 /*b0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
165 /*b8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
166 /*c0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
167 /*c8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
168 /*d0*/ { 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
169 /*d8*/ { 1, 1},{ 1, 1},{-1,-1},{-1,-1},{ 0, 1},{ 0,-1},{-1,-1},{-1,-1},
170 /*e0*/ {-1, 0},{ 4, 0},{ 0, 1},{-1, 0},{-1, 0},{ 4, 0},{-1, 0},{-1, 0},
171 /*e8*/ { 3,-1},{-1,-1},{ 0, 1},{-1,-1},{ 0,-1},{-1,-1},{-1,-1},{ 0, 0},
172 /*f0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
173 /*f8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
178 if (macintosh_config->adb_type == MAC_ADB_PB1) {
179 pmu_kind = PMU_68K_V1;
180 } else if (macintosh_config->adb_type == MAC_ADB_PB2) {
181 pmu_kind = PMU_68K_V2;
195 volatile struct adb_request req;
197 via2[B] |= TREQ; /* negate TREQ */
198 via2[DIRB] = (via2[DIRB] | TREQ) & ~TACK; /* TACK in, TREQ out */
200 pmu_request((struct adb_request *) &req, NULL, 2, PMU_SET_INTR_MASK, PMU_INT_ADB);
202 while (!req.complete) {
204 printk(KERN_ERR "pmu_init: no response from PMU\n");
211 /* ack all pending interrupts */
213 interrupt_data[0] = 1;
214 while (interrupt_data[0] || pmu_state != idle) {
216 printk(KERN_ERR "pmu_init: timed out acking intrs\n");
219 if (pmu_state == idle) {
221 pmu_interrupt(0, NULL);
227 pmu_request((struct adb_request *) &req, NULL, 2, PMU_SET_INTR_MASK,
228 PMU_INT_ADB_AUTO|PMU_INT_SNDBRT|PMU_INT_ADB);
230 while (!req.complete) {
232 printk(KERN_ERR "pmu_init: no response from PMU\n");
239 bright_req_1.complete = 1;
240 bright_req_2.complete = 1;
241 bright_req_3.complete = 1;
243 if (request_irq(IRQ_MAC_ADB_SR, pmu_interrupt, 0, "pmu-shift",
245 printk(KERN_ERR "pmu_init: can't get irq %d\n",
249 if (request_irq(IRQ_MAC_ADB_CL, pmu_interrupt, 0, "pmu-clock",
251 printk(KERN_ERR "pmu_init: can't get irq %d\n",
253 free_irq(IRQ_MAC_ADB_SR, pmu_interrupt);
257 pmu_fully_inited = 1;
259 /* Enable backlight */
260 pmu_enable_backlight(1);
262 printk("adb: PMU 68K driver v0.5 for Unified ADB.\n");
273 /* Send an ADB command */
275 pmu_send_request(struct adb_request *req, int sync)
279 if (!pmu_fully_inited)
287 switch (req->data[0]) {
289 for (i = 0; i < req->nbytes - 1; ++i)
290 req->data[i] = req->data[i+1];
292 if (pmu_data_len[req->data[0]][1] != 0) {
293 req->reply[0] = ADB_RET_OK;
297 ret = pmu_queue_request(req);
300 switch (req->data[1]) {
302 if (req->nbytes != 2)
304 req->data[0] = PMU_READ_RTC;
307 req->reply[0] = CUDA_PACKET;
309 req->reply[2] = CUDA_GET_TIME;
310 ret = pmu_queue_request(req);
313 if (req->nbytes != 6)
315 req->data[0] = PMU_SET_RTC;
317 for (i = 1; i <= 4; ++i)
318 req->data[i] = req->data[i+1];
320 req->reply[0] = CUDA_PACKET;
322 req->reply[2] = CUDA_SET_TIME;
323 ret = pmu_queue_request(req);
326 if (req->nbytes != 4)
328 req->data[0] = PMU_READ_NVRAM;
329 req->data[1] = req->data[2];
330 req->data[2] = req->data[3];
333 req->reply[0] = CUDA_PACKET;
335 req->reply[2] = CUDA_GET_PRAM;
336 ret = pmu_queue_request(req);
339 if (req->nbytes != 5)
341 req->data[0] = PMU_WRITE_NVRAM;
342 req->data[1] = req->data[2];
343 req->data[2] = req->data[3];
344 req->data[3] = req->data[4];
347 req->reply[0] = CUDA_PACKET;
349 req->reply[2] = CUDA_SET_PRAM;
350 ret = pmu_queue_request(req);
355 for (i = req->nbytes - 1; i > 1; --i)
356 req->data[i+2] = req->data[i];
357 req->data[3] = req->nbytes - 2;
358 req->data[2] = pmu_adb_flags;
359 /*req->data[1] = req->data[1];*/
360 req->data[0] = PMU_ADB_CMD;
362 req->reply_expected = 1;
364 ret = pmu_queue_request(req);
374 while (!req->complete)
381 /* Enable/disable autopolling */
383 pmu_autopoll(int devs)
385 struct adb_request req;
387 if (!pmu_fully_inited) return -ENXIO;
391 pmu_request(&req, NULL, 5, PMU_ADB_CMD, 0, 0x86,
392 adb_dev_map >> 8, adb_dev_map);
395 pmu_request(&req, NULL, 1, PMU_ADB_POLL_OFF);
398 while (!req.complete)
403 /* Reset the ADB bus */
407 struct adb_request req;
409 int save_autopoll = adb_dev_map;
411 if (!pmu_fully_inited) return -ENXIO;
413 /* anyone got a better idea?? */
418 req.data[0] = PMU_ADB_CMD;
420 req.data[2] = 3; /* ADB_BUSRESET ??? */
424 req.reply_expected = 1;
425 if (pmu_queue_request(&req) != 0)
427 printk(KERN_ERR "pmu_adb_reset_bus: pmu_queue_request failed\n");
430 while (!req.complete)
433 while (!req.complete) {
435 printk(KERN_ERR "pmu_adb_reset_bus (reset): no response from PMU\n");
442 if (save_autopoll != 0)
443 pmu_autopoll(save_autopoll);
448 /* Construct and send a pmu request */
450 pmu_request(struct adb_request *req, void (*done)(struct adb_request *),
456 if (nbytes < 0 || nbytes > 32) {
457 printk(KERN_ERR "pmu_request: bad nbytes (%d)\n", nbytes);
461 req->nbytes = nbytes;
463 va_start(list, nbytes);
464 for (i = 0; i < nbytes; ++i)
465 req->data[i] = va_arg(list, int);
467 if (pmu_data_len[req->data[0]][1] != 0) {
468 req->reply[0] = ADB_RET_OK;
472 req->reply_expected = 0;
473 return pmu_queue_request(req);
477 pmu_queue_request(struct adb_request *req)
482 if (req->nbytes <= 0) {
486 nsend = pmu_data_len[req->data[0]][0];
487 if (nsend >= 0 && req->nbytes != nsend + 1) {
495 local_irq_save(flags);
497 if (current_req != 0) {
498 last_req->next = req;
503 if (pmu_state == idle)
507 local_irq_restore(flags);
514 via1[ACR] |= SR_CTRL;
516 via2[B] &= ~TREQ; /* assert TREQ */
524 via1[ACR] = (via1[ACR] | SR_EXT) & ~SR_OUT;
525 c = via1[SR]; /* resets SR */
533 struct adb_request *req;
535 /* assert pmu_state == idle */
536 /* get the packet to send */
537 local_irq_save(flags);
539 if (req == 0 || pmu_state != idle
540 || (req->reply_expected && req_awaiting_reply))
545 data_len = pmu_data_len[req->data[0]][0];
547 /* set the shift register to shift out and send a byte */
548 send_byte(req->data[0]);
551 local_irq_restore(flags);
559 local_irq_save(flags);
560 if (via1[IFR] & SR_INT) {
562 pmu_interrupt(IRQ_MAC_ADB_SR, NULL);
564 if (via1[IFR] & CB1_INT) {
566 pmu_interrupt(IRQ_MAC_ADB_CL, NULL);
568 local_irq_restore(flags);
572 pmu_interrupt(int irq, void *dev_id)
574 struct adb_request *req;
575 int timeout, bite = 0; /* to prevent compiler warning */
578 printk("pmu_interrupt: irq %d state %d acr %02X, b %02X data_index %d/%d adb_int_pending %d\n",
579 irq, pmu_state, (uint) via1[ACR], (uint) via2[B], data_index, data_len, adb_int_pending);
582 if (irq == IRQ_MAC_ADB_CL) { /* CB1 interrupt */
584 } else if (irq == IRQ_MAC_ADB_SR) { /* SR interrupt */
585 if (via2[B] & TACK) {
586 printk(KERN_DEBUG "PMU: SR_INT but ack still high! (%x)\n", via2[B]);
589 /* if reading grab the byte */
590 if ((via1[ACR] & SR_OUT) == 0) bite = via1[SR];
592 /* reset TREQ and wait for TACK to go high */
595 while (!(via2[B] & TACK)) {
597 printk(KERN_ERR "PMU not responding (!ack)\n");
607 data_len = req->nbytes - 1;
611 if (data_index <= data_len) {
612 send_byte(req->data[data_index++]);
616 data_len = pmu_data_len[req->data[0]][1];
619 current_req = req->next;
620 if (req->reply_expected)
621 req_awaiting_reply = req;
627 reply_ptr = req->reply + req->reply_len;
635 pmu_state = reading_intr;
636 reply_ptr = interrupt_data;
642 if (data_len == -1) {
645 printk(KERN_ERR "PMU: bad reply len %d\n",
648 reply_ptr[data_index++] = bite;
650 if (data_index < data_len) {
655 if (pmu_state == reading_intr) {
656 pmu_handle_data(interrupt_data, data_index);
659 current_req = req->next;
660 req->reply_len += data_index;
668 printk(KERN_ERR "pmu_interrupt: unknown state %d?\n",
673 if (pmu_state == idle) {
674 if (adb_int_pending) {
676 send_byte(PMU_INT_ACK);
678 } else if (current_req) {
684 printk("pmu_interrupt: exit state %d acr %02X, b %02X data_index %d/%d adb_int_pending %d\n",
685 pmu_state, (uint) via1[ACR], (uint) via2[B], data_index, data_len, adb_int_pending);
691 pmu_done(struct adb_request *req)
698 /* Interrupt data could be the result data from an ADB cmd */
700 pmu_handle_data(unsigned char *data, int len)
702 static int show_pmu_ints = 1;
709 if (data[0] & PMU_INT_ADB) {
710 if ((data[0] & PMU_INT_ADB_AUTO) == 0) {
711 struct adb_request *req = req_awaiting_reply;
713 printk(KERN_ERR "PMU: extra ADB reply\n");
716 req_awaiting_reply = NULL;
720 memcpy(req->reply, data + 1, len - 1);
721 req->reply_len = len - 1;
725 adb_input(data+1, len-1, 1);
728 if (data[0] == 0x08 && len == 3) {
729 /* sound/brightness buttons pressed */
730 pmu_set_brightness(data[1] >> 3);
732 } else if (show_pmu_ints
733 && !(data[0] == PMU_INT_TICK && len == 1)) {
735 printk(KERN_DEBUG "pmu intr");
736 for (i = 0; i < len; ++i)
737 printk(" %.2x", data[i]);
743 static int backlight_level = -1;
744 static int backlight_enabled = 0;
746 #define LEVEL_TO_BRIGHT(lev) ((lev) < 1? 0x7f: 0x4a - ((lev) << 1))
749 pmu_enable_backlight(int on)
751 struct adb_request req;
754 /* first call: get current backlight value */
755 if (backlight_level < 0) {
759 pmu_request(&req, NULL, 3, PMU_READ_NVRAM, 0x14, 0xe);
760 while (!req.complete)
762 printk(KERN_DEBUG "pmu: nvram returned bright: %d\n", (int)req.reply[1]);
763 backlight_level = req.reply[1];
766 backlight_enabled = 0;
770 pmu_request(&req, NULL, 2, PMU_BACKLIGHT_BRIGHT,
771 LEVEL_TO_BRIGHT(backlight_level));
772 while (!req.complete)
775 pmu_request(&req, NULL, 2, PMU_POWER_CTRL,
776 PMU_POW_BACKLIGHT | (on ? PMU_POW_ON : PMU_POW_OFF));
777 while (!req.complete)
779 backlight_enabled = on;
783 pmu_set_brightness(int level)
787 backlight_level = level;
788 bright = LEVEL_TO_BRIGHT(level);
789 if (!backlight_enabled)
791 if (bright_req_1.complete)
792 pmu_request(&bright_req_1, NULL, 2, PMU_BACKLIGHT_BRIGHT,
794 if (bright_req_2.complete)
795 pmu_request(&bright_req_2, NULL, 2, PMU_POWER_CTRL,
796 PMU_POW_BACKLIGHT | (bright < 0x7f ? PMU_POW_ON : PMU_POW_OFF));
800 pmu_enable_irled(int on)
802 struct adb_request req;
804 pmu_request(&req, NULL, 2, PMU_POWER_CTRL, PMU_POW_IRLED |
805 (on ? PMU_POW_ON : PMU_POW_OFF));
806 while (!req.complete)
811 set_volume(int level)
818 return (pmu_kind != PMU_UNKNOWN);