2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
4 * Author: Vladimir Barinov, <vbarinov@ru.mvista.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
17 #include <linux/clk.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/initval.h>
23 #include <sound/soc.h>
25 #include "davinci-pcm.h"
27 #define DAVINCI_MCBSP_DRR_REG 0x00
28 #define DAVINCI_MCBSP_DXR_REG 0x04
29 #define DAVINCI_MCBSP_SPCR_REG 0x08
30 #define DAVINCI_MCBSP_RCR_REG 0x0c
31 #define DAVINCI_MCBSP_XCR_REG 0x10
32 #define DAVINCI_MCBSP_SRGR_REG 0x14
33 #define DAVINCI_MCBSP_PCR_REG 0x24
35 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
36 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
37 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
38 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
39 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
40 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
41 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
43 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
44 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
45 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
46 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
48 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
49 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
50 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
51 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
52 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
54 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
55 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
56 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
58 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
59 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
60 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
61 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
62 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
63 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
64 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
65 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
67 #define MOD_REG_BIT(val, mask, set) do { \
76 DAVINCI_MCBSP_WORD_8 = 0,
77 DAVINCI_MCBSP_WORD_12,
78 DAVINCI_MCBSP_WORD_16,
79 DAVINCI_MCBSP_WORD_20,
80 DAVINCI_MCBSP_WORD_24,
81 DAVINCI_MCBSP_WORD_32,
84 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
85 .name = "I2S PCM Stereo out",
88 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
89 .name = "I2S PCM Stereo in",
92 struct davinci_mcbsp_dev {
95 struct davinci_pcm_dma_params *dma_params[2];
98 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
101 __raw_writel(val, dev->base + reg);
104 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
106 return __raw_readl(dev->base + reg);
109 static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
111 struct snd_soc_pcm_runtime *rtd = substream->private_data;
112 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
115 /* Start the sample generator and enable transmitter/receiver */
116 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
117 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
118 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
119 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
121 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
122 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
124 /* Start frame sync */
125 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
126 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
127 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
130 static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
132 struct snd_soc_pcm_runtime *rtd = substream->private_data;
133 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
136 /* Reset transmitter/receiver and sample rate/frame sync generators */
137 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
138 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
139 DAVINCI_MCBSP_SPCR_FRST, 0);
140 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
141 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
143 MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
144 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
147 static int davinci_i2s_startup(struct snd_pcm_substream *substream)
149 struct snd_soc_pcm_runtime *rtd = substream->private_data;
150 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
151 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
153 cpu_dai->dma_data = dev->dma_params[substream->stream];
158 static int davinci_i2s_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai,
161 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
164 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
165 case SND_SOC_DAIFMT_CBS_CFS:
166 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
167 DAVINCI_MCBSP_PCR_FSXM |
168 DAVINCI_MCBSP_PCR_FSRM |
169 DAVINCI_MCBSP_PCR_CLKXM |
170 DAVINCI_MCBSP_PCR_CLKRM);
171 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
172 DAVINCI_MCBSP_SRGR_FSGM);
174 case SND_SOC_DAIFMT_CBM_CFM:
175 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
181 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
182 case SND_SOC_DAIFMT_IB_NF:
183 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
184 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
185 DAVINCI_MCBSP_PCR_CLKRP, 1);
186 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
188 case SND_SOC_DAIFMT_NB_IF:
189 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
190 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP |
191 DAVINCI_MCBSP_PCR_FSRP, 1);
192 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
194 case SND_SOC_DAIFMT_IB_IF:
195 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
196 MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
197 DAVINCI_MCBSP_PCR_CLKRP |
198 DAVINCI_MCBSP_PCR_FSXP |
199 DAVINCI_MCBSP_PCR_FSRP, 1);
200 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
202 case SND_SOC_DAIFMT_NB_NF:
211 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
212 struct snd_pcm_hw_params *params)
214 struct snd_soc_pcm_runtime *rtd = substream->private_data;
215 struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
216 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
217 struct snd_interval *i = NULL;
218 int mcbsp_word_length;
221 /* general line settings */
222 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
223 DAVINCI_MCBSP_SPCR_RINTM(3) |
224 DAVINCI_MCBSP_SPCR_XINTM(3) |
225 DAVINCI_MCBSP_SPCR_FREE);
226 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
227 DAVINCI_MCBSP_RCR_RFRLEN1(1) |
228 DAVINCI_MCBSP_RCR_RDATDLY(1));
229 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
230 DAVINCI_MCBSP_XCR_XFRLEN1(1) |
231 DAVINCI_MCBSP_XCR_XDATDLY(1) |
232 DAVINCI_MCBSP_XCR_XFIG);
234 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
235 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
236 MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
237 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
239 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
240 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
241 MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
242 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
244 /* Determine xfer data type */
245 switch (params_format(params)) {
246 case SNDRV_PCM_FORMAT_S8:
247 dma_params->data_type = 1;
248 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
250 case SNDRV_PCM_FORMAT_S16_LE:
251 dma_params->data_type = 2;
252 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
254 case SNDRV_PCM_FORMAT_S32_LE:
255 dma_params->data_type = 4;
256 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
259 printk(KERN_WARNING "davinci-i2s: unsupported PCM format");
263 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
264 MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
265 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
266 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
268 w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
269 MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
270 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
271 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
276 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
281 case SNDRV_PCM_TRIGGER_START:
282 case SNDRV_PCM_TRIGGER_RESUME:
283 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
284 davinci_mcbsp_start(substream);
286 case SNDRV_PCM_TRIGGER_STOP:
287 case SNDRV_PCM_TRIGGER_SUSPEND:
288 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
289 davinci_mcbsp_stop(substream);
298 static int davinci_i2s_probe(struct platform_device *pdev)
300 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
301 struct snd_soc_machine *machine = socdev->machine;
302 struct snd_soc_cpu_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
303 struct davinci_mcbsp_dev *dev;
304 struct resource *mem, *ioarea;
305 struct evm_snd_platform_data *pdata;
308 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
310 dev_err(&pdev->dev, "no mem resource?\n");
314 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
317 dev_err(&pdev->dev, "McBSP region already claimed\n");
321 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
324 goto err_release_region;
327 cpu_dai->private_data = dev;
329 dev->clk = clk_get(&pdev->dev, "McBSPCLK");
330 if (IS_ERR(dev->clk)) {
334 clk_enable(dev->clk);
336 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
337 pdata = pdev->dev.platform_data;
339 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
340 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
341 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
342 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
344 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
345 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
346 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
347 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
354 release_mem_region(mem->start, (mem->end - mem->start) + 1);
359 static void davinci_i2s_remove(struct platform_device *pdev)
361 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
362 struct snd_soc_machine *machine = socdev->machine;
363 struct snd_soc_cpu_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
364 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
365 struct resource *mem;
367 clk_disable(dev->clk);
373 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
374 release_mem_region(mem->start, (mem->end - mem->start) + 1);
377 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
379 struct snd_soc_cpu_dai davinci_i2s_dai = {
380 .name = "davinci-i2s",
382 .type = SND_SOC_DAI_I2S,
383 .probe = davinci_i2s_probe,
384 .remove = davinci_i2s_remove,
388 .rates = DAVINCI_I2S_RATES,
389 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
393 .rates = DAVINCI_I2S_RATES,
394 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
396 .startup = davinci_i2s_startup,
397 .trigger = davinci_i2s_trigger,
398 .hw_params = davinci_i2s_hw_params,},
400 .set_fmt = davinci_i2s_set_dai_fmt,
403 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
405 MODULE_AUTHOR("Vladimir Barinov");
406 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
407 MODULE_LICENSE("GPL");