git.oblomov.eu Git - linux-2.6/blob - drivers/pci/intel-iommu.c

   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17  * Copyright (C) 2006-2008 Intel Corporation
  18  * Author: Ashok Raj <ashok.raj@intel.com>
  19  * Author: Shaohua Li <shaohua.li@intel.com>
  20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  21  * Author: Fenghua Yu <fenghua.yu@intel.com>
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/bitmap.h>
  26 #include <linux/debugfs.h>
  27 #include <linux/slab.h>
  28 #include <linux/irq.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/pci.h>
  32 #include <linux/dmar.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/mempool.h>
  35 #include <linux/timer.h>
  36 #include <linux/iova.h>
  37 #include <linux/iommu.h>
  38 #include <linux/intel-iommu.h>
  39 #include <linux/sysdev.h>
  40 #include <asm/cacheflush.h>
  41 #include <asm/iommu.h>
  42 #include "pci.h"
  43
  44 #define ROOT_SIZE               VTD_PAGE_SIZE
  45 #define CONTEXT_SIZE            VTD_PAGE_SIZE
  46
  47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
  48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
  49
  50 #define IOAPIC_RANGE_START      (0xfee00000)
  51 #define IOAPIC_RANGE_END        (0xfeefffff)
  52 #define IOVA_START_ADDR         (0x1000)
  53
  54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
  55
  56 #define MAX_AGAW_WIDTH 64
  57
  58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
  59 #define DOMAIN_MAX_PFN(gaw)  ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
  60
  61 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
  62 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
  63 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
  64
  65
  66 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
  67    are never going to work. */
  68 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
  69 {
  70         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
  71 }
  72
  73 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
  74 {
  75         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
  76 }
  77 static inline unsigned long page_to_dma_pfn(struct page *pg)
  78 {
  79         return mm_to_dma_pfn(page_to_pfn(pg));
  80 }
  81 static inline unsigned long virt_to_dma_pfn(void *p)
  82 {
  83         return page_to_dma_pfn(virt_to_page(p));
  84 }
  85
  86 /* global iommu list, set NULL for ignored DMAR units */
  87 static struct intel_iommu **g_iommus;
  88
  89 static int rwbf_quirk;
  90
  91 /*
  92  * 0: Present
  93  * 1-11: Reserved
  94  * 12-63: Context Ptr (12 - (haw-1))
  95  * 64-127: Reserved
  96  */
  97 struct root_entry {
  98         u64     val;
  99         u64     rsvd1;
 100 };
 101 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
 102 static inline bool root_present(struct root_entry *root)
 103 {
 104         return (root->val & 1);
 105 }
 106 static inline void set_root_present(struct root_entry *root)
 107 {
 108         root->val |= 1;
 109 }
 110 static inline void set_root_value(struct root_entry *root, unsigned long value)
 111 {
 112         root->val |= value & VTD_PAGE_MASK;
 113 }
 114
 115 static inline struct context_entry *
 116 get_context_addr_from_root(struct root_entry *root)
 117 {
 118         return (struct context_entry *)
 119                 (root_present(root)?phys_to_virt(
 120                 root->val & VTD_PAGE_MASK) :
 121                 NULL);
 122 }
 123
 124 /*
 125  * low 64 bits:
 126  * 0: present
 127  * 1: fault processing disable
 128  * 2-3: translation type
 129  * 12-63: address space root
 130  * high 64 bits:
 131  * 0-2: address width
 132  * 3-6: aval
 133  * 8-23: domain id
 134  */
 135 struct context_entry {
 136         u64 lo;
 137         u64 hi;
 138 };
 139
 140 static inline bool context_present(struct context_entry *context)
 141 {
 142         return (context->lo & 1);
 143 }
 144 static inline void context_set_present(struct context_entry *context)
 145 {
 146         context->lo |= 1;
 147 }
 148
 149 static inline void context_set_fault_enable(struct context_entry *context)
 150 {
 151         context->lo &= (((u64)-1) << 2) | 1;
 152 }
 153
 154 static inline void context_set_translation_type(struct context_entry *context,
 155                                                 unsigned long value)
 156 {
 157         context->lo &= (((u64)-1) << 4) | 3;
 158         context->lo |= (value & 3) << 2;
 159 }
 160
 161 static inline void context_set_address_root(struct context_entry *context,
 162                                             unsigned long value)
 163 {
 164         context->lo |= value & VTD_PAGE_MASK;
 165 }
 166
 167 static inline void context_set_address_width(struct context_entry *context,
 168                                              unsigned long value)
 169 {
 170         context->hi |= value & 7;
 171 }
 172
 173 static inline void context_set_domain_id(struct context_entry *context,
 174                                          unsigned long value)
 175 {
 176         context->hi |= (value & ((1 << 16) - 1)) << 8;
 177 }
 178
 179 static inline void context_clear_entry(struct context_entry *context)
 180 {
 181         context->lo = 0;
 182         context->hi = 0;
 183 }
 184
 185 /*
 186  * 0: readable
 187  * 1: writable
 188  * 2-6: reserved
 189  * 7: super page
 190  * 8-10: available
 191  * 11: snoop behavior
 192  * 12-63: Host physcial address
 193  */
 194 struct dma_pte {
 195         u64 val;
 196 };
 197
 198 static inline void dma_clear_pte(struct dma_pte *pte)
 199 {
 200         pte->val = 0;
 201 }
 202
 203 static inline void dma_set_pte_readable(struct dma_pte *pte)
 204 {
 205         pte->val |= DMA_PTE_READ;
 206 }
 207
 208 static inline void dma_set_pte_writable(struct dma_pte *pte)
 209 {
 210         pte->val |= DMA_PTE_WRITE;
 211 }
 212
 213 static inline void dma_set_pte_snp(struct dma_pte *pte)
 214 {
 215         pte->val |= DMA_PTE_SNP;
 216 }
 217
 218 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
 219 {
 220         pte->val = (pte->val & ~3) | (prot & 3);
 221 }
 222
 223 static inline u64 dma_pte_addr(struct dma_pte *pte)
 224 {
 225         return (pte->val & VTD_PAGE_MASK);
 226 }
 227
 228 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
 229 {
 230         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
 231 }
 232
 233 static inline bool dma_pte_present(struct dma_pte *pte)
 234 {
 235         return (pte->val & 3) != 0;
 236 }
 237
 238 /*
 239  * This domain is a statically identity mapping domain.
 240  *      1. This domain creats a static 1:1 mapping to all usable memory.
 241  *      2. It maps to each iommu if successful.
 242  *      3. Each iommu mapps to this domain if successful.
 243  */
 244 struct dmar_domain *si_domain;
 245
 246 /* devices under the same p2p bridge are owned in one domain */
 247 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
 248
 249 /* domain represents a virtual machine, more than one devices
 250  * across iommus may be owned in one domain, e.g. kvm guest.
 251  */
 252 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
 253
 254 /* si_domain contains mulitple devices */
 255 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
 256
 257 struct dmar_domain {
 258         int     id;                     /* domain id */
 259         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
 260
 261         struct list_head devices;       /* all devices' list */
 262         struct iova_domain iovad;       /* iova's that belong to this domain */
 263
 264         struct dma_pte  *pgd;           /* virtual address */
 265         spinlock_t      mapping_lock;   /* page table lock */
 266         int             gaw;            /* max guest address width */
 267
 268         /* adjusted guest address width, 0 is level 2 30-bit */
 269         int             agaw;
 270
 271         int             flags;          /* flags to find out type of domain */
 272
 273         int             iommu_coherency;/* indicate coherency of iommu access */
 274         int             iommu_snooping; /* indicate snooping control feature*/
 275         int             iommu_count;    /* reference count of iommu */
 276         spinlock_t      iommu_lock;     /* protect iommu set in domain */
 277         u64             max_addr;       /* maximum mapped address */
 278 };
 279
 280 /* PCI domain-device relationship */
 281 struct device_domain_info {
 282         struct list_head link;  /* link to domain siblings */
 283         struct list_head global; /* link to global list */
 284         int segment;            /* PCI domain */
 285         u8 bus;                 /* PCI bus number */
 286         u8 devfn;               /* PCI devfn number */
 287         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
 288         struct intel_iommu *iommu; /* IOMMU used by this device */
 289         struct dmar_domain *domain; /* pointer to domain */
 290 };
 291
 292 static void flush_unmaps_timeout(unsigned long data);
 293
 294 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
 295
 296 #define HIGH_WATER_MARK 250
 297 struct deferred_flush_tables {
 298         int next;
 299         struct iova *iova[HIGH_WATER_MARK];
 300         struct dmar_domain *domain[HIGH_WATER_MARK];
 301 };
 302
 303 static struct deferred_flush_tables *deferred_flush;
 304
 305 /* bitmap for indexing intel_iommus */
 306 static int g_num_of_iommus;
 307
 308 static DEFINE_SPINLOCK(async_umap_flush_lock);
 309 static LIST_HEAD(unmaps_to_do);
 310
 311 static int timer_on;
 312 static long list_size;
 313
 314 static void domain_remove_dev_info(struct dmar_domain *domain);
 315
 316 #ifdef CONFIG_DMAR_DEFAULT_ON
 317 int dmar_disabled = 0;
 318 #else
 319 int dmar_disabled = 1;
 320 #endif /*CONFIG_DMAR_DEFAULT_ON*/
 321
 322 static int __initdata dmar_map_gfx = 1;
 323 static int dmar_forcedac;
 324 static int intel_iommu_strict;
 325
 326 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
 327 static DEFINE_SPINLOCK(device_domain_lock);
 328 static LIST_HEAD(device_domain_list);
 329
 330 static struct iommu_ops intel_iommu_ops;
 331
 332 static int __init intel_iommu_setup(char *str)
 333 {
 334         if (!str)
 335                 return -EINVAL;
 336         while (*str) {
 337                 if (!strncmp(str, "on", 2)) {
 338                         dmar_disabled = 0;
 339                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
 340                 } else if (!strncmp(str, "off", 3)) {
 341                         dmar_disabled = 1;
 342                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
 343                 } else if (!strncmp(str, "igfx_off", 8)) {
 344                         dmar_map_gfx = 0;
 345                         printk(KERN_INFO
 346                                 "Intel-IOMMU: disable GFX device mapping\n");
 347                 } else if (!strncmp(str, "forcedac", 8)) {
 348                         printk(KERN_INFO
 349                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
 350                         dmar_forcedac = 1;
 351                 } else if (!strncmp(str, "strict", 6)) {
 352                         printk(KERN_INFO
 353                                 "Intel-IOMMU: disable batched IOTLB flush\n");
 354                         intel_iommu_strict = 1;
 355                 }
 356
 357                 str += strcspn(str, ",");
 358                 while (*str == ',')
 359                         str++;
 360         }
 361         return 0;
 362 }
 363 __setup("intel_iommu=", intel_iommu_setup);
 364
 365 static struct kmem_cache *iommu_domain_cache;
 366 static struct kmem_cache *iommu_devinfo_cache;
 367 static struct kmem_cache *iommu_iova_cache;
 368
 369 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
 370 {
 371         unsigned int flags;
 372         void *vaddr;
 373
 374         /* trying to avoid low memory issues */
 375         flags = current->flags & PF_MEMALLOC;
 376         current->flags |= PF_MEMALLOC;
 377         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
 378         current->flags &= (~PF_MEMALLOC | flags);
 379         return vaddr;
 380 }
 381
 382
 383 static inline void *alloc_pgtable_page(void)
 384 {
 385         unsigned int flags;
 386         void *vaddr;
 387
 388         /* trying to avoid low memory issues */
 389         flags = current->flags & PF_MEMALLOC;
 390         current->flags |= PF_MEMALLOC;
 391         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
 392         current->flags &= (~PF_MEMALLOC | flags);
 393         return vaddr;
 394 }
 395
 396 static inline void free_pgtable_page(void *vaddr)
 397 {
 398         free_page((unsigned long)vaddr);
 399 }
 400
 401 static inline void *alloc_domain_mem(void)
 402 {
 403         return iommu_kmem_cache_alloc(iommu_domain_cache);
 404 }
 405
 406 static void free_domain_mem(void *vaddr)
 407 {
 408         kmem_cache_free(iommu_domain_cache, vaddr);
 409 }
 410
 411 static inline void * alloc_devinfo_mem(void)
 412 {
 413         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
 414 }
 415
 416 static inline void free_devinfo_mem(void *vaddr)
 417 {
 418         kmem_cache_free(iommu_devinfo_cache, vaddr);
 419 }
 420
 421 struct iova *alloc_iova_mem(void)
 422 {
 423         return iommu_kmem_cache_alloc(iommu_iova_cache);
 424 }
 425
 426 void free_iova_mem(struct iova *iova)
 427 {
 428         kmem_cache_free(iommu_iova_cache, iova);
 429 }
 430
 431
 432 static inline int width_to_agaw(int width);
 433
 434 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
 435 {
 436         unsigned long sagaw;
 437         int agaw = -1;
 438
 439         sagaw = cap_sagaw(iommu->cap);
 440         for (agaw = width_to_agaw(max_gaw);
 441              agaw >= 0; agaw--) {
 442                 if (test_bit(agaw, &sagaw))
 443                         break;
 444         }
 445
 446         return agaw;
 447 }
 448
 449 /*
 450  * Calculate max SAGAW for each iommu.
 451  */
 452 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
 453 {
 454         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
 455 }
 456
 457 /*
 458  * calculate agaw for each iommu.
 459  * "SAGAW" may be different across iommus, use a default agaw, and
 460  * get a supported less agaw for iommus that don't support the default agaw.
 461  */
 462 int iommu_calculate_agaw(struct intel_iommu *iommu)
 463 {
 464         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
 465 }
 466
 467 /* This functionin only returns single iommu in a domain */
 468 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
 469 {
 470         int iommu_id;
 471
 472         /* si_domain and vm domain should not get here. */
 473         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
 474         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
 475
 476         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 477         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
 478                 return NULL;
 479
 480         return g_iommus[iommu_id];
 481 }
 482
 483 static void domain_update_iommu_coherency(struct dmar_domain *domain)
 484 {
 485         int i;
 486
 487         domain->iommu_coherency = 1;
 488
 489         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 490         for (; i < g_num_of_iommus; ) {
 491                 if (!ecap_coherent(g_iommus[i]->ecap)) {
 492                         domain->iommu_coherency = 0;
 493                         break;
 494                 }
 495                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
 496         }
 497 }
 498
 499 static void domain_update_iommu_snooping(struct dmar_domain *domain)
 500 {
 501         int i;
 502
 503         domain->iommu_snooping = 1;
 504
 505         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 506         for (; i < g_num_of_iommus; ) {
 507                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
 508                         domain->iommu_snooping = 0;
 509                         break;
 510                 }
 511                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
 512         }
 513 }
 514
 515 /* Some capabilities may be different across iommus */
 516 static void domain_update_iommu_cap(struct dmar_domain *domain)
 517 {
 518         domain_update_iommu_coherency(domain);
 519         domain_update_iommu_snooping(domain);
 520 }
 521
 522 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
 523 {
 524         struct dmar_drhd_unit *drhd = NULL;
 525         int i;
 526
 527         for_each_drhd_unit(drhd) {
 528                 if (drhd->ignored)
 529                         continue;
 530                 if (segment != drhd->segment)
 531                         continue;
 532
 533                 for (i = 0; i < drhd->devices_cnt; i++) {
 534                         if (drhd->devices[i] &&
 535                             drhd->devices[i]->bus->number == bus &&
 536                             drhd->devices[i]->devfn == devfn)
 537                                 return drhd->iommu;
 538                         if (drhd->devices[i] &&
 539                             drhd->devices[i]->subordinate &&
 540                             drhd->devices[i]->subordinate->number <= bus &&
 541                             drhd->devices[i]->subordinate->subordinate >= bus)
 542                                 return drhd->iommu;
 543                 }
 544
 545                 if (drhd->include_all)
 546                         return drhd->iommu;
 547         }
 548
 549         return NULL;
 550 }
 551
 552 static void domain_flush_cache(struct dmar_domain *domain,
 553                                void *addr, int size)
 554 {
 555         if (!domain->iommu_coherency)
 556                 clflush_cache_range(addr, size);
 557 }
 558
 559 /* Gets context entry for a given bus and devfn */
 560 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
 561                 u8 bus, u8 devfn)
 562 {
 563         struct root_entry *root;
 564         struct context_entry *context;
 565         unsigned long phy_addr;
 566         unsigned long flags;
 567
 568         spin_lock_irqsave(&iommu->lock, flags);
 569         root = &iommu->root_entry[bus];
 570         context = get_context_addr_from_root(root);
 571         if (!context) {
 572                 context = (struct context_entry *)alloc_pgtable_page();
 573                 if (!context) {
 574                         spin_unlock_irqrestore(&iommu->lock, flags);
 575                         return NULL;
 576                 }
 577                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
 578                 phy_addr = virt_to_phys((void *)context);
 579                 set_root_value(root, phy_addr);
 580                 set_root_present(root);
 581                 __iommu_flush_cache(iommu, root, sizeof(*root));
 582         }
 583         spin_unlock_irqrestore(&iommu->lock, flags);
 584         return &context[devfn];
 585 }
 586
 587 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
 588 {
 589         struct root_entry *root;
 590         struct context_entry *context;
 591         int ret;
 592         unsigned long flags;
 593
 594         spin_lock_irqsave(&iommu->lock, flags);
 595         root = &iommu->root_entry[bus];
 596         context = get_context_addr_from_root(root);
 597         if (!context) {
 598                 ret = 0;
 599                 goto out;
 600         }
 601         ret = context_present(&context[devfn]);
 602 out:
 603         spin_unlock_irqrestore(&iommu->lock, flags);
 604         return ret;
 605 }
 606
 607 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
 608 {
 609         struct root_entry *root;
 610         struct context_entry *context;
 611         unsigned long flags;
 612
 613         spin_lock_irqsave(&iommu->lock, flags);
 614         root = &iommu->root_entry[bus];
 615         context = get_context_addr_from_root(root);
 616         if (context) {
 617                 context_clear_entry(&context[devfn]);
 618                 __iommu_flush_cache(iommu, &context[devfn], \
 619                         sizeof(*context));
 620         }
 621         spin_unlock_irqrestore(&iommu->lock, flags);
 622 }
 623
 624 static void free_context_table(struct intel_iommu *iommu)
 625 {
 626         struct root_entry *root;
 627         int i;
 628         unsigned long flags;
 629         struct context_entry *context;
 630
 631         spin_lock_irqsave(&iommu->lock, flags);
 632         if (!iommu->root_entry) {
 633                 goto out;
 634         }
 635         for (i = 0; i < ROOT_ENTRY_NR; i++) {
 636                 root = &iommu->root_entry[i];
 637                 context = get_context_addr_from_root(root);
 638                 if (context)
 639                         free_pgtable_page(context);
 640         }
 641         free_pgtable_page(iommu->root_entry);
 642         iommu->root_entry = NULL;
 643 out:
 644         spin_unlock_irqrestore(&iommu->lock, flags);
 645 }
 646
 647 /* page table handling */
 648 #define LEVEL_STRIDE            (9)
 649 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
 650
 651 static inline int agaw_to_level(int agaw)
 652 {
 653         return agaw + 2;
 654 }
 655
 656 static inline int agaw_to_width(int agaw)
 657 {
 658         return 30 + agaw * LEVEL_STRIDE;
 659
 660 }
 661
 662 static inline int width_to_agaw(int width)
 663 {
 664         return (width - 30) / LEVEL_STRIDE;
 665 }
 666
 667 static inline unsigned int level_to_offset_bits(int level)
 668 {
 669         return (level - 1) * LEVEL_STRIDE;
 670 }
 671
 672 static inline int pfn_level_offset(unsigned long pfn, int level)
 673 {
 674         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
 675 }
 676
 677 static inline unsigned long level_mask(int level)
 678 {
 679         return -1UL << level_to_offset_bits(level);
 680 }
 681
 682 static inline unsigned long level_size(int level)
 683 {
 684         return 1UL << level_to_offset_bits(level);
 685 }
 686
 687 static inline unsigned long align_to_level(unsigned long pfn, int level)
 688 {
 689         return (pfn + level_size(level) - 1) & level_mask(level);
 690 }
 691
 692 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
 693                                       unsigned long pfn)
 694 {
 695         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 696         struct dma_pte *parent, *pte = NULL;
 697         int level = agaw_to_level(domain->agaw);
 698         int offset;
 699         unsigned long flags;
 700
 701         BUG_ON(!domain->pgd);
 702         BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
 703         parent = domain->pgd;
 704
 705         spin_lock_irqsave(&domain->mapping_lock, flags);
 706         while (level > 0) {
 707                 void *tmp_page;
 708
 709                 offset = pfn_level_offset(pfn, level);
 710                 pte = &parent[offset];
 711                 if (level == 1)
 712                         break;
 713
 714                 if (!dma_pte_present(pte)) {
 715                         tmp_page = alloc_pgtable_page();
 716
 717                         if (!tmp_page) {
 718                                 spin_unlock_irqrestore(&domain->mapping_lock,
 719                                         flags);
 720                                 return NULL;
 721                         }
 722                         domain_flush_cache(domain, tmp_page, PAGE_SIZE);
 723                         dma_set_pte_pfn(pte, virt_to_dma_pfn(tmp_page));
 724                         /*
 725                          * high level table always sets r/w, last level page
 726                          * table control read/write
 727                          */
 728                         dma_set_pte_readable(pte);
 729                         dma_set_pte_writable(pte);
 730                         domain_flush_cache(domain, pte, sizeof(*pte));
 731                 }
 732                 parent = phys_to_virt(dma_pte_addr(pte));
 733                 level--;
 734         }
 735
 736         spin_unlock_irqrestore(&domain->mapping_lock, flags);
 737         return pte;
 738 }
 739
 740 /* return address's pte at specific level */
 741 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
 742                                          unsigned long pfn,
 743                                          int level)
 744 {
 745         struct dma_pte *parent, *pte = NULL;
 746         int total = agaw_to_level(domain->agaw);
 747         int offset;
 748
 749         parent = domain->pgd;
 750         while (level <= total) {
 751                 offset = pfn_level_offset(pfn, total);
 752                 pte = &parent[offset];
 753                 if (level == total)
 754                         return pte;
 755
 756                 if (!dma_pte_present(pte))
 757                         break;
 758                 parent = phys_to_virt(dma_pte_addr(pte));
 759                 total--;
 760         }
 761         return NULL;
 762 }
 763
 764 /* clear last level pte, a tlb flush should be followed */
 765 static void dma_pte_clear_range(struct dmar_domain *domain,
 766                                 unsigned long start_pfn,
 767                                 unsigned long last_pfn)
 768 {
 769         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 770         struct dma_pte *first_pte, *pte;
 771
 772         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
 773         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
 774
 775         /* we don't need lock here; nobody else touches the iova range */
 776         while (start_pfn <= last_pfn) {
 777                 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
 778                 if (!pte) {
 779                         start_pfn = align_to_level(start_pfn + 1, 2);
 780                         continue;
 781                 }
 782                 while (start_pfn <= last_pfn &&
 783                        (unsigned long)pte >> VTD_PAGE_SHIFT ==
 784                        (unsigned long)first_pte >> VTD_PAGE_SHIFT) {
 785                         dma_clear_pte(pte);
 786                         start_pfn++;
 787                         pte++;
 788                 }
 789                 domain_flush_cache(domain, first_pte,
 790                                    (void *)pte - (void *)first_pte);
 791         }
 792 }
 793
 794 /* free page table pages. last level pte should already be cleared */
 795 static void dma_pte_free_pagetable(struct dmar_domain *domain,
 796                                    unsigned long start_pfn,
 797                                    unsigned long last_pfn)
 798 {
 799         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 800         struct dma_pte *pte;
 801         int total = agaw_to_level(domain->agaw);
 802         int level;
 803         unsigned long tmp;
 804
 805         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
 806         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
 807
 808         /* we don't need lock here, nobody else touches the iova range */
 809         level = 2;
 810         while (level <= total) {
 811                 tmp = align_to_level(start_pfn, level);
 812
 813                 /* Only clear this pte/pmd if we're asked to clear its
 814                    _whole_ range */
 815                 if (tmp + level_size(level) - 1 > last_pfn)
 816                         return;
 817
 818                 while (tmp <= last_pfn) {
 819                         pte = dma_pfn_level_pte(domain, tmp, level);
 820                         if (pte) {
 821                                 free_pgtable_page(
 822                                         phys_to_virt(dma_pte_addr(pte)));
 823                                 dma_clear_pte(pte);
 824                                 domain_flush_cache(domain, pte, sizeof(*pte));
 825                         }
 826                         tmp += level_size(level);
 827                 }
 828                 level++;
 829         }
 830         /* free pgd */
 831         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
 832                 free_pgtable_page(domain->pgd);
 833                 domain->pgd = NULL;
 834         }
 835 }
 836
 837 /* iommu handling */
 838 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
 839 {
 840         struct root_entry *root;
 841         unsigned long flags;
 842
 843         root = (struct root_entry *)alloc_pgtable_page();
 844         if (!root)
 845                 return -ENOMEM;
 846
 847         __iommu_flush_cache(iommu, root, ROOT_SIZE);
 848
 849         spin_lock_irqsave(&iommu->lock, flags);
 850         iommu->root_entry = root;
 851         spin_unlock_irqrestore(&iommu->lock, flags);
 852
 853         return 0;
 854 }
 855
 856 static void iommu_set_root_entry(struct intel_iommu *iommu)
 857 {
 858         void *addr;
 859         u32 sts;
 860         unsigned long flag;
 861
 862         addr = iommu->root_entry;
 863
 864         spin_lock_irqsave(&iommu->register_lock, flag);
 865         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
 866
 867         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
 868
 869         /* Make sure hardware complete it */
 870         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 871                       readl, (sts & DMA_GSTS_RTPS), sts);
 872
 873         spin_unlock_irqrestore(&iommu->register_lock, flag);
 874 }
 875
 876 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
 877 {
 878         u32 val;
 879         unsigned long flag;
 880
 881         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
 882                 return;
 883
 884         spin_lock_irqsave(&iommu->register_lock, flag);
 885         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
 886
 887         /* Make sure hardware complete it */
 888         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 889                       readl, (!(val & DMA_GSTS_WBFS)), val);
 890
 891         spin_unlock_irqrestore(&iommu->register_lock, flag);
 892 }
 893
 894 /* return value determine if we need a write buffer flush */
 895 static void __iommu_flush_context(struct intel_iommu *iommu,
 896                                   u16 did, u16 source_id, u8 function_mask,
 897                                   u64 type)
 898 {
 899         u64 val = 0;
 900         unsigned long flag;
 901
 902         switch (type) {
 903         case DMA_CCMD_GLOBAL_INVL:
 904                 val = DMA_CCMD_GLOBAL_INVL;
 905                 break;
 906         case DMA_CCMD_DOMAIN_INVL:
 907                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
 908                 break;
 909         case DMA_CCMD_DEVICE_INVL:
 910                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
 911                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
 912                 break;
 913         default:
 914                 BUG();
 915         }
 916         val |= DMA_CCMD_ICC;
 917
 918         spin_lock_irqsave(&iommu->register_lock, flag);
 919         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
 920
 921         /* Make sure hardware complete it */
 922         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
 923                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
 924
 925         spin_unlock_irqrestore(&iommu->register_lock, flag);
 926 }
 927
 928 /* return value determine if we need a write buffer flush */
 929 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
 930                                 u64 addr, unsigned int size_order, u64 type)
 931 {
 932         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
 933         u64 val = 0, val_iva = 0;
 934         unsigned long flag;
 935
 936         switch (type) {
 937         case DMA_TLB_GLOBAL_FLUSH:
 938                 /* global flush doesn't need set IVA_REG */
 939                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
 940                 break;
 941         case DMA_TLB_DSI_FLUSH:
 942                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
 943                 break;
 944         case DMA_TLB_PSI_FLUSH:
 945                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
 946                 /* Note: always flush non-leaf currently */
 947                 val_iva = size_order | addr;
 948                 break;
 949         default:
 950                 BUG();
 951         }
 952         /* Note: set drain read/write */
 953 #if 0
 954         /*
 955          * This is probably to be super secure.. Looks like we can
 956          * ignore it without any impact.
 957          */
 958         if (cap_read_drain(iommu->cap))
 959                 val |= DMA_TLB_READ_DRAIN;
 960 #endif
 961         if (cap_write_drain(iommu->cap))
 962                 val |= DMA_TLB_WRITE_DRAIN;
 963
 964         spin_lock_irqsave(&iommu->register_lock, flag);
 965         /* Note: Only uses first TLB reg currently */
 966         if (val_iva)
 967                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
 968         dmar_writeq(iommu->reg + tlb_offset + 8, val);
 969
 970         /* Make sure hardware complete it */
 971         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
 972                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
 973
 974         spin_unlock_irqrestore(&iommu->register_lock, flag);
 975
 976         /* check IOTLB invalidation granularity */
 977         if (DMA_TLB_IAIG(val) == 0)
 978                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
 979         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
 980                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
 981                         (unsigned long long)DMA_TLB_IIRG(type),
 982                         (unsigned long long)DMA_TLB_IAIG(val));
 983 }
 984
 985 static struct device_domain_info *iommu_support_dev_iotlb(
 986         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
 987 {
 988         int found = 0;
 989         unsigned long flags;
 990         struct device_domain_info *info;
 991         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
 992
 993         if (!ecap_dev_iotlb_support(iommu->ecap))
 994                 return NULL;
 995
 996         if (!iommu->qi)
 997                 return NULL;
 998
 999         spin_lock_irqsave(&device_domain_lock, flags);
1000         list_for_each_entry(info, &domain->devices, link)
1001                 if (info->bus == bus && info->devfn == devfn) {
1002                         found = 1;
1003                         break;
1004                 }
1005         spin_unlock_irqrestore(&device_domain_lock, flags);
1006
1007         if (!found || !info->dev)
1008                 return NULL;
1009
1010         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1011                 return NULL;
1012
1013         if (!dmar_find_matched_atsr_unit(info->dev))
1014                 return NULL;
1015
1016         info->iommu = iommu;
1017
1018         return info;
1019 }
1020
1021 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1022 {
1023         if (!info)
1024                 return;
1025
1026         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1027 }
1028
1029 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1030 {
1031         if (!info->dev || !pci_ats_enabled(info->dev))
1032                 return;
1033
1034         pci_disable_ats(info->dev);
1035 }
1036
1037 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1038                                   u64 addr, unsigned mask)
1039 {
1040         u16 sid, qdep;
1041         unsigned long flags;
1042         struct device_domain_info *info;
1043
1044         spin_lock_irqsave(&device_domain_lock, flags);
1045         list_for_each_entry(info, &domain->devices, link) {
1046                 if (!info->dev || !pci_ats_enabled(info->dev))
1047                         continue;
1048
1049                 sid = info->bus << 8 | info->devfn;
1050                 qdep = pci_ats_queue_depth(info->dev);
1051                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1052         }
1053         spin_unlock_irqrestore(&device_domain_lock, flags);
1054 }
1055
1056 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1057                                   unsigned long pfn, unsigned int pages)
1058 {
1059         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1060         uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1061
1062         BUG_ON(pages == 0);
1063
1064         /*
1065          * Fallback to domain selective flush if no PSI support or the size is
1066          * too big.
1067          * PSI requires page size to be 2 ^ x, and the base address is naturally
1068          * aligned to the size
1069          */
1070         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1071                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1072                                                 DMA_TLB_DSI_FLUSH);
1073         else
1074                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1075                                                 DMA_TLB_PSI_FLUSH);
1076
1077         /*
1078          * In caching mode, domain ID 0 is reserved for non-present to present
1079          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1080          */
1081         if (!cap_caching_mode(iommu->cap) || did)
1082                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1083 }
1084
1085 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1086 {
1087         u32 pmen;
1088         unsigned long flags;
1089
1090         spin_lock_irqsave(&iommu->register_lock, flags);
1091         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1092         pmen &= ~DMA_PMEN_EPM;
1093         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1094
1095         /* wait for the protected region status bit to clear */
1096         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1097                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1098
1099         spin_unlock_irqrestore(&iommu->register_lock, flags);
1100 }
1101
1102 static int iommu_enable_translation(struct intel_iommu *iommu)
1103 {
1104         u32 sts;
1105         unsigned long flags;
1106
1107         spin_lock_irqsave(&iommu->register_lock, flags);
1108         iommu->gcmd |= DMA_GCMD_TE;
1109         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1110
1111         /* Make sure hardware complete it */
1112         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1113                       readl, (sts & DMA_GSTS_TES), sts);
1114
1115         spin_unlock_irqrestore(&iommu->register_lock, flags);
1116         return 0;
1117 }
1118
1119 static int iommu_disable_translation(struct intel_iommu *iommu)
1120 {
1121         u32 sts;
1122         unsigned long flag;
1123
1124         spin_lock_irqsave(&iommu->register_lock, flag);
1125         iommu->gcmd &= ~DMA_GCMD_TE;
1126         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1127
1128         /* Make sure hardware complete it */
1129         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1130                       readl, (!(sts & DMA_GSTS_TES)), sts);
1131
1132         spin_unlock_irqrestore(&iommu->register_lock, flag);
1133         return 0;
1134 }
1135
1136
1137 static int iommu_init_domains(struct intel_iommu *iommu)
1138 {
1139         unsigned long ndomains;
1140         unsigned long nlongs;
1141
1142         ndomains = cap_ndoms(iommu->cap);
1143         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1144         nlongs = BITS_TO_LONGS(ndomains);
1145
1146         /* TBD: there might be 64K domains,
1147          * consider other allocation for future chip
1148          */
1149         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1150         if (!iommu->domain_ids) {
1151                 printk(KERN_ERR "Allocating domain id array failed\n");
1152                 return -ENOMEM;
1153         }
1154         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1155                         GFP_KERNEL);
1156         if (!iommu->domains) {
1157                 printk(KERN_ERR "Allocating domain array failed\n");
1158                 kfree(iommu->domain_ids);
1159                 return -ENOMEM;
1160         }
1161
1162         spin_lock_init(&iommu->lock);
1163
1164         /*
1165          * if Caching mode is set, then invalid translations are tagged
1166          * with domainid 0. Hence we need to pre-allocate it.
1167          */
1168         if (cap_caching_mode(iommu->cap))
1169                 set_bit(0, iommu->domain_ids);
1170         return 0;
1171 }
1172
1173
1174 static void domain_exit(struct dmar_domain *domain);
1175 static void vm_domain_exit(struct dmar_domain *domain);
1176
1177 void free_dmar_iommu(struct intel_iommu *iommu)
1178 {
1179         struct dmar_domain *domain;
1180         int i;
1181         unsigned long flags;
1182
1183         i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1184         for (; i < cap_ndoms(iommu->cap); ) {
1185                 domain = iommu->domains[i];
1186                 clear_bit(i, iommu->domain_ids);
1187
1188                 spin_lock_irqsave(&domain->iommu_lock, flags);
1189                 if (--domain->iommu_count == 0) {
1190                         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1191                                 vm_domain_exit(domain);
1192                         else
1193                                 domain_exit(domain);
1194                 }
1195                 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1196
1197                 i = find_next_bit(iommu->domain_ids,
1198                         cap_ndoms(iommu->cap), i+1);
1199         }
1200
1201         if (iommu->gcmd & DMA_GCMD_TE)
1202                 iommu_disable_translation(iommu);
1203
1204         if (iommu->irq) {
1205                 set_irq_data(iommu->irq, NULL);
1206                 /* This will mask the irq */
1207                 free_irq(iommu->irq, iommu);
1208                 destroy_irq(iommu->irq);
1209         }
1210
1211         kfree(iommu->domains);
1212         kfree(iommu->domain_ids);
1213
1214         g_iommus[iommu->seq_id] = NULL;
1215
1216         /* if all iommus are freed, free g_iommus */
1217         for (i = 0; i < g_num_of_iommus; i++) {
1218                 if (g_iommus[i])
1219                         break;
1220         }
1221
1222         if (i == g_num_of_iommus)
1223                 kfree(g_iommus);
1224
1225         /* free context mapping */
1226         free_context_table(iommu);
1227 }
1228
1229 static struct dmar_domain *alloc_domain(void)
1230 {
1231         struct dmar_domain *domain;
1232
1233         domain = alloc_domain_mem();
1234         if (!domain)
1235                 return NULL;
1236
1237         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1238         domain->flags = 0;
1239
1240         return domain;
1241 }
1242
1243 static int iommu_attach_domain(struct dmar_domain *domain,
1244                                struct intel_iommu *iommu)
1245 {
1246         int num;
1247         unsigned long ndomains;
1248         unsigned long flags;
1249
1250         ndomains = cap_ndoms(iommu->cap);
1251
1252         spin_lock_irqsave(&iommu->lock, flags);
1253
1254         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1255         if (num >= ndomains) {
1256                 spin_unlock_irqrestore(&iommu->lock, flags);
1257                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1258                 return -ENOMEM;
1259         }
1260
1261         domain->id = num;
1262         set_bit(num, iommu->domain_ids);
1263         set_bit(iommu->seq_id, &domain->iommu_bmp);
1264         iommu->domains[num] = domain;
1265         spin_unlock_irqrestore(&iommu->lock, flags);
1266
1267         return 0;
1268 }
1269
1270 static void iommu_detach_domain(struct dmar_domain *domain,
1271                                 struct intel_iommu *iommu)
1272 {
1273         unsigned long flags;
1274         int num, ndomains;
1275         int found = 0;
1276
1277         spin_lock_irqsave(&iommu->lock, flags);
1278         ndomains = cap_ndoms(iommu->cap);
1279         num = find_first_bit(iommu->domain_ids, ndomains);
1280         for (; num < ndomains; ) {
1281                 if (iommu->domains[num] == domain) {
1282                         found = 1;
1283                         break;
1284                 }
1285                 num = find_next_bit(iommu->domain_ids,
1286                                     cap_ndoms(iommu->cap), num+1);
1287         }
1288
1289         if (found) {
1290                 clear_bit(num, iommu->domain_ids);
1291                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1292                 iommu->domains[num] = NULL;
1293         }
1294         spin_unlock_irqrestore(&iommu->lock, flags);
1295 }
1296
1297 static struct iova_domain reserved_iova_list;
1298 static struct lock_class_key reserved_alloc_key;
1299 static struct lock_class_key reserved_rbtree_key;
1300
1301 static void dmar_init_reserved_ranges(void)
1302 {
1303         struct pci_dev *pdev = NULL;
1304         struct iova *iova;
1305         int i;
1306
1307         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1308
1309         lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1310                 &reserved_alloc_key);
1311         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1312                 &reserved_rbtree_key);
1313
1314         /* IOAPIC ranges shouldn't be accessed by DMA */
1315         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1316                 IOVA_PFN(IOAPIC_RANGE_END));
1317         if (!iova)
1318                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1319
1320         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1321         for_each_pci_dev(pdev) {
1322                 struct resource *r;
1323
1324                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1325                         r = &pdev->resource[i];
1326                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1327                                 continue;
1328                         iova = reserve_iova(&reserved_iova_list,
1329                                             IOVA_PFN(r->start),
1330                                             IOVA_PFN(r->end));
1331                         if (!iova)
1332                                 printk(KERN_ERR "Reserve iova failed\n");
1333                 }
1334         }
1335
1336 }
1337
1338 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1339 {
1340         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1341 }
1342
1343 static inline int guestwidth_to_adjustwidth(int gaw)
1344 {
1345         int agaw;
1346         int r = (gaw - 12) % 9;
1347
1348         if (r == 0)
1349                 agaw = gaw;
1350         else
1351                 agaw = gaw + 9 - r;
1352         if (agaw > 64)
1353                 agaw = 64;
1354         return agaw;
1355 }
1356
1357 static int domain_init(struct dmar_domain *domain, int guest_width)
1358 {
1359         struct intel_iommu *iommu;
1360         int adjust_width, agaw;
1361         unsigned long sagaw;
1362
1363         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1364         spin_lock_init(&domain->mapping_lock);
1365         spin_lock_init(&domain->iommu_lock);
1366
1367         domain_reserve_special_ranges(domain);
1368
1369         /* calculate AGAW */
1370         iommu = domain_get_iommu(domain);
1371         if (guest_width > cap_mgaw(iommu->cap))
1372                 guest_width = cap_mgaw(iommu->cap);
1373         domain->gaw = guest_width;
1374         adjust_width = guestwidth_to_adjustwidth(guest_width);
1375         agaw = width_to_agaw(adjust_width);
1376         sagaw = cap_sagaw(iommu->cap);
1377         if (!test_bit(agaw, &sagaw)) {
1378                 /* hardware doesn't support it, choose a bigger one */
1379                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1380                 agaw = find_next_bit(&sagaw, 5, agaw);
1381                 if (agaw >= 5)
1382                         return -ENODEV;
1383         }
1384         domain->agaw = agaw;
1385         INIT_LIST_HEAD(&domain->devices);
1386
1387         if (ecap_coherent(iommu->ecap))
1388                 domain->iommu_coherency = 1;
1389         else
1390                 domain->iommu_coherency = 0;
1391
1392         if (ecap_sc_support(iommu->ecap))
1393                 domain->iommu_snooping = 1;
1394         else
1395                 domain->iommu_snooping = 0;
1396
1397         domain->iommu_count = 1;
1398
1399         /* always allocate the top pgd */
1400         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1401         if (!domain->pgd)
1402                 return -ENOMEM;
1403         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1404         return 0;
1405 }
1406
1407 static void domain_exit(struct dmar_domain *domain)
1408 {
1409         struct dmar_drhd_unit *drhd;
1410         struct intel_iommu *iommu;
1411
1412         /* Domain 0 is reserved, so dont process it */
1413         if (!domain)
1414                 return;
1415
1416         domain_remove_dev_info(domain);
1417         /* destroy iovas */
1418         put_iova_domain(&domain->iovad);
1419
1420         /* clear ptes */
1421         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1422
1423         /* free page tables */
1424         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1425
1426         for_each_active_iommu(iommu, drhd)
1427                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1428                         iommu_detach_domain(domain, iommu);
1429
1430         free_domain_mem(domain);
1431 }
1432
1433 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1434                                  u8 bus, u8 devfn, int translation)
1435 {
1436         struct context_entry *context;
1437         unsigned long flags;
1438         struct intel_iommu *iommu;
1439         struct dma_pte *pgd;
1440         unsigned long num;
1441         unsigned long ndomains;
1442         int id;
1443         int agaw;
1444         struct device_domain_info *info = NULL;
1445
1446         pr_debug("Set context mapping for %02x:%02x.%d\n",
1447                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1448
1449         BUG_ON(!domain->pgd);
1450         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1451                translation != CONTEXT_TT_MULTI_LEVEL);
1452
1453         iommu = device_to_iommu(segment, bus, devfn);
1454         if (!iommu)
1455                 return -ENODEV;
1456
1457         context = device_to_context_entry(iommu, bus, devfn);
1458         if (!context)
1459                 return -ENOMEM;
1460         spin_lock_irqsave(&iommu->lock, flags);
1461         if (context_present(context)) {
1462                 spin_unlock_irqrestore(&iommu->lock, flags);
1463                 return 0;
1464         }
1465
1466         id = domain->id;
1467         pgd = domain->pgd;
1468
1469         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1470             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1471                 int found = 0;
1472
1473                 /* find an available domain id for this device in iommu */
1474                 ndomains = cap_ndoms(iommu->cap);
1475                 num = find_first_bit(iommu->domain_ids, ndomains);
1476                 for (; num < ndomains; ) {
1477                         if (iommu->domains[num] == domain) {
1478                                 id = num;
1479                                 found = 1;
1480                                 break;
1481                         }
1482                         num = find_next_bit(iommu->domain_ids,
1483                                             cap_ndoms(iommu->cap), num+1);
1484                 }
1485
1486                 if (found == 0) {
1487                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1488                         if (num >= ndomains) {
1489                                 spin_unlock_irqrestore(&iommu->lock, flags);
1490                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1491                                 return -EFAULT;
1492                         }
1493
1494                         set_bit(num, iommu->domain_ids);
1495                         set_bit(iommu->seq_id, &domain->iommu_bmp);
1496                         iommu->domains[num] = domain;
1497                         id = num;
1498                 }
1499
1500                 /* Skip top levels of page tables for
1501                  * iommu which has less agaw than default.
1502                  */
1503                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1504                         pgd = phys_to_virt(dma_pte_addr(pgd));
1505                         if (!dma_pte_present(pgd)) {
1506                                 spin_unlock_irqrestore(&iommu->lock, flags);
1507                                 return -ENOMEM;
1508                         }
1509                 }
1510         }
1511
1512         context_set_domain_id(context, id);
1513
1514         if (translation != CONTEXT_TT_PASS_THROUGH) {
1515                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1516                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1517                                      CONTEXT_TT_MULTI_LEVEL;
1518         }
1519         /*
1520          * In pass through mode, AW must be programmed to indicate the largest
1521          * AGAW value supported by hardware. And ASR is ignored by hardware.
1522          */
1523         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1524                 context_set_address_width(context, iommu->msagaw);
1525         else {
1526                 context_set_address_root(context, virt_to_phys(pgd));
1527                 context_set_address_width(context, iommu->agaw);
1528         }
1529
1530         context_set_translation_type(context, translation);
1531         context_set_fault_enable(context);
1532         context_set_present(context);
1533         domain_flush_cache(domain, context, sizeof(*context));
1534
1535         /*
1536          * It's a non-present to present mapping. If hardware doesn't cache
1537          * non-present entry we only need to flush the write-buffer. If the
1538          * _does_ cache non-present entries, then it does so in the special
1539          * domain #0, which we have to flush:
1540          */
1541         if (cap_caching_mode(iommu->cap)) {
1542                 iommu->flush.flush_context(iommu, 0,
1543                                            (((u16)bus) << 8) | devfn,
1544                                            DMA_CCMD_MASK_NOBIT,
1545                                            DMA_CCMD_DEVICE_INVL);
1546                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1547         } else {
1548                 iommu_flush_write_buffer(iommu);
1549         }
1550         iommu_enable_dev_iotlb(info);
1551         spin_unlock_irqrestore(&iommu->lock, flags);
1552
1553         spin_lock_irqsave(&domain->iommu_lock, flags);
1554         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1555                 domain->iommu_count++;
1556                 domain_update_iommu_cap(domain);
1557         }
1558         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1559         return 0;
1560 }
1561
1562 static int
1563 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1564                         int translation)
1565 {
1566         int ret;
1567         struct pci_dev *tmp, *parent;
1568
1569         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1570                                          pdev->bus->number, pdev->devfn,
1571                                          translation);
1572         if (ret)
1573                 return ret;
1574
1575         /* dependent device mapping */
1576         tmp = pci_find_upstream_pcie_bridge(pdev);
1577         if (!tmp)
1578                 return 0;
1579         /* Secondary interface's bus number and devfn 0 */
1580         parent = pdev->bus->self;
1581         while (parent != tmp) {
1582                 ret = domain_context_mapping_one(domain,
1583                                                  pci_domain_nr(parent->bus),
1584                                                  parent->bus->number,
1585                                                  parent->devfn, translation);
1586                 if (ret)
1587                         return ret;
1588                 parent = parent->bus->self;
1589         }
1590         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1591                 return domain_context_mapping_one(domain,
1592                                         pci_domain_nr(tmp->subordinate),
1593                                         tmp->subordinate->number, 0,
1594                                         translation);
1595         else /* this is a legacy PCI bridge */
1596                 return domain_context_mapping_one(domain,
1597                                                   pci_domain_nr(tmp->bus),
1598                                                   tmp->bus->number,
1599                                                   tmp->devfn,
1600                                                   translation);
1601 }
1602
1603 static int domain_context_mapped(struct pci_dev *pdev)
1604 {
1605         int ret;
1606         struct pci_dev *tmp, *parent;
1607         struct intel_iommu *iommu;
1608
1609         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1610                                 pdev->devfn);
1611         if (!iommu)
1612                 return -ENODEV;
1613
1614         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1615         if (!ret)
1616                 return ret;
1617         /* dependent device mapping */
1618         tmp = pci_find_upstream_pcie_bridge(pdev);
1619         if (!tmp)
1620                 return ret;
1621         /* Secondary interface's bus number and devfn 0 */
1622         parent = pdev->bus->self;
1623         while (parent != tmp) {
1624                 ret = device_context_mapped(iommu, parent->bus->number,
1625                                             parent->devfn);
1626                 if (!ret)
1627                         return ret;
1628                 parent = parent->bus->self;
1629         }
1630         if (tmp->is_pcie)
1631                 return device_context_mapped(iommu, tmp->subordinate->number,
1632                                              0);
1633         else
1634                 return device_context_mapped(iommu, tmp->bus->number,
1635                                              tmp->devfn);
1636 }
1637
1638 static int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1639                               unsigned long phys_pfn, unsigned long nr_pages,
1640                               int prot)
1641 {
1642         struct dma_pte *pte;
1643         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1644
1645         BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1646
1647         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1648                 return -EINVAL;
1649
1650         while (nr_pages--) {
1651                 pte = pfn_to_dma_pte(domain, iov_pfn);
1652                 if (!pte)
1653                         return -ENOMEM;
1654                 /* We don't need lock here, nobody else
1655                  * touches the iova range
1656                  */
1657                 BUG_ON(dma_pte_addr(pte));
1658                 dma_set_pte_pfn(pte, phys_pfn);
1659                 dma_set_pte_prot(pte, prot);
1660                 if (prot & DMA_PTE_SNP)
1661                         dma_set_pte_snp(pte);
1662                 domain_flush_cache(domain, pte, sizeof(*pte));
1663                 iov_pfn++;
1664                 phys_pfn++;
1665         }
1666         return 0;
1667 }
1668
1669 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1670 {
1671         if (!iommu)
1672                 return;
1673
1674         clear_context_table(iommu, bus, devfn);
1675         iommu->flush.flush_context(iommu, 0, 0, 0,
1676                                            DMA_CCMD_GLOBAL_INVL);
1677         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1678 }
1679
1680 static void domain_remove_dev_info(struct dmar_domain *domain)
1681 {
1682         struct device_domain_info *info;
1683         unsigned long flags;
1684         struct intel_iommu *iommu;
1685
1686         spin_lock_irqsave(&device_domain_lock, flags);
1687         while (!list_empty(&domain->devices)) {
1688                 info = list_entry(domain->devices.next,
1689                         struct device_domain_info, link);
1690                 list_del(&info->link);
1691                 list_del(&info->global);
1692                 if (info->dev)
1693                         info->dev->dev.archdata.iommu = NULL;
1694                 spin_unlock_irqrestore(&device_domain_lock, flags);
1695
1696                 iommu_disable_dev_iotlb(info);
1697                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1698                 iommu_detach_dev(iommu, info->bus, info->devfn);
1699                 free_devinfo_mem(info);
1700
1701                 spin_lock_irqsave(&device_domain_lock, flags);
1702         }
1703         spin_unlock_irqrestore(&device_domain_lock, flags);
1704 }
1705
1706 /*
1707  * find_domain
1708  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1709  */
1710 static struct dmar_domain *
1711 find_domain(struct pci_dev *pdev)
1712 {
1713         struct device_domain_info *info;
1714
1715         /* No lock here, assumes no domain exit in normal case */
1716         info = pdev->dev.archdata.iommu;
1717         if (info)
1718                 return info->domain;
1719         return NULL;
1720 }
1721
1722 /* domain is initialized */
1723 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1724 {
1725         struct dmar_domain *domain, *found = NULL;
1726         struct intel_iommu *iommu;
1727         struct dmar_drhd_unit *drhd;
1728         struct device_domain_info *info, *tmp;
1729         struct pci_dev *dev_tmp;
1730         unsigned long flags;
1731         int bus = 0, devfn = 0;
1732         int segment;
1733         int ret;
1734
1735         domain = find_domain(pdev);
1736         if (domain)
1737                 return domain;
1738
1739         segment = pci_domain_nr(pdev->bus);
1740
1741         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1742         if (dev_tmp) {
1743                 if (dev_tmp->is_pcie) {
1744                         bus = dev_tmp->subordinate->number;
1745                         devfn = 0;
1746                 } else {
1747                         bus = dev_tmp->bus->number;
1748                         devfn = dev_tmp->devfn;
1749                 }
1750                 spin_lock_irqsave(&device_domain_lock, flags);
1751                 list_for_each_entry(info, &device_domain_list, global) {
1752                         if (info->segment == segment &&
1753                             info->bus == bus && info->devfn == devfn) {
1754                                 found = info->domain;
1755                                 break;
1756                         }
1757                 }
1758                 spin_unlock_irqrestore(&device_domain_lock, flags);
1759                 /* pcie-pci bridge already has a domain, uses it */
1760                 if (found) {
1761                         domain = found;
1762                         goto found_domain;
1763                 }
1764         }
1765
1766         domain = alloc_domain();
1767         if (!domain)
1768                 goto error;
1769
1770         /* Allocate new domain for the device */
1771         drhd = dmar_find_matched_drhd_unit(pdev);
1772         if (!drhd) {
1773                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1774                         pci_name(pdev));
1775                 return NULL;
1776         }
1777         iommu = drhd->iommu;
1778
1779         ret = iommu_attach_domain(domain, iommu);
1780         if (ret) {
1781                 domain_exit(domain);
1782                 goto error;
1783         }
1784
1785         if (domain_init(domain, gaw)) {
1786                 domain_exit(domain);
1787                 goto error;
1788         }
1789
1790         /* register pcie-to-pci device */
1791         if (dev_tmp) {
1792                 info = alloc_devinfo_mem();
1793                 if (!info) {
1794                         domain_exit(domain);
1795                         goto error;
1796                 }
1797                 info->segment = segment;
1798                 info->bus = bus;
1799                 info->devfn = devfn;
1800                 info->dev = NULL;
1801                 info->domain = domain;
1802                 /* This domain is shared by devices under p2p bridge */
1803                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1804
1805                 /* pcie-to-pci bridge already has a domain, uses it */
1806                 found = NULL;
1807                 spin_lock_irqsave(&device_domain_lock, flags);
1808                 list_for_each_entry(tmp, &device_domain_list, global) {
1809                         if (tmp->segment == segment &&
1810                             tmp->bus == bus && tmp->devfn == devfn) {
1811                                 found = tmp->domain;
1812                                 break;
1813                         }
1814                 }
1815                 if (found) {
1816                         free_devinfo_mem(info);
1817                         domain_exit(domain);
1818                         domain = found;
1819                 } else {
1820                         list_add(&info->link, &domain->devices);
1821                         list_add(&info->global, &device_domain_list);
1822                 }
1823                 spin_unlock_irqrestore(&device_domain_lock, flags);
1824         }
1825
1826 found_domain:
1827         info = alloc_devinfo_mem();
1828         if (!info)
1829                 goto error;
1830         info->segment = segment;
1831         info->bus = pdev->bus->number;
1832         info->devfn = pdev->devfn;
1833         info->dev = pdev;
1834         info->domain = domain;
1835         spin_lock_irqsave(&device_domain_lock, flags);
1836         /* somebody is fast */
1837         found = find_domain(pdev);
1838         if (found != NULL) {
1839                 spin_unlock_irqrestore(&device_domain_lock, flags);
1840                 if (found != domain) {
1841                         domain_exit(domain);
1842                         domain = found;
1843                 }
1844                 free_devinfo_mem(info);
1845                 return domain;
1846         }
1847         list_add(&info->link, &domain->devices);
1848         list_add(&info->global, &device_domain_list);
1849         pdev->dev.archdata.iommu = info;
1850         spin_unlock_irqrestore(&device_domain_lock, flags);
1851         return domain;
1852 error:
1853         /* recheck it here, maybe others set it */
1854         return find_domain(pdev);
1855 }
1856
1857 static int iommu_identity_mapping;
1858
1859 static int iommu_domain_identity_map(struct dmar_domain *domain,
1860                                      unsigned long long start,
1861                                      unsigned long long end)
1862 {
1863         unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1864         unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1865
1866         if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1867                           dma_to_mm_pfn(last_vpfn))) {
1868                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1869                 return -ENOMEM;
1870         }
1871
1872         pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1873                  start, end, domain->id);
1874         /*
1875          * RMRR range might have overlap with physical memory range,
1876          * clear it first
1877          */
1878         dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1879
1880         return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1881                                   last_vpfn - first_vpfn + 1,
1882                                   DMA_PTE_READ|DMA_PTE_WRITE);
1883 }
1884
1885 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1886                                       unsigned long long start,
1887                                       unsigned long long end)
1888 {
1889         struct dmar_domain *domain;
1890         int ret;
1891
1892         printk(KERN_INFO
1893                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1894                pci_name(pdev), start, end);
1895
1896         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1897         if (!domain)
1898                 return -ENOMEM;
1899
1900         ret = iommu_domain_identity_map(domain, start, end);
1901         if (ret)
1902                 goto error;
1903
1904         /* context entry init */
1905         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1906         if (ret)
1907                 goto error;
1908
1909         return 0;
1910
1911  error:
1912         domain_exit(domain);
1913         return ret;
1914 }
1915
1916 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1917         struct pci_dev *pdev)
1918 {
1919         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1920                 return 0;
1921         return iommu_prepare_identity_map(pdev, rmrr->base_address,
1922                 rmrr->end_address + 1);
1923 }
1924
1925 #ifdef CONFIG_DMAR_FLOPPY_WA
1926 static inline void iommu_prepare_isa(void)
1927 {
1928         struct pci_dev *pdev;
1929         int ret;
1930
1931         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1932         if (!pdev)
1933                 return;
1934
1935         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
1936         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1937
1938         if (ret)
1939                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
1940                        "floppy might not work\n");
1941
1942 }
1943 #else
1944 static inline void iommu_prepare_isa(void)
1945 {
1946         return;
1947 }
1948 #endif /* !CONFIG_DMAR_FLPY_WA */
1949
1950 /* Initialize each context entry as pass through.*/
1951 static int __init init_context_pass_through(void)
1952 {
1953         struct pci_dev *pdev = NULL;
1954         struct dmar_domain *domain;
1955         int ret;
1956
1957         for_each_pci_dev(pdev) {
1958                 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1959                 ret = domain_context_mapping(domain, pdev,
1960                                              CONTEXT_TT_PASS_THROUGH);
1961                 if (ret)
1962                         return ret;
1963         }
1964         return 0;
1965 }
1966
1967 static int md_domain_init(struct dmar_domain *domain, int guest_width);
1968
1969 static int __init si_domain_work_fn(unsigned long start_pfn,
1970                                     unsigned long end_pfn, void *datax)
1971 {
1972         int *ret = datax;
1973
1974         *ret = iommu_domain_identity_map(si_domain,
1975                                          (uint64_t)start_pfn << PAGE_SHIFT,
1976                                          (uint64_t)end_pfn << PAGE_SHIFT);
1977         return *ret;
1978
1979 }
1980
1981 static int si_domain_init(void)
1982 {
1983         struct dmar_drhd_unit *drhd;
1984         struct intel_iommu *iommu;
1985         int nid, ret = 0;
1986
1987         si_domain = alloc_domain();
1988         if (!si_domain)
1989                 return -EFAULT;
1990
1991         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
1992
1993         for_each_active_iommu(iommu, drhd) {
1994                 ret = iommu_attach_domain(si_domain, iommu);
1995                 if (ret) {
1996                         domain_exit(si_domain);
1997                         return -EFAULT;
1998                 }
1999         }
2000
2001         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2002                 domain_exit(si_domain);
2003                 return -EFAULT;
2004         }
2005
2006         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2007
2008         for_each_online_node(nid) {
2009                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2010                 if (ret)
2011                         return ret;
2012         }
2013
2014         return 0;
2015 }
2016
2017 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2018                                           struct pci_dev *pdev);
2019 static int identity_mapping(struct pci_dev *pdev)
2020 {
2021         struct device_domain_info *info;
2022
2023         if (likely(!iommu_identity_mapping))
2024                 return 0;
2025
2026
2027         list_for_each_entry(info, &si_domain->devices, link)
2028                 if (info->dev == pdev)
2029                         return 1;
2030         return 0;
2031 }
2032
2033 static int domain_add_dev_info(struct dmar_domain *domain,
2034                                   struct pci_dev *pdev)
2035 {
2036         struct device_domain_info *info;
2037         unsigned long flags;
2038
2039         info = alloc_devinfo_mem();
2040         if (!info)
2041                 return -ENOMEM;
2042
2043         info->segment = pci_domain_nr(pdev->bus);
2044         info->bus = pdev->bus->number;
2045         info->devfn = pdev->devfn;
2046         info->dev = pdev;
2047         info->domain = domain;
2048
2049         spin_lock_irqsave(&device_domain_lock, flags);
2050         list_add(&info->link, &domain->devices);
2051         list_add(&info->global, &device_domain_list);
2052         pdev->dev.archdata.iommu = info;
2053         spin_unlock_irqrestore(&device_domain_lock, flags);
2054
2055         return 0;
2056 }
2057
2058 static int iommu_prepare_static_identity_mapping(void)
2059 {
2060         struct pci_dev *pdev = NULL;
2061         int ret;
2062
2063         ret = si_domain_init();
2064         if (ret)
2065                 return -EFAULT;
2066
2067         for_each_pci_dev(pdev) {
2068                 printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2069                        pci_name(pdev));
2070
2071                 ret = domain_context_mapping(si_domain, pdev,
2072                                              CONTEXT_TT_MULTI_LEVEL);
2073                 if (ret)
2074                         return ret;
2075                 ret = domain_add_dev_info(si_domain, pdev);
2076                 if (ret)
2077                         return ret;
2078         }
2079
2080         return 0;
2081 }
2082
2083 int __init init_dmars(void)
2084 {
2085         struct dmar_drhd_unit *drhd;
2086         struct dmar_rmrr_unit *rmrr;
2087         struct pci_dev *pdev;
2088         struct intel_iommu *iommu;
2089         int i, ret;
2090         int pass_through = 1;
2091
2092         /*
2093          * In case pass through can not be enabled, iommu tries to use identity
2094          * mapping.
2095          */
2096         if (iommu_pass_through)
2097                 iommu_identity_mapping = 1;
2098
2099         /*
2100          * for each drhd
2101          *    allocate root
2102          *    initialize and program root entry to not present
2103          * endfor
2104          */
2105         for_each_drhd_unit(drhd) {
2106                 g_num_of_iommus++;
2107                 /*
2108                  * lock not needed as this is only incremented in the single
2109                  * threaded kernel __init code path all other access are read
2110                  * only
2111                  */
2112         }
2113
2114         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2115                         GFP_KERNEL);
2116         if (!g_iommus) {
2117                 printk(KERN_ERR "Allocating global iommu array failed\n");
2118                 ret = -ENOMEM;
2119                 goto error;
2120         }
2121
2122         deferred_flush = kzalloc(g_num_of_iommus *
2123                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2124         if (!deferred_flush) {
2125                 kfree(g_iommus);
2126                 ret = -ENOMEM;
2127                 goto error;
2128         }
2129
2130         for_each_drhd_unit(drhd) {
2131                 if (drhd->ignored)
2132                         continue;
2133
2134                 iommu = drhd->iommu;
2135                 g_iommus[iommu->seq_id] = iommu;
2136
2137                 ret = iommu_init_domains(iommu);
2138                 if (ret)
2139                         goto error;
2140
2141                 /*
2142                  * TBD:
2143                  * we could share the same root & context tables
2144                  * amoung all IOMMU's. Need to Split it later.
2145                  */
2146                 ret = iommu_alloc_root_entry(iommu);
2147                 if (ret) {
2148                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2149                         goto error;
2150                 }
2151                 if (!ecap_pass_through(iommu->ecap))
2152                         pass_through = 0;
2153         }
2154         if (iommu_pass_through)
2155                 if (!pass_through) {
2156                         printk(KERN_INFO
2157                                "Pass Through is not supported by hardware.\n");
2158                         iommu_pass_through = 0;
2159                 }
2160
2161         /*
2162          * Start from the sane iommu hardware state.
2163          */
2164         for_each_drhd_unit(drhd) {
2165                 if (drhd->ignored)
2166                         continue;
2167
2168                 iommu = drhd->iommu;
2169
2170                 /*
2171                  * If the queued invalidation is already initialized by us
2172                  * (for example, while enabling interrupt-remapping) then
2173                  * we got the things already rolling from a sane state.
2174                  */
2175                 if (iommu->qi)
2176                         continue;
2177
2178                 /*
2179                  * Clear any previous faults.
2180                  */
2181                 dmar_fault(-1, iommu);
2182                 /*
2183                  * Disable queued invalidation if supported and already enabled
2184                  * before OS handover.
2185                  */
2186                 dmar_disable_qi(iommu);
2187         }
2188
2189         for_each_drhd_unit(drhd) {
2190                 if (drhd->ignored)
2191                         continue;
2192
2193                 iommu = drhd->iommu;
2194
2195                 if (dmar_enable_qi(iommu)) {
2196                         /*
2197                          * Queued Invalidate not enabled, use Register Based
2198                          * Invalidate
2199                          */
2200                         iommu->flush.flush_context = __iommu_flush_context;
2201                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2202                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2203                                "invalidation\n",
2204                                (unsigned long long)drhd->reg_base_addr);
2205                 } else {
2206                         iommu->flush.flush_context = qi_flush_context;
2207                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2208                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2209                                "invalidation\n",
2210                                (unsigned long long)drhd->reg_base_addr);
2211                 }
2212         }
2213
2214         /*
2215          * If pass through is set and enabled, context entries of all pci
2216          * devices are intialized by pass through translation type.
2217          */
2218         if (iommu_pass_through) {
2219                 ret = init_context_pass_through();
2220                 if (ret) {
2221                         printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2222                         iommu_pass_through = 0;
2223                 }
2224         }
2225
2226         /*
2227          * If pass through is not set or not enabled, setup context entries for
2228          * identity mappings for rmrr, gfx, and isa and may fall back to static
2229          * identity mapping if iommu_identity_mapping is set.
2230          */
2231         if (!iommu_pass_through) {
2232                 if (iommu_identity_mapping)
2233                         iommu_prepare_static_identity_mapping();
2234                 /*
2235                  * For each rmrr
2236                  *   for each dev attached to rmrr
2237                  *   do
2238                  *     locate drhd for dev, alloc domain for dev
2239                  *     allocate free domain
2240                  *     allocate page table entries for rmrr
2241                  *     if context not allocated for bus
2242                  *           allocate and init context
2243                  *           set present in root table for this bus
2244                  *     init context with domain, translation etc
2245                  *    endfor
2246                  * endfor
2247                  */
2248                 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2249                 for_each_rmrr_units(rmrr) {
2250                         for (i = 0; i < rmrr->devices_cnt; i++) {
2251                                 pdev = rmrr->devices[i];
2252                                 /*
2253                                  * some BIOS lists non-exist devices in DMAR
2254                                  * table.
2255                                  */
2256                                 if (!pdev)
2257                                         continue;
2258                                 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2259                                 if (ret)
2260                                         printk(KERN_ERR
2261                                  "IOMMU: mapping reserved region failed\n");
2262                         }
2263                 }
2264
2265                 iommu_prepare_isa();
2266         }
2267
2268         /*
2269          * for each drhd
2270          *   enable fault log
2271          *   global invalidate context cache
2272          *   global invalidate iotlb
2273          *   enable translation
2274          */
2275         for_each_drhd_unit(drhd) {
2276                 if (drhd->ignored)
2277                         continue;
2278                 iommu = drhd->iommu;
2279
2280                 iommu_flush_write_buffer(iommu);
2281
2282                 ret = dmar_set_interrupt(iommu);
2283                 if (ret)
2284                         goto error;
2285
2286                 iommu_set_root_entry(iommu);
2287
2288                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2289                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2290                 iommu_disable_protect_mem_regions(iommu);
2291
2292                 ret = iommu_enable_translation(iommu);
2293                 if (ret)
2294                         goto error;
2295         }
2296
2297         return 0;
2298 error:
2299         for_each_drhd_unit(drhd) {
2300                 if (drhd->ignored)
2301                         continue;
2302                 iommu = drhd->iommu;
2303                 free_iommu(iommu);
2304         }
2305         kfree(g_iommus);
2306         return ret;
2307 }
2308
2309 static inline unsigned long aligned_nrpages(unsigned long host_addr,
2310                                             size_t size)
2311 {
2312         host_addr &= ~PAGE_MASK;
2313         host_addr += size + PAGE_SIZE - 1;
2314
2315         return host_addr >> VTD_PAGE_SHIFT;
2316 }
2317
2318 struct iova *
2319 iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
2320 {
2321         struct iova *piova;
2322
2323         /* Make sure it's in range */
2324         end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
2325         if (!size || (IOVA_START_ADDR + size > end))
2326                 return NULL;
2327
2328         piova = alloc_iova(&domain->iovad,
2329                         size >> PAGE_SHIFT, IOVA_PFN(end), 1);
2330         return piova;
2331 }
2332
2333 static struct iova *
2334 __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
2335                    size_t size, u64 dma_mask)
2336 {
2337         struct pci_dev *pdev = to_pci_dev(dev);
2338         struct iova *iova = NULL;
2339
2340         if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
2341                 iova = iommu_alloc_iova(domain, size, dma_mask);
2342         else {
2343                 /*
2344                  * First try to allocate an io virtual address in
2345                  * DMA_BIT_MASK(32) and if that fails then try allocating
2346                  * from higher range
2347                  */
2348                 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
2349                 if (!iova)
2350                         iova = iommu_alloc_iova(domain, size, dma_mask);
2351         }
2352
2353         if (!iova) {
2354                 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
2355                 return NULL;
2356         }
2357
2358         return iova;
2359 }
2360
2361 static struct dmar_domain *
2362 get_valid_domain_for_dev(struct pci_dev *pdev)
2363 {
2364         struct dmar_domain *domain;
2365         int ret;
2366
2367         domain = get_domain_for_dev(pdev,
2368                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2369         if (!domain) {
2370                 printk(KERN_ERR
2371                         "Allocating domain for %s failed", pci_name(pdev));
2372                 return NULL;
2373         }
2374
2375         /* make sure context mapping is ok */
2376         if (unlikely(!domain_context_mapped(pdev))) {
2377                 ret = domain_context_mapping(domain, pdev,
2378                                              CONTEXT_TT_MULTI_LEVEL);
2379                 if (ret) {
2380                         printk(KERN_ERR
2381                                 "Domain context map for %s failed",
2382                                 pci_name(pdev));
2383                         return NULL;
2384                 }
2385         }
2386
2387         return domain;
2388 }
2389
2390 static int iommu_dummy(struct pci_dev *pdev)
2391 {
2392         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2393 }
2394
2395 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2396 static int iommu_no_mapping(struct pci_dev *pdev)
2397 {
2398         int found;
2399
2400         if (!iommu_identity_mapping)
2401                 return iommu_dummy(pdev);
2402
2403         found = identity_mapping(pdev);
2404         if (found) {
2405                 if (pdev->dma_mask > DMA_BIT_MASK(32))
2406                         return 1;
2407                 else {
2408                         /*
2409                          * 32 bit DMA is removed from si_domain and fall back
2410                          * to non-identity mapping.
2411                          */
2412                         domain_remove_one_dev_info(si_domain, pdev);
2413                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2414                                pci_name(pdev));
2415                         return 0;
2416                 }
2417         } else {
2418                 /*
2419                  * In case of a detached 64 bit DMA device from vm, the device
2420                  * is put into si_domain for identity mapping.
2421                  */
2422                 if (pdev->dma_mask > DMA_BIT_MASK(32)) {
2423                         int ret;
2424                         ret = domain_add_dev_info(si_domain, pdev);
2425                         if (!ret) {
2426                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2427                                        pci_name(pdev));
2428                                 return 1;
2429                         }
2430                 }
2431         }
2432
2433         return iommu_dummy(pdev);
2434 }
2435
2436 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2437                                      size_t size, int dir, u64 dma_mask)
2438 {
2439         struct pci_dev *pdev = to_pci_dev(hwdev);
2440         struct dmar_domain *domain;
2441         phys_addr_t start_paddr;
2442         struct iova *iova;
2443         int prot = 0;
2444         int ret;
2445         struct intel_iommu *iommu;
2446
2447         BUG_ON(dir == DMA_NONE);
2448
2449         if (iommu_no_mapping(pdev))
2450                 return paddr;
2451
2452         domain = get_valid_domain_for_dev(pdev);
2453         if (!domain)
2454                 return 0;
2455
2456         iommu = domain_get_iommu(domain);
2457         size = aligned_nrpages(paddr, size);
2458
2459         iova = __intel_alloc_iova(hwdev, domain, size << VTD_PAGE_SHIFT, pdev->dma_mask);
2460         if (!iova)
2461                 goto error;
2462
2463         /*
2464          * Check if DMAR supports zero-length reads on write only
2465          * mappings..
2466          */
2467         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2468                         !cap_zlr(iommu->cap))
2469                 prot |= DMA_PTE_READ;
2470         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2471                 prot |= DMA_PTE_WRITE;
2472         /*
2473          * paddr - (paddr + size) might be partial page, we should map the whole
2474          * page.  Note: if two part of one page are separately mapped, we
2475          * might have two guest_addr mapping to the same host paddr, but this
2476          * is not a big problem
2477          */
2478         ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2479                                  paddr >> VTD_PAGE_SHIFT, size, prot);
2480         if (ret)
2481                 goto error;
2482
2483         /* it's a non-present to present mapping. Only flush if caching mode */
2484         if (cap_caching_mode(iommu->cap))
2485                 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2486         else
2487                 iommu_flush_write_buffer(iommu);
2488
2489         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2490         start_paddr += paddr & ~PAGE_MASK;
2491         return start_paddr;
2492
2493 error:
2494         if (iova)
2495                 __free_iova(&domain->iovad, iova);
2496         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2497                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2498         return 0;
2499 }
2500
2501 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2502                                  unsigned long offset, size_t size,
2503                                  enum dma_data_direction dir,
2504                                  struct dma_attrs *attrs)
2505 {
2506         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2507                                   dir, to_pci_dev(dev)->dma_mask);
2508 }
2509
2510 static void flush_unmaps(void)
2511 {
2512         int i, j;
2513
2514         timer_on = 0;
2515
2516         /* just flush them all */
2517         for (i = 0; i < g_num_of_iommus; i++) {
2518                 struct intel_iommu *iommu = g_iommus[i];
2519                 if (!iommu)
2520                         continue;
2521
2522                 if (!deferred_flush[i].next)
2523                         continue;
2524
2525                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2526                                          DMA_TLB_GLOBAL_FLUSH);
2527                 for (j = 0; j < deferred_flush[i].next; j++) {
2528                         unsigned long mask;
2529                         struct iova *iova = deferred_flush[i].iova[j];
2530
2531                         mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2532                         mask = ilog2(mask >> VTD_PAGE_SHIFT);
2533                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2534                                         iova->pfn_lo << PAGE_SHIFT, mask);
2535                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2536                 }
2537                 deferred_flush[i].next = 0;
2538         }
2539
2540         list_size = 0;
2541 }
2542
2543 static void flush_unmaps_timeout(unsigned long data)
2544 {
2545         unsigned long flags;
2546
2547         spin_lock_irqsave(&async_umap_flush_lock, flags);
2548         flush_unmaps();
2549         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2550 }
2551
2552 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2553 {
2554         unsigned long flags;
2555         int next, iommu_id;
2556         struct intel_iommu *iommu;
2557
2558         spin_lock_irqsave(&async_umap_flush_lock, flags);
2559         if (list_size == HIGH_WATER_MARK)
2560                 flush_unmaps();
2561
2562         iommu = domain_get_iommu(dom);
2563         iommu_id = iommu->seq_id;
2564
2565         next = deferred_flush[iommu_id].next;
2566         deferred_flush[iommu_id].domain[next] = dom;
2567         deferred_flush[iommu_id].iova[next] = iova;
2568         deferred_flush[iommu_id].next++;
2569
2570         if (!timer_on) {
2571                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2572                 timer_on = 1;
2573         }
2574         list_size++;
2575         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2576 }
2577
2578 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2579                              size_t size, enum dma_data_direction dir,
2580                              struct dma_attrs *attrs)
2581 {
2582         struct pci_dev *pdev = to_pci_dev(dev);
2583         struct dmar_domain *domain;
2584         unsigned long start_pfn, last_pfn;
2585         struct iova *iova;
2586         struct intel_iommu *iommu;
2587
2588         if (iommu_no_mapping(pdev))
2589                 return;
2590
2591         domain = find_domain(pdev);
2592         BUG_ON(!domain);
2593
2594         iommu = domain_get_iommu(domain);
2595
2596         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2597         if (!iova)
2598                 return;
2599
2600         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2601         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2602
2603         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2604                  pci_name(pdev), start_pfn, last_pfn);
2605
2606         /*  clear the whole page */
2607         dma_pte_clear_range(domain, start_pfn, last_pfn);
2608
2609         /* free page tables */
2610         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2611
2612         if (intel_iommu_strict) {
2613                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2614                                       last_pfn - start_pfn + 1);
2615                 /* free iova */
2616                 __free_iova(&domain->iovad, iova);
2617         } else {
2618                 add_unmap(domain, iova);
2619                 /*
2620                  * queue up the release of the unmap to save the 1/6th of the
2621                  * cpu used up by the iotlb flush operation...
2622                  */
2623         }
2624 }
2625
2626 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2627                                int dir)
2628 {
2629         intel_unmap_page(dev, dev_addr, size, dir, NULL);
2630 }
2631
2632 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2633                                   dma_addr_t *dma_handle, gfp_t flags)
2634 {
2635         void *vaddr;
2636         int order;
2637
2638         size = PAGE_ALIGN(size);
2639         order = get_order(size);
2640         flags &= ~(GFP_DMA | GFP_DMA32);
2641
2642         vaddr = (void *)__get_free_pages(flags, order);
2643         if (!vaddr)
2644                 return NULL;
2645         memset(vaddr, 0, size);
2646
2647         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2648                                          DMA_BIDIRECTIONAL,
2649                                          hwdev->coherent_dma_mask);
2650         if (*dma_handle)
2651                 return vaddr;
2652         free_pages((unsigned long)vaddr, order);
2653         return NULL;
2654 }
2655
2656 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2657                                 dma_addr_t dma_handle)
2658 {
2659         int order;
2660
2661         size = PAGE_ALIGN(size);
2662         order = get_order(size);
2663
2664         intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2665         free_pages((unsigned long)vaddr, order);
2666 }
2667
2668 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2669                            int nelems, enum dma_data_direction dir,
2670                            struct dma_attrs *attrs)
2671 {
2672         struct pci_dev *pdev = to_pci_dev(hwdev);
2673         struct dmar_domain *domain;
2674         unsigned long start_pfn, last_pfn;
2675         struct iova *iova;
2676         struct intel_iommu *iommu;
2677
2678         if (iommu_no_mapping(pdev))
2679                 return;
2680
2681         domain = find_domain(pdev);
2682         BUG_ON(!domain);
2683
2684         iommu = domain_get_iommu(domain);
2685
2686         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2687         if (!iova)
2688                 return;
2689
2690         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2691         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2692
2693         /*  clear the whole page */
2694         dma_pte_clear_range(domain, start_pfn, last_pfn);
2695
2696         /* free page tables */
2697         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2698
2699         iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2700                               (last_pfn - start_pfn + 1));
2701
2702         /* free iova */
2703         __free_iova(&domain->iovad, iova);
2704 }
2705
2706 static int intel_nontranslate_map_sg(struct device *hddev,
2707         struct scatterlist *sglist, int nelems, int dir)
2708 {
2709         int i;
2710         struct scatterlist *sg;
2711
2712         for_each_sg(sglist, sg, nelems, i) {
2713                 BUG_ON(!sg_page(sg));
2714                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2715                 sg->dma_length = sg->length;
2716         }
2717         return nelems;
2718 }
2719
2720 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2721                         enum dma_data_direction dir, struct dma_attrs *attrs)
2722 {
2723         int i;
2724         struct pci_dev *pdev = to_pci_dev(hwdev);
2725         struct dmar_domain *domain;
2726         size_t size = 0;
2727         int prot = 0;
2728         size_t offset_pfn = 0;
2729         struct iova *iova = NULL;
2730         int ret;
2731         struct scatterlist *sg;
2732         unsigned long start_vpfn;
2733         struct intel_iommu *iommu;
2734
2735         BUG_ON(dir == DMA_NONE);
2736         if (iommu_no_mapping(pdev))
2737                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2738
2739         domain = get_valid_domain_for_dev(pdev);
2740         if (!domain)
2741                 return 0;
2742
2743         iommu = domain_get_iommu(domain);
2744
2745         for_each_sg(sglist, sg, nelems, i)
2746                 size += aligned_nrpages(sg->offset, sg->length);
2747
2748         iova = __intel_alloc_iova(hwdev, domain, size << VTD_PAGE_SHIFT,
2749                                   pdev->dma_mask);
2750         if (!iova) {
2751                 sglist->dma_length = 0;
2752                 return 0;
2753         }
2754
2755         /*
2756          * Check if DMAR supports zero-length reads on write only
2757          * mappings..
2758          */
2759         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2760                         !cap_zlr(iommu->cap))
2761                 prot |= DMA_PTE_READ;
2762         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2763                 prot |= DMA_PTE_WRITE;
2764
2765         start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2766         offset_pfn = 0;
2767         for_each_sg(sglist, sg, nelems, i) {
2768                 int nr_pages = aligned_nrpages(sg->offset, sg->length);
2769                 ret = domain_pfn_mapping(domain, start_vpfn + offset_pfn,
2770                                          page_to_dma_pfn(sg_page(sg)),
2771                                          nr_pages, prot);
2772                 if (ret) {
2773                         /*  clear the page */
2774                         dma_pte_clear_range(domain, start_vpfn,
2775                                             start_vpfn + offset_pfn);
2776                         /* free page tables */
2777                         dma_pte_free_pagetable(domain, start_vpfn,
2778                                                start_vpfn + offset_pfn);
2779                         /* free iova */
2780                         __free_iova(&domain->iovad, iova);
2781                         return 0;
2782                 }
2783                 sg->dma_address = ((dma_addr_t)(start_vpfn + offset_pfn)
2784                                    << VTD_PAGE_SHIFT) + sg->offset;
2785                 sg->dma_length = sg->length;
2786                 offset_pfn += nr_pages;
2787         }
2788
2789         /* it's a non-present to present mapping. Only flush if caching mode */
2790         if (cap_caching_mode(iommu->cap))
2791                 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2792         else
2793                 iommu_flush_write_buffer(iommu);
2794
2795         return nelems;
2796 }
2797
2798 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2799 {
2800         return !dma_addr;
2801 }
2802
2803 struct dma_map_ops intel_dma_ops = {
2804         .alloc_coherent = intel_alloc_coherent,
2805         .free_coherent = intel_free_coherent,
2806         .map_sg = intel_map_sg,
2807         .unmap_sg = intel_unmap_sg,
2808         .map_page = intel_map_page,
2809         .unmap_page = intel_unmap_page,
2810         .mapping_error = intel_mapping_error,
2811 };
2812
2813 static inline int iommu_domain_cache_init(void)
2814 {
2815         int ret = 0;
2816
2817         iommu_domain_cache = kmem_cache_create("iommu_domain",
2818                                          sizeof(struct dmar_domain),
2819                                          0,
2820                                          SLAB_HWCACHE_ALIGN,
2821
2822                                          NULL);
2823         if (!iommu_domain_cache) {
2824                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2825                 ret = -ENOMEM;
2826         }
2827
2828         return ret;
2829 }
2830
2831 static inline int iommu_devinfo_cache_init(void)
2832 {
2833         int ret = 0;
2834
2835         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2836                                          sizeof(struct device_domain_info),
2837                                          0,
2838                                          SLAB_HWCACHE_ALIGN,
2839                                          NULL);
2840         if (!iommu_devinfo_cache) {
2841                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2842                 ret = -ENOMEM;
2843         }
2844
2845         return ret;
2846 }
2847
2848 static inline int iommu_iova_cache_init(void)
2849 {
2850         int ret = 0;
2851
2852         iommu_iova_cache = kmem_cache_create("iommu_iova",
2853                                          sizeof(struct iova),
2854                                          0,
2855                                          SLAB_HWCACHE_ALIGN,
2856                                          NULL);
2857         if (!iommu_iova_cache) {
2858                 printk(KERN_ERR "Couldn't create iova cache\n");
2859                 ret = -ENOMEM;
2860         }
2861
2862         return ret;
2863 }
2864
2865 static int __init iommu_init_mempool(void)
2866 {
2867         int ret;
2868         ret = iommu_iova_cache_init();
2869         if (ret)
2870                 return ret;
2871
2872         ret = iommu_domain_cache_init();
2873         if (ret)
2874                 goto domain_error;
2875
2876         ret = iommu_devinfo_cache_init();
2877         if (!ret)
2878                 return ret;
2879
2880         kmem_cache_destroy(iommu_domain_cache);
2881 domain_error:
2882         kmem_cache_destroy(iommu_iova_cache);
2883
2884         return -ENOMEM;
2885 }
2886
2887 static void __init iommu_exit_mempool(void)
2888 {
2889         kmem_cache_destroy(iommu_devinfo_cache);
2890         kmem_cache_destroy(iommu_domain_cache);
2891         kmem_cache_destroy(iommu_iova_cache);
2892
2893 }
2894
2895 static void __init init_no_remapping_devices(void)
2896 {
2897         struct dmar_drhd_unit *drhd;
2898
2899         for_each_drhd_unit(drhd) {
2900                 if (!drhd->include_all) {
2901                         int i;
2902                         for (i = 0; i < drhd->devices_cnt; i++)
2903                                 if (drhd->devices[i] != NULL)
2904                                         break;
2905                         /* ignore DMAR unit if no pci devices exist */
2906                         if (i == drhd->devices_cnt)
2907                                 drhd->ignored = 1;
2908                 }
2909         }
2910
2911         if (dmar_map_gfx)
2912                 return;
2913
2914         for_each_drhd_unit(drhd) {
2915                 int i;
2916                 if (drhd->ignored || drhd->include_all)
2917                         continue;
2918
2919                 for (i = 0; i < drhd->devices_cnt; i++)
2920                         if (drhd->devices[i] &&
2921                                 !IS_GFX_DEVICE(drhd->devices[i]))
2922                                 break;
2923
2924                 if (i < drhd->devices_cnt)
2925                         continue;
2926
2927                 /* bypass IOMMU if it is just for gfx devices */
2928                 drhd->ignored = 1;
2929                 for (i = 0; i < drhd->devices_cnt; i++) {
2930                         if (!drhd->devices[i])
2931                                 continue;
2932                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
2933                 }
2934         }
2935 }
2936
2937 #ifdef CONFIG_SUSPEND
2938 static int init_iommu_hw(void)
2939 {
2940         struct dmar_drhd_unit *drhd;
2941         struct intel_iommu *iommu = NULL;
2942
2943         for_each_active_iommu(iommu, drhd)
2944                 if (iommu->qi)
2945                         dmar_reenable_qi(iommu);
2946
2947         for_each_active_iommu(iommu, drhd) {
2948                 iommu_flush_write_buffer(iommu);
2949
2950                 iommu_set_root_entry(iommu);
2951
2952                 iommu->flush.flush_context(iommu, 0, 0, 0,
2953                                            DMA_CCMD_GLOBAL_INVL);
2954                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2955                                          DMA_TLB_GLOBAL_FLUSH);
2956                 iommu_disable_protect_mem_regions(iommu);
2957                 iommu_enable_translation(iommu);
2958         }
2959
2960         return 0;
2961 }
2962
2963 static void iommu_flush_all(void)
2964 {
2965         struct dmar_drhd_unit *drhd;
2966         struct intel_iommu *iommu;
2967
2968         for_each_active_iommu(iommu, drhd) {
2969                 iommu->flush.flush_context(iommu, 0, 0, 0,
2970                                            DMA_CCMD_GLOBAL_INVL);
2971                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2972                                          DMA_TLB_GLOBAL_FLUSH);
2973         }
2974 }
2975
2976 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
2977 {
2978         struct dmar_drhd_unit *drhd;
2979         struct intel_iommu *iommu = NULL;
2980         unsigned long flag;
2981
2982         for_each_active_iommu(iommu, drhd) {
2983                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
2984                                                  GFP_ATOMIC);
2985                 if (!iommu->iommu_state)
2986                         goto nomem;
2987         }
2988
2989         iommu_flush_all();
2990
2991         for_each_active_iommu(iommu, drhd) {
2992                 iommu_disable_translation(iommu);
2993
2994                 spin_lock_irqsave(&iommu->register_lock, flag);
2995
2996                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
2997                         readl(iommu->reg + DMAR_FECTL_REG);
2998                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
2999                         readl(iommu->reg + DMAR_FEDATA_REG);
3000                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3001                         readl(iommu->reg + DMAR_FEADDR_REG);
3002                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3003                         readl(iommu->reg + DMAR_FEUADDR_REG);
3004
3005                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3006         }
3007         return 0;
3008
3009 nomem:
3010         for_each_active_iommu(iommu, drhd)
3011                 kfree(iommu->iommu_state);
3012
3013         return -ENOMEM;
3014 }
3015
3016 static int iommu_resume(struct sys_device *dev)
3017 {
3018         struct dmar_drhd_unit *drhd;
3019         struct intel_iommu *iommu = NULL;
3020         unsigned long flag;
3021
3022         if (init_iommu_hw()) {
3023                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3024                 return -EIO;
3025         }
3026
3027         for_each_active_iommu(iommu, drhd) {
3028
3029                 spin_lock_irqsave(&iommu->register_lock, flag);
3030
3031                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3032                         iommu->reg + DMAR_FECTL_REG);
3033                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3034                         iommu->reg + DMAR_FEDATA_REG);
3035                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3036                         iommu->reg + DMAR_FEADDR_REG);
3037                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3038                         iommu->reg + DMAR_FEUADDR_REG);
3039
3040                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3041         }
3042
3043         for_each_active_iommu(iommu, drhd)
3044                 kfree(iommu->iommu_state);
3045
3046         return 0;
3047 }
3048
3049 static struct sysdev_class iommu_sysclass = {
3050         .name           = "iommu",
3051         .resume         = iommu_resume,
3052         .suspend        = iommu_suspend,
3053 };
3054
3055 static struct sys_device device_iommu = {
3056         .cls    = &iommu_sysclass,
3057 };
3058
3059 static int __init init_iommu_sysfs(void)
3060 {
3061         int error;
3062
3063         error = sysdev_class_register(&iommu_sysclass);
3064         if (error)
3065                 return error;
3066
3067         error = sysdev_register(&device_iommu);
3068         if (error)
3069                 sysdev_class_unregister(&iommu_sysclass);
3070
3071         return error;
3072 }
3073
3074 #else
3075 static int __init init_iommu_sysfs(void)
3076 {
3077         return 0;
3078 }
3079 #endif  /* CONFIG_PM */
3080
3081 int __init intel_iommu_init(void)
3082 {
3083         int ret = 0;
3084
3085         if (dmar_table_init())
3086                 return  -ENODEV;
3087
3088         if (dmar_dev_scope_init())
3089                 return  -ENODEV;
3090
3091         /*
3092          * Check the need for DMA-remapping initialization now.
3093          * Above initialization will also be used by Interrupt-remapping.
3094          */
3095         if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3096                 return -ENODEV;
3097
3098         iommu_init_mempool();
3099         dmar_init_reserved_ranges();
3100
3101         init_no_remapping_devices();
3102
3103         ret = init_dmars();
3104         if (ret) {
3105                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3106                 put_iova_domain(&reserved_iova_list);
3107                 iommu_exit_mempool();
3108                 return ret;
3109         }
3110         printk(KERN_INFO
3111         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3112
3113         init_timer(&unmap_timer);
3114         force_iommu = 1;
3115
3116         if (!iommu_pass_through) {
3117                 printk(KERN_INFO
3118                        "Multi-level page-table translation for DMAR.\n");
3119                 dma_ops = &intel_dma_ops;
3120         } else
3121                 printk(KERN_INFO
3122                        "DMAR: Pass through translation for DMAR.\n");
3123
3124         init_iommu_sysfs();
3125
3126         register_iommu(&intel_iommu_ops);
3127
3128         return 0;
3129 }
3130
3131 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3132                                            struct pci_dev *pdev)
3133 {
3134         struct pci_dev *tmp, *parent;
3135
3136         if (!iommu || !pdev)
3137                 return;
3138
3139         /* dependent device detach */
3140         tmp = pci_find_upstream_pcie_bridge(pdev);
3141         /* Secondary interface's bus number and devfn 0 */
3142         if (tmp) {
3143                 parent = pdev->bus->self;
3144                 while (parent != tmp) {
3145                         iommu_detach_dev(iommu, parent->bus->number,
3146                                          parent->devfn);
3147                         parent = parent->bus->self;
3148                 }
3149                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3150                         iommu_detach_dev(iommu,
3151                                 tmp->subordinate->number, 0);
3152                 else /* this is a legacy PCI bridge */
3153                         iommu_detach_dev(iommu, tmp->bus->number,
3154                                          tmp->devfn);
3155         }
3156 }
3157
3158 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3159                                           struct pci_dev *pdev)
3160 {
3161         struct device_domain_info *info;
3162         struct intel_iommu *iommu;
3163         unsigned long flags;
3164         int found = 0;
3165         struct list_head *entry, *tmp;
3166
3167         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3168                                 pdev->devfn);
3169         if (!iommu)
3170                 return;
3171
3172         spin_lock_irqsave(&device_domain_lock, flags);
3173         list_for_each_safe(entry, tmp, &domain->devices) {
3174                 info = list_entry(entry, struct device_domain_info, link);
3175                 /* No need to compare PCI domain; it has to be the same */
3176                 if (info->bus == pdev->bus->number &&
3177                     info->devfn == pdev->devfn) {
3178                         list_del(&info->link);
3179                         list_del(&info->global);
3180                         if (info->dev)
3181                                 info->dev->dev.archdata.iommu = NULL;
3182                         spin_unlock_irqrestore(&device_domain_lock, flags);
3183
3184                         iommu_disable_dev_iotlb(info);
3185                         iommu_detach_dev(iommu, info->bus, info->devfn);
3186                         iommu_detach_dependent_devices(iommu, pdev);
3187                         free_devinfo_mem(info);
3188
3189                         spin_lock_irqsave(&device_domain_lock, flags);
3190
3191                         if (found)
3192                                 break;
3193                         else
3194                                 continue;
3195                 }
3196
3197                 /* if there is no other devices under the same iommu
3198                  * owned by this domain, clear this iommu in iommu_bmp
3199                  * update iommu count and coherency
3200                  */
3201                 if (iommu == device_to_iommu(info->segment, info->bus,
3202                                             info->devfn))
3203                         found = 1;
3204         }
3205
3206         if (found == 0) {
3207                 unsigned long tmp_flags;
3208                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3209                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3210                 domain->iommu_count--;
3211                 domain_update_iommu_cap(domain);
3212                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3213         }
3214
3215         spin_unlock_irqrestore(&device_domain_lock, flags);
3216 }
3217
3218 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3219 {
3220         struct device_domain_info *info;
3221         struct intel_iommu *iommu;
3222         unsigned long flags1, flags2;
3223
3224         spin_lock_irqsave(&device_domain_lock, flags1);
3225         while (!list_empty(&domain->devices)) {
3226                 info = list_entry(domain->devices.next,
3227                         struct device_domain_info, link);
3228                 list_del(&info->link);
3229                 list_del(&info->global);
3230                 if (info->dev)
3231                         info->dev->dev.archdata.iommu = NULL;
3232
3233                 spin_unlock_irqrestore(&device_domain_lock, flags1);
3234
3235                 iommu_disable_dev_iotlb(info);
3236                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3237                 iommu_detach_dev(iommu, info->bus, info->devfn);
3238                 iommu_detach_dependent_devices(iommu, info->dev);
3239
3240                 /* clear this iommu in iommu_bmp, update iommu count
3241                  * and capabilities
3242                  */
3243                 spin_lock_irqsave(&domain->iommu_lock, flags2);
3244                 if (test_and_clear_bit(iommu->seq_id,
3245                                        &domain->iommu_bmp)) {
3246                         domain->iommu_count--;
3247                         domain_update_iommu_cap(domain);
3248                 }
3249                 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3250
3251                 free_devinfo_mem(info);
3252                 spin_lock_irqsave(&device_domain_lock, flags1);
3253         }
3254         spin_unlock_irqrestore(&device_domain_lock, flags1);
3255 }
3256
3257 /* domain id for virtual machine, it won't be set in context */
3258 static unsigned long vm_domid;
3259
3260 static int vm_domain_min_agaw(struct dmar_domain *domain)
3261 {
3262         int i;
3263         int min_agaw = domain->agaw;
3264
3265         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3266         for (; i < g_num_of_iommus; ) {
3267                 if (min_agaw > g_iommus[i]->agaw)
3268                         min_agaw = g_iommus[i]->agaw;
3269
3270                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3271         }
3272
3273         return min_agaw;
3274 }
3275
3276 static struct dmar_domain *iommu_alloc_vm_domain(void)
3277 {
3278         struct dmar_domain *domain;
3279
3280         domain = alloc_domain_mem();
3281         if (!domain)
3282                 return NULL;
3283
3284         domain->id = vm_domid++;
3285         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3286         domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3287
3288         return domain;
3289 }
3290
3291 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3292 {
3293         int adjust_width;
3294
3295         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3296         spin_lock_init(&domain->mapping_lock);
3297         spin_lock_init(&domain->iommu_lock);
3298
3299         domain_reserve_special_ranges(domain);
3300
3301         /* calculate AGAW */
3302         domain->gaw = guest_width;
3303         adjust_width = guestwidth_to_adjustwidth(guest_width);
3304         domain->agaw = width_to_agaw(adjust_width);
3305
3306         INIT_LIST_HEAD(&domain->devices);
3307
3308         domain->iommu_count = 0;
3309         domain->iommu_coherency = 0;
3310         domain->max_addr = 0;
3311
3312         /* always allocate the top pgd */
3313         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3314         if (!domain->pgd)
3315                 return -ENOMEM;
3316         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3317         return 0;
3318 }
3319
3320 static void iommu_free_vm_domain(struct dmar_domain *domain)
3321 {
3322         unsigned long flags;
3323         struct dmar_drhd_unit *drhd;
3324         struct intel_iommu *iommu;
3325         unsigned long i;
3326         unsigned long ndomains;
3327
3328         for_each_drhd_unit(drhd) {
3329                 if (drhd->ignored)
3330                         continue;
3331                 iommu = drhd->iommu;
3332
3333                 ndomains = cap_ndoms(iommu->cap);
3334                 i = find_first_bit(iommu->domain_ids, ndomains);
3335                 for (; i < ndomains; ) {
3336                         if (iommu->domains[i] == domain) {
3337                                 spin_lock_irqsave(&iommu->lock, flags);
3338                                 clear_bit(i, iommu->domain_ids);
3339                                 iommu->domains[i] = NULL;
3340                                 spin_unlock_irqrestore(&iommu->lock, flags);
3341                                 break;
3342                         }
3343                         i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3344                 }
3345         }
3346 }
3347
3348 static void vm_domain_exit(struct dmar_domain *domain)
3349 {
3350         /* Domain 0 is reserved, so dont process it */
3351         if (!domain)
3352                 return;
3353
3354         vm_domain_remove_all_dev_info(domain);
3355         /* destroy iovas */
3356         put_iova_domain(&domain->iovad);
3357
3358         /* clear ptes */
3359         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3360
3361         /* free page tables */
3362         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3363
3364         iommu_free_vm_domain(domain);
3365         free_domain_mem(domain);
3366 }
3367
3368 static int intel_iommu_domain_init(struct iommu_domain *domain)
3369 {
3370         struct dmar_domain *dmar_domain;
3371
3372         dmar_domain = iommu_alloc_vm_domain();
3373         if (!dmar_domain) {
3374                 printk(KERN_ERR
3375                         "intel_iommu_domain_init: dmar_domain == NULL\n");
3376                 return -ENOMEM;
3377         }
3378         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3379                 printk(KERN_ERR
3380                         "intel_iommu_domain_init() failed\n");
3381                 vm_domain_exit(dmar_domain);
3382                 return -ENOMEM;
3383         }
3384         domain->priv = dmar_domain;
3385
3386         return 0;
3387 }
3388
3389 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3390 {
3391         struct dmar_domain *dmar_domain = domain->priv;
3392
3393         domain->priv = NULL;
3394         vm_domain_exit(dmar_domain);
3395 }
3396
3397 static int intel_iommu_attach_device(struct iommu_domain *domain,
3398                                      struct device *dev)
3399 {
3400         struct dmar_domain *dmar_domain = domain->priv;
3401         struct pci_dev *pdev = to_pci_dev(dev);
3402         struct intel_iommu *iommu;
3403         int addr_width;
3404         u64 end;
3405         int ret;
3406
3407         /* normally pdev is not mapped */
3408         if (unlikely(domain_context_mapped(pdev))) {
3409                 struct dmar_domain *old_domain;
3410
3411                 old_domain = find_domain(pdev);
3412                 if (old_domain) {
3413                         if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3414                             dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3415                                 domain_remove_one_dev_info(old_domain, pdev);
3416                         else
3417                                 domain_remove_dev_info(old_domain);
3418                 }
3419         }
3420
3421         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3422                                 pdev->devfn);
3423         if (!iommu)
3424                 return -ENODEV;
3425
3426         /* check if this iommu agaw is sufficient for max mapped address */
3427         addr_width = agaw_to_width(iommu->agaw);
3428         end = DOMAIN_MAX_ADDR(addr_width);
3429         end = end & VTD_PAGE_MASK;
3430         if (end < dmar_domain->max_addr) {
3431                 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3432                        "sufficient for the mapped address (%llx)\n",
3433                        __func__, iommu->agaw, dmar_domain->max_addr);
3434                 return -EFAULT;
3435         }
3436
3437         ret = domain_add_dev_info(dmar_domain, pdev);
3438         if (ret)
3439                 return ret;
3440
3441         ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3442         return ret;
3443 }
3444
3445 static void intel_iommu_detach_device(struct iommu_domain *domain,
3446                                       struct device *dev)
3447 {
3448         struct dmar_domain *dmar_domain = domain->priv;
3449         struct pci_dev *pdev = to_pci_dev(dev);
3450
3451         domain_remove_one_dev_info(dmar_domain, pdev);
3452 }
3453
3454 static int intel_iommu_map_range(struct iommu_domain *domain,
3455                                  unsigned long iova, phys_addr_t hpa,
3456                                  size_t size, int iommu_prot)
3457 {
3458         struct dmar_domain *dmar_domain = domain->priv;
3459         u64 max_addr;
3460         int addr_width;
3461         int prot = 0;
3462         int ret;
3463
3464         if (iommu_prot & IOMMU_READ)
3465                 prot |= DMA_PTE_READ;
3466         if (iommu_prot & IOMMU_WRITE)
3467                 prot |= DMA_PTE_WRITE;
3468         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3469                 prot |= DMA_PTE_SNP;
3470
3471         max_addr = iova + size;
3472         if (dmar_domain->max_addr < max_addr) {
3473                 int min_agaw;
3474                 u64 end;
3475
3476                 /* check if minimum agaw is sufficient for mapped address */
3477                 min_agaw = vm_domain_min_agaw(dmar_domain);
3478                 addr_width = agaw_to_width(min_agaw);
3479                 end = DOMAIN_MAX_ADDR(addr_width);
3480                 end = end & VTD_PAGE_MASK;
3481                 if (end < max_addr) {
3482                         printk(KERN_ERR "%s: iommu agaw (%d) is not "
3483                                "sufficient for the mapped address (%llx)\n",
3484                                __func__, min_agaw, max_addr);
3485                         return -EFAULT;
3486                 }
3487                 dmar_domain->max_addr = max_addr;
3488         }
3489         /* Round up size to next multiple of PAGE_SIZE, if it and
3490            the low bits of hpa would take us onto the next page */
3491         size = aligned_nrpages(hpa, size);
3492         ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3493                                  hpa >> VTD_PAGE_SHIFT, size, prot);
3494         return ret;
3495 }
3496
3497 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3498                                     unsigned long iova, size_t size)
3499 {
3500         struct dmar_domain *dmar_domain = domain->priv;
3501
3502         dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3503                             (iova + size - 1) >> VTD_PAGE_SHIFT);
3504
3505         if (dmar_domain->max_addr == iova + size)
3506                 dmar_domain->max_addr = iova;
3507 }
3508
3509 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3510                                             unsigned long iova)
3511 {
3512         struct dmar_domain *dmar_domain = domain->priv;
3513         struct dma_pte *pte;
3514         u64 phys = 0;
3515
3516         pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3517         if (pte)
3518                 phys = dma_pte_addr(pte);
3519
3520         return phys;
3521 }
3522
3523 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3524                                       unsigned long cap)
3525 {
3526         struct dmar_domain *dmar_domain = domain->priv;
3527
3528         if (cap == IOMMU_CAP_CACHE_COHERENCY)
3529                 return dmar_domain->iommu_snooping;
3530
3531         return 0;
3532 }
3533
3534 static struct iommu_ops intel_iommu_ops = {
3535         .domain_init    = intel_iommu_domain_init,
3536         .domain_destroy = intel_iommu_domain_destroy,
3537         .attach_dev     = intel_iommu_attach_device,
3538         .detach_dev     = intel_iommu_detach_device,
3539         .map            = intel_iommu_map_range,
3540         .unmap          = intel_iommu_unmap_range,
3541         .iova_to_phys   = intel_iommu_iova_to_phys,
3542         .domain_has_cap = intel_iommu_domain_has_cap,
3543 };
3544
3545 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3546 {
3547         /*
3548          * Mobile 4 Series Chipset neglects to set RWBF capability,
3549          * but needs it:
3550          */
3551         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3552         rwbf_quirk = 1;
3553 }
3554
3555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);