git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/pci.h>
  37 #include <linux/errno.h>
  38 #include <asm/io.h>
  39 #include <ib_mad.h>
  40
  41 #include "mthca_dev.h"
  42 #include "mthca_config_reg.h"
  43 #include "mthca_cmd.h"
  44 #include "mthca_memfree.h"
  45
  46 #define CMD_POLL_TOKEN 0xffff
  47
  48 enum {
  49         HCR_IN_PARAM_OFFSET    = 0x00,
  50         HCR_IN_MODIFIER_OFFSET = 0x08,
  51         HCR_OUT_PARAM_OFFSET   = 0x0c,
  52         HCR_TOKEN_OFFSET       = 0x14,
  53         HCR_STATUS_OFFSET      = 0x18,
  54
  55         HCR_OPMOD_SHIFT        = 12,
  56         HCA_E_BIT              = 22,
  57         HCR_GO_BIT             = 23
  58 };
  59
  60 enum {
  61         /* initialization and general commands */
  62         CMD_SYS_EN          = 0x1,
  63         CMD_SYS_DIS         = 0x2,
  64         CMD_MAP_FA          = 0xfff,
  65         CMD_UNMAP_FA        = 0xffe,
  66         CMD_RUN_FW          = 0xff6,
  67         CMD_MOD_STAT_CFG    = 0x34,
  68         CMD_QUERY_DEV_LIM   = 0x3,
  69         CMD_QUERY_FW        = 0x4,
  70         CMD_ENABLE_LAM      = 0xff8,
  71         CMD_DISABLE_LAM     = 0xff7,
  72         CMD_QUERY_DDR       = 0x5,
  73         CMD_QUERY_ADAPTER   = 0x6,
  74         CMD_INIT_HCA        = 0x7,
  75         CMD_CLOSE_HCA       = 0x8,
  76         CMD_INIT_IB         = 0x9,
  77         CMD_CLOSE_IB        = 0xa,
  78         CMD_QUERY_HCA       = 0xb,
  79         CMD_SET_IB          = 0xc,
  80         CMD_ACCESS_DDR      = 0x2e,
  81         CMD_MAP_ICM         = 0xffa,
  82         CMD_UNMAP_ICM       = 0xff9,
  83         CMD_MAP_ICM_AUX     = 0xffc,
  84         CMD_UNMAP_ICM_AUX   = 0xffb,
  85         CMD_SET_ICM_SIZE    = 0xffd,
  86
  87         /* TPT commands */
  88         CMD_SW2HW_MPT       = 0xd,
  89         CMD_QUERY_MPT       = 0xe,
  90         CMD_HW2SW_MPT       = 0xf,
  91         CMD_READ_MTT        = 0x10,
  92         CMD_WRITE_MTT       = 0x11,
  93         CMD_SYNC_TPT        = 0x2f,
  94
  95         /* EQ commands */
  96         CMD_MAP_EQ          = 0x12,
  97         CMD_SW2HW_EQ        = 0x13,
  98         CMD_HW2SW_EQ        = 0x14,
  99         CMD_QUERY_EQ        = 0x15,
 100
 101         /* CQ commands */
 102         CMD_SW2HW_CQ        = 0x16,
 103         CMD_HW2SW_CQ        = 0x17,
 104         CMD_QUERY_CQ        = 0x18,
 105         CMD_RESIZE_CQ       = 0x2c,
 106
 107         /* SRQ commands */
 108         CMD_SW2HW_SRQ       = 0x35,
 109         CMD_HW2SW_SRQ       = 0x36,
 110         CMD_QUERY_SRQ       = 0x37,
 111
 112         /* QP/EE commands */
 113         CMD_RST2INIT_QPEE   = 0x19,
 114         CMD_INIT2RTR_QPEE   = 0x1a,
 115         CMD_RTR2RTS_QPEE    = 0x1b,
 116         CMD_RTS2RTS_QPEE    = 0x1c,
 117         CMD_SQERR2RTS_QPEE  = 0x1d,
 118         CMD_2ERR_QPEE       = 0x1e,
 119         CMD_RTS2SQD_QPEE    = 0x1f,
 120         CMD_SQD2SQD_QPEE    = 0x38,
 121         CMD_SQD2RTS_QPEE    = 0x20,
 122         CMD_ERR2RST_QPEE    = 0x21,
 123         CMD_QUERY_QPEE      = 0x22,
 124         CMD_INIT2INIT_QPEE  = 0x2d,
 125         CMD_SUSPEND_QPEE    = 0x32,
 126         CMD_UNSUSPEND_QPEE  = 0x33,
 127         /* special QPs and management commands */
 128         CMD_CONF_SPECIAL_QP = 0x23,
 129         CMD_MAD_IFC         = 0x24,
 130
 131         /* multicast commands */
 132         CMD_READ_MGM        = 0x25,
 133         CMD_WRITE_MGM       = 0x26,
 134         CMD_MGID_HASH       = 0x27,
 135
 136         /* miscellaneous commands */
 137         CMD_DIAG_RPRT       = 0x30,
 138         CMD_NOP             = 0x31,
 139
 140         /* debug commands */
 141         CMD_QUERY_DEBUG_MSG = 0x2a,
 142         CMD_SET_DEBUG_MSG   = 0x2b,
 143 };
 144
 145 /*
 146  * According to Mellanox code, FW may be starved and never complete
 147  * commands.  So we can't use strict timeouts described in PRM -- we
 148  * just arbitrarily select 60 seconds for now.
 149  */
 150 #if 0
 151 /*
 152  * Round up and add 1 to make sure we get the full wait time (since we
 153  * will be starting in the middle of a jiffy)
 154  */
 155 enum {
 156         CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
 157         CMD_TIME_CLASS_B = (HZ +  99) /  100 + 1,
 158         CMD_TIME_CLASS_C = (HZ +   9) /   10 + 1
 159 };
 160 #else
 161 enum {
 162         CMD_TIME_CLASS_A = 60 * HZ,
 163         CMD_TIME_CLASS_B = 60 * HZ,
 164         CMD_TIME_CLASS_C = 60 * HZ
 165 };
 166 #endif
 167
 168 enum {
 169         GO_BIT_TIMEOUT = HZ * 10
 170 };
 171
 172 struct mthca_cmd_context {
 173         struct completion done;
 174         struct timer_list timer;
 175         int               result;
 176         int               next;
 177         u64               out_param;
 178         u16               token;
 179         u8                status;
 180 };
 181
 182 static inline int go_bit(struct mthca_dev *dev)
 183 {
 184         return readl(dev->hcr + HCR_STATUS_OFFSET) &
 185                 swab32(1 << HCR_GO_BIT);
 186 }
 187
 188 static int mthca_cmd_post(struct mthca_dev *dev,
 189                           u64 in_param,
 190                           u64 out_param,
 191                           u32 in_modifier,
 192                           u8 op_modifier,
 193                           u16 op,
 194                           u16 token,
 195                           int event)
 196 {
 197         int err = 0;
 198
 199         if (down_interruptible(&dev->cmd.hcr_sem))
 200                 return -EINTR;
 201
 202         if (event) {
 203                 unsigned long end = jiffies + GO_BIT_TIMEOUT;
 204
 205                 while (go_bit(dev) && time_before(jiffies, end)) {
 206                         set_current_state(TASK_RUNNING);
 207                         schedule();
 208                 }
 209         }
 210
 211         if (go_bit(dev)) {
 212                 err = -EAGAIN;
 213                 goto out;
 214         }
 215
 216         /*
 217          * We use writel (instead of something like memcpy_toio)
 218          * because writes of less than 32 bits to the HCR don't work
 219          * (and some architectures such as ia64 implement memcpy_toio
 220          * in terms of writeb).
 221          */
 222         __raw_writel(cpu_to_be32(in_param >> 32),           dev->hcr + 0 * 4);
 223         __raw_writel(cpu_to_be32(in_param & 0xfffffffful),  dev->hcr + 1 * 4);
 224         __raw_writel(cpu_to_be32(in_modifier),              dev->hcr + 2 * 4);
 225         __raw_writel(cpu_to_be32(out_param >> 32),          dev->hcr + 3 * 4);
 226         __raw_writel(cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
 227         __raw_writel(cpu_to_be32(token << 16),              dev->hcr + 5 * 4);
 228
 229         /* __raw_writel may not order writes. */
 230         wmb();
 231
 232         __raw_writel(cpu_to_be32((1 << HCR_GO_BIT)                |
 233                                  (event ? (1 << HCA_E_BIT) : 0)   |
 234                                  (op_modifier << HCR_OPMOD_SHIFT) |
 235                                  op),                       dev->hcr + 6 * 4);
 236
 237 out:
 238         up(&dev->cmd.hcr_sem);
 239         return err;
 240 }
 241
 242 static int mthca_cmd_poll(struct mthca_dev *dev,
 243                           u64 in_param,
 244                           u64 *out_param,
 245                           int out_is_imm,
 246                           u32 in_modifier,
 247                           u8 op_modifier,
 248                           u16 op,
 249                           unsigned long timeout,
 250                           u8 *status)
 251 {
 252         int err = 0;
 253         unsigned long end;
 254
 255         if (down_interruptible(&dev->cmd.poll_sem))
 256                 return -EINTR;
 257
 258         err = mthca_cmd_post(dev, in_param,
 259                              out_param ? *out_param : 0,
 260                              in_modifier, op_modifier,
 261                              op, CMD_POLL_TOKEN, 0);
 262         if (err)
 263                 goto out;
 264
 265         end = timeout + jiffies;
 266         while (go_bit(dev) && time_before(jiffies, end)) {
 267                 set_current_state(TASK_RUNNING);
 268                 schedule();
 269         }
 270
 271         if (go_bit(dev)) {
 272                 err = -EBUSY;
 273                 goto out;
 274         }
 275
 276         if (out_is_imm) {
 277                 memcpy_fromio(out_param, dev->hcr + HCR_OUT_PARAM_OFFSET, sizeof (u64));
 278                 be64_to_cpus(out_param);
 279         }
 280
 281         *status = be32_to_cpu(__raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
 282
 283 out:
 284         up(&dev->cmd.poll_sem);
 285         return err;
 286 }
 287
 288 void mthca_cmd_event(struct mthca_dev *dev,
 289                      u16 token,
 290                      u8  status,
 291                      u64 out_param)
 292 {
 293         struct mthca_cmd_context *context =
 294                 &dev->cmd.context[token & dev->cmd.token_mask];
 295
 296         /* previously timed out command completing at long last */
 297         if (token != context->token)
 298                 return;
 299
 300         context->result    = 0;
 301         context->status    = status;
 302         context->out_param = out_param;
 303
 304         context->token += dev->cmd.token_mask + 1;
 305
 306         complete(&context->done);
 307 }
 308
 309 static void event_timeout(unsigned long context_ptr)
 310 {
 311         struct mthca_cmd_context *context =
 312                 (struct mthca_cmd_context *) context_ptr;
 313
 314         context->result = -EBUSY;
 315         complete(&context->done);
 316 }
 317
 318 static int mthca_cmd_wait(struct mthca_dev *dev,
 319                           u64 in_param,
 320                           u64 *out_param,
 321                           int out_is_imm,
 322                           u32 in_modifier,
 323                           u8 op_modifier,
 324                           u16 op,
 325                           unsigned long timeout,
 326                           u8 *status)
 327 {
 328         int err = 0;
 329         struct mthca_cmd_context *context;
 330
 331         if (down_interruptible(&dev->cmd.event_sem))
 332                 return -EINTR;
 333
 334         spin_lock(&dev->cmd.context_lock);
 335         BUG_ON(dev->cmd.free_head < 0);
 336         context = &dev->cmd.context[dev->cmd.free_head];
 337         dev->cmd.free_head = context->next;
 338         spin_unlock(&dev->cmd.context_lock);
 339
 340         init_completion(&context->done);
 341
 342         err = mthca_cmd_post(dev, in_param,
 343                              out_param ? *out_param : 0,
 344                              in_modifier, op_modifier,
 345                              op, context->token, 1);
 346         if (err)
 347                 goto out;
 348
 349         context->timer.expires  = jiffies + timeout;
 350         add_timer(&context->timer);
 351
 352         wait_for_completion(&context->done);
 353         del_timer_sync(&context->timer);
 354
 355         err = context->result;
 356         if (err)
 357                 goto out;
 358
 359         *status = context->status;
 360         if (*status)
 361                 mthca_dbg(dev, "Command %02x completed with status %02x\n",
 362                           op, *status);
 363
 364         if (out_is_imm)
 365                 *out_param = context->out_param;
 366
 367 out:
 368         spin_lock(&dev->cmd.context_lock);
 369         context->next = dev->cmd.free_head;
 370         dev->cmd.free_head = context - dev->cmd.context;
 371         spin_unlock(&dev->cmd.context_lock);
 372
 373         up(&dev->cmd.event_sem);
 374         return err;
 375 }
 376
 377 /* Invoke a command with an output mailbox */
 378 static int mthca_cmd_box(struct mthca_dev *dev,
 379                          u64 in_param,
 380                          u64 out_param,
 381                          u32 in_modifier,
 382                          u8 op_modifier,
 383                          u16 op,
 384                          unsigned long timeout,
 385                          u8 *status)
 386 {
 387         if (dev->cmd.use_events)
 388                 return mthca_cmd_wait(dev, in_param, &out_param, 0,
 389                                       in_modifier, op_modifier, op,
 390                                       timeout, status);
 391         else
 392                 return mthca_cmd_poll(dev, in_param, &out_param, 0,
 393                                       in_modifier, op_modifier, op,
 394                                       timeout, status);
 395 }
 396
 397 /* Invoke a command with no output parameter */
 398 static int mthca_cmd(struct mthca_dev *dev,
 399                      u64 in_param,
 400                      u32 in_modifier,
 401                      u8 op_modifier,
 402                      u16 op,
 403                      unsigned long timeout,
 404                      u8 *status)
 405 {
 406         return mthca_cmd_box(dev, in_param, 0, in_modifier,
 407                              op_modifier, op, timeout, status);
 408 }
 409
 410 /*
 411  * Invoke a command with an immediate output parameter (and copy the
 412  * output into the caller's out_param pointer after the command
 413  * executes).
 414  */
 415 static int mthca_cmd_imm(struct mthca_dev *dev,
 416                          u64 in_param,
 417                          u64 *out_param,
 418                          u32 in_modifier,
 419                          u8 op_modifier,
 420                          u16 op,
 421                          unsigned long timeout,
 422                          u8 *status)
 423 {
 424         if (dev->cmd.use_events)
 425                 return mthca_cmd_wait(dev, in_param, out_param, 1,
 426                                       in_modifier, op_modifier, op,
 427                                       timeout, status);
 428         else
 429                 return mthca_cmd_poll(dev, in_param, out_param, 1,
 430                                       in_modifier, op_modifier, op,
 431                                       timeout, status);
 432 }
 433
 434 int mthca_cmd_init(struct mthca_dev *dev)
 435 {
 436         sema_init(&dev->cmd.hcr_sem, 1);
 437         sema_init(&dev->cmd.poll_sem, 1);
 438         dev->cmd.use_events = 0;
 439
 440         dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
 441                            MTHCA_HCR_SIZE);
 442         if (!dev->hcr) {
 443                 mthca_err(dev, "Couldn't map command register.");
 444                 return -ENOMEM;
 445         }
 446
 447         dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
 448                                         MTHCA_MAILBOX_SIZE,
 449                                         MTHCA_MAILBOX_SIZE, 0);
 450         if (!dev->cmd.pool) {
 451                 iounmap(dev->hcr);
 452                 return -ENOMEM;
 453         }
 454
 455         return 0;
 456 }
 457
 458 void mthca_cmd_cleanup(struct mthca_dev *dev)
 459 {
 460         pci_pool_destroy(dev->cmd.pool);
 461         iounmap(dev->hcr);
 462 }
 463
 464 /*
 465  * Switch to using events to issue FW commands (should be called after
 466  * event queue to command events has been initialized).
 467  */
 468 int mthca_cmd_use_events(struct mthca_dev *dev)
 469 {
 470         int i;
 471
 472         dev->cmd.context = kmalloc(dev->cmd.max_cmds *
 473                                    sizeof (struct mthca_cmd_context),
 474                                    GFP_KERNEL);
 475         if (!dev->cmd.context)
 476                 return -ENOMEM;
 477
 478         for (i = 0; i < dev->cmd.max_cmds; ++i) {
 479                 dev->cmd.context[i].token = i;
 480                 dev->cmd.context[i].next = i + 1;
 481                 init_timer(&dev->cmd.context[i].timer);
 482                 dev->cmd.context[i].timer.data     =
 483                         (unsigned long) &dev->cmd.context[i];
 484                 dev->cmd.context[i].timer.function = event_timeout;
 485         }
 486
 487         dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
 488         dev->cmd.free_head = 0;
 489
 490         sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
 491         spin_lock_init(&dev->cmd.context_lock);
 492
 493         for (dev->cmd.token_mask = 1;
 494              dev->cmd.token_mask < dev->cmd.max_cmds;
 495              dev->cmd.token_mask <<= 1)
 496                 ; /* nothing */
 497         --dev->cmd.token_mask;
 498
 499         dev->cmd.use_events = 1;
 500         down(&dev->cmd.poll_sem);
 501
 502         return 0;
 503 }
 504
 505 /*
 506  * Switch back to polling (used when shutting down the device)
 507  */
 508 void mthca_cmd_use_polling(struct mthca_dev *dev)
 509 {
 510         int i;
 511
 512         dev->cmd.use_events = 0;
 513
 514         for (i = 0; i < dev->cmd.max_cmds; ++i)
 515                 down(&dev->cmd.event_sem);
 516
 517         kfree(dev->cmd.context);
 518
 519         up(&dev->cmd.poll_sem);
 520 }
 521
 522 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
 523                                           unsigned int gfp_mask)
 524 {
 525         struct mthca_mailbox *mailbox;
 526
 527         mailbox = kmalloc(sizeof *mailbox, gfp_mask);
 528         if (!mailbox)
 529                 return ERR_PTR(-ENOMEM);
 530
 531         mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
 532         if (!mailbox->buf) {
 533                 kfree(mailbox);
 534                 return ERR_PTR(-ENOMEM);
 535         }
 536
 537         return mailbox;
 538 }
 539
 540 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
 541 {
 542         if (!mailbox)
 543                 return;
 544
 545         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 546         kfree(mailbox);
 547 }
 548
 549 int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
 550 {
 551         u64 out;
 552         int ret;
 553
 554         ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
 555
 556         if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
 557                 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
 558                            "sladdr=%d, SPD source=%s\n",
 559                            (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
 560                            (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
 561
 562         return ret;
 563 }
 564
 565 int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
 566 {
 567         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
 568 }
 569
 570 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
 571                          u64 virt, u8 *status)
 572 {
 573         struct mthca_mailbox *mailbox;
 574         struct mthca_icm_iter iter;
 575         __be64 *pages;
 576         int lg;
 577         int nent = 0;
 578         int i;
 579         int err = 0;
 580         int ts = 0, tc = 0;
 581
 582         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 583         if (IS_ERR(mailbox))
 584                 return PTR_ERR(mailbox);
 585         memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
 586         pages = mailbox->buf;
 587
 588         for (mthca_icm_first(icm, &iter);
 589              !mthca_icm_last(&iter);
 590              mthca_icm_next(&iter)) {
 591                 /*
 592                  * We have to pass pages that are aligned to their
 593                  * size, so find the least significant 1 in the
 594                  * address or size and use that as our log2 size.
 595                  */
 596                 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
 597                 if (lg < 12) {
 598                         mthca_warn(dev, "Got FW area not aligned to 4K (%llx/%lx).\n",
 599                                    (unsigned long long) mthca_icm_addr(&iter),
 600                                    mthca_icm_size(&iter));
 601                         err = -EINVAL;
 602                         goto out;
 603                 }
 604                 for (i = 0; i < mthca_icm_size(&iter) / (1 << lg); ++i, ++nent) {
 605                         if (virt != -1) {
 606                                 pages[nent * 2] = cpu_to_be64(virt);
 607                                 virt += 1 << lg;
 608                         }
 609
 610                         pages[nent * 2 + 1] = cpu_to_be64((mthca_icm_addr(&iter) +
 611                                                            (i << lg)) | (lg - 12));
 612                         ts += 1 << (lg - 10);
 613                         ++tc;
 614
 615                         if (nent == MTHCA_MAILBOX_SIZE / 16) {
 616                                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 617                                                 CMD_TIME_CLASS_B, status);
 618                                 if (err || *status)
 619                                         goto out;
 620                                 nent = 0;
 621                         }
 622                 }
 623         }
 624
 625         if (nent)
 626                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 627                                 CMD_TIME_CLASS_B, status);
 628
 629         switch (op) {
 630         case CMD_MAP_FA:
 631                 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
 632                 break;
 633         case CMD_MAP_ICM_AUX:
 634                 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
 635                 break;
 636         case CMD_MAP_ICM:
 637                 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
 638                           tc, ts, (unsigned long long) virt - (ts << 10));
 639                 break;
 640         }
 641
 642 out:
 643         mthca_free_mailbox(dev, mailbox);
 644         return err;
 645 }
 646
 647 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
 648 {
 649         return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
 650 }
 651
 652 int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
 653 {
 654         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
 655 }
 656
 657 int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
 658 {
 659         return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
 660 }
 661
 662 int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
 663 {
 664         struct mthca_mailbox *mailbox;
 665         u32 *outbox;
 666         int err = 0;
 667         u8 lg;
 668
 669 #define QUERY_FW_OUT_SIZE             0x100
 670 #define QUERY_FW_VER_OFFSET            0x00
 671 #define QUERY_FW_MAX_CMD_OFFSET        0x0f
 672 #define QUERY_FW_ERR_START_OFFSET      0x30
 673 #define QUERY_FW_ERR_SIZE_OFFSET       0x38
 674
 675 #define QUERY_FW_START_OFFSET          0x20
 676 #define QUERY_FW_END_OFFSET            0x28
 677
 678 #define QUERY_FW_SIZE_OFFSET           0x00
 679 #define QUERY_FW_CLR_INT_BASE_OFFSET   0x20
 680 #define QUERY_FW_EQ_ARM_BASE_OFFSET    0x40
 681 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
 682
 683         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 684         if (IS_ERR(mailbox))
 685                 return PTR_ERR(mailbox);
 686         outbox = mailbox->buf;
 687
 688         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
 689                             CMD_TIME_CLASS_A, status);
 690
 691         if (err)
 692                 goto out;
 693
 694         MTHCA_GET(dev->fw_ver,   outbox, QUERY_FW_VER_OFFSET);
 695         /*
 696          * FW subminor version is at more signifant bits than minor
 697          * version, so swap here.
 698          */
 699         dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
 700                 ((dev->fw_ver & 0xffff0000ull) >> 16) |
 701                 ((dev->fw_ver & 0x0000ffffull) << 16);
 702
 703         MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
 704         dev->cmd.max_cmds = 1 << lg;
 705
 706         mthca_dbg(dev, "FW version %012llx, max commands %d\n",
 707                   (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
 708
 709         if (mthca_is_memfree(dev)) {
 710                 MTHCA_GET(dev->fw.arbel.fw_pages,       outbox, QUERY_FW_SIZE_OFFSET);
 711                 MTHCA_GET(dev->fw.arbel.clr_int_base,   outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
 712                 MTHCA_GET(dev->fw.arbel.eq_arm_base,    outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
 713                 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
 714                 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
 715
 716                 /*
 717                  * Arbel page size is always 4 KB; round up number of
 718                  * system pages needed.
 719                  */
 720                 dev->fw.arbel.fw_pages =
 721                         (dev->fw.arbel.fw_pages + (1 << (PAGE_SHIFT - 12)) - 1) >>
 722                         (PAGE_SHIFT - 12);
 723
 724                 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
 725                           (unsigned long long) dev->fw.arbel.clr_int_base,
 726                           (unsigned long long) dev->fw.arbel.eq_arm_base,
 727                           (unsigned long long) dev->fw.arbel.eq_set_ci_base);
 728         } else {
 729                 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
 730                 MTHCA_GET(dev->fw.tavor.fw_end,   outbox, QUERY_FW_END_OFFSET);
 731
 732                 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
 733                           (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
 734                           (unsigned long long) dev->fw.tavor.fw_start,
 735                           (unsigned long long) dev->fw.tavor.fw_end);
 736         }
 737
 738 out:
 739         mthca_free_mailbox(dev, mailbox);
 740         return err;
 741 }
 742
 743 int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
 744 {
 745         struct mthca_mailbox *mailbox;
 746         u8 info;
 747         u32 *outbox;
 748         int err = 0;
 749
 750 #define ENABLE_LAM_OUT_SIZE         0x100
 751 #define ENABLE_LAM_START_OFFSET     0x00
 752 #define ENABLE_LAM_END_OFFSET       0x08
 753 #define ENABLE_LAM_INFO_OFFSET      0x13
 754
 755 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
 756 #define ENABLE_LAM_INFO_ECC_MASK    0x3
 757
 758         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 759         if (IS_ERR(mailbox))
 760                 return PTR_ERR(mailbox);
 761         outbox = mailbox->buf;
 762
 763         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
 764                             CMD_TIME_CLASS_C, status);
 765
 766         if (err)
 767                 goto out;
 768
 769         if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
 770                 goto out;
 771
 772         MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
 773         MTHCA_GET(dev->ddr_end,   outbox, ENABLE_LAM_END_OFFSET);
 774         MTHCA_GET(info,           outbox, ENABLE_LAM_INFO_OFFSET);
 775
 776         if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
 777             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 778                 mthca_info(dev, "FW reports that HCA-attached memory "
 779                            "is %s hidden; does not match PCI config\n",
 780                            (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
 781                            "" : "not");
 782         }
 783         if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
 784                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 785
 786         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 787                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 788                   (unsigned long long) dev->ddr_start,
 789                   (unsigned long long) dev->ddr_end);
 790
 791 out:
 792         mthca_free_mailbox(dev, mailbox);
 793         return err;
 794 }
 795
 796 int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
 797 {
 798         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
 799 }
 800
 801 int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
 802 {
 803         struct mthca_mailbox *mailbox;
 804         u8 info;
 805         u32 *outbox;
 806         int err = 0;
 807
 808 #define QUERY_DDR_OUT_SIZE         0x100
 809 #define QUERY_DDR_START_OFFSET     0x00
 810 #define QUERY_DDR_END_OFFSET       0x08
 811 #define QUERY_DDR_INFO_OFFSET      0x13
 812
 813 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
 814 #define QUERY_DDR_INFO_ECC_MASK    0x3
 815
 816         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 817         if (IS_ERR(mailbox))
 818                 return PTR_ERR(mailbox);
 819         outbox = mailbox->buf;
 820
 821         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
 822                             CMD_TIME_CLASS_A, status);
 823
 824         if (err)
 825                 goto out;
 826
 827         MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
 828         MTHCA_GET(dev->ddr_end,   outbox, QUERY_DDR_END_OFFSET);
 829         MTHCA_GET(info,           outbox, QUERY_DDR_INFO_OFFSET);
 830
 831         if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
 832             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 833                 mthca_info(dev, "FW reports that HCA-attached memory "
 834                            "is %s hidden; does not match PCI config\n",
 835                            (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
 836                            "" : "not");
 837         }
 838         if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
 839                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 840
 841         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 842                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 843                   (unsigned long long) dev->ddr_start,
 844                   (unsigned long long) dev->ddr_end);
 845
 846 out:
 847         mthca_free_mailbox(dev, mailbox);
 848         return err;
 849 }
 850
 851 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
 852                         struct mthca_dev_lim *dev_lim, u8 *status)
 853 {
 854         struct mthca_mailbox *mailbox;
 855         u32 *outbox;
 856         u8 field;
 857         u16 size;
 858         int err;
 859
 860 #define QUERY_DEV_LIM_OUT_SIZE             0x100
 861 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET     0x10
 862 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET      0x11
 863 #define QUERY_DEV_LIM_RSVD_QP_OFFSET        0x12
 864 #define QUERY_DEV_LIM_MAX_QP_OFFSET         0x13
 865 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET       0x14
 866 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET        0x15
 867 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET       0x16
 868 #define QUERY_DEV_LIM_MAX_EEC_OFFSET        0x17
 869 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET      0x19
 870 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET        0x1a
 871 #define QUERY_DEV_LIM_MAX_CQ_OFFSET         0x1b
 872 #define QUERY_DEV_LIM_MAX_MPT_OFFSET        0x1d
 873 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET        0x1e
 874 #define QUERY_DEV_LIM_MAX_EQ_OFFSET         0x1f
 875 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET       0x20
 876 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET     0x21
 877 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET       0x22
 878 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET    0x23
 879 #define QUERY_DEV_LIM_MAX_AV_OFFSET         0x27
 880 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET     0x29
 881 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET     0x2b
 882 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET       0x2f
 883 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET        0x33
 884 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET      0x35
 885 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET      0x36
 886 #define QUERY_DEV_LIM_VL_PORT_OFFSET        0x37
 887 #define QUERY_DEV_LIM_MAX_GID_OFFSET        0x3b
 888 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET       0x3f
 889 #define QUERY_DEV_LIM_FLAGS_OFFSET          0x44
 890 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET       0x48
 891 #define QUERY_DEV_LIM_UAR_SZ_OFFSET         0x49
 892 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET        0x4b
 893 #define QUERY_DEV_LIM_MAX_SG_OFFSET         0x51
 894 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET    0x52
 895 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET      0x55
 896 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
 897 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET     0x61
 898 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET       0x62
 899 #define QUERY_DEV_LIM_MAX_MCG_OFFSET        0x63
 900 #define QUERY_DEV_LIM_RSVD_PD_OFFSET        0x64
 901 #define QUERY_DEV_LIM_MAX_PD_OFFSET         0x65
 902 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET       0x66
 903 #define QUERY_DEV_LIM_MAX_RDD_OFFSET        0x67
 904 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80
 905 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82
 906 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET  0x84
 907 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET  0x86
 908 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88
 909 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a
 910 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c
 911 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e
 912 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90
 913 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92
 914 #define QUERY_DEV_LIM_PBL_SZ_OFFSET         0x96
 915 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET     0x97
 916 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET      0x98
 917 #define QUERY_DEV_LIM_LAMR_OFFSET           0x9f
 918 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET     0xa0
 919
 920         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 921         if (IS_ERR(mailbox))
 922                 return PTR_ERR(mailbox);
 923         outbox = mailbox->buf;
 924
 925         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
 926                             CMD_TIME_CLASS_A, status);
 927
 928         if (err)
 929                 goto out;
 930
 931         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
 932         dev_lim->max_srq_sz = 1 << field;
 933         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
 934         dev_lim->max_qp_sz = 1 << field;
 935         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
 936         dev_lim->reserved_qps = 1 << (field & 0xf);
 937         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
 938         dev_lim->max_qps = 1 << (field & 0x1f);
 939         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
 940         dev_lim->reserved_srqs = 1 << (field >> 4);
 941         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
 942         dev_lim->max_srqs = 1 << (field & 0x1f);
 943         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
 944         dev_lim->reserved_eecs = 1 << (field & 0xf);
 945         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
 946         dev_lim->max_eecs = 1 << (field & 0x1f);
 947         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
 948         dev_lim->max_cq_sz = 1 << field;
 949         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
 950         dev_lim->reserved_cqs = 1 << (field & 0xf);
 951         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
 952         dev_lim->max_cqs = 1 << (field & 0x1f);
 953         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
 954         dev_lim->max_mpts = 1 << (field & 0x3f);
 955         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
 956         dev_lim->reserved_eqs = 1 << (field & 0xf);
 957         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
 958         dev_lim->max_eqs = 1 << (field & 0x7);
 959         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
 960         dev_lim->reserved_mtts = 1 << (field >> 4);
 961         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
 962         dev_lim->max_mrw_sz = 1 << field;
 963         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
 964         dev_lim->reserved_mrws = 1 << (field & 0xf);
 965         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
 966         dev_lim->max_mtt_seg = 1 << (field & 0x3f);
 967         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
 968         dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
 969         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
 970         dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
 971         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
 972         dev_lim->max_rdma_global = 1 << (field & 0x3f);
 973         MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
 974         dev_lim->local_ca_ack_delay = field & 0x1f;
 975         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
 976         dev_lim->max_mtu        = field >> 4;
 977         dev_lim->max_port_width = field & 0xf;
 978         MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
 979         dev_lim->max_vl    = field >> 4;
 980         dev_lim->num_ports = field & 0xf;
 981         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
 982         dev_lim->max_gids = 1 << (field & 0xf);
 983         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
 984         dev_lim->max_pkeys = 1 << (field & 0xf);
 985         MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
 986         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
 987         dev_lim->reserved_uars = field >> 4;
 988         MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
 989         dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
 990         MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
 991         dev_lim->min_page_sz = 1 << field;
 992         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
 993         dev_lim->max_sg = field;
 994
 995         MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
 996         dev_lim->max_desc_sz = size;
 997
 998         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
 999         dev_lim->max_qp_per_mcg = 1 << field;
1000         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1001         dev_lim->reserved_mgms = field & 0xf;
1002         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1003         dev_lim->max_mcgs = 1 << field;
1004         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1005         dev_lim->reserved_pds = field >> 4;
1006         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1007         dev_lim->max_pds = 1 << (field & 0x3f);
1008         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1009         dev_lim->reserved_rdds = field >> 4;
1010         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1011         dev_lim->max_rdds = 1 << (field & 0x3f);
1012
1013         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1014         dev_lim->eec_entry_sz = size;
1015         MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1016         dev_lim->qpc_entry_sz = size;
1017         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1018         dev_lim->eeec_entry_sz = size;
1019         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1020         dev_lim->eqpc_entry_sz = size;
1021         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1022         dev_lim->eqc_entry_sz = size;
1023         MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1024         dev_lim->cqc_entry_sz = size;
1025         MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1026         dev_lim->srq_entry_sz = size;
1027         MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1028         dev_lim->uar_scratch_entry_sz = size;
1029
1030         mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1031                   dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1032         mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1033                   dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1034         mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1035                   dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1036         mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1037                   dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1038         mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1039                   dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1040         mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1041                   dev_lim->max_pds, dev_lim->reserved_mgms);
1042
1043         mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1044
1045         if (mthca_is_memfree(dev)) {
1046                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1047                 dev_lim->hca.arbel.resize_srq = field & 1;
1048                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1049                 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1050                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1051                 dev_lim->mpt_entry_sz = size;
1052                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1053                 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1054                 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1055                           QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1056                 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1057                           QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1058                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1059                 dev_lim->hca.arbel.lam_required = field & 1;
1060                 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1061                           QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1062
1063                 if (dev_lim->hca.arbel.bmme_flags & 1)
1064                         mthca_dbg(dev, "Base MM extensions: yes "
1065                                   "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1066                                   dev_lim->hca.arbel.bmme_flags,
1067                                   dev_lim->hca.arbel.max_pbl_sz,
1068                                   dev_lim->hca.arbel.reserved_lkey);
1069                 else
1070                         mthca_dbg(dev, "Base MM extensions: no\n");
1071
1072                 mthca_dbg(dev, "Max ICM size %lld MB\n",
1073                           (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1074         } else {
1075                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1076                 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1077                 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1078         }
1079
1080 out:
1081         mthca_free_mailbox(dev, mailbox);
1082         return err;
1083 }
1084
1085 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1086                         struct mthca_adapter *adapter, u8 *status)
1087 {
1088         struct mthca_mailbox *mailbox;
1089         u32 *outbox;
1090         int err;
1091
1092 #define QUERY_ADAPTER_OUT_SIZE             0x100
1093 #define QUERY_ADAPTER_VENDOR_ID_OFFSET     0x00
1094 #define QUERY_ADAPTER_DEVICE_ID_OFFSET     0x04
1095 #define QUERY_ADAPTER_REVISION_ID_OFFSET   0x08
1096 #define QUERY_ADAPTER_INTA_PIN_OFFSET      0x10
1097
1098         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1099         if (IS_ERR(mailbox))
1100                 return PTR_ERR(mailbox);
1101         outbox = mailbox->buf;
1102
1103         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1104                             CMD_TIME_CLASS_A, status);
1105
1106         if (err)
1107                 goto out;
1108
1109         MTHCA_GET(adapter->vendor_id, outbox,   QUERY_ADAPTER_VENDOR_ID_OFFSET);
1110         MTHCA_GET(adapter->device_id, outbox,   QUERY_ADAPTER_DEVICE_ID_OFFSET);
1111         MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
1112         MTHCA_GET(adapter->inta_pin, outbox,    QUERY_ADAPTER_INTA_PIN_OFFSET);
1113
1114 out:
1115         mthca_free_mailbox(dev, mailbox);
1116         return err;
1117 }
1118
1119 int mthca_INIT_HCA(struct mthca_dev *dev,
1120                    struct mthca_init_hca_param *param,
1121                    u8 *status)
1122 {
1123         struct mthca_mailbox *mailbox;
1124         u32 *inbox;
1125         int err;
1126
1127 #define INIT_HCA_IN_SIZE                 0x200
1128 #define INIT_HCA_FLAGS_OFFSET            0x014
1129 #define INIT_HCA_QPC_OFFSET              0x020
1130 #define  INIT_HCA_QPC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x10)
1131 #define  INIT_HCA_LOG_QP_OFFSET          (INIT_HCA_QPC_OFFSET + 0x17)
1132 #define  INIT_HCA_EEC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x20)
1133 #define  INIT_HCA_LOG_EEC_OFFSET         (INIT_HCA_QPC_OFFSET + 0x27)
1134 #define  INIT_HCA_SRQC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x28)
1135 #define  INIT_HCA_LOG_SRQ_OFFSET         (INIT_HCA_QPC_OFFSET + 0x2f)
1136 #define  INIT_HCA_CQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x30)
1137 #define  INIT_HCA_LOG_CQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x37)
1138 #define  INIT_HCA_EQPC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x40)
1139 #define  INIT_HCA_EEEC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x50)
1140 #define  INIT_HCA_EQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x60)
1141 #define  INIT_HCA_LOG_EQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x67)
1142 #define  INIT_HCA_RDB_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x70)
1143 #define INIT_HCA_UDAV_OFFSET             0x0b0
1144 #define  INIT_HCA_UDAV_LKEY_OFFSET       (INIT_HCA_UDAV_OFFSET + 0x0)
1145 #define  INIT_HCA_UDAV_PD_OFFSET         (INIT_HCA_UDAV_OFFSET + 0x4)
1146 #define INIT_HCA_MCAST_OFFSET            0x0c0
1147 #define  INIT_HCA_MC_BASE_OFFSET         (INIT_HCA_MCAST_OFFSET + 0x00)
1148 #define  INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1149 #define  INIT_HCA_MC_HASH_SZ_OFFSET      (INIT_HCA_MCAST_OFFSET + 0x16)
1150 #define  INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1151 #define INIT_HCA_TPT_OFFSET              0x0f0
1152 #define  INIT_HCA_MPT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x00)
1153 #define  INIT_HCA_MTT_SEG_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x09)
1154 #define  INIT_HCA_LOG_MPT_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x0b)
1155 #define  INIT_HCA_MTT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x10)
1156 #define INIT_HCA_UAR_OFFSET              0x120
1157 #define  INIT_HCA_UAR_BASE_OFFSET        (INIT_HCA_UAR_OFFSET + 0x00)
1158 #define  INIT_HCA_UARC_SZ_OFFSET         (INIT_HCA_UAR_OFFSET + 0x09)
1159 #define  INIT_HCA_LOG_UAR_SZ_OFFSET      (INIT_HCA_UAR_OFFSET + 0x0a)
1160 #define  INIT_HCA_UAR_PAGE_SZ_OFFSET     (INIT_HCA_UAR_OFFSET + 0x0b)
1161 #define  INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1162 #define  INIT_HCA_UAR_CTX_BASE_OFFSET    (INIT_HCA_UAR_OFFSET + 0x18)
1163
1164         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1165         if (IS_ERR(mailbox))
1166                 return PTR_ERR(mailbox);
1167         inbox = mailbox->buf;
1168
1169         memset(inbox, 0, INIT_HCA_IN_SIZE);
1170
1171 #if defined(__LITTLE_ENDIAN)
1172         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1173 #elif defined(__BIG_ENDIAN)
1174         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1175 #else
1176 #error Host endianness not defined
1177 #endif
1178         /* Check port for UD address vector: */
1179         *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1180
1181         /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1182
1183         /* QPC/EEC/CQC/EQC/RDB attributes */
1184
1185         MTHCA_PUT(inbox, param->qpc_base,     INIT_HCA_QPC_BASE_OFFSET);
1186         MTHCA_PUT(inbox, param->log_num_qps,  INIT_HCA_LOG_QP_OFFSET);
1187         MTHCA_PUT(inbox, param->eec_base,     INIT_HCA_EEC_BASE_OFFSET);
1188         MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1189         MTHCA_PUT(inbox, param->srqc_base,    INIT_HCA_SRQC_BASE_OFFSET);
1190         MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1191         MTHCA_PUT(inbox, param->cqc_base,     INIT_HCA_CQC_BASE_OFFSET);
1192         MTHCA_PUT(inbox, param->log_num_cqs,  INIT_HCA_LOG_CQ_OFFSET);
1193         MTHCA_PUT(inbox, param->eqpc_base,    INIT_HCA_EQPC_BASE_OFFSET);
1194         MTHCA_PUT(inbox, param->eeec_base,    INIT_HCA_EEEC_BASE_OFFSET);
1195         MTHCA_PUT(inbox, param->eqc_base,     INIT_HCA_EQC_BASE_OFFSET);
1196         MTHCA_PUT(inbox, param->log_num_eqs,  INIT_HCA_LOG_EQ_OFFSET);
1197         MTHCA_PUT(inbox, param->rdb_base,     INIT_HCA_RDB_BASE_OFFSET);
1198
1199         /* UD AV attributes */
1200
1201         /* multicast attributes */
1202
1203         MTHCA_PUT(inbox, param->mc_base,         INIT_HCA_MC_BASE_OFFSET);
1204         MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1205         MTHCA_PUT(inbox, param->mc_hash_sz,      INIT_HCA_MC_HASH_SZ_OFFSET);
1206         MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1207
1208         /* TPT attributes */
1209
1210         MTHCA_PUT(inbox, param->mpt_base,   INIT_HCA_MPT_BASE_OFFSET);
1211         if (!mthca_is_memfree(dev))
1212                 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1213         MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1214         MTHCA_PUT(inbox, param->mtt_base,   INIT_HCA_MTT_BASE_OFFSET);
1215
1216         /* UAR attributes */
1217         {
1218                 u8 uar_page_sz = PAGE_SHIFT - 12;
1219                 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1220         }
1221
1222         MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1223
1224         if (mthca_is_memfree(dev)) {
1225                 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1226                 MTHCA_PUT(inbox, param->log_uar_sz,  INIT_HCA_LOG_UAR_SZ_OFFSET);
1227                 MTHCA_PUT(inbox, param->uarc_base,   INIT_HCA_UAR_CTX_BASE_OFFSET);
1228         }
1229
1230         err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
1231
1232         mthca_free_mailbox(dev, mailbox);
1233         return err;
1234 }
1235
1236 int mthca_INIT_IB(struct mthca_dev *dev,
1237                   struct mthca_init_ib_param *param,
1238                   int port, u8 *status)
1239 {
1240         struct mthca_mailbox *mailbox;
1241         u32 *inbox;
1242         int err;
1243         u32 flags;
1244
1245 #define INIT_IB_IN_SIZE          56
1246 #define INIT_IB_FLAGS_OFFSET     0x00
1247 #define INIT_IB_FLAG_SIG         (1 << 18)
1248 #define INIT_IB_FLAG_NG          (1 << 17)
1249 #define INIT_IB_FLAG_G0          (1 << 16)
1250 #define INIT_IB_FLAG_1X          (1 << 8)
1251 #define INIT_IB_FLAG_4X          (1 << 9)
1252 #define INIT_IB_FLAG_12X         (1 << 11)
1253 #define INIT_IB_VL_SHIFT         4
1254 #define INIT_IB_MTU_SHIFT        12
1255 #define INIT_IB_MAX_GID_OFFSET   0x06
1256 #define INIT_IB_MAX_PKEY_OFFSET  0x0a
1257 #define INIT_IB_GUID0_OFFSET     0x10
1258 #define INIT_IB_NODE_GUID_OFFSET 0x18
1259 #define INIT_IB_SI_GUID_OFFSET   0x20
1260
1261         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1262         if (IS_ERR(mailbox))
1263                 return PTR_ERR(mailbox);
1264         inbox = mailbox->buf;
1265
1266         memset(inbox, 0, INIT_IB_IN_SIZE);
1267
1268         flags = 0;
1269         flags |= param->enable_1x     ? INIT_IB_FLAG_1X  : 0;
1270         flags |= param->enable_4x     ? INIT_IB_FLAG_4X  : 0;
1271         flags |= param->set_guid0     ? INIT_IB_FLAG_G0  : 0;
1272         flags |= param->set_node_guid ? INIT_IB_FLAG_NG  : 0;
1273         flags |= param->set_si_guid   ? INIT_IB_FLAG_SIG : 0;
1274         flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1275         flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1276         MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1277
1278         MTHCA_PUT(inbox, param->gid_cap,   INIT_IB_MAX_GID_OFFSET);
1279         MTHCA_PUT(inbox, param->pkey_cap,  INIT_IB_MAX_PKEY_OFFSET);
1280         MTHCA_PUT(inbox, param->guid0,     INIT_IB_GUID0_OFFSET);
1281         MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1282         MTHCA_PUT(inbox, param->si_guid,   INIT_IB_SI_GUID_OFFSET);
1283
1284         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1285                         CMD_TIME_CLASS_A, status);
1286
1287         mthca_free_mailbox(dev, mailbox);
1288         return err;
1289 }
1290
1291 int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1292 {
1293         return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
1294 }
1295
1296 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1297 {
1298         return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
1299 }
1300
1301 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1302                  int port, u8 *status)
1303 {
1304         struct mthca_mailbox *mailbox;
1305         u32 *inbox;
1306         int err;
1307         u32 flags = 0;
1308
1309 #define SET_IB_IN_SIZE         0x40
1310 #define SET_IB_FLAGS_OFFSET    0x00
1311 #define SET_IB_FLAG_SIG        (1 << 18)
1312 #define SET_IB_FLAG_RQK        (1 <<  0)
1313 #define SET_IB_CAP_MASK_OFFSET 0x04
1314 #define SET_IB_SI_GUID_OFFSET  0x08
1315
1316         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1317         if (IS_ERR(mailbox))
1318                 return PTR_ERR(mailbox);
1319         inbox = mailbox->buf;
1320
1321         memset(inbox, 0, SET_IB_IN_SIZE);
1322
1323         flags |= param->set_si_guid     ? SET_IB_FLAG_SIG : 0;
1324         flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1325         MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1326
1327         MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1328         MTHCA_PUT(inbox, param->si_guid,  SET_IB_SI_GUID_OFFSET);
1329
1330         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1331                         CMD_TIME_CLASS_B, status);
1332
1333         mthca_free_mailbox(dev, mailbox);
1334         return err;
1335 }
1336
1337 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1338 {
1339         return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1340 }
1341
1342 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1343 {
1344         struct mthca_mailbox *mailbox;
1345         u64 *inbox;
1346         int err;
1347
1348         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1349         if (IS_ERR(mailbox))
1350                 return PTR_ERR(mailbox);
1351         inbox = mailbox->buf;
1352
1353         inbox[0] = cpu_to_be64(virt);
1354         inbox[1] = cpu_to_be64(dma_addr);
1355
1356         err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1357                         CMD_TIME_CLASS_B, status);
1358
1359         mthca_free_mailbox(dev, mailbox);
1360
1361         if (!err)
1362                 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1363                           (unsigned long long) dma_addr, (unsigned long long) virt);
1364
1365         return err;
1366 }
1367
1368 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1369 {
1370         mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1371                   page_count, (unsigned long long) virt);
1372
1373         return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1374 }
1375
1376 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1377 {
1378         return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1379 }
1380
1381 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1382 {
1383         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1384 }
1385
1386 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1387                        u8 *status)
1388 {
1389         int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1390                                 CMD_TIME_CLASS_A, status);
1391
1392         if (ret || status)
1393                 return ret;
1394
1395         /*
1396          * Arbel page size is always 4 KB; round up number of system
1397          * pages needed.
1398          */
1399         *aux_pages = (*aux_pages + (1 << (PAGE_SHIFT - 12)) - 1) >> (PAGE_SHIFT - 12);
1400
1401         return 0;
1402 }
1403
1404 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1405                     int mpt_index, u8 *status)
1406 {
1407         return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1408                          CMD_TIME_CLASS_B, status);
1409 }
1410
1411 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1412                     int mpt_index, u8 *status)
1413 {
1414         return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1415                              !mailbox, CMD_HW2SW_MPT,
1416                              CMD_TIME_CLASS_B, status);
1417 }
1418
1419 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1420                     int num_mtt, u8 *status)
1421 {
1422         return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1423                          CMD_TIME_CLASS_B, status);
1424 }
1425
1426 int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1427 {
1428         return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1429 }
1430
1431 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1432                  int eq_num, u8 *status)
1433 {
1434         mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1435                   unmap ? "Clearing" : "Setting",
1436                   (unsigned long long) event_mask, eq_num);
1437         return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1438                          0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1439 }
1440
1441 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1442                    int eq_num, u8 *status)
1443 {
1444         return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1445                          CMD_TIME_CLASS_A, status);
1446 }
1447
1448 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1449                    int eq_num, u8 *status)
1450 {
1451         return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1452                              CMD_HW2SW_EQ,
1453                              CMD_TIME_CLASS_A, status);
1454 }
1455
1456 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1457                    int cq_num, u8 *status)
1458 {
1459         return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1460                         CMD_TIME_CLASS_A, status);
1461 }
1462
1463 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1464                    int cq_num, u8 *status)
1465 {
1466         return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1467                              CMD_HW2SW_CQ,
1468                              CMD_TIME_CLASS_A, status);
1469 }
1470
1471 int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
1472                     int is_ee, struct mthca_mailbox *mailbox, u32 optmask,
1473                     u8 *status)
1474 {
1475         static const u16 op[] = {
1476                 [MTHCA_TRANS_RST2INIT]  = CMD_RST2INIT_QPEE,
1477                 [MTHCA_TRANS_INIT2INIT] = CMD_INIT2INIT_QPEE,
1478                 [MTHCA_TRANS_INIT2RTR]  = CMD_INIT2RTR_QPEE,
1479                 [MTHCA_TRANS_RTR2RTS]   = CMD_RTR2RTS_QPEE,
1480                 [MTHCA_TRANS_RTS2RTS]   = CMD_RTS2RTS_QPEE,
1481                 [MTHCA_TRANS_SQERR2RTS] = CMD_SQERR2RTS_QPEE,
1482                 [MTHCA_TRANS_ANY2ERR]   = CMD_2ERR_QPEE,
1483                 [MTHCA_TRANS_RTS2SQD]   = CMD_RTS2SQD_QPEE,
1484                 [MTHCA_TRANS_SQD2SQD]   = CMD_SQD2SQD_QPEE,
1485                 [MTHCA_TRANS_SQD2RTS]   = CMD_SQD2RTS_QPEE,
1486                 [MTHCA_TRANS_ANY2RST]   = CMD_ERR2RST_QPEE
1487         };
1488         u8 op_mod = 0;
1489         int my_mailbox = 0;
1490         int err;
1491
1492         if (trans < 0 || trans >= ARRAY_SIZE(op))
1493                 return -EINVAL;
1494
1495         if (trans == MTHCA_TRANS_ANY2RST) {
1496                 op_mod = 3;     /* don't write outbox, any->reset */
1497
1498                 /* For debugging */
1499                 if (!mailbox) {
1500                         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1501                         if (!IS_ERR(mailbox)) {
1502                                 my_mailbox = 1;
1503                                 op_mod     = 2; /* write outbox, any->reset */
1504                         } else
1505                                 mailbox = NULL;
1506                 }
1507         } else {
1508                 if (0) {
1509                         int i;
1510                         mthca_dbg(dev, "Dumping QP context:\n");
1511                         printk("  opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1512                         for (i = 0; i < 0x100 / 4; ++i) {
1513                                 if (i % 8 == 0)
1514                                         printk("  [%02x] ", i * 4);
1515                                 printk(" %08x",
1516                                        be32_to_cpu(((u32 *) mailbox->buf)[i + 2]));
1517                                 if ((i + 1) % 8 == 0)
1518                                         printk("\n");
1519                         }
1520                 }
1521         }
1522
1523         if (trans == MTHCA_TRANS_ANY2RST) {
1524                 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1525                                     (!!is_ee << 24) | num, op_mod,
1526                                     op[trans], CMD_TIME_CLASS_C, status);
1527
1528                 if (0 && mailbox) {
1529                         int i;
1530                         mthca_dbg(dev, "Dumping QP context:\n");
1531                         printk(" %08x\n", be32_to_cpup(mailbox->buf));
1532                         for (i = 0; i < 0x100 / 4; ++i) {
1533                                 if (i % 8 == 0)
1534                                         printk("[%02x] ", i * 4);
1535                                 printk(" %08x",
1536                                        be32_to_cpu(((u32 *) mailbox->buf)[i + 2]));
1537                                 if ((i + 1) % 8 == 0)
1538                                         printk("\n");
1539                         }
1540                 }
1541
1542         } else
1543                 err = mthca_cmd(dev, mailbox->dma, (!!is_ee << 24) | num,
1544                                 op_mod, op[trans], CMD_TIME_CLASS_C, status);
1545
1546         if (my_mailbox)
1547                 mthca_free_mailbox(dev, mailbox);
1548
1549         return err;
1550 }
1551
1552 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1553                    struct mthca_mailbox *mailbox, u8 *status)
1554 {
1555         return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1556                              CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1557 }
1558
1559 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1560                           u8 *status)
1561 {
1562         u8 op_mod;
1563
1564         switch (type) {
1565         case IB_QPT_SMI:
1566                 op_mod = 0;
1567                 break;
1568         case IB_QPT_GSI:
1569                 op_mod = 1;
1570                 break;
1571         case IB_QPT_RAW_IPV6:
1572                 op_mod = 2;
1573                 break;
1574         case IB_QPT_RAW_ETY:
1575                 op_mod = 3;
1576                 break;
1577         default:
1578                 return -EINVAL;
1579         }
1580
1581         return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1582                          CMD_TIME_CLASS_B, status);
1583 }
1584
1585 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1586                   int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1587                   void *in_mad, void *response_mad, u8 *status)
1588 {
1589         struct mthca_mailbox *inmailbox, *outmailbox;
1590         void *inbox;
1591         int err;
1592         u32 in_modifier = port;
1593         u8 op_modifier = 0;
1594
1595 #define MAD_IFC_BOX_SIZE      0x400
1596 #define MAD_IFC_MY_QPN_OFFSET 0x100
1597 #define MAD_IFC_RQPN_OFFSET   0x104
1598 #define MAD_IFC_SL_OFFSET     0x108
1599 #define MAD_IFC_G_PATH_OFFSET 0x109
1600 #define MAD_IFC_RLID_OFFSET   0x10a
1601 #define MAD_IFC_PKEY_OFFSET   0x10e
1602 #define MAD_IFC_GRH_OFFSET    0x140
1603
1604         inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1605         if (IS_ERR(inmailbox))
1606                 return PTR_ERR(inmailbox);
1607         inbox = inmailbox->buf;
1608
1609         outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1610         if (IS_ERR(outmailbox)) {
1611                 mthca_free_mailbox(dev, inmailbox);
1612                 return PTR_ERR(outmailbox);
1613         }
1614
1615         memcpy(inbox, in_mad, 256);
1616
1617         /*
1618          * Key check traps can't be generated unless we have in_wc to
1619          * tell us where to send the trap.
1620          */
1621         if (ignore_mkey || !in_wc)
1622                 op_modifier |= 0x1;
1623         if (ignore_bkey || !in_wc)
1624                 op_modifier |= 0x2;
1625
1626         if (in_wc) {
1627                 u8 val;
1628
1629                 memset(inbox + 256, 0, 256);
1630
1631                 MTHCA_PUT(inbox, in_wc->qp_num,     MAD_IFC_MY_QPN_OFFSET);
1632                 MTHCA_PUT(inbox, in_wc->src_qp,     MAD_IFC_RQPN_OFFSET);
1633
1634                 val = in_wc->sl << 4;
1635                 MTHCA_PUT(inbox, val,               MAD_IFC_SL_OFFSET);
1636
1637                 val = in_wc->dlid_path_bits |
1638                         (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1639                 MTHCA_PUT(inbox, val,               MAD_IFC_GRH_OFFSET);
1640
1641                 MTHCA_PUT(inbox, in_wc->slid,       MAD_IFC_RLID_OFFSET);
1642                 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1643
1644                 if (in_grh)
1645                         memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1646
1647                 op_modifier |= 0x10;
1648
1649                 in_modifier |= in_wc->slid << 16;
1650         }
1651
1652         err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1653                             in_modifier, op_modifier,
1654                             CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1655
1656         if (!err && !*status)
1657                 memcpy(response_mad, outmailbox->buf, 256);
1658
1659         mthca_free_mailbox(dev, inmailbox);
1660         mthca_free_mailbox(dev, outmailbox);
1661         return err;
1662 }
1663
1664 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1665                    struct mthca_mailbox *mailbox, u8 *status)
1666 {
1667         return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1668                              CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1669 }
1670
1671 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1672                     struct mthca_mailbox *mailbox, u8 *status)
1673 {
1674         return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1675                          CMD_TIME_CLASS_A, status);
1676 }
1677
1678 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1679                     u16 *hash, u8 *status)
1680 {
1681         u64 imm;
1682         int err;
1683
1684         err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1685                             CMD_TIME_CLASS_A, status);
1686
1687         *hash = imm;
1688         return err;
1689 }
1690
1691 int mthca_NOP(struct mthca_dev *dev, u8 *status)
1692 {
1693         return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1694 }