3 * Purpose: Generic MCA handling layer
5 * Updated for latest kernel
6 * Copyright (C) 2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Dell Inc.
10 * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
12 * Copyright (C) 2002 Intel
13 * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
15 * Copyright (C) 2001 Intel
16 * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
18 * Copyright (C) 2000 Intel
19 * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
21 * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
22 * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
24 * 03/04/15 D. Mosberger Added INIT backtrace support.
25 * 02/03/25 M. Domsch GUID cleanups
27 * 02/01/04 J. Hall Aligned MCA stack to 16 bytes, added platform vs. CPU
28 * error flag, set SAL default return values, changed
29 * error record structure to linked list, added init call
30 * to sal_get_state_info_size().
32 * 01/01/03 F. Lewis Added setup of CMCI and CPEI IRQs, logging of corrected
33 * platform errors, completed code for logging of
34 * corrected & uncorrected machine check errors, and
35 * updated for conformance with Nov. 2000 revision of the
37 * 00/03/29 C. Fleckenstein Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38 * added min save state dump, added INIT handler.
40 * 2003-12-08 Keith Owens <kaos@sgi.com>
41 * smp_call_function() must not be called from interrupt context (can
42 * deadlock on tasklist_lock). Use keventd to call smp_call_function().
44 * 2004-02-01 Keith Owens <kaos@sgi.com>
45 * Avoid deadlock when using printk() for MCA and INIT records.
46 * Delete all record printing code, moved to salinfo_decode in user space.
47 * Mark variables and functions static where possible.
48 * Delete dead variables and functions.
49 * Reorder to remove the need for forward declarations and to consolidate
52 * 2005-08-12 Keith Owens <kaos@sgi.com>
53 * Convert MCA/INIT handlers to use per event stacks and SAL/OS state.
55 * 2005-10-07 Keith Owens <kaos@sgi.com>
56 * Add notify_die() hooks.
58 #include <linux/config.h>
59 #include <linux/types.h>
60 #include <linux/init.h>
61 #include <linux/sched.h>
62 #include <linux/interrupt.h>
63 #include <linux/irq.h>
64 #include <linux/smp_lock.h>
65 #include <linux/bootmem.h>
66 #include <linux/acpi.h>
67 #include <linux/timer.h>
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/smp.h>
71 #include <linux/workqueue.h>
72 #include <linux/cpumask.h>
74 #include <asm/delay.h>
75 #include <asm/kdebug.h>
76 #include <asm/machvec.h>
77 #include <asm/meminit.h>
79 #include <asm/ptrace.h>
80 #include <asm/system.h>
85 #include <asm/hw_irq.h>
90 #if defined(IA64_MCA_DEBUG_INFO)
91 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
93 # define IA64_MCA_DEBUG(fmt...)
96 /* Used by mca_asm.S */
97 u32 ia64_mca_serialize;
98 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
99 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
100 DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */
101 DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */
103 unsigned long __per_cpu_mca[NR_CPUS];
106 extern void ia64_os_init_dispatch_monarch (void);
107 extern void ia64_os_init_dispatch_slave (void);
109 static int monarch_cpu = -1;
111 static ia64_mc_info_t ia64_mc_info;
113 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
114 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
115 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
116 #define CPE_HISTORY_LENGTH 5
117 #define CMC_HISTORY_LENGTH 5
119 static struct timer_list cpe_poll_timer;
120 static struct timer_list cmc_poll_timer;
122 * This variable tells whether we are currently in polling mode.
123 * Start with this in the wrong state so we won't play w/ timers
124 * before the system is ready.
126 static int cmc_polling_enabled = 1;
129 * Clearing this variable prevents CPE polling from getting activated
130 * in mca_late_init. Use it if your system doesn't provide a CPEI,
131 * but encounters problems retrieving CPE logs. This should only be
132 * necessary for debugging.
134 static int cpe_poll_enabled = 1;
136 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
138 static int mca_init __initdata;
142 ia64_mca_spin(const char *func)
144 printk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
149 * IA64_MCA log support
151 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
152 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
154 typedef struct ia64_state_log_s
158 unsigned long isl_count;
159 ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
162 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
164 #define IA64_LOG_ALLOCATE(it, size) \
165 {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
166 (ia64_err_rec_t *)alloc_bootmem(size); \
167 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
168 (ia64_err_rec_t *)alloc_bootmem(size);}
169 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
170 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
171 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
172 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
173 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
174 #define IA64_LOG_INDEX_INC(it) \
175 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
176 ia64_state_log[it].isl_count++;}
177 #define IA64_LOG_INDEX_DEC(it) \
178 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
179 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
180 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
181 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
185 * Reset the OS ia64 log buffer
186 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
190 ia64_log_init(int sal_info_type)
194 IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
195 IA64_LOG_LOCK_INIT(sal_info_type);
197 // SAL will tell us the maximum size of any error record of this type
198 max_size = ia64_sal_get_state_info_size(sal_info_type);
200 /* alloc_bootmem() doesn't like zero-sized allocations! */
203 // set up OS data structures to hold error info
204 IA64_LOG_ALLOCATE(sal_info_type, max_size);
205 memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
206 memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
212 * Get the current MCA log from SAL and copy it into the OS log buffer.
214 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
215 * irq_safe whether you can use printk at this point
216 * Outputs : size (total record length)
217 * *buffer (ptr to error record)
221 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
223 sal_log_record_header_t *log_buffer;
227 IA64_LOG_LOCK(sal_info_type);
229 /* Get the process state information */
230 log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
232 total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
235 IA64_LOG_INDEX_INC(sal_info_type);
236 IA64_LOG_UNLOCK(sal_info_type);
238 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
239 "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
241 *buffer = (u8 *) log_buffer;
244 IA64_LOG_UNLOCK(sal_info_type);
250 * ia64_mca_log_sal_error_record
252 * This function retrieves a specified error record type from SAL
253 * and wakes up any processes waiting for error records.
255 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE)
256 * FIXME: remove MCA and irq_safe.
259 ia64_mca_log_sal_error_record(int sal_info_type)
262 sal_log_record_header_t *rh;
264 int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
265 #ifdef IA64_MCA_DEBUG_INFO
266 static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
269 size = ia64_log_get(sal_info_type, &buffer, irq_safe);
273 salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
276 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
278 sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
280 /* Clear logs from corrected errors in case there's no user-level logger */
281 rh = (sal_log_record_header_t *)buffer;
282 if (rh->severity == sal_log_severity_corrected)
283 ia64_sal_clear_state_info(sal_info_type);
288 * See if the MCA surfaced in an instruction range
289 * that has been tagged as recoverable.
292 * first First address range to check
293 * last Last address range to check
294 * ip Instruction pointer, address we are looking for
297 * 1 on Success (in the table)/ 0 on Failure (not in the table)
300 search_mca_table (const struct mca_table_entry *first,
301 const struct mca_table_entry *last,
304 const struct mca_table_entry *curr;
305 u64 curr_start, curr_end;
308 while (curr <= last) {
309 curr_start = (u64) &curr->start_addr + curr->start_addr;
310 curr_end = (u64) &curr->end_addr + curr->end_addr;
312 if ((ip >= curr_start) && (ip <= curr_end)) {
320 /* Given an address, look for it in the mca tables. */
321 int mca_recover_range(unsigned long addr)
323 extern struct mca_table_entry __start___mca_table[];
324 extern struct mca_table_entry __stop___mca_table[];
326 return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
328 EXPORT_SYMBOL_GPL(mca_recover_range);
333 int ia64_cpe_irq = -1;
336 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
338 static unsigned long cpe_history[CPE_HISTORY_LENGTH];
340 static DEFINE_SPINLOCK(cpe_history_lock);
342 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
343 __FUNCTION__, cpe_irq, smp_processor_id());
345 /* SAL spec states this should run w/ interrupts enabled */
348 /* Get the CPE error record and log it */
349 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
351 spin_lock(&cpe_history_lock);
352 if (!cpe_poll_enabled && cpe_vector >= 0) {
354 int i, count = 1; /* we know 1 happened now */
355 unsigned long now = jiffies;
357 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
358 if (now - cpe_history[i] <= HZ)
362 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
363 if (count >= CPE_HISTORY_LENGTH) {
365 cpe_poll_enabled = 1;
366 spin_unlock(&cpe_history_lock);
367 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
370 * Corrected errors will still be corrected, but
371 * make sure there's a log somewhere that indicates
372 * something is generating more than we can handle.
374 printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
376 mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
378 /* lock already released, get out now */
381 cpe_history[index++] = now;
382 if (index == CPE_HISTORY_LENGTH)
386 spin_unlock(&cpe_history_lock);
390 #endif /* CONFIG_ACPI */
394 * ia64_mca_register_cpev
396 * Register the corrected platform error vector with SAL.
399 * cpev Corrected Platform Error Vector number
405 ia64_mca_register_cpev (int cpev)
407 /* Register the CPE interrupt vector with SAL */
408 struct ia64_sal_retval isrv;
410 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
412 printk(KERN_ERR "Failed to register Corrected Platform "
413 "Error interrupt vector with SAL (status %ld)\n", isrv.status);
417 IA64_MCA_DEBUG("%s: corrected platform error "
418 "vector %#x registered\n", __FUNCTION__, cpev);
420 #endif /* CONFIG_ACPI */
423 * ia64_mca_cmc_vector_setup
425 * Setup the corrected machine check vector register in the processor.
426 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
427 * This function is invoked on a per-processor basis.
436 ia64_mca_cmc_vector_setup (void)
440 cmcv.cmcv_regval = 0;
441 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */
442 cmcv.cmcv_vector = IA64_CMC_VECTOR;
443 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
445 IA64_MCA_DEBUG("%s: CPU %d corrected "
446 "machine check vector %#x registered.\n",
447 __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
449 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
450 __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
454 * ia64_mca_cmc_vector_disable
456 * Mask the corrected machine check vector register in the processor.
457 * This function is invoked on a per-processor basis.
466 ia64_mca_cmc_vector_disable (void *dummy)
470 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
472 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
473 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
475 IA64_MCA_DEBUG("%s: CPU %d corrected "
476 "machine check vector %#x disabled.\n",
477 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
481 * ia64_mca_cmc_vector_enable
483 * Unmask the corrected machine check vector register in the processor.
484 * This function is invoked on a per-processor basis.
493 ia64_mca_cmc_vector_enable (void *dummy)
497 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
499 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
500 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
502 IA64_MCA_DEBUG("%s: CPU %d corrected "
503 "machine check vector %#x enabled.\n",
504 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
508 * ia64_mca_cmc_vector_disable_keventd
510 * Called via keventd (smp_call_function() is not safe in interrupt context) to
511 * disable the cmc interrupt vector.
514 ia64_mca_cmc_vector_disable_keventd(void *unused)
516 on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
520 * ia64_mca_cmc_vector_enable_keventd
522 * Called via keventd (smp_call_function() is not safe in interrupt context) to
523 * enable the cmc interrupt vector.
526 ia64_mca_cmc_vector_enable_keventd(void *unused)
528 on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
534 * Send an inter-cpu interrupt to wake-up a particular cpu
535 * and mark that cpu to be out of rendez.
541 ia64_mca_wakeup(int cpu)
543 platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
544 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
549 * ia64_mca_wakeup_all
551 * Wakeup all the cpus which have rendez'ed previously.
557 ia64_mca_wakeup_all(void)
561 /* Clear the Rendez checkin flag for all cpus */
562 for_each_online_cpu(cpu) {
563 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
564 ia64_mca_wakeup(cpu);
570 * ia64_mca_rendez_interrupt_handler
572 * This is handler used to put slave processors into spinloop
573 * while the monarch processor does the mca handling and later
574 * wake each slave up once the monarch is done.
580 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *regs)
583 int cpu = smp_processor_id();
584 struct ia64_mca_notify_die nd =
585 { .sos = NULL, .monarch_cpu = &monarch_cpu };
587 /* Mask all interrupts */
588 local_irq_save(flags);
589 if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", regs, (long)&nd, 0, 0)
591 ia64_mca_spin(__FUNCTION__);
593 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
594 /* Register with the SAL monarch that the slave has
597 ia64_sal_mc_rendez();
599 if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", regs, (long)&nd, 0, 0)
601 ia64_mca_spin(__FUNCTION__);
603 /* Wait for the monarch cpu to exit. */
604 while (monarch_cpu != -1)
605 cpu_relax(); /* spin until monarch leaves */
607 if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", regs, (long)&nd, 0, 0)
609 ia64_mca_spin(__FUNCTION__);
611 /* Enable all interrupts */
612 local_irq_restore(flags);
617 * ia64_mca_wakeup_int_handler
619 * The interrupt handler for processing the inter-cpu interrupt to the
620 * slave cpu which was spinning in the rendez loop.
621 * Since this spinning is done by turning off the interrupts and
622 * polling on the wakeup-interrupt bit in the IRR, there is
623 * nothing useful to be done in the handler.
625 * Inputs : wakeup_irq (Wakeup-interrupt bit)
626 * arg (Interrupt handler specific argument)
627 * ptregs (Exception frame at the time of the interrupt)
632 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
637 /* Function pointer for extra MCA recovery */
638 int (*ia64_mca_ucmc_extension)
639 (void*,struct ia64_sal_os_state*)
643 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
645 if (ia64_mca_ucmc_extension)
648 ia64_mca_ucmc_extension = fn;
653 ia64_unreg_MCA_extension(void)
655 if (ia64_mca_ucmc_extension)
656 ia64_mca_ucmc_extension = NULL;
659 EXPORT_SYMBOL(ia64_reg_MCA_extension);
660 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
664 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat)
666 u64 fslot, tslot, nat;
668 fslot = ((unsigned long)fr >> 3) & 63;
669 tslot = ((unsigned long)tr >> 3) & 63;
670 *tnat &= ~(1UL << tslot);
671 nat = (fnat >> fslot) & 1;
672 *tnat |= (nat << tslot);
675 /* Change the comm field on the MCA/INT task to include the pid that
676 * was interrupted, it makes for easier debugging. If that pid was 0
677 * (swapper or nested MCA/INIT) then use the start of the previous comm
678 * field suffixed with its cpu.
682 ia64_mca_modify_comm(const task_t *previous_current)
684 char *p, comm[sizeof(current->comm)];
685 if (previous_current->pid)
686 snprintf(comm, sizeof(comm), "%s %d",
687 current->comm, previous_current->pid);
690 if ((p = strchr(previous_current->comm, ' ')))
691 l = p - previous_current->comm;
693 l = strlen(previous_current->comm);
694 snprintf(comm, sizeof(comm), "%s %*s %d",
695 current->comm, l, previous_current->comm,
696 task_thread_info(previous_current)->cpu);
698 memcpy(current->comm, comm, sizeof(current->comm));
701 /* On entry to this routine, we are running on the per cpu stack, see
702 * mca_asm.h. The original stack has not been touched by this event. Some of
703 * the original stack's registers will be in the RBS on this stack. This stack
704 * also contains a partial pt_regs and switch_stack, the rest of the data is in
707 * The first thing to do is modify the original stack to look like a blocked
708 * task so we can run backtrace on the original task. Also mark the per cpu
709 * stack as current to ensure that we use the correct task state, it also means
710 * that we can do backtrace on the MCA/INIT handler code itself.
714 ia64_mca_modify_original_stack(struct pt_regs *regs,
715 const struct switch_stack *sw,
716 struct ia64_sal_os_state *sos,
721 extern char ia64_leave_kernel[]; /* Need asm address, not function descriptor */
722 const pal_min_state_area_t *ms = sos->pal_min_state;
723 task_t *previous_current;
724 struct pt_regs *old_regs;
725 struct switch_stack *old_sw;
726 unsigned size = sizeof(struct pt_regs) +
727 sizeof(struct switch_stack) + 16;
728 u64 *old_bspstore, *old_bsp;
729 u64 *new_bspstore, *new_bsp;
730 u64 old_unat, old_rnat, new_rnat, nat;
731 u64 slots, loadrs = regs->loadrs;
732 u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
733 u64 ar_bspstore = regs->ar_bspstore;
734 u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
737 int cpu = smp_processor_id();
739 previous_current = curr_task(cpu);
740 set_curr_task(cpu, current);
741 if ((p = strchr(current->comm, ' ')))
744 /* Best effort attempt to cope with MCA/INIT delivered while in
747 regs->cr_ipsr = ms->pmsa_ipsr;
748 if (ia64_psr(regs)->dt == 0) {
760 if (ia64_psr(regs)->rt == 0) {
773 /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
774 * have been copied to the old stack, the old stack may fail the
775 * validation tests below. So ia64_old_stack() must restore the dirty
776 * registers from the new stack. The old and new bspstore probably
777 * have different alignments, so loadrs calculated on the old bsp
778 * cannot be used to restore from the new bsp. Calculate a suitable
779 * loadrs for the new stack and save it in the new pt_regs, where
780 * ia64_old_stack() can get it.
782 old_bspstore = (u64 *)ar_bspstore;
783 old_bsp = (u64 *)ar_bsp;
784 slots = ia64_rse_num_regs(old_bspstore, old_bsp);
785 new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET);
786 new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
787 regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
789 /* Verify the previous stack state before we change it */
790 if (user_mode(regs)) {
791 msg = "occurred in user space";
792 /* previous_current is guaranteed to be valid when the task was
793 * in user space, so ...
795 ia64_mca_modify_comm(previous_current);
799 if (!mca_recover_range(ms->pmsa_iip)) {
800 if (r13 != sos->prev_IA64_KR_CURRENT) {
801 msg = "inconsistent previous current and r13";
804 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
805 msg = "inconsistent r12 and r13";
808 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
809 msg = "inconsistent ar.bspstore and r13";
814 msg = "old_bspstore is in the wrong region";
817 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
818 msg = "inconsistent ar.bsp and r13";
821 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
822 if (ar_bspstore + size > r12) {
823 msg = "no room for blocked state";
828 ia64_mca_modify_comm(previous_current);
830 /* Make the original task look blocked. First stack a struct pt_regs,
831 * describing the state at the time of interrupt. mca_asm.S built a
832 * partial pt_regs, copy it and fill in the blanks using minstate.
834 p = (char *)r12 - sizeof(*regs);
835 old_regs = (struct pt_regs *)p;
836 memcpy(old_regs, regs, sizeof(*regs));
837 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
838 * pmsa_{xip,xpsr,xfs}
840 if (ia64_psr(regs)->ic) {
841 old_regs->cr_iip = ms->pmsa_iip;
842 old_regs->cr_ipsr = ms->pmsa_ipsr;
843 old_regs->cr_ifs = ms->pmsa_ifs;
845 old_regs->cr_iip = ms->pmsa_xip;
846 old_regs->cr_ipsr = ms->pmsa_xpsr;
847 old_regs->cr_ifs = ms->pmsa_xfs;
849 old_regs->pr = ms->pmsa_pr;
850 old_regs->b0 = ms->pmsa_br0;
851 old_regs->loadrs = loadrs;
852 old_regs->ar_rsc = ms->pmsa_rsc;
853 old_unat = old_regs->ar_unat;
854 copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat);
855 copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
856 copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
857 copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
858 copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
859 copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
860 copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
861 copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
862 copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
863 copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
864 copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
865 if (ia64_psr(old_regs)->bn)
866 bank = ms->pmsa_bank1_gr;
868 bank = ms->pmsa_bank0_gr;
869 copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
870 copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
871 copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
872 copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
873 copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
874 copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
875 copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
876 copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
877 copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
878 copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
879 copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
880 copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
881 copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
882 copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
883 copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
884 copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
886 /* Next stack a struct switch_stack. mca_asm.S built a partial
887 * switch_stack, copy it and fill in the blanks using pt_regs and
890 * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
891 * ar.pfs is set to 0.
893 * unwind.c::unw_unwind() does special processing for interrupt frames.
894 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
895 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not
896 * that this is documented, of course. Set PRED_NON_SYSCALL in the
897 * switch_stack on the original stack so it will unwind correctly when
898 * unwind.c reads pt_regs.
900 * thread.ksp is updated to point to the synthesized switch_stack.
902 p -= sizeof(struct switch_stack);
903 old_sw = (struct switch_stack *)p;
904 memcpy(old_sw, sw, sizeof(*sw));
905 old_sw->caller_unat = old_unat;
906 old_sw->ar_fpsr = old_regs->ar_fpsr;
907 copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
908 copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
909 copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
910 copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
911 old_sw->b0 = (u64)ia64_leave_kernel;
912 old_sw->b1 = ms->pmsa_br1;
914 old_sw->ar_unat = old_unat;
915 old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
916 previous_current->thread.ksp = (u64)p - 16;
918 /* Finally copy the original stack's registers back to its RBS.
919 * Registers from ar.bspstore through ar.bsp at the time of the event
920 * are in the current RBS, copy them back to the original stack. The
921 * copy must be done register by register because the original bspstore
922 * and the current one have different alignments, so the saved RNAT
923 * data occurs at different places.
925 * mca_asm does cover, so the old_bsp already includes all registers at
926 * the time of MCA/INIT. It also does flushrs, so all registers before
927 * this function have been written to backing store on the MCA/INIT
930 new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
931 old_rnat = regs->ar_rnat;
933 if (ia64_rse_is_rnat_slot(new_bspstore)) {
934 new_rnat = ia64_get_rnat(new_bspstore++);
936 if (ia64_rse_is_rnat_slot(old_bspstore)) {
937 *old_bspstore++ = old_rnat;
940 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
941 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
942 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
943 *old_bspstore++ = *new_bspstore++;
945 old_sw->ar_bspstore = (unsigned long)old_bspstore;
946 old_sw->ar_rnat = old_rnat;
948 sos->prev_task = previous_current;
949 return previous_current;
952 printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
953 smp_processor_id(), type, msg);
954 return previous_current;
957 /* The monarch/slave interaction is based on monarch_cpu and requires that all
958 * slaves have entered rendezvous before the monarch leaves. If any cpu has
959 * not entered rendezvous yet then wait a bit. The assumption is that any
960 * slave that has not rendezvoused after a reasonable time is never going to do
961 * so. In this context, slave includes cpus that respond to the MCA rendezvous
962 * interrupt, as well as cpus that receive the INIT slave event.
966 ia64_wait_for_slaves(int monarch, const char *type)
968 int c, wait = 0, missing = 0;
969 for_each_online_cpu(c) {
972 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
973 udelay(1000); /* short wait first */
980 for_each_online_cpu(c) {
983 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
984 udelay(5*1000000); /* wait 5 seconds for slaves (arbitrary) */
985 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
992 printk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
993 for_each_online_cpu(c) {
996 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
1003 printk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
1010 * This is uncorrectable machine check handler called from OS_MCA
1011 * dispatch code which is in turn called from SAL_CHECK().
1012 * This is the place where the core of OS MCA handling is done.
1013 * Right now the logs are extracted and displayed in a well-defined
1014 * format. This handler code is supposed to be run only on the
1015 * monarch processor. Once the monarch is done with MCA handling
1016 * further MCA logging is enabled by clearing logs.
1017 * Monarch also has the duty of sending wakeup-IPIs to pull the
1018 * slave processors out of rendezvous spinloop.
1021 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1022 struct ia64_sal_os_state *sos)
1024 pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
1025 &sos->proc_state_param;
1026 int recover, cpu = smp_processor_id();
1027 task_t *previous_current;
1028 struct ia64_mca_notify_die nd =
1029 { .sos = sos, .monarch_cpu = &monarch_cpu };
1031 oops_in_progress = 1; /* FIXME: make printk NMI/MCA/INIT safe */
1032 console_loglevel = 15; /* make sure printks make it to console */
1033 printk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d monarch=%ld\n",
1034 sos->proc_state_param, cpu, sos->monarch);
1036 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1038 if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, (long)&nd, 0, 0)
1040 ia64_mca_spin(__FUNCTION__);
1041 ia64_wait_for_slaves(cpu, "MCA");
1043 /* Wakeup all the processors which are spinning in the rendezvous loop.
1044 * They will leave SAL, then spin in the OS with interrupts disabled
1045 * until this monarch cpu leaves the MCA handler. That gets control
1046 * back to the OS so we can backtrace the other cpus, backtrace when
1047 * spinning in SAL does not work.
1049 ia64_mca_wakeup_all();
1050 if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, (long)&nd, 0, 0)
1052 ia64_mca_spin(__FUNCTION__);
1054 /* Get the MCA error record and log it */
1055 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1057 /* TLB error is only exist in this SAL error record */
1058 recover = (psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc))
1059 /* other error recovery */
1060 || (ia64_mca_ucmc_extension
1061 && ia64_mca_ucmc_extension(
1062 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1066 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1067 rh->severity = sal_log_severity_corrected;
1068 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1069 sos->os_status = IA64_MCA_CORRECTED;
1071 if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, (long)&nd, 0, recover)
1073 ia64_mca_spin(__FUNCTION__);
1075 set_curr_task(cpu, previous_current);
1079 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
1080 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
1083 * ia64_mca_cmc_int_handler
1085 * This is corrected machine check interrupt handler.
1086 * Right now the logs are extracted and displayed in a well-defined
1091 * client data arg ptr
1092 * saved registers ptr
1098 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
1100 static unsigned long cmc_history[CMC_HISTORY_LENGTH];
1102 static DEFINE_SPINLOCK(cmc_history_lock);
1104 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1105 __FUNCTION__, cmc_irq, smp_processor_id());
1107 /* SAL spec states this should run w/ interrupts enabled */
1110 /* Get the CMC error record and log it */
1111 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1113 spin_lock(&cmc_history_lock);
1114 if (!cmc_polling_enabled) {
1115 int i, count = 1; /* we know 1 happened now */
1116 unsigned long now = jiffies;
1118 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1119 if (now - cmc_history[i] <= HZ)
1123 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1124 if (count >= CMC_HISTORY_LENGTH) {
1126 cmc_polling_enabled = 1;
1127 spin_unlock(&cmc_history_lock);
1128 /* If we're being hit with CMC interrupts, we won't
1129 * ever execute the schedule_work() below. Need to
1130 * disable CMC interrupts on this processor now.
1132 ia64_mca_cmc_vector_disable(NULL);
1133 schedule_work(&cmc_disable_work);
1136 * Corrected errors will still be corrected, but
1137 * make sure there's a log somewhere that indicates
1138 * something is generating more than we can handle.
1140 printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1142 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1144 /* lock already released, get out now */
1147 cmc_history[index++] = now;
1148 if (index == CMC_HISTORY_LENGTH)
1152 spin_unlock(&cmc_history_lock);
1157 * ia64_mca_cmc_int_caller
1159 * Triggered by sw interrupt from CMC polling routine. Calls
1160 * real interrupt handler and either triggers a sw interrupt
1161 * on the next cpu or does cleanup at the end.
1165 * client data arg ptr
1166 * saved registers ptr
1171 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
1173 static int start_count = -1;
1176 cpuid = smp_processor_id();
1178 /* If first cpu, update count */
1179 if (start_count == -1)
1180 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1182 ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
1184 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1186 if (cpuid < NR_CPUS) {
1187 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1189 /* If no log record, switch out of polling mode */
1190 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1192 printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1193 schedule_work(&cmc_enable_work);
1194 cmc_polling_enabled = 0;
1198 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1210 * Poll for Corrected Machine Checks (CMCs)
1212 * Inputs : dummy(unused)
1217 ia64_mca_cmc_poll (unsigned long dummy)
1219 /* Trigger a CMC interrupt cascade */
1220 platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1224 * ia64_mca_cpe_int_caller
1226 * Triggered by sw interrupt from CPE polling routine. Calls
1227 * real interrupt handler and either triggers a sw interrupt
1228 * on the next cpu or does cleanup at the end.
1232 * client data arg ptr
1233 * saved registers ptr
1240 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1242 static int start_count = -1;
1243 static int poll_time = MIN_CPE_POLL_INTERVAL;
1246 cpuid = smp_processor_id();
1248 /* If first cpu, update count */
1249 if (start_count == -1)
1250 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1252 ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1254 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1256 if (cpuid < NR_CPUS) {
1257 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1260 * If a log was recorded, increase our polling frequency,
1261 * otherwise, backoff or return to interrupt mode.
1263 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1264 poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1265 } else if (cpe_vector < 0) {
1266 poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1268 poll_time = MIN_CPE_POLL_INTERVAL;
1270 printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1271 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1272 cpe_poll_enabled = 0;
1275 if (cpe_poll_enabled)
1276 mod_timer(&cpe_poll_timer, jiffies + poll_time);
1286 * Poll for Corrected Platform Errors (CPEs), trigger interrupt
1287 * on first cpu, from there it will trickle through all the cpus.
1289 * Inputs : dummy(unused)
1294 ia64_mca_cpe_poll (unsigned long dummy)
1296 /* Trigger a CPE interrupt cascade */
1297 platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1300 #endif /* CONFIG_ACPI */
1303 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1306 struct task_struct *g, *t;
1307 if (val != DIE_INIT_MONARCH_PROCESS)
1309 printk(KERN_ERR "Processes interrupted by INIT -");
1310 for_each_online_cpu(c) {
1311 struct ia64_sal_os_state *s;
1312 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1313 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1317 printk(" %d", g->pid);
1319 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1323 if (read_trylock(&tasklist_lock)) {
1324 do_each_thread (g, t) {
1325 printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1326 show_stack(t, NULL);
1327 } while_each_thread (g, t);
1328 read_unlock(&tasklist_lock);
1334 * C portion of the OS INIT handler
1336 * Called from ia64_os_init_dispatch
1338 * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for
1339 * this event. This code is used for both monarch and slave INIT events, see
1342 * All INIT events switch to the INIT stack and change the previous process to
1343 * blocked status. If one of the INIT events is the monarch then we are
1344 * probably processing the nmi button/command. Use the monarch cpu to dump all
1345 * the processes. The slave INIT events all spin until the monarch cpu
1346 * returns. We can also get INIT slave events for MCA, in which case the MCA
1347 * process is the monarch.
1351 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1352 struct ia64_sal_os_state *sos)
1354 static atomic_t slaves;
1355 static atomic_t monarchs;
1356 task_t *previous_current;
1357 int cpu = smp_processor_id();
1358 struct ia64_mca_notify_die nd =
1359 { .sos = sos, .monarch_cpu = &monarch_cpu };
1361 oops_in_progress = 1; /* FIXME: make printk NMI/MCA/INIT safe */
1362 console_loglevel = 15; /* make sure printks make it to console */
1364 (void) notify_die(DIE_INIT_ENTER, "INIT", regs, (long)&nd, 0, 0);
1366 printk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1367 sos->proc_state_param, cpu, sos->monarch);
1368 salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1370 previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1371 sos->os_status = IA64_INIT_RESUME;
1373 /* FIXME: Workaround for broken proms that drive all INIT events as
1374 * slaves. The last slave that enters is promoted to be a monarch.
1375 * Remove this code in September 2006, that gives platforms a year to
1376 * fix their proms and get their customers updated.
1378 if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1379 printk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1381 atomic_dec(&slaves);
1385 /* FIXME: Workaround for broken proms that drive all INIT events as
1386 * monarchs. Second and subsequent monarchs are demoted to slaves.
1387 * Remove this code in September 2006, that gives platforms a year to
1388 * fix their proms and get their customers updated.
1390 if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1391 printk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1393 atomic_dec(&monarchs);
1397 if (!sos->monarch) {
1398 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1399 while (monarch_cpu == -1)
1400 cpu_relax(); /* spin until monarch enters */
1401 if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, (long)&nd, 0, 0)
1403 ia64_mca_spin(__FUNCTION__);
1404 if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, (long)&nd, 0, 0)
1406 ia64_mca_spin(__FUNCTION__);
1407 while (monarch_cpu != -1)
1408 cpu_relax(); /* spin until monarch leaves */
1409 if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, (long)&nd, 0, 0)
1411 ia64_mca_spin(__FUNCTION__);
1412 printk("Slave on cpu %d returning to normal service.\n", cpu);
1413 set_curr_task(cpu, previous_current);
1414 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1415 atomic_dec(&slaves);
1420 if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, (long)&nd, 0, 0)
1422 ia64_mca_spin(__FUNCTION__);
1425 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1426 * generated via the BMC's command-line interface, but since the console is on the
1427 * same serial line, the user will need some time to switch out of the BMC before
1430 printk("Delaying for 5 seconds...\n");
1432 ia64_wait_for_slaves(cpu, "INIT");
1433 /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1434 * to default_monarch_init_process() above and just print all the
1437 if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, (long)&nd, 0, 0)
1439 ia64_mca_spin(__FUNCTION__);
1440 if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, (long)&nd, 0, 0)
1442 ia64_mca_spin(__FUNCTION__);
1443 printk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu);
1444 atomic_dec(&monarchs);
1445 set_curr_task(cpu, previous_current);
1451 ia64_mca_disable_cpe_polling(char *str)
1453 cpe_poll_enabled = 0;
1457 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1459 static struct irqaction cmci_irqaction = {
1460 .handler = ia64_mca_cmc_int_handler,
1461 .flags = SA_INTERRUPT,
1465 static struct irqaction cmcp_irqaction = {
1466 .handler = ia64_mca_cmc_int_caller,
1467 .flags = SA_INTERRUPT,
1471 static struct irqaction mca_rdzv_irqaction = {
1472 .handler = ia64_mca_rendez_int_handler,
1473 .flags = SA_INTERRUPT,
1477 static struct irqaction mca_wkup_irqaction = {
1478 .handler = ia64_mca_wakeup_int_handler,
1479 .flags = SA_INTERRUPT,
1484 static struct irqaction mca_cpe_irqaction = {
1485 .handler = ia64_mca_cpe_int_handler,
1486 .flags = SA_INTERRUPT,
1490 static struct irqaction mca_cpep_irqaction = {
1491 .handler = ia64_mca_cpe_int_caller,
1492 .flags = SA_INTERRUPT,
1495 #endif /* CONFIG_ACPI */
1497 /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on
1498 * these stacks can never sleep, they cannot return from the kernel to user
1499 * space, they do not appear in a normal ps listing. So there is no need to
1500 * format most of the fields.
1503 static void __cpuinit
1504 format_mca_init_stack(void *mca_data, unsigned long offset,
1505 const char *type, int cpu)
1507 struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1508 struct thread_info *ti;
1509 memset(p, 0, KERNEL_STACK_SIZE);
1510 ti = task_thread_info(p);
1511 ti->flags = _TIF_MCA_INIT;
1512 ti->preempt_count = 1;
1515 p->thread_info = ti;
1516 p->state = TASK_UNINTERRUPTIBLE;
1517 cpu_set(cpu, p->cpus_allowed);
1518 INIT_LIST_HEAD(&p->tasks);
1519 p->parent = p->real_parent = p->group_leader = p;
1520 INIT_LIST_HEAD(&p->children);
1521 INIT_LIST_HEAD(&p->sibling);
1522 strncpy(p->comm, type, sizeof(p->comm)-1);
1525 /* Do per-CPU MCA-related initialization. */
1528 ia64_mca_cpu_init(void *cpu_data)
1531 static int first_time = 1;
1538 mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
1539 * NR_CPUS + KERNEL_STACK_SIZE);
1540 mca_data = (void *)(((unsigned long)mca_data +
1541 KERNEL_STACK_SIZE - 1) &
1542 (-KERNEL_STACK_SIZE));
1543 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1544 format_mca_init_stack(mca_data,
1545 offsetof(struct ia64_mca_cpu, mca_stack),
1547 format_mca_init_stack(mca_data,
1548 offsetof(struct ia64_mca_cpu, init_stack),
1550 __per_cpu_mca[cpu] = __pa(mca_data);
1551 mca_data += sizeof(struct ia64_mca_cpu);
1556 * The MCA info structure was allocated earlier and its
1557 * physical address saved in __per_cpu_mca[cpu]. Copy that
1558 * address * to ia64_mca_data so we can access it as a per-CPU
1561 __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
1564 * Stash away a copy of the PTE needed to map the per-CPU page.
1565 * We may need it during MCA recovery.
1567 __get_cpu_var(ia64_mca_per_cpu_pte) =
1568 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1571 * Also, stash away a copy of the PAL address and the PTE
1574 pal_vaddr = efi_get_pal_addr();
1577 __get_cpu_var(ia64_mca_pal_base) =
1578 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1579 __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1586 * Do all the system level mca specific initialization.
1588 * 1. Register spinloop and wakeup request interrupt vectors
1590 * 2. Register OS_MCA handler entry point
1592 * 3. Register OS_INIT handler entry point
1594 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1596 * Note that this initialization is done very early before some kernel
1597 * services are available.
1606 ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1607 ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1608 ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1611 struct ia64_sal_retval isrv;
1612 u64 timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */
1613 static struct notifier_block default_init_monarch_nb = {
1614 .notifier_call = default_monarch_init_process,
1615 .priority = 0/* we need to notified last */
1618 IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1620 /* Clear the Rendez checkin flag for all cpus */
1621 for(i = 0 ; i < NR_CPUS; i++)
1622 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1625 * Register the rendezvous spinloop and wakeup mechanism with SAL
1628 /* Register the rendezvous interrupt vector with SAL */
1630 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1631 SAL_MC_PARAM_MECHANISM_INT,
1632 IA64_MCA_RENDEZ_VECTOR,
1634 SAL_MC_PARAM_RZ_ALWAYS);
1639 printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1640 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1642 (void) notify_die(DIE_MCA_NEW_TIMEOUT, "MCA", NULL, timeout, 0, 0);
1645 printk(KERN_ERR "Failed to register rendezvous interrupt "
1646 "with SAL (status %ld)\n", rc);
1650 /* Register the wakeup interrupt vector with SAL */
1651 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1652 SAL_MC_PARAM_MECHANISM_INT,
1653 IA64_MCA_WAKEUP_VECTOR,
1657 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1658 "(status %ld)\n", rc);
1662 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1664 ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp);
1666 * XXX - disable SAL checksum by setting size to 0; should be
1667 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1669 ia64_mc_info.imi_mca_handler_size = 0;
1671 /* Register the os mca handler with SAL */
1672 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1673 ia64_mc_info.imi_mca_handler,
1674 ia64_tpa(mca_hldlr_ptr->gp),
1675 ia64_mc_info.imi_mca_handler_size,
1678 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1679 "(status %ld)\n", rc);
1683 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1684 ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1687 * XXX - disable SAL checksum by setting size to 0, should be
1688 * size of the actual init handler in mca_asm.S.
1690 ia64_mc_info.imi_monarch_init_handler = ia64_tpa(init_hldlr_ptr_monarch->fp);
1691 ia64_mc_info.imi_monarch_init_handler_size = 0;
1692 ia64_mc_info.imi_slave_init_handler = ia64_tpa(init_hldlr_ptr_slave->fp);
1693 ia64_mc_info.imi_slave_init_handler_size = 0;
1695 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1696 ia64_mc_info.imi_monarch_init_handler);
1698 /* Register the os init handler with SAL */
1699 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1700 ia64_mc_info.imi_monarch_init_handler,
1701 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1702 ia64_mc_info.imi_monarch_init_handler_size,
1703 ia64_mc_info.imi_slave_init_handler,
1704 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1705 ia64_mc_info.imi_slave_init_handler_size)))
1707 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1708 "(status %ld)\n", rc);
1711 if (register_die_notifier(&default_init_monarch_nb)) {
1712 printk(KERN_ERR "Failed to register default monarch INIT process\n");
1716 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1719 * Configure the CMCI/P vector and handler. Interrupts for CMC are
1720 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1722 register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1723 register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1724 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
1726 /* Setup the MCA rendezvous interrupt vector */
1727 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1729 /* Setup the MCA wakeup interrupt vector */
1730 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1733 /* Setup the CPEI/P handler */
1734 register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1737 /* Initialize the areas set aside by the OS to buffer the
1738 * platform/processor error states for MCA/INIT/CMC
1741 ia64_log_init(SAL_INFO_TYPE_MCA);
1742 ia64_log_init(SAL_INFO_TYPE_INIT);
1743 ia64_log_init(SAL_INFO_TYPE_CMC);
1744 ia64_log_init(SAL_INFO_TYPE_CPE);
1747 printk(KERN_INFO "MCA related initialization done\n");
1751 * ia64_mca_late_init
1753 * Opportunity to setup things that require initialization later
1754 * than ia64_mca_init. Setup a timer to poll for CPEs if the
1755 * platform doesn't support an interrupt driven mechanism.
1761 ia64_mca_late_init(void)
1766 /* Setup the CMCI/P vector and handler */
1767 init_timer(&cmc_poll_timer);
1768 cmc_poll_timer.function = ia64_mca_cmc_poll;
1770 /* Unmask/enable the vector */
1771 cmc_polling_enabled = 0;
1772 schedule_work(&cmc_enable_work);
1774 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1777 /* Setup the CPEI/P vector and handler */
1778 cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1779 init_timer(&cpe_poll_timer);
1780 cpe_poll_timer.function = ia64_mca_cpe_poll;
1786 if (cpe_vector >= 0) {
1787 /* If platform supports CPEI, enable the irq. */
1788 cpe_poll_enabled = 0;
1789 for (irq = 0; irq < NR_IRQS; ++irq)
1790 if (irq_to_vector(irq) == cpe_vector) {
1791 desc = irq_descp(irq);
1792 desc->status |= IRQ_PER_CPU;
1793 setup_irq(irq, &mca_cpe_irqaction);
1796 ia64_mca_register_cpev(cpe_vector);
1797 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1799 /* If platform doesn't support CPEI, get the timer going. */
1800 if (cpe_poll_enabled) {
1801 ia64_mca_cpe_poll(0UL);
1802 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1811 device_initcall(ia64_mca_late_init);