rt2x00: Cleanup mode registration
[linux-2.6] / drivers / net / wireless / rt2x00 / rt2500pci.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2500pci
23         Abstract: rt2500pci device specific routines.
24         Supported chipsets: RT2560.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
53 {
54         u32 reg;
55         unsigned int i;
56
57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60                         break;
61                 udelay(REGISTER_BUSY_DELAY);
62         }
63
64         return reg;
65 }
66
67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68                                 const unsigned int word, const u8 value)
69 {
70         u32 reg;
71
72         /*
73          * Wait until the BBP becomes ready.
74          */
75         reg = rt2500pci_bbp_check(rt2x00dev);
76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78                 return;
79         }
80
81         /*
82          * Write the data into the BBP.
83          */
84         reg = 0;
85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91 }
92
93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94                                const unsigned int word, u8 *value)
95 {
96         u32 reg;
97
98         /*
99          * Wait until the BBP becomes ready.
100          */
101         reg = rt2500pci_bbp_check(rt2x00dev);
102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104                 return;
105         }
106
107         /*
108          * Write the request into the BBP.
109          */
110         reg = 0;
111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117         /*
118          * Wait until the BBP becomes ready.
119          */
120         reg = rt2500pci_bbp_check(rt2x00dev);
121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123                 *value = 0xff;
124                 return;
125         }
126
127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128 }
129
130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
131                                const unsigned int word, const u32 value)
132 {
133         u32 reg;
134         unsigned int i;
135
136         if (!word)
137                 return;
138
139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142                         goto rf_write;
143                 udelay(REGISTER_BUSY_DELAY);
144         }
145
146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147         return;
148
149 rf_write:
150         reg = 0;
151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157         rt2x00_rf_write(rt2x00dev, word, value);
158 }
159
160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161 {
162         struct rt2x00_dev *rt2x00dev = eeprom->data;
163         u32 reg;
164
165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169         eeprom->reg_data_clock =
170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171         eeprom->reg_chip_select =
172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173 }
174
175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176 {
177         struct rt2x00_dev *rt2x00dev = eeprom->data;
178         u32 reg = 0;
179
180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183                            !!eeprom->reg_data_clock);
184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185                            !!eeprom->reg_chip_select);
186
187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188 }
189
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
194                                const unsigned int word, u32 *data)
195 {
196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197 }
198
199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
200                                 const unsigned int word, u32 data)
201 {
202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203 }
204
205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
206         .owner  = THIS_MODULE,
207         .csr    = {
208                 .read           = rt2500pci_read_csr,
209                 .write          = rt2500pci_write_csr,
210                 .word_size      = sizeof(u32),
211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
212         },
213         .eeprom = {
214                 .read           = rt2x00_eeprom_read,
215                 .write          = rt2x00_eeprom_write,
216                 .word_size      = sizeof(u16),
217                 .word_count     = EEPROM_SIZE / sizeof(u16),
218         },
219         .bbp    = {
220                 .read           = rt2500pci_bbp_read,
221                 .write          = rt2500pci_bbp_write,
222                 .word_size      = sizeof(u8),
223                 .word_count     = BBP_SIZE / sizeof(u8),
224         },
225         .rf     = {
226                 .read           = rt2x00_rf_read,
227                 .write          = rt2500pci_rf_write,
228                 .word_size      = sizeof(u32),
229                 .word_count     = RF_SIZE / sizeof(u32),
230         },
231 };
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234 #ifdef CONFIG_RT2500PCI_RFKILL
235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236 {
237         u32 reg;
238
239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241 }
242 #else
243 #define rt2500pci_rfkill_poll   NULL
244 #endif /* CONFIG_RT2500PCI_RFKILL */
245
246 #ifdef CONFIG_RT2500PCI_LEDS
247 static void rt2500pci_led_brightness(struct led_classdev *led_cdev,
248                                      enum led_brightness brightness)
249 {
250         struct rt2x00_led *led =
251             container_of(led_cdev, struct rt2x00_led, led_dev);
252         unsigned int enabled = brightness != LED_OFF;
253         unsigned int activity =
254             led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255         u32 reg;
256
257         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
258
259         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
261                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262         }
263
264         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265 }
266 #else
267 #define rt2500pci_led_brightness        NULL
268 #endif /* CONFIG_RT2500PCI_LEDS */
269
270 /*
271  * Configuration handlers.
272  */
273 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
274                                   struct rt2x00_intf *intf,
275                                   struct rt2x00intf_conf *conf,
276                                   const unsigned int flags)
277 {
278         struct data_queue *queue =
279             rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
280         unsigned int bcn_preload;
281         u32 reg;
282
283         if (flags & CONFIG_UPDATE_TYPE) {
284                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
285
286                 /*
287                  * Enable beacon config
288                  */
289                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
290                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
291                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
292                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
293                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
294
295                 /*
296                  * Enable synchronisation.
297                  */
298                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
299                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
300                 rt2x00_set_field32(&reg, CSR14_TBCN,
301                                    (conf->sync == TSF_SYNC_BEACON));
302                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
303                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
304                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
305         }
306
307         if (flags & CONFIG_UPDATE_MAC)
308                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
309                                               conf->mac, sizeof(conf->mac));
310
311         if (flags & CONFIG_UPDATE_BSSID)
312                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
313                                               conf->bssid, sizeof(conf->bssid));
314 }
315
316 static int rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
317                                      const int short_preamble,
318                                      const int ack_timeout,
319                                      const int ack_consume_time)
320 {
321         int preamble_mask;
322         u32 reg;
323
324         /*
325          * When short preamble is enabled, we should set bit 0x08
326          */
327         preamble_mask = short_preamble << 3;
328
329         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
330         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
331         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
332         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
333
334         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
335         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
336         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
337         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
338         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
339
340         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
341         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
342         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
343         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
344         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
345
346         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
347         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
348         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
349         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
350         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
351
352         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
353         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
354         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
355         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
356         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
357
358         return 0;
359 }
360
361 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
362                                      const int basic_rate_mask)
363 {
364         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
365 }
366
367 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
368                                      struct rf_channel *rf, const int txpower)
369 {
370         u8 r70;
371
372         /*
373          * Set TXpower.
374          */
375         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
376
377         /*
378          * Switch on tuning bits.
379          * For RT2523 devices we do not need to update the R1 register.
380          */
381         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
382                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
383         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
384
385         /*
386          * For RT2525 we should first set the channel to half band higher.
387          */
388         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
389                 static const u32 vals[] = {
390                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
391                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
392                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
393                         0x00080d2e, 0x00080d3a
394                 };
395
396                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
397                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
398                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
399                 if (rf->rf4)
400                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
401         }
402
403         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
404         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
405         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
406         if (rf->rf4)
407                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
408
409         /*
410          * Channel 14 requires the Japan filter bit to be set.
411          */
412         r70 = 0x46;
413         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
414         rt2500pci_bbp_write(rt2x00dev, 70, r70);
415
416         msleep(1);
417
418         /*
419          * Switch off tuning bits.
420          * For RT2523 devices we do not need to update the R1 register.
421          */
422         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
423                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
424                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
425         }
426
427         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
428         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
429
430         /*
431          * Clear false CRC during channel switch.
432          */
433         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
434 }
435
436 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
437                                      const int txpower)
438 {
439         u32 rf3;
440
441         rt2x00_rf_read(rt2x00dev, 3, &rf3);
442         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
443         rt2500pci_rf_write(rt2x00dev, 3, rf3);
444 }
445
446 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
447                                      struct antenna_setup *ant)
448 {
449         u32 reg;
450         u8 r14;
451         u8 r2;
452
453         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
454         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
455         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
456
457         /*
458          * Configure the TX antenna.
459          */
460         switch (ant->tx) {
461         case ANTENNA_A:
462                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
463                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
464                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
465                 break;
466         case ANTENNA_HW_DIVERSITY:
467         case ANTENNA_SW_DIVERSITY:
468                 /*
469                  * NOTE: We should never come here because rt2x00lib is
470                  * supposed to catch this and send us the correct antenna
471                  * explicitely. However we are nog going to bug about this.
472                  * Instead, just default to antenna B.
473                  */
474         case ANTENNA_B:
475                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
476                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
477                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
478                 break;
479         }
480
481         /*
482          * Configure the RX antenna.
483          */
484         switch (ant->rx) {
485         case ANTENNA_A:
486                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
487                 break;
488         case ANTENNA_HW_DIVERSITY:
489         case ANTENNA_SW_DIVERSITY:
490                 /*
491                  * NOTE: We should never come here because rt2x00lib is
492                  * supposed to catch this and send us the correct antenna
493                  * explicitely. However we are nog going to bug about this.
494                  * Instead, just default to antenna B.
495                  */
496         case ANTENNA_B:
497                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
498                 break;
499         }
500
501         /*
502          * RT2525E and RT5222 need to flip TX I/Q
503          */
504         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
505             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
506                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
507                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
508                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
509
510                 /*
511                  * RT2525E does not need RX I/Q Flip.
512                  */
513                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
514                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
515         } else {
516                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
517                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
518         }
519
520         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
521         rt2500pci_bbp_write(rt2x00dev, 14, r14);
522         rt2500pci_bbp_write(rt2x00dev, 2, r2);
523 }
524
525 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
526                                       struct rt2x00lib_conf *libconf)
527 {
528         u32 reg;
529
530         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
531         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
532         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
533
534         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
535         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
536         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
537         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
538
539         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
540         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
541         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
542         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
543
544         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
545         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
546         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
547         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
548
549         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
550         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
551                            libconf->conf->beacon_int * 16);
552         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
553                            libconf->conf->beacon_int * 16);
554         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
555 }
556
557 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
558                              struct rt2x00lib_conf *libconf,
559                              const unsigned int flags)
560 {
561         if (flags & CONFIG_UPDATE_PHYMODE)
562                 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
563         if (flags & CONFIG_UPDATE_CHANNEL)
564                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
565                                          libconf->conf->power_level);
566         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
567                 rt2500pci_config_txpower(rt2x00dev,
568                                          libconf->conf->power_level);
569         if (flags & CONFIG_UPDATE_ANTENNA)
570                 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
571         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
572                 rt2500pci_config_duration(rt2x00dev, libconf);
573 }
574
575 /*
576  * Link tuning
577  */
578 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
579                                  struct link_qual *qual)
580 {
581         u32 reg;
582
583         /*
584          * Update FCS error count from register.
585          */
586         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
587         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
588
589         /*
590          * Update False CCA count from register.
591          */
592         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
593         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
594 }
595
596 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
597 {
598         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
599         rt2x00dev->link.vgc_level = 0x48;
600 }
601
602 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
603 {
604         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
605         u8 r17;
606
607         /*
608          * To prevent collisions with MAC ASIC on chipsets
609          * up to version C the link tuning should halt after 20
610          * seconds while being associated.
611          */
612         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
613             rt2x00dev->intf_associated &&
614             rt2x00dev->link.count > 20)
615                 return;
616
617         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
618
619         /*
620          * Chipset versions C and lower should directly continue
621          * to the dynamic CCA tuning. Chipset version D and higher
622          * should go straight to dynamic CCA tuning when they
623          * are not associated.
624          */
625         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
626             !rt2x00dev->intf_associated)
627                 goto dynamic_cca_tune;
628
629         /*
630          * A too low RSSI will cause too much false CCA which will
631          * then corrupt the R17 tuning. To remidy this the tuning should
632          * be stopped (While making sure the R17 value will not exceed limits)
633          */
634         if (rssi < -80 && rt2x00dev->link.count > 20) {
635                 if (r17 >= 0x41) {
636                         r17 = rt2x00dev->link.vgc_level;
637                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
638                 }
639                 return;
640         }
641
642         /*
643          * Special big-R17 for short distance
644          */
645         if (rssi >= -58) {
646                 if (r17 != 0x50)
647                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
648                 return;
649         }
650
651         /*
652          * Special mid-R17 for middle distance
653          */
654         if (rssi >= -74) {
655                 if (r17 != 0x41)
656                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
657                 return;
658         }
659
660         /*
661          * Leave short or middle distance condition, restore r17
662          * to the dynamic tuning range.
663          */
664         if (r17 >= 0x41) {
665                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
666                 return;
667         }
668
669 dynamic_cca_tune:
670
671         /*
672          * R17 is inside the dynamic tuning range,
673          * start tuning the link based on the false cca counter.
674          */
675         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
676                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
677                 rt2x00dev->link.vgc_level = r17;
678         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
679                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
680                 rt2x00dev->link.vgc_level = r17;
681         }
682 }
683
684 /*
685  * Initialization functions.
686  */
687 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
688                                    struct queue_entry *entry)
689 {
690         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
691         u32 word;
692
693         rt2x00_desc_read(priv_rx->desc, 1, &word);
694         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
695         rt2x00_desc_write(priv_rx->desc, 1, word);
696
697         rt2x00_desc_read(priv_rx->desc, 0, &word);
698         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
699         rt2x00_desc_write(priv_rx->desc, 0, word);
700 }
701
702 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
703                                    struct queue_entry *entry)
704 {
705         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
706         u32 word;
707
708         rt2x00_desc_read(priv_tx->desc, 1, &word);
709         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
710         rt2x00_desc_write(priv_tx->desc, 1, word);
711
712         rt2x00_desc_read(priv_tx->desc, 0, &word);
713         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
714         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
715         rt2x00_desc_write(priv_tx->desc, 0, word);
716 }
717
718 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
719 {
720         struct queue_entry_priv_pci_rx *priv_rx;
721         struct queue_entry_priv_pci_tx *priv_tx;
722         u32 reg;
723
724         /*
725          * Initialize registers.
726          */
727         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
728         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
729         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
730         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
731         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
732         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
733
734         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
735         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
736         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
737                            priv_tx->desc_dma);
738         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
739
740         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
741         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
742         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
743                            priv_tx->desc_dma);
744         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
745
746         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
747         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
748         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
749                            priv_tx->desc_dma);
750         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
751
752         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
753         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
754         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
755                            priv_tx->desc_dma);
756         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
757
758         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
759         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
760         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
761         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
762
763         priv_rx = rt2x00dev->rx->entries[0].priv_data;
764         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
765         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
766         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
767
768         return 0;
769 }
770
771 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
772 {
773         u32 reg;
774
775         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
776         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
777         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
778         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
779
780         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
781         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
782         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
783         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
784         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
785
786         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
787         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
788                            rt2x00dev->rx->data_size / 128);
789         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
790
791         /*
792          * Always use CWmin and CWmax set in descriptor.
793          */
794         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
795         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
796         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
797
798         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
799         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
800         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
801         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
802
803         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
804
805         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
806         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
807         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
808         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
809         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
810         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
811         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
812         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
813         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
814         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
815
816         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
817         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
818         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
819         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
820         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
821         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
822
823         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
824         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
825         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
826         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
827         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
828         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
829
830         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
831         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
832         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
833         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
834         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
835         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
836
837         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
838         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
839         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
840         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
841         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
842         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
843         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
844         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
845         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
846         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
847
848         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
849         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
850         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
851         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
852         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
853         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
854         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
855         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
856         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
857
858         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
859
860         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
861         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
862
863         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
864                 return -EBUSY;
865
866         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
867         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
868
869         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
870         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
871         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
872
873         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
874         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
875         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
876         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
877         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
878         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
879         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
880         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
881
882         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
883
884         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
885
886         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
887         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
888         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
889         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
890         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
891
892         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
893         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
894         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
895         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
896
897         /*
898          * We must clear the FCS and FIFO error count.
899          * These registers are cleared on read,
900          * so we may pass a useless variable to store the value.
901          */
902         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
903         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
904
905         return 0;
906 }
907
908 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
909 {
910         unsigned int i;
911         u16 eeprom;
912         u8 reg_id;
913         u8 value;
914
915         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
916                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
917                 if ((value != 0xff) && (value != 0x00))
918                         goto continue_csr_init;
919                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
920                 udelay(REGISTER_BUSY_DELAY);
921         }
922
923         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
924         return -EACCES;
925
926 continue_csr_init:
927         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
928         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
929         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
930         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
931         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
932         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
933         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
934         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
935         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
936         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
937         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
938         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
939         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
940         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
941         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
942         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
943         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
944         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
945         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
946         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
947         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
948         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
949         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
950         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
951         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
952         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
953         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
954         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
955         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
956         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
957
958         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
959                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
960
961                 if (eeprom != 0xffff && eeprom != 0x0000) {
962                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
963                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
964                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
965                 }
966         }
967
968         return 0;
969 }
970
971 /*
972  * Device state switch handlers.
973  */
974 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
975                                 enum dev_state state)
976 {
977         u32 reg;
978
979         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
980         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
981                            state == STATE_RADIO_RX_OFF);
982         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
983 }
984
985 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
986                                  enum dev_state state)
987 {
988         int mask = (state == STATE_RADIO_IRQ_OFF);
989         u32 reg;
990
991         /*
992          * When interrupts are being enabled, the interrupt registers
993          * should clear the register to assure a clean state.
994          */
995         if (state == STATE_RADIO_IRQ_ON) {
996                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
997                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
998         }
999
1000         /*
1001          * Only toggle the interrupts bits we are going to use.
1002          * Non-checked interrupt bits are disabled by default.
1003          */
1004         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1005         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1006         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1007         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1008         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1009         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1010         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1011 }
1012
1013 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1014 {
1015         /*
1016          * Initialize all registers.
1017          */
1018         if (rt2500pci_init_queues(rt2x00dev) ||
1019             rt2500pci_init_registers(rt2x00dev) ||
1020             rt2500pci_init_bbp(rt2x00dev)) {
1021                 ERROR(rt2x00dev, "Register initialization failed.\n");
1022                 return -EIO;
1023         }
1024
1025         /*
1026          * Enable interrupts.
1027          */
1028         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1029
1030         return 0;
1031 }
1032
1033 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1034 {
1035         u32 reg;
1036
1037         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1038
1039         /*
1040          * Disable synchronisation.
1041          */
1042         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1043
1044         /*
1045          * Cancel RX and TX.
1046          */
1047         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1048         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1049         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1050
1051         /*
1052          * Disable interrupts.
1053          */
1054         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1055 }
1056
1057 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1058                                enum dev_state state)
1059 {
1060         u32 reg;
1061         unsigned int i;
1062         char put_to_sleep;
1063         char bbp_state;
1064         char rf_state;
1065
1066         put_to_sleep = (state != STATE_AWAKE);
1067
1068         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1069         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1070         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1071         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1072         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1073         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1074
1075         /*
1076          * Device is not guaranteed to be in the requested state yet.
1077          * We must wait until the register indicates that the
1078          * device has entered the correct state.
1079          */
1080         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1081                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1082                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1083                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1084                 if (bbp_state == state && rf_state == state)
1085                         return 0;
1086                 msleep(10);
1087         }
1088
1089         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1090                "current device state: bbp %d and rf %d.\n",
1091                state, bbp_state, rf_state);
1092
1093         return -EBUSY;
1094 }
1095
1096 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1097                                       enum dev_state state)
1098 {
1099         int retval = 0;
1100
1101         switch (state) {
1102         case STATE_RADIO_ON:
1103                 retval = rt2500pci_enable_radio(rt2x00dev);
1104                 break;
1105         case STATE_RADIO_OFF:
1106                 rt2500pci_disable_radio(rt2x00dev);
1107                 break;
1108         case STATE_RADIO_RX_ON:
1109         case STATE_RADIO_RX_ON_LINK:
1110                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1111                 break;
1112         case STATE_RADIO_RX_OFF:
1113         case STATE_RADIO_RX_OFF_LINK:
1114                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1115                 break;
1116         case STATE_DEEP_SLEEP:
1117         case STATE_SLEEP:
1118         case STATE_STANDBY:
1119         case STATE_AWAKE:
1120                 retval = rt2500pci_set_state(rt2x00dev, state);
1121                 break;
1122         default:
1123                 retval = -ENOTSUPP;
1124                 break;
1125         }
1126
1127         return retval;
1128 }
1129
1130 /*
1131  * TX descriptor initialization
1132  */
1133 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1134                                     struct sk_buff *skb,
1135                                     struct txentry_desc *txdesc,
1136                                     struct ieee80211_tx_control *control)
1137 {
1138         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1139         __le32 *txd = skbdesc->desc;
1140         u32 word;
1141
1142         /*
1143          * Start writing the descriptor words.
1144          */
1145         rt2x00_desc_read(txd, 2, &word);
1146         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1147         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1148         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1149         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1150         rt2x00_desc_write(txd, 2, word);
1151
1152         rt2x00_desc_read(txd, 3, &word);
1153         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1154         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1155         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1156         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1157         rt2x00_desc_write(txd, 3, word);
1158
1159         rt2x00_desc_read(txd, 10, &word);
1160         rt2x00_set_field32(&word, TXD_W10_RTS,
1161                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1162         rt2x00_desc_write(txd, 10, word);
1163
1164         rt2x00_desc_read(txd, 0, &word);
1165         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1166         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1167         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1168                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1169         rt2x00_set_field32(&word, TXD_W0_ACK,
1170                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1171         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1172                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1173         rt2x00_set_field32(&word, TXD_W0_OFDM,
1174                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1175         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1176         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1177         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1178                            !!(control->flags &
1179                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1180         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1181         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1182         rt2x00_desc_write(txd, 0, word);
1183 }
1184
1185 /*
1186  * TX data initialization
1187  */
1188 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1189                                     const unsigned int queue)
1190 {
1191         u32 reg;
1192
1193         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1194                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1195                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1196                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1197                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1198                 }
1199                 return;
1200         }
1201
1202         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1203         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1204                            (queue == IEEE80211_TX_QUEUE_DATA0));
1205         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1206                            (queue == IEEE80211_TX_QUEUE_DATA1));
1207         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1208                            (queue == RT2X00_BCN_QUEUE_ATIM));
1209         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1210 }
1211
1212 /*
1213  * RX control handlers
1214  */
1215 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1216                                   struct rxdone_entry_desc *rxdesc)
1217 {
1218         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1219         u32 word0;
1220         u32 word2;
1221
1222         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1223         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1224
1225         rxdesc->flags = 0;
1226         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1227                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1228         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1229                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1230
1231         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1232         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1233             entry->queue->rt2x00dev->rssi_offset;
1234         rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1235         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1236         rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1237 }
1238
1239 /*
1240  * Interrupt functions.
1241  */
1242 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1243                              const enum ieee80211_tx_queue queue_idx)
1244 {
1245         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1246         struct queue_entry_priv_pci_tx *priv_tx;
1247         struct queue_entry *entry;
1248         struct txdone_entry_desc txdesc;
1249         u32 word;
1250
1251         while (!rt2x00queue_empty(queue)) {
1252                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1253                 priv_tx = entry->priv_data;
1254                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1255
1256                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1257                     !rt2x00_get_field32(word, TXD_W0_VALID))
1258                         break;
1259
1260                 /*
1261                  * Obtain the status about this packet.
1262                  */
1263                 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1264                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1265
1266                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1267         }
1268 }
1269
1270 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1271 {
1272         struct rt2x00_dev *rt2x00dev = dev_instance;
1273         u32 reg;
1274
1275         /*
1276          * Get the interrupt sources & saved to local variable.
1277          * Write register value back to clear pending interrupts.
1278          */
1279         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1280         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1281
1282         if (!reg)
1283                 return IRQ_NONE;
1284
1285         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1286                 return IRQ_HANDLED;
1287
1288         /*
1289          * Handle interrupts, walk through all bits
1290          * and run the tasks, the bits are checked in order of
1291          * priority.
1292          */
1293
1294         /*
1295          * 1 - Beacon timer expired interrupt.
1296          */
1297         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1298                 rt2x00lib_beacondone(rt2x00dev);
1299
1300         /*
1301          * 2 - Rx ring done interrupt.
1302          */
1303         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1304                 rt2x00pci_rxdone(rt2x00dev);
1305
1306         /*
1307          * 3 - Atim ring transmit done interrupt.
1308          */
1309         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1310                 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1311
1312         /*
1313          * 4 - Priority ring transmit done interrupt.
1314          */
1315         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1316                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1317
1318         /*
1319          * 5 - Tx ring transmit done interrupt.
1320          */
1321         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1322                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1323
1324         return IRQ_HANDLED;
1325 }
1326
1327 /*
1328  * Device probe functions.
1329  */
1330 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1331 {
1332         struct eeprom_93cx6 eeprom;
1333         u32 reg;
1334         u16 word;
1335         u8 *mac;
1336
1337         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1338
1339         eeprom.data = rt2x00dev;
1340         eeprom.register_read = rt2500pci_eepromregister_read;
1341         eeprom.register_write = rt2500pci_eepromregister_write;
1342         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1343             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1344         eeprom.reg_data_in = 0;
1345         eeprom.reg_data_out = 0;
1346         eeprom.reg_data_clock = 0;
1347         eeprom.reg_chip_select = 0;
1348
1349         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1350                                EEPROM_SIZE / sizeof(u16));
1351
1352         /*
1353          * Start validation of the data that has been read.
1354          */
1355         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1356         if (!is_valid_ether_addr(mac)) {
1357                 DECLARE_MAC_BUF(macbuf);
1358
1359                 random_ether_addr(mac);
1360                 EEPROM(rt2x00dev, "MAC: %s\n",
1361                        print_mac(macbuf, mac));
1362         }
1363
1364         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1365         if (word == 0xffff) {
1366                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1367                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1368                                    ANTENNA_SW_DIVERSITY);
1369                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1370                                    ANTENNA_SW_DIVERSITY);
1371                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1372                                    LED_MODE_DEFAULT);
1373                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1374                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1375                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1376                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1377                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1378         }
1379
1380         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1381         if (word == 0xffff) {
1382                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1383                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1384                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1385                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1386                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1387         }
1388
1389         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1390         if (word == 0xffff) {
1391                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1392                                    DEFAULT_RSSI_OFFSET);
1393                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1394                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1401 {
1402         u32 reg;
1403         u16 value;
1404         u16 eeprom;
1405
1406         /*
1407          * Read EEPROM word for configuration.
1408          */
1409         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1410
1411         /*
1412          * Identify RF chipset.
1413          */
1414         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1415         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1416         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1417
1418         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1419             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1420             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1421             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1422             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1423             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1424                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1425                 return -ENODEV;
1426         }
1427
1428         /*
1429          * Identify default antenna configuration.
1430          */
1431         rt2x00dev->default_ant.tx =
1432             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1433         rt2x00dev->default_ant.rx =
1434             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1435
1436         /*
1437          * Store led mode, for correct led behaviour.
1438          */
1439 #ifdef CONFIG_RT2500PCI_LEDS
1440         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1441
1442         switch (value) {
1443         case LED_MODE_ASUS:
1444         case LED_MODE_ALPHA:
1445         case LED_MODE_DEFAULT:
1446                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1447                 break;
1448         case LED_MODE_TXRX_ACTIVITY:
1449                 rt2x00dev->led_flags =
1450                     LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1451                 break;
1452         case LED_MODE_SIGNAL_STRENGTH:
1453                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1454                 break;
1455         }
1456 #endif /* CONFIG_RT2500PCI_LEDS */
1457
1458         /*
1459          * Detect if this device has an hardware controlled radio.
1460          */
1461 #ifdef CONFIG_RT2500PCI_RFKILL
1462         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1463                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1464 #endif /* CONFIG_RT2500PCI_RFKILL */
1465
1466         /*
1467          * Check if the BBP tuning should be enabled.
1468          */
1469         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1470
1471         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1472                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1473
1474         /*
1475          * Read the RSSI <-> dBm offset information.
1476          */
1477         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1478         rt2x00dev->rssi_offset =
1479             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1480
1481         return 0;
1482 }
1483
1484 /*
1485  * RF value list for RF2522
1486  * Supports: 2.4 GHz
1487  */
1488 static const struct rf_channel rf_vals_bg_2522[] = {
1489         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1490         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1491         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1492         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1493         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1494         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1495         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1496         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1497         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1498         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1499         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1500         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1501         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1502         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1503 };
1504
1505 /*
1506  * RF value list for RF2523
1507  * Supports: 2.4 GHz
1508  */
1509 static const struct rf_channel rf_vals_bg_2523[] = {
1510         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1511         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1512         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1513         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1514         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1515         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1516         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1517         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1518         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1519         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1520         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1521         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1522         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1523         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1524 };
1525
1526 /*
1527  * RF value list for RF2524
1528  * Supports: 2.4 GHz
1529  */
1530 static const struct rf_channel rf_vals_bg_2524[] = {
1531         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1532         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1533         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1534         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1535         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1536         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1537         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1538         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1539         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1540         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1541         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1542         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1543         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1544         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1545 };
1546
1547 /*
1548  * RF value list for RF2525
1549  * Supports: 2.4 GHz
1550  */
1551 static const struct rf_channel rf_vals_bg_2525[] = {
1552         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1553         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1554         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1555         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1556         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1557         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1558         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1559         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1560         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1561         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1562         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1563         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1564         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1565         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1566 };
1567
1568 /*
1569  * RF value list for RF2525e
1570  * Supports: 2.4 GHz
1571  */
1572 static const struct rf_channel rf_vals_bg_2525e[] = {
1573         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1574         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1575         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1576         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1577         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1578         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1579         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1580         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1581         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1582         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1583         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1584         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1585         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1586         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1587 };
1588
1589 /*
1590  * RF value list for RF5222
1591  * Supports: 2.4 GHz & 5.2 GHz
1592  */
1593 static const struct rf_channel rf_vals_5222[] = {
1594         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1595         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1596         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1597         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1598         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1599         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1600         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1601         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1602         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1603         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1604         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1605         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1606         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1607         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1608
1609         /* 802.11 UNI / HyperLan 2 */
1610         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1611         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1612         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1613         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1614         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1615         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1616         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1617         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1618
1619         /* 802.11 HyperLan 2 */
1620         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1621         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1622         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1623         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1624         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1625         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1626         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1627         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1628         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1629         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1630
1631         /* 802.11 UNII */
1632         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1633         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1634         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1635         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1636         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1637 };
1638
1639 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1640 {
1641         struct hw_mode_spec *spec = &rt2x00dev->spec;
1642         u8 *txpower;
1643         unsigned int i;
1644
1645         /*
1646          * Initialize all hw fields.
1647          */
1648         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1649         rt2x00dev->hw->extra_tx_headroom = 0;
1650         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1651         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1652         rt2x00dev->hw->queues = 2;
1653
1654         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1655         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1656                                 rt2x00_eeprom_addr(rt2x00dev,
1657                                                    EEPROM_MAC_ADDR_0));
1658
1659         /*
1660          * Convert tx_power array in eeprom.
1661          */
1662         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1663         for (i = 0; i < 14; i++)
1664                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1665
1666         /*
1667          * Initialize hw_mode information.
1668          */
1669         spec->supported_bands = SUPPORT_BAND_2GHZ;
1670         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1671         spec->tx_power_a = NULL;
1672         spec->tx_power_bg = txpower;
1673         spec->tx_power_default = DEFAULT_TXPOWER;
1674
1675         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1676                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1677                 spec->channels = rf_vals_bg_2522;
1678         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1679                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1680                 spec->channels = rf_vals_bg_2523;
1681         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1682                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1683                 spec->channels = rf_vals_bg_2524;
1684         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1685                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1686                 spec->channels = rf_vals_bg_2525;
1687         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1688                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1689                 spec->channels = rf_vals_bg_2525e;
1690         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1691                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1692                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1693                 spec->channels = rf_vals_5222;
1694         }
1695 }
1696
1697 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1698 {
1699         int retval;
1700
1701         /*
1702          * Allocate eeprom data.
1703          */
1704         retval = rt2500pci_validate_eeprom(rt2x00dev);
1705         if (retval)
1706                 return retval;
1707
1708         retval = rt2500pci_init_eeprom(rt2x00dev);
1709         if (retval)
1710                 return retval;
1711
1712         /*
1713          * Initialize hw specifications.
1714          */
1715         rt2500pci_probe_hw_mode(rt2x00dev);
1716
1717         /*
1718          * This device requires the atim queue
1719          */
1720         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1721
1722         /*
1723          * Set the rssi offset.
1724          */
1725         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1726
1727         return 0;
1728 }
1729
1730 /*
1731  * IEEE80211 stack callback functions.
1732  */
1733 static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1734                                        unsigned int changed_flags,
1735                                        unsigned int *total_flags,
1736                                        int mc_count,
1737                                        struct dev_addr_list *mc_list)
1738 {
1739         struct rt2x00_dev *rt2x00dev = hw->priv;
1740         u32 reg;
1741
1742         /*
1743          * Mask off any flags we are going to ignore from
1744          * the total_flags field.
1745          */
1746         *total_flags &=
1747             FIF_ALLMULTI |
1748             FIF_FCSFAIL |
1749             FIF_PLCPFAIL |
1750             FIF_CONTROL |
1751             FIF_OTHER_BSS |
1752             FIF_PROMISC_IN_BSS;
1753
1754         /*
1755          * Apply some rules to the filters:
1756          * - Some filters imply different filters to be set.
1757          * - Some things we can't filter out at all.
1758          */
1759         if (mc_count)
1760                 *total_flags |= FIF_ALLMULTI;
1761         if (*total_flags & FIF_OTHER_BSS ||
1762             *total_flags & FIF_PROMISC_IN_BSS)
1763                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1764
1765         /*
1766          * Check if there is any work left for us.
1767          */
1768         if (rt2x00dev->packet_filter == *total_flags)
1769                 return;
1770         rt2x00dev->packet_filter = *total_flags;
1771
1772         /*
1773          * Start configuration steps.
1774          * Note that the version error will always be dropped
1775          * and broadcast frames will always be accepted since
1776          * there is no filter for it at this time.
1777          */
1778         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1779         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1780                            !(*total_flags & FIF_FCSFAIL));
1781         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1782                            !(*total_flags & FIF_PLCPFAIL));
1783         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1784                            !(*total_flags & FIF_CONTROL));
1785         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1786                            !(*total_flags & FIF_PROMISC_IN_BSS));
1787         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1788                            !(*total_flags & FIF_PROMISC_IN_BSS));
1789         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1790         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1791                            !(*total_flags & FIF_ALLMULTI));
1792         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1793         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1794 }
1795
1796 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1797                                      u32 short_retry, u32 long_retry)
1798 {
1799         struct rt2x00_dev *rt2x00dev = hw->priv;
1800         u32 reg;
1801
1802         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1803         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1804         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1805         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1806
1807         return 0;
1808 }
1809
1810 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1811 {
1812         struct rt2x00_dev *rt2x00dev = hw->priv;
1813         u64 tsf;
1814         u32 reg;
1815
1816         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1817         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1818         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1819         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1820
1821         return tsf;
1822 }
1823
1824 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1825                                    struct ieee80211_tx_control *control)
1826 {
1827         struct rt2x00_dev *rt2x00dev = hw->priv;
1828         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1829         struct queue_entry_priv_pci_tx *priv_tx;
1830         struct skb_frame_desc *skbdesc;
1831
1832         if (unlikely(!intf->beacon))
1833                 return -ENOBUFS;
1834
1835         priv_tx = intf->beacon->priv_data;
1836
1837         /*
1838          * Fill in skb descriptor
1839          */
1840         skbdesc = get_skb_frame_desc(skb);
1841         memset(skbdesc, 0, sizeof(*skbdesc));
1842         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1843         skbdesc->data = skb->data;
1844         skbdesc->data_len = skb->len;
1845         skbdesc->desc = priv_tx->desc;
1846         skbdesc->desc_len = intf->beacon->queue->desc_size;
1847         skbdesc->entry = intf->beacon;
1848
1849         /*
1850          * mac80211 doesn't provide the control->queue variable
1851          * for beacons. Set our own queue identification so
1852          * it can be used during descriptor initialization.
1853          */
1854         control->queue = RT2X00_BCN_QUEUE_BEACON;
1855         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1856
1857         /*
1858          * Enable beacon generation.
1859          * Write entire beacon with descriptor to register,
1860          * and kick the beacon generator.
1861          */
1862         memcpy(priv_tx->data, skb->data, skb->len);
1863         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1864
1865         return 0;
1866 }
1867
1868 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1869 {
1870         struct rt2x00_dev *rt2x00dev = hw->priv;
1871         u32 reg;
1872
1873         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1874         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1875 }
1876
1877 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1878         .tx                     = rt2x00mac_tx,
1879         .start                  = rt2x00mac_start,
1880         .stop                   = rt2x00mac_stop,
1881         .add_interface          = rt2x00mac_add_interface,
1882         .remove_interface       = rt2x00mac_remove_interface,
1883         .config                 = rt2x00mac_config,
1884         .config_interface       = rt2x00mac_config_interface,
1885         .configure_filter       = rt2500pci_configure_filter,
1886         .get_stats              = rt2x00mac_get_stats,
1887         .set_retry_limit        = rt2500pci_set_retry_limit,
1888         .bss_info_changed       = rt2x00mac_bss_info_changed,
1889         .conf_tx                = rt2x00mac_conf_tx,
1890         .get_tx_stats           = rt2x00mac_get_tx_stats,
1891         .get_tsf                = rt2500pci_get_tsf,
1892         .beacon_update          = rt2500pci_beacon_update,
1893         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1894 };
1895
1896 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1897         .irq_handler            = rt2500pci_interrupt,
1898         .probe_hw               = rt2500pci_probe_hw,
1899         .initialize             = rt2x00pci_initialize,
1900         .uninitialize           = rt2x00pci_uninitialize,
1901         .init_rxentry           = rt2500pci_init_rxentry,
1902         .init_txentry           = rt2500pci_init_txentry,
1903         .set_device_state       = rt2500pci_set_device_state,
1904         .rfkill_poll            = rt2500pci_rfkill_poll,
1905         .link_stats             = rt2500pci_link_stats,
1906         .reset_tuner            = rt2500pci_reset_tuner,
1907         .link_tuner             = rt2500pci_link_tuner,
1908         .led_brightness         = rt2500pci_led_brightness,
1909         .write_tx_desc          = rt2500pci_write_tx_desc,
1910         .write_tx_data          = rt2x00pci_write_tx_data,
1911         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1912         .fill_rxdone            = rt2500pci_fill_rxdone,
1913         .config_intf            = rt2500pci_config_intf,
1914         .config_preamble        = rt2500pci_config_preamble,
1915         .config                 = rt2500pci_config,
1916 };
1917
1918 static const struct data_queue_desc rt2500pci_queue_rx = {
1919         .entry_num              = RX_ENTRIES,
1920         .data_size              = DATA_FRAME_SIZE,
1921         .desc_size              = RXD_DESC_SIZE,
1922         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1923 };
1924
1925 static const struct data_queue_desc rt2500pci_queue_tx = {
1926         .entry_num              = TX_ENTRIES,
1927         .data_size              = DATA_FRAME_SIZE,
1928         .desc_size              = TXD_DESC_SIZE,
1929         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1930 };
1931
1932 static const struct data_queue_desc rt2500pci_queue_bcn = {
1933         .entry_num              = BEACON_ENTRIES,
1934         .data_size              = MGMT_FRAME_SIZE,
1935         .desc_size              = TXD_DESC_SIZE,
1936         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1937 };
1938
1939 static const struct data_queue_desc rt2500pci_queue_atim = {
1940         .entry_num              = ATIM_ENTRIES,
1941         .data_size              = DATA_FRAME_SIZE,
1942         .desc_size              = TXD_DESC_SIZE,
1943         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1944 };
1945
1946 static const struct rt2x00_ops rt2500pci_ops = {
1947         .name           = KBUILD_MODNAME,
1948         .max_sta_intf   = 1,
1949         .max_ap_intf    = 1,
1950         .eeprom_size    = EEPROM_SIZE,
1951         .rf_size        = RF_SIZE,
1952         .rx             = &rt2500pci_queue_rx,
1953         .tx             = &rt2500pci_queue_tx,
1954         .bcn            = &rt2500pci_queue_bcn,
1955         .atim           = &rt2500pci_queue_atim,
1956         .lib            = &rt2500pci_rt2x00_ops,
1957         .hw             = &rt2500pci_mac80211_ops,
1958 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1959         .debugfs        = &rt2500pci_rt2x00debug,
1960 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1961 };
1962
1963 /*
1964  * RT2500pci module information.
1965  */
1966 static struct pci_device_id rt2500pci_device_table[] = {
1967         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1968         { 0, }
1969 };
1970
1971 MODULE_AUTHOR(DRV_PROJECT);
1972 MODULE_VERSION(DRV_VERSION);
1973 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1974 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1975 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1976 MODULE_LICENSE("GPL");
1977
1978 static struct pci_driver rt2500pci_driver = {
1979         .name           = KBUILD_MODNAME,
1980         .id_table       = rt2500pci_device_table,
1981         .probe          = rt2x00pci_probe,
1982         .remove         = __devexit_p(rt2x00pci_remove),
1983         .suspend        = rt2x00pci_suspend,
1984         .resume         = rt2x00pci_resume,
1985 };
1986
1987 static int __init rt2500pci_init(void)
1988 {
1989         return pci_register_driver(&rt2500pci_driver);
1990 }
1991
1992 static void __exit rt2500pci_exit(void)
1993 {
1994         pci_unregister_driver(&rt2500pci_driver);
1995 }
1996
1997 module_init(rt2500pci_init);
1998 module_exit(rt2500pci_exit);