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   1 /*
   2  * arch/sh/kernel/cpu/sh4/probe.c
   3  *
   4  * CPU Subtype Probing for SH-4.
   5  *
   6  * Copyright (C) 2001 - 2006  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17 #include <asm/io.h>
  18
  19 int __init detect_cpu_and_cache_system(void)
  20 {
  21         unsigned long pvr, prr, cvr;
  22         unsigned long size;
  23
  24         static unsigned long sizes[16] = {
  25                 [1] = (1 << 12),
  26                 [2] = (1 << 13),
  27                 [4] = (1 << 14),
  28                 [8] = (1 << 15),
  29                 [9] = (1 << 16)
  30         };
  31
  32         pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffff;
  33         prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
  34         cvr = (ctrl_inl(CCN_CVR));
  35
  36         /*
  37          * Setup some sane SH-4 defaults for the icache
  38          */
  39         cpu_data->icache.way_incr       = (1 << 13);
  40         cpu_data->icache.entry_shift    = 5;
  41         cpu_data->icache.entry_mask     = 0x1fe0;
  42         cpu_data->icache.sets           = 256;
  43         cpu_data->icache.ways           = 1;
  44         cpu_data->icache.linesz         = L1_CACHE_BYTES;
  45
  46         /*
  47          * And again for the dcache ..
  48          */
  49         cpu_data->dcache.way_incr       = (1 << 14);
  50         cpu_data->dcache.entry_shift    = 5;
  51         cpu_data->dcache.entry_mask     = 0x3fe0;
  52         cpu_data->dcache.sets           = 512;
  53         cpu_data->dcache.ways           = 1;
  54         cpu_data->dcache.linesz         = L1_CACHE_BYTES;
  55
  56         /*
  57          * Probe the underlying processor version/revision and
  58          * adjust cpu_data setup accordingly.
  59          */
  60         switch (pvr) {
  61         case 0x205:
  62                 cpu_data->type = CPU_SH7750;
  63                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  64                                    CPU_HAS_PERF_COUNTER | CPU_HAS_PTEA;
  65                 break;
  66         case 0x206:
  67                 cpu_data->type = CPU_SH7750S;
  68                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  69                                    CPU_HAS_PERF_COUNTER | CPU_HAS_PTEA;
  70                 break;
  71         case 0x1100:
  72                 cpu_data->type = CPU_SH7751;
  73                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
  74                 break;
  75         case 0x2000:
  76                 cpu_data->type = CPU_SH73180;
  77                 cpu_data->icache.ways = 4;
  78                 cpu_data->dcache.ways = 4;
  79                 cpu_data->flags |= CPU_HAS_LLSC;
  80                 break;
  81         case 0x2001:
  82         case 0x2004:
  83                 cpu_data->type = CPU_SH7770;
  84                 cpu_data->icache.ways = 4;
  85                 cpu_data->dcache.ways = 4;
  86
  87                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
  88                 break;
  89         case 0x2006:
  90         case 0x200A:
  91                 if (prr == 0x61)
  92                         cpu_data->type = CPU_SH7781;
  93                 else
  94                         cpu_data->type = CPU_SH7780;
  95
  96                 cpu_data->icache.ways = 4;
  97                 cpu_data->dcache.ways = 4;
  98
  99                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 100                                    CPU_HAS_LLSC;
 101                 break;
 102         case 0x3000:
 103         case 0x3003:
 104                 cpu_data->type = CPU_SH7343;
 105                 cpu_data->icache.ways = 4;
 106                 cpu_data->dcache.ways = 4;
 107                 cpu_data->flags |= CPU_HAS_LLSC;
 108                 break;
 109         case 0x8000:
 110                 cpu_data->type = CPU_ST40RA;
 111                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
 112                 break;
 113         case 0x8100:
 114                 cpu_data->type = CPU_ST40GX1;
 115                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
 116                 break;
 117         case 0x700:
 118                 cpu_data->type = CPU_SH4_501;
 119                 cpu_data->icache.ways = 2;
 120                 cpu_data->dcache.ways = 2;
 121                 cpu_data->flags |= CPU_HAS_PTEA;
 122                 break;
 123         case 0x600:
 124                 cpu_data->type = CPU_SH4_202;
 125                 cpu_data->icache.ways = 2;
 126                 cpu_data->dcache.ways = 2;
 127                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
 128                 break;
 129         case 0x500 ... 0x501:
 130                 switch (prr) {
 131                 case 0x10:
 132                         cpu_data->type = CPU_SH7750R;
 133                         break;
 134                 case 0x11:
 135                         cpu_data->type = CPU_SH7751R;
 136                         break;
 137                 case 0x50 ... 0x5f:
 138                         cpu_data->type = CPU_SH7760;
 139                         break;
 140                 }
 141
 142                 cpu_data->icache.ways = 2;
 143                 cpu_data->dcache.ways = 2;
 144
 145                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
 146
 147                 break;
 148         default:
 149                 cpu_data->type = CPU_SH_NONE;
 150                 break;
 151         }
 152
 153 #ifdef CONFIG_SH_DIRECT_MAPPED
 154         cpu_data->icache.ways = 1;
 155         cpu_data->dcache.ways = 1;
 156 #endif
 157
 158         /*
 159          * On anything that's not a direct-mapped cache, look to the CVR
 160          * for I/D-cache specifics.
 161          */
 162         if (cpu_data->icache.ways > 1) {
 163                 size = sizes[(cvr >> 20) & 0xf];
 164                 cpu_data->icache.way_incr       = (size >> 1);
 165                 cpu_data->icache.sets           = (size >> 6);
 166                 cpu_data->icache.entry_mask     =
 167                         (cpu_data->icache.way_incr - (1 << 5));
 168         }
 169
 170         cpu_data->icache.way_size = cpu_data->icache.sets *
 171                                     cpu_data->icache.linesz;
 172
 173         if (cpu_data->dcache.ways > 1) {
 174                 size = sizes[(cvr >> 16) & 0xf];
 175                 cpu_data->dcache.way_incr       = (size >> 1);
 176                 cpu_data->dcache.sets           = (size >> 6);
 177                 cpu_data->dcache.entry_mask     =
 178                         (cpu_data->dcache.way_incr - (1 << 5));
 179         }
 180
 181         cpu_data->dcache.way_size = cpu_data->dcache.sets *
 182                                     cpu_data->dcache.linesz;
 183
 184         return 0;
 185 }