sis5513: add ->udma_filter method for chipset_family >= ATA_133
[linux-2.6] / drivers / ide / pci / slc90e66.c
1 /*
2  *  linux/drivers/ide/pci/slc90e66.c    Version 0.15    Jul 6, 2007
3  *
4  *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5  *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
6  *
7  * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
8  * but this keeps the ISA-Bridge and slots alive.
9  *
10  */
11
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/hdreg.h>
18 #include <linux/ide.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21
22 #include <asm/io.h>
23
24 static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
25         switch(xfer_rate) {
26                 case XFER_UDMA_4:
27                 case XFER_UDMA_3:
28                 case XFER_UDMA_2:
29                 case XFER_UDMA_1:
30                 case XFER_UDMA_0:
31                 case XFER_MW_DMA_2:
32                         return 4;
33                 case XFER_MW_DMA_1:
34                         return 3;
35                 case XFER_SW_DMA_2:
36                         return 2;
37                 case XFER_MW_DMA_0:
38                 case XFER_SW_DMA_1:
39                 case XFER_SW_DMA_0:
40                 default:
41                         return 0;
42         }
43 }
44
45 static void slc90e66_tune_pio (ide_drive_t *drive, u8 pio)
46 {
47         ide_hwif_t *hwif        = HWIF(drive);
48         struct pci_dev *dev     = hwif->pci_dev;
49         int is_slave            = drive->dn & 1;
50         int master_port         = hwif->channel ? 0x42 : 0x40;
51         int slave_port          = 0x44;
52         unsigned long flags;
53         u16 master_data;
54         u8 slave_data;
55         int control = 0;
56                                      /* ISP  RTC */
57         static const u8 timings[][2]= {
58                                         { 0, 0 },
59                                         { 0, 0 },
60                                         { 1, 0 },
61                                         { 2, 1 },
62                                         { 2, 3 }, };
63
64         spin_lock_irqsave(&ide_lock, flags);
65         pci_read_config_word(dev, master_port, &master_data);
66
67         if (pio > 1)
68                 control |= 1;   /* Programmable timing on */
69         if (drive->media == ide_disk)
70                 control |= 4;   /* Prefetch, post write */
71         if (pio > 2)
72                 control |= 2;   /* IORDY */
73         if (is_slave) {
74                 master_data |=  0x4000;
75                 master_data &= ~0x0070;
76                 if (pio > 1) {
77                         /* Set PPE, IE and TIME */
78                         master_data |= control << 4;
79                 }
80                 pci_read_config_byte(dev, slave_port, &slave_data);
81                 slave_data &= hwif->channel ? 0x0f : 0xf0;
82                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
83                                (hwif->channel ? 4 : 0);
84         } else {
85                 master_data &= ~0x3307;
86                 if (pio > 1) {
87                         /* enable PPE, IE and TIME */
88                         master_data |= control;
89                 }
90                 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
91         }
92         pci_write_config_word(dev, master_port, master_data);
93         if (is_slave)
94                 pci_write_config_byte(dev, slave_port, slave_data);
95         spin_unlock_irqrestore(&ide_lock, flags);
96 }
97
98 static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
99 {
100         pio = ide_get_best_pio_mode(drive, pio, 4);
101         slc90e66_tune_pio(drive, pio);
102         (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
103 }
104
105 static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
106 {
107         ide_hwif_t *hwif        = HWIF(drive);
108         struct pci_dev *dev     = hwif->pci_dev;
109         u8 maslave              = hwif->channel ? 0x42 : 0x40;
110         u8 speed                = ide_rate_filter(drive, xferspeed);
111         int sitre = 0, a_speed  = 7 << (drive->dn * 4);
112         int u_speed = 0, u_flag = 1 << drive->dn;
113         u16                     reg4042, reg44, reg48, reg4a;
114
115         pci_read_config_word(dev, maslave, &reg4042);
116         sitre = (reg4042 & 0x4000) ? 1 : 0;
117         pci_read_config_word(dev, 0x44, &reg44);
118         pci_read_config_word(dev, 0x48, &reg48);
119         pci_read_config_word(dev, 0x4a, &reg4a);
120
121         switch(speed) {
122                 case XFER_UDMA_4:       u_speed = 4 << (drive->dn * 4); break;
123                 case XFER_UDMA_3:       u_speed = 3 << (drive->dn * 4); break;
124                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
125                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
126                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
127                 case XFER_MW_DMA_2:
128                 case XFER_MW_DMA_1:
129                 case XFER_SW_DMA_2:     break;
130                 case XFER_PIO_4:
131                 case XFER_PIO_3:
132                 case XFER_PIO_2:
133                 case XFER_PIO_1:
134                 case XFER_PIO_0:        break;
135                 default:                return -1;
136         }
137
138         if (speed >= XFER_UDMA_0) {
139                 if (!(reg48 & u_flag))
140                         pci_write_config_word(dev, 0x48, reg48|u_flag);
141                 /* FIXME: (reg4a & a_speed) ? */
142                 if ((reg4a & u_speed) != u_speed) {
143                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
144                         pci_read_config_word(dev, 0x4a, &reg4a);
145                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
146                 }
147         } else {
148                 if (reg48 & u_flag)
149                         pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
150                 if (reg4a & a_speed)
151                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
152         }
153
154         if (speed > XFER_PIO_4)
155                 slc90e66_tune_pio(drive, slc90e66_dma_2_pio(speed));
156         else
157                 slc90e66_tune_pio(drive, speed - XFER_PIO_0);
158
159         return ide_config_drive_speed(drive, speed);
160 }
161
162 static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
163 {
164         drive->init_speed = 0;
165
166         if (ide_tune_dma(drive))
167                 return 0;
168
169         if (ide_use_fast_pio(drive))
170                 slc90e66_tune_drive(drive, 255);
171
172         return -1;
173 }
174
175 static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
176 {
177         u8 reg47 = 0;
178         u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */
179
180         hwif->autodma = 0;
181
182         if (!hwif->irq)
183                 hwif->irq = hwif->channel ? 15 : 14;
184
185         hwif->speedproc = &slc90e66_tune_chipset;
186         hwif->tuneproc  = &slc90e66_tune_drive;
187
188         pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
189
190         if (!hwif->dma_base) {
191                 hwif->drives[0].autotune = 1;
192                 hwif->drives[1].autotune = 1;
193                 return;
194         }
195
196         hwif->atapi_dma = 1;
197         hwif->ultra_mask = 0x1f;
198         hwif->mwdma_mask = 0x06;
199         hwif->swdma_mask = 0x04;
200
201         if (hwif->cbl != ATA_CBL_PATA40_SHORT)
202                 /* bit[0(1)]: 0:80, 1:40 */
203                 hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
204
205         hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
206
207         if (!noautodma)
208                 hwif->autodma = 1;
209         hwif->drives[0].autodma = hwif->autodma;
210         hwif->drives[1].autodma = hwif->autodma;
211 }
212
213 static ide_pci_device_t slc90e66_chipset __devinitdata = {
214         .name           = "SLC90E66",
215         .init_hwif      = init_hwif_slc90e66,
216         .autodma        = AUTODMA,
217         .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
218         .bootable       = ON_BOARD,
219         .pio_mask       = ATA_PIO4,
220 };
221
222 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
223 {
224         return ide_setup_pci_device(dev, &slc90e66_chipset);
225 }
226
227 static struct pci_device_id slc90e66_pci_tbl[] = {
228         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
229         { 0, },
230 };
231 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
232
233 static struct pci_driver driver = {
234         .name           = "SLC90e66_IDE",
235         .id_table       = slc90e66_pci_tbl,
236         .probe          = slc90e66_init_one,
237 };
238
239 static int __init slc90e66_ide_init(void)
240 {
241         return ide_pci_register_driver(&driver);
242 }
243
244 module_init(slc90e66_ide_init);
245
246 MODULE_AUTHOR("Andre Hedrick");
247 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
248 MODULE_LICENSE("GPL");