Merge branch 'x86/fpu' into x86/urgent
[linux-2.6] / arch / powerpc / boot / dts / mpc8555cds.dts
1 /*
2  * MPC8555 CDS Device Tree Source
3  *
4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         model = "MPC8555CDS";
16         compatible = "MPC8555CDS", "MPC85xxCDS";
17         #address-cells = <1>;
18         #size-cells = <1>;
19
20         aliases {
21                 ethernet0 = &enet0;
22                 ethernet1 = &enet1;
23                 serial0 = &serial0;
24                 serial1 = &serial1;
25                 pci0 = &pci0;
26                 pci1 = &pci1;
27         };
28
29         cpus {
30                 #address-cells = <1>;
31                 #size-cells = <0>;
32
33                 PowerPC,8555@0 {
34                         device_type = "cpu";
35                         reg = <0x0>;
36                         d-cache-line-size = <32>;       // 32 bytes
37                         i-cache-line-size = <32>;       // 32 bytes
38                         d-cache-size = <0x8000>;                // L1, 32K
39                         i-cache-size = <0x8000>;                // L1, 32K
40                         timebase-frequency = <0>;       //  33 MHz, from uboot
41                         bus-frequency = <0>;    // 166 MHz
42                         clock-frequency = <0>;  // 825 MHz, from uboot
43                         next-level-cache = <&L2>;
44                 };
45         };
46
47         memory {
48                 device_type = "memory";
49                 reg = <0x0 0x8000000>;  // 128M at 0x0
50         };
51
52         soc8555@e0000000 {
53                 #address-cells = <1>;
54                 #size-cells = <1>;
55                 device_type = "soc";
56                 compatible = "simple-bus";
57                 ranges = <0x0 0xe0000000 0x100000>;
58                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
59                 bus-frequency = <0>;
60
61                 memory-controller@2000 {
62                         compatible = "fsl,8555-memory-controller";
63                         reg = <0x2000 0x1000>;
64                         interrupt-parent = <&mpic>;
65                         interrupts = <18 2>;
66                 };
67
68                 L2: l2-cache-controller@20000 {
69                         compatible = "fsl,8555-l2-cache-controller";
70                         reg = <0x20000 0x1000>;
71                         cache-line-size = <32>; // 32 bytes
72                         cache-size = <0x40000>; // L2, 256K
73                         interrupt-parent = <&mpic>;
74                         interrupts = <16 2>;
75                 };
76
77                 i2c@3000 {
78                         #address-cells = <1>;
79                         #size-cells = <0>;
80                         cell-index = <0>;
81                         compatible = "fsl-i2c";
82                         reg = <0x3000 0x100>;
83                         interrupts = <43 2>;
84                         interrupt-parent = <&mpic>;
85                         dfsrr;
86                 };
87
88                 dma@21300 {
89                         #address-cells = <1>;
90                         #size-cells = <1>;
91                         compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
92                         reg = <0x21300 0x4>;
93                         ranges = <0x0 0x21100 0x200>;
94                         cell-index = <0>;
95                         dma-channel@0 {
96                                 compatible = "fsl,mpc8555-dma-channel",
97                                                 "fsl,eloplus-dma-channel";
98                                 reg = <0x0 0x80>;
99                                 cell-index = <0>;
100                                 interrupt-parent = <&mpic>;
101                                 interrupts = <20 2>;
102                         };
103                         dma-channel@80 {
104                                 compatible = "fsl,mpc8555-dma-channel",
105                                                 "fsl,eloplus-dma-channel";
106                                 reg = <0x80 0x80>;
107                                 cell-index = <1>;
108                                 interrupt-parent = <&mpic>;
109                                 interrupts = <21 2>;
110                         };
111                         dma-channel@100 {
112                                 compatible = "fsl,mpc8555-dma-channel",
113                                                 "fsl,eloplus-dma-channel";
114                                 reg = <0x100 0x80>;
115                                 cell-index = <2>;
116                                 interrupt-parent = <&mpic>;
117                                 interrupts = <22 2>;
118                         };
119                         dma-channel@180 {
120                                 compatible = "fsl,mpc8555-dma-channel",
121                                                 "fsl,eloplus-dma-channel";
122                                 reg = <0x180 0x80>;
123                                 cell-index = <3>;
124                                 interrupt-parent = <&mpic>;
125                                 interrupts = <23 2>;
126                         };
127                 };
128
129                 mdio@24520 {
130                         #address-cells = <1>;
131                         #size-cells = <0>;
132                         compatible = "fsl,gianfar-mdio";
133                         reg = <0x24520 0x20>;
134
135                         phy0: ethernet-phy@0 {
136                                 interrupt-parent = <&mpic>;
137                                 interrupts = <5 1>;
138                                 reg = <0x0>;
139                                 device_type = "ethernet-phy";
140                         };
141                         phy1: ethernet-phy@1 {
142                                 interrupt-parent = <&mpic>;
143                                 interrupts = <5 1>;
144                                 reg = <0x1>;
145                                 device_type = "ethernet-phy";
146                         };
147                 };
148
149                 enet0: ethernet@24000 {
150                         cell-index = <0>;
151                         device_type = "network";
152                         model = "TSEC";
153                         compatible = "gianfar";
154                         reg = <0x24000 0x1000>;
155                         local-mac-address = [ 00 00 00 00 00 00 ];
156                         interrupts = <29 2 30 2 34 2>;
157                         interrupt-parent = <&mpic>;
158                         phy-handle = <&phy0>;
159                 };
160
161                 enet1: ethernet@25000 {
162                         cell-index = <1>;
163                         device_type = "network";
164                         model = "TSEC";
165                         compatible = "gianfar";
166                         reg = <0x25000 0x1000>;
167                         local-mac-address = [ 00 00 00 00 00 00 ];
168                         interrupts = <35 2 36 2 40 2>;
169                         interrupt-parent = <&mpic>;
170                         phy-handle = <&phy1>;
171                 };
172
173                 serial0: serial@4500 {
174                         cell-index = <0>;
175                         device_type = "serial";
176                         compatible = "ns16550";
177                         reg = <0x4500 0x100>;   // reg base, size
178                         clock-frequency = <0>;  // should we fill in in uboot?
179                         interrupts = <42 2>;
180                         interrupt-parent = <&mpic>;
181                 };
182
183                 serial1: serial@4600 {
184                         cell-index = <1>;
185                         device_type = "serial";
186                         compatible = "ns16550";
187                         reg = <0x4600 0x100>;   // reg base, size
188                         clock-frequency = <0>;  // should we fill in in uboot?
189                         interrupts = <42 2>;
190                         interrupt-parent = <&mpic>;
191                 };
192
193                 crypto@30000 {
194                         compatible = "fsl,sec2.0";
195                         reg = <0x30000 0x10000>;
196                         interrupts = <45 2>;
197                         interrupt-parent = <&mpic>;
198                         fsl,num-channels = <4>;
199                         fsl,channel-fifo-len = <24>;
200                         fsl,exec-units-mask = <0x7e>;
201                         fsl,descriptor-types-mask = <0x01010ebf>;
202                 };
203
204                 mpic: pic@40000 {
205                         interrupt-controller;
206                         #address-cells = <0>;
207                         #interrupt-cells = <2>;
208                         reg = <0x40000 0x40000>;
209                         compatible = "chrp,open-pic";
210                         device_type = "open-pic";
211                 };
212
213                 cpm@919c0 {
214                         #address-cells = <1>;
215                         #size-cells = <1>;
216                         compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
217                         reg = <0x919c0 0x30>;
218                         ranges;
219
220                         muram@80000 {
221                                 #address-cells = <1>;
222                                 #size-cells = <1>;
223                                 ranges = <0x0 0x80000 0x10000>;
224
225                                 data@0 {
226                                         compatible = "fsl,cpm-muram-data";
227                                         reg = <0x0 0x2000 0x9000 0x1000>;
228                                 };
229                         };
230
231                         brg@919f0 {
232                                 compatible = "fsl,mpc8555-brg",
233                                              "fsl,cpm2-brg",
234                                              "fsl,cpm-brg";
235                                 reg = <0x919f0 0x10 0x915f0 0x10>;
236                         };
237
238                         cpmpic: pic@90c00 {
239                                 interrupt-controller;
240                                 #address-cells = <0>;
241                                 #interrupt-cells = <2>;
242                                 interrupts = <46 2>;
243                                 interrupt-parent = <&mpic>;
244                                 reg = <0x90c00 0x80>;
245                                 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
246                         };
247                 };
248         };
249
250         pci0: pci@e0008000 {
251                 cell-index = <0>;
252                 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
253                 interrupt-map = <
254
255                         /* IDSEL 0x10 */
256                         0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
257                         0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
258                         0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
259                         0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
260
261                         /* IDSEL 0x11 */
262                         0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
263                         0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
264                         0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
265                         0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
266
267                         /* IDSEL 0x12 (Slot 1) */
268                         0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
269                         0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
270                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
271                         0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
272
273                         /* IDSEL 0x13 (Slot 2) */
274                         0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
275                         0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
276                         0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
277                         0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
278
279                         /* IDSEL 0x14 (Slot 3) */
280                         0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
281                         0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
282                         0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
283                         0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
284
285                         /* IDSEL 0x15 (Slot 4) */
286                         0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
287                         0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
288                         0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
289                         0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
290
291                         /* Bus 1 (Tundra Bridge) */
292                         /* IDSEL 0x12 (ISA bridge) */
293                         0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
294                         0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
295                         0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
296                         0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
297                 interrupt-parent = <&mpic>;
298                 interrupts = <24 2>;
299                 bus-range = <0 0>;
300                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
301                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
302                 clock-frequency = <66666666>;
303                 #interrupt-cells = <1>;
304                 #size-cells = <2>;
305                 #address-cells = <3>;
306                 reg = <0xe0008000 0x1000>;
307                 compatible = "fsl,mpc8540-pci";
308                 device_type = "pci";
309
310                 i8259@19000 {
311                         interrupt-controller;
312                         device_type = "interrupt-controller";
313                         reg = <0x19000 0x0 0x0 0x0 0x1>;
314                         #address-cells = <0>;
315                         #interrupt-cells = <2>;
316                         compatible = "chrp,iic";
317                         interrupts = <1>;
318                         interrupt-parent = <&pci0>;
319                 };
320         };
321
322         pci1: pci@e0009000 {
323                 cell-index = <1>;
324                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
325                 interrupt-map = <
326
327                         /* IDSEL 0x15 */
328                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
329                         0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
330                         0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
331                         0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
332                 interrupt-parent = <&mpic>;
333                 interrupts = <25 2>;
334                 bus-range = <0 0>;
335                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
336                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
337                 clock-frequency = <66666666>;
338                 #interrupt-cells = <1>;
339                 #size-cells = <2>;
340                 #address-cells = <3>;
341                 reg = <0xe0009000 0x1000>;
342                 compatible = "fsl,mpc8540-pci";
343                 device_type = "pci";
344         };
345 };