git.oblomov.eu Git - linux-2.6/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
   4  *
   5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   6  *
   7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   8  *                     PeiSen Hou <pshou@realtek.com.tw>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the Free
  12  *  Software Foundation; either version 2 of the License, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  *  more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along with
  21  *  this program; if not, write to the Free Software Foundation, Inc., 59
  22  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  23  *
  24  *  CONTACTS:
  25  *
  26  *  Matt Jared          matt.jared@intel.com
  27  *  Andy Kopp           andy.kopp@intel.com
  28  *  Dan Kogan           dan.d.kogan@intel.com
  29  *
  30  *  CHANGES:
  31  *
  32  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  33  *
  34  */
  35
  36 #include <sound/driver.h>
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/module.h>
  41 #include <linux/moduleparam.h>
  42 #include <linux/init.h>
  43 #include <linux/slab.h>
  44 #include <linux/pci.h>
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include "hda_codec.h"
  48
  49
  50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  53 static char *model[SNDRV_CARDS];
  54 static int position_fix[SNDRV_CARDS];
  55
  56 module_param_array(index, int, NULL, 0444);
  57 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  58 module_param_array(id, charp, NULL, 0444);
  59 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  60 module_param_array(enable, bool, NULL, 0444);
  61 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  62 module_param_array(model, charp, NULL, 0444);
  63 MODULE_PARM_DESC(model, "Use the given board model.");
  64 module_param_array(position_fix, int, NULL, 0444);
  65 MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
  66
  67 MODULE_LICENSE("GPL");
  68 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  69                          "{Intel, ICH6M},"
  70                          "{Intel, ICH7},"
  71                          "{Intel, ESB2},"
  72                          "{ATI, SB450},"
  73                          "{VIA, VT8251},"
  74                          "{VIA, VT8237A},"
  75                          "{SiS, SIS966},"
  76                          "{ULI, M5461}}");
  77 MODULE_DESCRIPTION("Intel HDA driver");
  78
  79 #define SFX     "hda-intel: "
  80
  81 /*
  82  * registers
  83  */
  84 #define ICH6_REG_GCAP                   0x00
  85 #define ICH6_REG_VMIN                   0x02
  86 #define ICH6_REG_VMAJ                   0x03
  87 #define ICH6_REG_OUTPAY                 0x04
  88 #define ICH6_REG_INPAY                  0x06
  89 #define ICH6_REG_GCTL                   0x08
  90 #define ICH6_REG_WAKEEN                 0x0c
  91 #define ICH6_REG_STATESTS               0x0e
  92 #define ICH6_REG_GSTS                   0x10
  93 #define ICH6_REG_INTCTL                 0x20
  94 #define ICH6_REG_INTSTS                 0x24
  95 #define ICH6_REG_WALCLK                 0x30
  96 #define ICH6_REG_SYNC                   0x34
  97 #define ICH6_REG_CORBLBASE              0x40
  98 #define ICH6_REG_CORBUBASE              0x44
  99 #define ICH6_REG_CORBWP                 0x48
 100 #define ICH6_REG_CORBRP                 0x4A
 101 #define ICH6_REG_CORBCTL                0x4c
 102 #define ICH6_REG_CORBSTS                0x4d
 103 #define ICH6_REG_CORBSIZE               0x4e
 104
 105 #define ICH6_REG_RIRBLBASE              0x50
 106 #define ICH6_REG_RIRBUBASE              0x54
 107 #define ICH6_REG_RIRBWP                 0x58
 108 #define ICH6_REG_RINTCNT                0x5a
 109 #define ICH6_REG_RIRBCTL                0x5c
 110 #define ICH6_REG_RIRBSTS                0x5d
 111 #define ICH6_REG_RIRBSIZE               0x5e
 112
 113 #define ICH6_REG_IC                     0x60
 114 #define ICH6_REG_IR                     0x64
 115 #define ICH6_REG_IRS                    0x68
 116 #define   ICH6_IRS_VALID        (1<<1)
 117 #define   ICH6_IRS_BUSY         (1<<0)
 118
 119 #define ICH6_REG_DPLBASE                0x70
 120 #define ICH6_REG_DPUBASE                0x74
 121 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 122
 123 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 124 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 125
 126 /* stream register offsets from stream base */
 127 #define ICH6_REG_SD_CTL                 0x00
 128 #define ICH6_REG_SD_STS                 0x03
 129 #define ICH6_REG_SD_LPIB                0x04
 130 #define ICH6_REG_SD_CBL                 0x08
 131 #define ICH6_REG_SD_LVI                 0x0c
 132 #define ICH6_REG_SD_FIFOW               0x0e
 133 #define ICH6_REG_SD_FIFOSIZE            0x10
 134 #define ICH6_REG_SD_FORMAT              0x12
 135 #define ICH6_REG_SD_BDLPL               0x18
 136 #define ICH6_REG_SD_BDLPU               0x1c
 137
 138 /* PCI space */
 139 #define ICH6_PCIREG_TCSEL       0x44
 140
 141 /*
 142  * other constants
 143  */
 144
 145 /* max number of SDs */
 146 /* ICH, ATI and VIA have 4 playback and 4 capture */
 147 #define ICH6_CAPTURE_INDEX      0
 148 #define ICH6_NUM_CAPTURE        4
 149 #define ICH6_PLAYBACK_INDEX     4
 150 #define ICH6_NUM_PLAYBACK       4
 151
 152 /* ULI has 6 playback and 5 capture */
 153 #define ULI_CAPTURE_INDEX       0
 154 #define ULI_NUM_CAPTURE         5
 155 #define ULI_PLAYBACK_INDEX      5
 156 #define ULI_NUM_PLAYBACK        6
 157
 158 /* this number is statically defined for simplicity */
 159 #define MAX_AZX_DEV             16
 160
 161 /* max number of fragments - we may use more if allocating more pages for BDL */
 162 #define BDL_SIZE                PAGE_ALIGN(8192)
 163 #define AZX_MAX_FRAG            (BDL_SIZE / (MAX_AZX_DEV * 16))
 164 /* max buffer size - no h/w limit, you can increase as you like */
 165 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 166 /* max number of PCM devics per card */
 167 #define AZX_MAX_AUDIO_PCMS      6
 168 #define AZX_MAX_MODEM_PCMS      2
 169 #define AZX_MAX_PCMS            (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
 170
 171 /* RIRB int mask: overrun[2], response[0] */
 172 #define RIRB_INT_RESPONSE       0x01
 173 #define RIRB_INT_OVERRUN        0x04
 174 #define RIRB_INT_MASK           0x05
 175
 176 /* STATESTS int mask: SD2,SD1,SD0 */
 177 #define STATESTS_INT_MASK       0x07
 178 #define AZX_MAX_CODECS          4
 179
 180 /* SD_CTL bits */
 181 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 182 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 183 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 184 #define SD_CTL_STREAM_TAG_SHIFT 20
 185
 186 /* SD_CTL and SD_STS */
 187 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 188 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 189 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 190 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
 191
 192 /* SD_STS */
 193 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 194
 195 /* INTCTL and INTSTS */
 196 #define ICH6_INT_ALL_STREAM     0xff            /* all stream interrupts */
 197 #define ICH6_INT_CTRL_EN        0x40000000      /* controller interrupt enable bit */
 198 #define ICH6_INT_GLOBAL_EN      0x80000000      /* global interrupt enable bit */
 199
 200 /* GCTL unsolicited response enable bit */
 201 #define ICH6_GCTL_UREN          (1<<8)
 202
 203 /* GCTL reset bit */
 204 #define ICH6_GCTL_RESET         (1<<0)
 205
 206 /* CORB/RIRB control, read/write pointer */
 207 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 208 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 209 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 210 /* below are so far hardcoded - should read registers in future */
 211 #define ICH6_MAX_CORB_ENTRIES   256
 212 #define ICH6_MAX_RIRB_ENTRIES   256
 213
 214 /* position fix mode */
 215 enum {
 216         POS_FIX_AUTO,
 217         POS_FIX_NONE,
 218         POS_FIX_POSBUF,
 219         POS_FIX_FIFO,
 220 };
 221
 222 /* Defines for ATI HD Audio support in SB450 south bridge */
 223 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 224 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 225
 226
 227 /*
 228  * Use CORB/RIRB for communication from/to codecs.
 229  * This is the way recommended by Intel (see below).
 230  */
 231 #define USE_CORB_RIRB
 232
 233 /*
 234  */
 235
 236 typedef struct snd_azx azx_t;
 237 typedef struct snd_azx_rb azx_rb_t;
 238 typedef struct snd_azx_dev azx_dev_t;
 239
 240 struct snd_azx_dev {
 241         u32 *bdl;                       /* virtual address of the BDL */
 242         dma_addr_t bdl_addr;            /* physical address of the BDL */
 243         volatile u32 *posbuf;                   /* position buffer pointer */
 244
 245         unsigned int bufsize;           /* size of the play buffer in bytes */
 246         unsigned int fragsize;          /* size of each period in bytes */
 247         unsigned int frags;             /* number for period in the play buffer */
 248         unsigned int fifo_size;         /* FIFO size */
 249         unsigned int last_pos;          /* last updated period position */
 250
 251         void __iomem *sd_addr;          /* stream descriptor pointer */
 252
 253         u32 sd_int_sta_mask;            /* stream int status mask */
 254
 255         /* pcm support */
 256         snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
 257         unsigned int format_val;        /* format value to be set in the controller and the codec */
 258         unsigned char stream_tag;       /* assigned stream */
 259         unsigned char index;            /* stream index */
 260
 261         unsigned int opened: 1;
 262         unsigned int running: 1;
 263         unsigned int period_updating: 1;
 264 };
 265
 266 /* CORB/RIRB */
 267 struct snd_azx_rb {
 268         u32 *buf;               /* CORB/RIRB buffer
 269                                  * Each CORB entry is 4byte, RIRB is 8byte
 270                                  */
 271         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 272         /* for RIRB */
 273         unsigned short rp, wp;  /* read/write pointers */
 274         int cmds;               /* number of pending requests */
 275         u32 res;                /* last read value */
 276 };
 277
 278 struct snd_azx {
 279         snd_card_t *card;
 280         struct pci_dev *pci;
 281
 282         /* chip type specific */
 283         int driver_type;
 284         int playback_streams;
 285         int playback_index_offset;
 286         int capture_streams;
 287         int capture_index_offset;
 288         int num_streams;
 289
 290         /* pci resources */
 291         unsigned long addr;
 292         void __iomem *remap_addr;
 293         int irq;
 294
 295         /* locks */
 296         spinlock_t reg_lock;
 297         struct semaphore open_mutex;
 298
 299         /* streams (x num_streams) */
 300         azx_dev_t *azx_dev;
 301
 302         /* PCM */
 303         unsigned int pcm_devs;
 304         snd_pcm_t *pcm[AZX_MAX_PCMS];
 305
 306         /* HD codec */
 307         unsigned short codec_mask;
 308         struct hda_bus *bus;
 309
 310         /* CORB/RIRB */
 311         azx_rb_t corb;
 312         azx_rb_t rirb;
 313
 314         /* BDL, CORB/RIRB and position buffers */
 315         struct snd_dma_buffer bdl;
 316         struct snd_dma_buffer rb;
 317         struct snd_dma_buffer posbuf;
 318
 319         /* flags */
 320         int position_fix;
 321         unsigned int initialized: 1;
 322 };
 323
 324 /* driver types */
 325 enum {
 326         AZX_DRIVER_ICH,
 327         AZX_DRIVER_ATI,
 328         AZX_DRIVER_VIA,
 329         AZX_DRIVER_SIS,
 330         AZX_DRIVER_ULI,
 331 };
 332
 333 static char *driver_short_names[] __devinitdata = {
 334         [AZX_DRIVER_ICH] = "HDA Intel",
 335         [AZX_DRIVER_ATI] = "HDA ATI SB",
 336         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 337         [AZX_DRIVER_SIS] = "HDA SIS966",
 338         [AZX_DRIVER_ULI] = "HDA ULI M5461"
 339 };
 340
 341 /*
 342  * macros for easy use
 343  */
 344 #define azx_writel(chip,reg,value) \
 345         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 346 #define azx_readl(chip,reg) \
 347         readl((chip)->remap_addr + ICH6_REG_##reg)
 348 #define azx_writew(chip,reg,value) \
 349         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 350 #define azx_readw(chip,reg) \
 351         readw((chip)->remap_addr + ICH6_REG_##reg)
 352 #define azx_writeb(chip,reg,value) \
 353         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 354 #define azx_readb(chip,reg) \
 355         readb((chip)->remap_addr + ICH6_REG_##reg)
 356
 357 #define azx_sd_writel(dev,reg,value) \
 358         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 359 #define azx_sd_readl(dev,reg) \
 360         readl((dev)->sd_addr + ICH6_REG_##reg)
 361 #define azx_sd_writew(dev,reg,value) \
 362         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 363 #define azx_sd_readw(dev,reg) \
 364         readw((dev)->sd_addr + ICH6_REG_##reg)
 365 #define azx_sd_writeb(dev,reg,value) \
 366         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 367 #define azx_sd_readb(dev,reg) \
 368         readb((dev)->sd_addr + ICH6_REG_##reg)
 369
 370 /* for pcm support */
 371 #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
 372
 373 /* Get the upper 32bit of the given dma_addr_t
 374  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 375  */
 376 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 377
 378
 379 /*
 380  * Interface for HD codec
 381  */
 382
 383 #ifdef USE_CORB_RIRB
 384 /*
 385  * CORB / RIRB interface
 386  */
 387 static int azx_alloc_cmd_io(azx_t *chip)
 388 {
 389         int err;
 390
 391         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 392         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
 393                                   PAGE_SIZE, &chip->rb);
 394         if (err < 0) {
 395                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 396                 return err;
 397         }
 398         return 0;
 399 }
 400
 401 static void azx_init_cmd_io(azx_t *chip)
 402 {
 403         /* CORB set up */
 404         chip->corb.addr = chip->rb.addr;
 405         chip->corb.buf = (u32 *)chip->rb.area;
 406         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 407         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 408
 409         /* set the corb size to 256 entries (ULI requires explicitly) */
 410         azx_writeb(chip, CORBSIZE, 0x02);
 411         /* set the corb write pointer to 0 */
 412         azx_writew(chip, CORBWP, 0);
 413         /* reset the corb hw read pointer */
 414         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 415         /* enable corb dma */
 416         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 417
 418         /* RIRB set up */
 419         chip->rirb.addr = chip->rb.addr + 2048;
 420         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 421         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 422         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 423
 424         /* set the rirb size to 256 entries (ULI requires explicitly) */
 425         azx_writeb(chip, RIRBSIZE, 0x02);
 426         /* reset the rirb hw write pointer */
 427         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 428         /* set N=1, get RIRB response interrupt for new entry */
 429         azx_writew(chip, RINTCNT, 1);
 430         /* enable rirb dma and response irq */
 431 #ifdef USE_CORB_RIRB
 432         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 433 #else
 434         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
 435 #endif
 436         chip->rirb.rp = chip->rirb.cmds = 0;
 437 }
 438
 439 static void azx_free_cmd_io(azx_t *chip)
 440 {
 441         /* disable ringbuffer DMAs */
 442         azx_writeb(chip, RIRBCTL, 0);
 443         azx_writeb(chip, CORBCTL, 0);
 444 }
 445
 446 /* send a command */
 447 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 448                         unsigned int verb, unsigned int para)
 449 {
 450         azx_t *chip = codec->bus->private_data;
 451         unsigned int wp;
 452         u32 val;
 453
 454         val = (u32)(codec->addr & 0x0f) << 28;
 455         val |= (u32)direct << 27;
 456         val |= (u32)nid << 20;
 457         val |= verb << 8;
 458         val |= para;
 459
 460         /* add command to corb */
 461         wp = azx_readb(chip, CORBWP);
 462         wp++;
 463         wp %= ICH6_MAX_CORB_ENTRIES;
 464
 465         spin_lock_irq(&chip->reg_lock);
 466         chip->rirb.cmds++;
 467         chip->corb.buf[wp] = cpu_to_le32(val);
 468         azx_writel(chip, CORBWP, wp);
 469         spin_unlock_irq(&chip->reg_lock);
 470
 471         return 0;
 472 }
 473
 474 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 475
 476 /* retrieve RIRB entry - called from interrupt handler */
 477 static void azx_update_rirb(azx_t *chip)
 478 {
 479         unsigned int rp, wp;
 480         u32 res, res_ex;
 481
 482         wp = azx_readb(chip, RIRBWP);
 483         if (wp == chip->rirb.wp)
 484                 return;
 485         chip->rirb.wp = wp;
 486
 487         while (chip->rirb.rp != wp) {
 488                 chip->rirb.rp++;
 489                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 490
 491                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 492                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 493                 res = le32_to_cpu(chip->rirb.buf[rp]);
 494                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 495                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 496                 else if (chip->rirb.cmds) {
 497                         chip->rirb.cmds--;
 498                         chip->rirb.res = res;
 499                 }
 500         }
 501 }
 502
 503 /* receive a response */
 504 static unsigned int azx_get_response(struct hda_codec *codec)
 505 {
 506         azx_t *chip = codec->bus->private_data;
 507         int timeout = 50;
 508
 509         while (chip->rirb.cmds) {
 510                 if (! --timeout) {
 511                         snd_printk(KERN_ERR "azx_get_response timeout\n");
 512                         chip->rirb.rp = azx_readb(chip, RIRBWP);
 513                         chip->rirb.cmds = 0;
 514                         return -1;
 515                 }
 516                 msleep(1);
 517         }
 518         return chip->rirb.res; /* the last value */
 519 }
 520
 521 #else
 522 /*
 523  * Use the single immediate command instead of CORB/RIRB for simplicity
 524  *
 525  * Note: according to Intel, this is not preferred use.  The command was
 526  *       intended for the BIOS only, and may get confused with unsolicited
 527  *       responses.  So, we shouldn't use it for normal operation from the
 528  *       driver.
 529  *       I left the codes, however, for debugging/testing purposes.
 530  */
 531
 532 #define azx_alloc_cmd_io(chip)  0
 533 #define azx_init_cmd_io(chip)
 534 #define azx_free_cmd_io(chip)
 535
 536 /* send a command */
 537 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 538                         unsigned int verb, unsigned int para)
 539 {
 540         azx_t *chip = codec->bus->private_data;
 541         u32 val;
 542         int timeout = 50;
 543
 544         val = (u32)(codec->addr & 0x0f) << 28;
 545         val |= (u32)direct << 27;
 546         val |= (u32)nid << 20;
 547         val |= verb << 8;
 548         val |= para;
 549
 550         while (timeout--) {
 551                 /* check ICB busy bit */
 552                 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
 553                         /* Clear IRV valid bit */
 554                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
 555                         azx_writel(chip, IC, val);
 556                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
 557                         return 0;
 558                 }
 559                 udelay(1);
 560         }
 561         snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
 562         return -EIO;
 563 }
 564
 565 /* receive a response */
 566 static unsigned int azx_get_response(struct hda_codec *codec)
 567 {
 568         azx_t *chip = codec->bus->private_data;
 569         int timeout = 50;
 570
 571         while (timeout--) {
 572                 /* check IRV busy bit */
 573                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 574                         return azx_readl(chip, IR);
 575                 udelay(1);
 576         }
 577         snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
 578         return (unsigned int)-1;
 579 }
 580
 581 #define azx_update_rirb(chip)
 582
 583 #endif /* USE_CORB_RIRB */
 584
 585 /* reset codec link */
 586 static int azx_reset(azx_t *chip)
 587 {
 588         int count;
 589
 590         /* reset controller */
 591         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 592
 593         count = 50;
 594         while (azx_readb(chip, GCTL) && --count)
 595                 msleep(1);
 596
 597         /* delay for >= 100us for codec PLL to settle per spec
 598          * Rev 0.9 section 5.5.1
 599          */
 600         msleep(1);
 601
 602         /* Bring controller out of reset */
 603         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 604
 605         count = 50;
 606         while (! azx_readb(chip, GCTL) && --count)
 607                 msleep(1);
 608
 609         /* Brent Chartrand said to wait >= 540us for codecs to intialize */
 610         msleep(1);
 611
 612         /* check to see if controller is ready */
 613         if (! azx_readb(chip, GCTL)) {
 614                 snd_printd("azx_reset: controller not ready!\n");
 615                 return -EBUSY;
 616         }
 617
 618         /* Accept unsolicited responses */
 619         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 620
 621         /* detect codecs */
 622         if (! chip->codec_mask) {
 623                 chip->codec_mask = azx_readw(chip, STATESTS);
 624                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 625         }
 626
 627         return 0;
 628 }
 629
 630
 631 /*
 632  * Lowlevel interface
 633  */
 634
 635 /* enable interrupts */
 636 static void azx_int_enable(azx_t *chip)
 637 {
 638         /* enable controller CIE and GIE */
 639         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 640                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 641 }
 642
 643 /* disable interrupts */
 644 static void azx_int_disable(azx_t *chip)
 645 {
 646         int i;
 647
 648         /* disable interrupts in stream descriptor */
 649         for (i = 0; i < chip->num_streams; i++) {
 650                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 651                 azx_sd_writeb(azx_dev, SD_CTL,
 652                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 653         }
 654
 655         /* disable SIE for all streams */
 656         azx_writeb(chip, INTCTL, 0);
 657
 658         /* disable controller CIE and GIE */
 659         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 660                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 661 }
 662
 663 /* clear interrupts */
 664 static void azx_int_clear(azx_t *chip)
 665 {
 666         int i;
 667
 668         /* clear stream status */
 669         for (i = 0; i < chip->num_streams; i++) {
 670                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 671                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 672         }
 673
 674         /* clear STATESTS */
 675         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 676
 677         /* clear rirb status */
 678         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 679
 680         /* clear int status */
 681         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 682 }
 683
 684 /* start a stream */
 685 static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
 686 {
 687         /* enable SIE */
 688         azx_writeb(chip, INTCTL,
 689                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 690         /* set DMA start and interrupt mask */
 691         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 692                       SD_CTL_DMA_START | SD_INT_MASK);
 693 }
 694
 695 /* stop a stream */
 696 static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
 697 {
 698         /* stop DMA */
 699         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 700                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 701         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 702         /* disable SIE */
 703         azx_writeb(chip, INTCTL,
 704                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 705 }
 706
 707
 708 /*
 709  * initialize the chip
 710  */
 711 static void azx_init_chip(azx_t *chip)
 712 {
 713         unsigned char tcsel_reg, ati_misc_cntl2;
 714
 715         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 716          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 717          * Ensuring these bits are 0 clears playback static on some HD Audio codecs
 718          */
 719         pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg);
 720         pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8);
 721
 722         /* reset controller */
 723         azx_reset(chip);
 724
 725         /* initialize interrupts */
 726         azx_int_clear(chip);
 727         azx_int_enable(chip);
 728
 729         /* initialize the codec command I/O */
 730         azx_init_cmd_io(chip);
 731
 732         /* program the position buffer */
 733         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 734         azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 735
 736         /* For ATI SB450 azalia HD audio, we need to enable snoop */
 737         if (chip->driver_type == AZX_DRIVER_ATI) {
 738                 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 739                                      &ati_misc_cntl2);
 740                 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 741                                       (ati_misc_cntl2 & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 742         }
 743 }
 744
 745
 746 /*
 747  * interrupt handler
 748  */
 749 static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
 750 {
 751         azx_t *chip = dev_id;
 752         azx_dev_t *azx_dev;
 753         u32 status;
 754         int i;
 755
 756         spin_lock(&chip->reg_lock);
 757
 758         status = azx_readl(chip, INTSTS);
 759         if (status == 0) {
 760                 spin_unlock(&chip->reg_lock);
 761                 return IRQ_NONE;
 762         }
 763
 764         for (i = 0; i < chip->num_streams; i++) {
 765                 azx_dev = &chip->azx_dev[i];
 766                 if (status & azx_dev->sd_int_sta_mask) {
 767                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 768                         if (azx_dev->substream && azx_dev->running) {
 769                                 azx_dev->period_updating = 1;
 770                                 spin_unlock(&chip->reg_lock);
 771                                 snd_pcm_period_elapsed(azx_dev->substream);
 772                                 spin_lock(&chip->reg_lock);
 773                                 azx_dev->period_updating = 0;
 774                         }
 775                 }
 776         }
 777
 778         /* clear rirb int */
 779         status = azx_readb(chip, RIRBSTS);
 780         if (status & RIRB_INT_MASK) {
 781                 if (status & RIRB_INT_RESPONSE)
 782                         azx_update_rirb(chip);
 783                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 784         }
 785
 786 #if 0
 787         /* clear state status int */
 788         if (azx_readb(chip, STATESTS) & 0x04)
 789                 azx_writeb(chip, STATESTS, 0x04);
 790 #endif
 791         spin_unlock(&chip->reg_lock);
 792
 793         return IRQ_HANDLED;
 794 }
 795
 796
 797 /*
 798  * set up BDL entries
 799  */
 800 static void azx_setup_periods(azx_dev_t *azx_dev)
 801 {
 802         u32 *bdl = azx_dev->bdl;
 803         dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
 804         int idx;
 805
 806         /* reset BDL address */
 807         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 808         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 809
 810         /* program the initial BDL entries */
 811         for (idx = 0; idx < azx_dev->frags; idx++) {
 812                 unsigned int off = idx << 2; /* 4 dword step */
 813                 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
 814                 /* program the address field of the BDL entry */
 815                 bdl[off] = cpu_to_le32((u32)addr);
 816                 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
 817
 818                 /* program the size field of the BDL entry */
 819                 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
 820
 821                 /* program the IOC to enable interrupt when buffer completes */
 822                 bdl[off+3] = cpu_to_le32(0x01);
 823         }
 824 }
 825
 826 /*
 827  * set up the SD for streaming
 828  */
 829 static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
 830 {
 831         unsigned char val;
 832         int timeout;
 833
 834         /* make sure the run bit is zero for SD */
 835         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
 836         /* reset stream */
 837         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
 838         udelay(3);
 839         timeout = 300;
 840         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 841                --timeout)
 842                 ;
 843         val &= ~SD_CTL_STREAM_RESET;
 844         azx_sd_writeb(azx_dev, SD_CTL, val);
 845         udelay(3);
 846
 847         timeout = 300;
 848         /* waiting for hardware to report that the stream is out of reset */
 849         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 850                --timeout)
 851                 ;
 852
 853         /* program the stream_tag */
 854         azx_sd_writel(azx_dev, SD_CTL,
 855                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
 856                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
 857
 858         /* program the length of samples in cyclic buffer */
 859         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 860
 861         /* program the stream format */
 862         /* this value needs to be the same as the one programmed */
 863         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 864
 865         /* program the stream LVI (last valid index) of the BDL */
 866         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 867
 868         /* program the BDL address */
 869         /* lower BDL address */
 870         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
 871         /* upper BDL address */
 872         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
 873
 874         /* enable the position buffer */
 875         if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
 876                 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
 877
 878         /* set the interrupt enable bits in the descriptor control register */
 879         azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
 880
 881         return 0;
 882 }
 883
 884
 885 /*
 886  * Codec initialization
 887  */
 888
 889 static int __devinit azx_codec_create(azx_t *chip, const char *model)
 890 {
 891         struct hda_bus_template bus_temp;
 892         int c, codecs, err;
 893
 894         memset(&bus_temp, 0, sizeof(bus_temp));
 895         bus_temp.private_data = chip;
 896         bus_temp.modelname = model;
 897         bus_temp.pci = chip->pci;
 898         bus_temp.ops.command = azx_send_cmd;
 899         bus_temp.ops.get_response = azx_get_response;
 900
 901         if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
 902                 return err;
 903
 904         codecs = 0;
 905         for (c = 0; c < AZX_MAX_CODECS; c++) {
 906                 if (chip->codec_mask & (1 << c)) {
 907                         err = snd_hda_codec_new(chip->bus, c, NULL);
 908                         if (err < 0)
 909                                 continue;
 910                         codecs++;
 911                 }
 912         }
 913         if (! codecs) {
 914                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
 915                 return -ENXIO;
 916         }
 917
 918         return 0;
 919 }
 920
 921
 922 /*
 923  * PCM support
 924  */
 925
 926 /* assign a stream for the PCM */
 927 static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
 928 {
 929         int dev, i, nums;
 930         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 931                 dev = chip->playback_index_offset;
 932                 nums = chip->playback_streams;
 933         } else {
 934                 dev = chip->capture_index_offset;
 935                 nums = chip->capture_streams;
 936         }
 937         for (i = 0; i < nums; i++, dev++)
 938                 if (! chip->azx_dev[dev].opened) {
 939                         chip->azx_dev[dev].opened = 1;
 940                         return &chip->azx_dev[dev];
 941                 }
 942         return NULL;
 943 }
 944
 945 /* release the assigned stream */
 946 static inline void azx_release_device(azx_dev_t *azx_dev)
 947 {
 948         azx_dev->opened = 0;
 949 }
 950
 951 static snd_pcm_hardware_t azx_pcm_hw = {
 952         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 953                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 954                                  SNDRV_PCM_INFO_MMAP_VALID |
 955                                  SNDRV_PCM_INFO_PAUSE /*|*/
 956                                  /*SNDRV_PCM_INFO_RESUME*/),
 957         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 958         .rates =                SNDRV_PCM_RATE_48000,
 959         .rate_min =             48000,
 960         .rate_max =             48000,
 961         .channels_min =         2,
 962         .channels_max =         2,
 963         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 964         .period_bytes_min =     128,
 965         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 966         .periods_min =          2,
 967         .periods_max =          AZX_MAX_FRAG,
 968         .fifo_size =            0,
 969 };
 970
 971 struct azx_pcm {
 972         azx_t *chip;
 973         struct hda_codec *codec;
 974         struct hda_pcm_stream *hinfo[2];
 975 };
 976
 977 static int azx_pcm_open(snd_pcm_substream_t *substream)
 978 {
 979         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 980         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 981         azx_t *chip = apcm->chip;
 982         azx_dev_t *azx_dev;
 983         snd_pcm_runtime_t *runtime = substream->runtime;
 984         unsigned long flags;
 985         int err;
 986
 987         down(&chip->open_mutex);
 988         azx_dev = azx_assign_device(chip, substream->stream);
 989         if (azx_dev == NULL) {
 990                 up(&chip->open_mutex);
 991                 return -EBUSY;
 992         }
 993         runtime->hw = azx_pcm_hw;
 994         runtime->hw.channels_min = hinfo->channels_min;
 995         runtime->hw.channels_max = hinfo->channels_max;
 996         runtime->hw.formats = hinfo->formats;
 997         runtime->hw.rates = hinfo->rates;
 998         snd_pcm_limit_hw_rates(runtime);
 999         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1000         if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
1001                 azx_release_device(azx_dev);
1002                 up(&chip->open_mutex);
1003                 return err;
1004         }
1005         spin_lock_irqsave(&chip->reg_lock, flags);
1006         azx_dev->substream = substream;
1007         azx_dev->running = 0;
1008         spin_unlock_irqrestore(&chip->reg_lock, flags);
1009
1010         runtime->private_data = azx_dev;
1011         up(&chip->open_mutex);
1012         return 0;
1013 }
1014
1015 static int azx_pcm_close(snd_pcm_substream_t *substream)
1016 {
1017         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1018         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1019         azx_t *chip = apcm->chip;
1020         azx_dev_t *azx_dev = get_azx_dev(substream);
1021         unsigned long flags;
1022
1023         down(&chip->open_mutex);
1024         spin_lock_irqsave(&chip->reg_lock, flags);
1025         azx_dev->substream = NULL;
1026         azx_dev->running = 0;
1027         spin_unlock_irqrestore(&chip->reg_lock, flags);
1028         azx_release_device(azx_dev);
1029         hinfo->ops.close(hinfo, apcm->codec, substream);
1030         up(&chip->open_mutex);
1031         return 0;
1032 }
1033
1034 static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
1035 {
1036         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1037 }
1038
1039 static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
1040 {
1041         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1042         azx_dev_t *azx_dev = get_azx_dev(substream);
1043         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1044
1045         /* reset BDL address */
1046         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1047         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1048         azx_sd_writel(azx_dev, SD_CTL, 0);
1049
1050         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1051
1052         return snd_pcm_lib_free_pages(substream);
1053 }
1054
1055 static int azx_pcm_prepare(snd_pcm_substream_t *substream)
1056 {
1057         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1058         azx_t *chip = apcm->chip;
1059         azx_dev_t *azx_dev = get_azx_dev(substream);
1060         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1061         snd_pcm_runtime_t *runtime = substream->runtime;
1062
1063         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1064         azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1065         azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1066         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1067                                                          runtime->channels,
1068                                                          runtime->format,
1069                                                          hinfo->maxbps);
1070         if (! azx_dev->format_val) {
1071                 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1072                            runtime->rate, runtime->channels, runtime->format);
1073                 return -EINVAL;
1074         }
1075
1076         snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1077                     azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1078         azx_setup_periods(azx_dev);
1079         azx_setup_controller(chip, azx_dev);
1080         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1081                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1082         else
1083                 azx_dev->fifo_size = 0;
1084         azx_dev->last_pos = 0;
1085
1086         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1087                                   azx_dev->format_val, substream);
1088 }
1089
1090 static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1091 {
1092         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1093         azx_dev_t *azx_dev = get_azx_dev(substream);
1094         azx_t *chip = apcm->chip;
1095         int err = 0;
1096
1097         spin_lock(&chip->reg_lock);
1098         switch (cmd) {
1099         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1100         case SNDRV_PCM_TRIGGER_RESUME:
1101         case SNDRV_PCM_TRIGGER_START:
1102                 azx_stream_start(chip, azx_dev);
1103                 azx_dev->running = 1;
1104                 break;
1105         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1106         case SNDRV_PCM_TRIGGER_SUSPEND:
1107         case SNDRV_PCM_TRIGGER_STOP:
1108                 azx_stream_stop(chip, azx_dev);
1109                 azx_dev->running = 0;
1110                 break;
1111         default:
1112                 err = -EINVAL;
1113         }
1114         spin_unlock(&chip->reg_lock);
1115         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1116             cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1117             cmd == SNDRV_PCM_TRIGGER_STOP) {
1118                 int timeout = 5000;
1119                 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1120                         ;
1121         }
1122         return err;
1123 }
1124
1125 static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
1126 {
1127         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1128         azx_t *chip = apcm->chip;
1129         azx_dev_t *azx_dev = get_azx_dev(substream);
1130         unsigned int pos;
1131
1132         if (chip->position_fix == POS_FIX_POSBUF) {
1133                 /* use the position buffer */
1134                 pos = *azx_dev->posbuf;
1135         } else {
1136                 /* read LPIB */
1137                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1138                 if (chip->position_fix == POS_FIX_FIFO)
1139                         pos += azx_dev->fifo_size;
1140 #if 0 /* disabled temprarily, auto-correction doesn't work well... */
1141                 else if (chip->position_fix == POS_FIX_AUTO && azx_dev->period_updating) {
1142                         /* check the validity of DMA position */
1143                         unsigned int diff = 0;
1144                         azx_dev->last_pos += azx_dev->fragsize;
1145                         if (azx_dev->last_pos > pos)
1146                                 diff = azx_dev->last_pos - pos;
1147                         if (azx_dev->last_pos >= azx_dev->bufsize) {
1148                                 if (pos < azx_dev->fragsize)
1149                                         diff = 0;
1150                                 azx_dev->last_pos = 0;
1151                         }
1152                         if (diff > 0 && diff <= azx_dev->fifo_size)
1153                                 pos += azx_dev->fifo_size;
1154                         else {
1155                                 snd_printdd(KERN_INFO "hda_intel: DMA position fix %d, switching to posbuf\n", diff);
1156                                 chip->position_fix = POS_FIX_POSBUF;
1157                                 pos = *azx_dev->posbuf;
1158                         }
1159                         azx_dev->period_updating = 0;
1160                 }
1161 #else
1162                 else if (chip->position_fix == POS_FIX_AUTO)
1163                         pos += azx_dev->fifo_size;
1164 #endif
1165         }
1166         if (pos >= azx_dev->bufsize)
1167                 pos = 0;
1168         return bytes_to_frames(substream->runtime, pos);
1169 }
1170
1171 static snd_pcm_ops_t azx_pcm_ops = {
1172         .open = azx_pcm_open,
1173         .close = azx_pcm_close,
1174         .ioctl = snd_pcm_lib_ioctl,
1175         .hw_params = azx_pcm_hw_params,
1176         .hw_free = azx_pcm_hw_free,
1177         .prepare = azx_pcm_prepare,
1178         .trigger = azx_pcm_trigger,
1179         .pointer = azx_pcm_pointer,
1180 };
1181
1182 static void azx_pcm_free(snd_pcm_t *pcm)
1183 {
1184         kfree(pcm->private_data);
1185 }
1186
1187 static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
1188                                       struct hda_pcm *cpcm, int pcm_dev)
1189 {
1190         int err;
1191         snd_pcm_t *pcm;
1192         struct azx_pcm *apcm;
1193
1194         snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1195         snd_assert(cpcm->name, return -EINVAL);
1196
1197         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1198                           cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1199                           &pcm);
1200         if (err < 0)
1201                 return err;
1202         strcpy(pcm->name, cpcm->name);
1203         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1204         if (apcm == NULL)
1205                 return -ENOMEM;
1206         apcm->chip = chip;
1207         apcm->codec = codec;
1208         apcm->hinfo[0] = &cpcm->stream[0];
1209         apcm->hinfo[1] = &cpcm->stream[1];
1210         pcm->private_data = apcm;
1211         pcm->private_free = azx_pcm_free;
1212         if (cpcm->stream[0].substreams)
1213                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1214         if (cpcm->stream[1].substreams)
1215                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1216         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1217                                               snd_dma_pci_data(chip->pci),
1218                                               1024 * 64, 1024 * 128);
1219         chip->pcm[pcm_dev] = pcm;
1220         chip->pcm_devs = pcm_dev + 1;
1221
1222         return 0;
1223 }
1224
1225 static int __devinit azx_pcm_create(azx_t *chip)
1226 {
1227         struct list_head *p;
1228         struct hda_codec *codec;
1229         int c, err;
1230         int pcm_dev;
1231
1232         if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1233                 return err;
1234
1235         /* create audio PCMs */
1236         pcm_dev = 0;
1237         list_for_each(p, &chip->bus->codec_list) {
1238                 codec = list_entry(p, struct hda_codec, list);
1239                 for (c = 0; c < codec->num_pcms; c++) {
1240                         if (codec->pcm_info[c].is_modem)
1241                                 continue; /* create later */
1242                         if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1243                                 snd_printk(KERN_ERR SFX "Too many audio PCMs\n");
1244                                 return -EINVAL;
1245                         }
1246                         err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1247                         if (err < 0)
1248                                 return err;
1249                         pcm_dev++;
1250                 }
1251         }
1252
1253         /* create modem PCMs */
1254         pcm_dev = AZX_MAX_AUDIO_PCMS;
1255         list_for_each(p, &chip->bus->codec_list) {
1256                 codec = list_entry(p, struct hda_codec, list);
1257                 for (c = 0; c < codec->num_pcms; c++) {
1258                         if (! codec->pcm_info[c].is_modem)
1259                                 continue; /* already created */
1260                         if (pcm_dev >= AZX_MAX_PCMS) {
1261                                 snd_printk(KERN_ERR SFX "Too many modem PCMs\n");
1262                                 return -EINVAL;
1263                         }
1264                         err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1265                         if (err < 0)
1266                                 return err;
1267                         pcm_dev++;
1268                 }
1269         }
1270         return 0;
1271 }
1272
1273 /*
1274  * mixer creation - all stuff is implemented in hda module
1275  */
1276 static int __devinit azx_mixer_create(azx_t *chip)
1277 {
1278         return snd_hda_build_controls(chip->bus);
1279 }
1280
1281
1282 /*
1283  * initialize SD streams
1284  */
1285 static int __devinit azx_init_stream(azx_t *chip)
1286 {
1287         int i;
1288
1289         /* initialize each stream (aka device)
1290          * assign the starting bdl address to each stream (device) and initialize
1291          */
1292         for (i = 0; i < chip->num_streams; i++) {
1293                 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1294                 azx_dev_t *azx_dev = &chip->azx_dev[i];
1295                 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1296                 azx_dev->bdl_addr = chip->bdl.addr + off;
1297                 azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1298                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1299                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1300                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1301                 azx_dev->sd_int_sta_mask = 1 << i;
1302                 /* stream tag: must be non-zero and unique */
1303                 azx_dev->index = i;
1304                 azx_dev->stream_tag = i + 1;
1305         }
1306
1307         return 0;
1308 }
1309
1310
1311 #ifdef CONFIG_PM
1312 /*
1313  * power management
1314  */
1315 static int azx_suspend(snd_card_t *card, pm_message_t state)
1316 {
1317         azx_t *chip = card->pm_private_data;
1318         int i;
1319
1320         for (i = 0; i < chip->pcm_devs; i++)
1321                 if (chip->pcm[i])
1322                         snd_pcm_suspend_all(chip->pcm[i]);
1323         snd_hda_suspend(chip->bus, state);
1324         azx_free_cmd_io(chip);
1325         pci_disable_device(chip->pci);
1326         return 0;
1327 }
1328
1329 static int azx_resume(snd_card_t *card)
1330 {
1331         azx_t *chip = card->pm_private_data;
1332
1333         pci_enable_device(chip->pci);
1334         pci_set_master(chip->pci);
1335         azx_init_chip(chip);
1336         snd_hda_resume(chip->bus);
1337         return 0;
1338 }
1339 #endif /* CONFIG_PM */
1340
1341
1342 /*
1343  * destructor
1344  */
1345 static int azx_free(azx_t *chip)
1346 {
1347         if (chip->initialized) {
1348                 int i;
1349
1350                 for (i = 0; i < chip->num_streams; i++)
1351                         azx_stream_stop(chip, &chip->azx_dev[i]);
1352
1353                 /* disable interrupts */
1354                 azx_int_disable(chip);
1355                 azx_int_clear(chip);
1356
1357                 /* disable CORB/RIRB */
1358                 azx_free_cmd_io(chip);
1359
1360                 /* disable position buffer */
1361                 azx_writel(chip, DPLBASE, 0);
1362                 azx_writel(chip, DPUBASE, 0);
1363
1364                 /* wait a little for interrupts to finish */
1365                 msleep(1);
1366         }
1367
1368         if (chip->remap_addr)
1369                 iounmap(chip->remap_addr);
1370         if (chip->irq >= 0)
1371                 free_irq(chip->irq, (void*)chip);
1372
1373         if (chip->bdl.area)
1374                 snd_dma_free_pages(&chip->bdl);
1375         if (chip->rb.area)
1376                 snd_dma_free_pages(&chip->rb);
1377         if (chip->posbuf.area)
1378                 snd_dma_free_pages(&chip->posbuf);
1379         pci_release_regions(chip->pci);
1380         pci_disable_device(chip->pci);
1381         kfree(chip->azx_dev);
1382         kfree(chip);
1383
1384         return 0;
1385 }
1386
1387 static int azx_dev_free(snd_device_t *device)
1388 {
1389         return azx_free(device->device_data);
1390 }
1391
1392 /*
1393  * constructor
1394  */
1395 static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci,
1396                                 int posfix, int driver_type,
1397                                 azx_t **rchip)
1398 {
1399         azx_t *chip;
1400         int err = 0;
1401         static snd_device_ops_t ops = {
1402                 .dev_free = azx_dev_free,
1403         };
1404
1405         *rchip = NULL;
1406
1407         if ((err = pci_enable_device(pci)) < 0)
1408                 return err;
1409
1410         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1411
1412         if (NULL == chip) {
1413                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1414                 pci_disable_device(pci);
1415                 return -ENOMEM;
1416         }
1417
1418         spin_lock_init(&chip->reg_lock);
1419         init_MUTEX(&chip->open_mutex);
1420         chip->card = card;
1421         chip->pci = pci;
1422         chip->irq = -1;
1423         chip->driver_type = driver_type;
1424
1425         chip->position_fix = posfix;
1426
1427 #if BITS_PER_LONG != 64
1428         /* Fix up base address on ULI M5461 */
1429         if (chip->driver_type == AZX_DRIVER_ULI) {
1430                 u16 tmp3;
1431                 pci_read_config_word(pci, 0x40, &tmp3);
1432                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1433                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1434         }
1435 #endif
1436
1437         if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1438                 kfree(chip);
1439                 pci_disable_device(pci);
1440                 return err;
1441         }
1442
1443         chip->addr = pci_resource_start(pci,0);
1444         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1445         if (chip->remap_addr == NULL) {
1446                 snd_printk(KERN_ERR SFX "ioremap error\n");
1447                 err = -ENXIO;
1448                 goto errout;
1449         }
1450
1451         if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1452                         "HDA Intel", (void*)chip)) {
1453                 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1454                 err = -EBUSY;
1455                 goto errout;
1456         }
1457         chip->irq = pci->irq;
1458
1459         pci_set_master(pci);
1460         synchronize_irq(chip->irq);
1461
1462         switch (chip->driver_type) {
1463         case AZX_DRIVER_ULI:
1464                 chip->playback_streams = ULI_NUM_PLAYBACK;
1465                 chip->capture_streams = ULI_NUM_CAPTURE;
1466                 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1467                 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1468                 break;
1469         default:
1470                 chip->playback_streams = ICH6_NUM_PLAYBACK;
1471                 chip->capture_streams = ICH6_NUM_CAPTURE;
1472                 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1473                 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1474                 break;
1475         }
1476         chip->num_streams = chip->playback_streams + chip->capture_streams;
1477         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL);
1478         if (! chip->azx_dev) {
1479                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1480                 goto errout;
1481         }
1482
1483         /* allocate memory for the BDL for each stream */
1484         if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1485                                        BDL_SIZE, &chip->bdl)) < 0) {
1486                 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1487                 goto errout;
1488         }
1489         /* allocate memory for the position buffer */
1490         if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1491                                        chip->num_streams * 8, &chip->posbuf)) < 0) {
1492                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1493                 goto errout;
1494         }
1495         /* allocate CORB/RIRB */
1496         if ((err = azx_alloc_cmd_io(chip)) < 0)
1497                 goto errout;
1498
1499         /* initialize streams */
1500         azx_init_stream(chip);
1501
1502         /* initialize chip */
1503         azx_init_chip(chip);
1504
1505         chip->initialized = 1;
1506
1507         /* codec detection */
1508         if (! chip->codec_mask) {
1509                 snd_printk(KERN_ERR SFX "no codecs found!\n");
1510                 err = -ENODEV;
1511                 goto errout;
1512         }
1513
1514         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1515                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1516                 goto errout;
1517         }
1518
1519         strcpy(card->driver, "HDA-Intel");
1520         strcpy(card->shortname, driver_short_names[chip->driver_type]);
1521         sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1522
1523         *rchip = chip;
1524         return 0;
1525
1526  errout:
1527         azx_free(chip);
1528         return err;
1529 }
1530
1531 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1532 {
1533         static int dev;
1534         snd_card_t *card;
1535         azx_t *chip;
1536         int err = 0;
1537
1538         if (dev >= SNDRV_CARDS)
1539                 return -ENODEV;
1540         if (! enable[dev]) {
1541                 dev++;
1542                 return -ENOENT;
1543         }
1544
1545         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1546         if (NULL == card) {
1547                 snd_printk(KERN_ERR SFX "Error creating card!\n");
1548                 return -ENOMEM;
1549         }
1550
1551         if ((err = azx_create(card, pci, position_fix[dev], pci_id->driver_data,
1552                               &chip)) < 0) {
1553                 snd_card_free(card);
1554                 return err;
1555         }
1556
1557         /* create codec instances */
1558         if ((err = azx_codec_create(chip, model[dev])) < 0) {
1559                 snd_card_free(card);
1560                 return err;
1561         }
1562
1563         /* create PCM streams */
1564         if ((err = azx_pcm_create(chip)) < 0) {
1565                 snd_card_free(card);
1566                 return err;
1567         }
1568
1569         /* create mixer controls */
1570         if ((err = azx_mixer_create(chip)) < 0) {
1571                 snd_card_free(card);
1572                 return err;
1573         }
1574
1575         snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
1576         snd_card_set_dev(card, &pci->dev);
1577
1578         if ((err = snd_card_register(card)) < 0) {
1579                 snd_card_free(card);
1580                 return err;
1581         }
1582
1583         pci_set_drvdata(pci, card);
1584         dev++;
1585
1586         return err;
1587 }
1588
1589 static void __devexit azx_remove(struct pci_dev *pci)
1590 {
1591         snd_card_free(pci_get_drvdata(pci));
1592         pci_set_drvdata(pci, NULL);
1593 }
1594
1595 /* PCI IDs */
1596 static struct pci_device_id azx_ids[] = {
1597         { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1598         { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1599         { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1600         { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1601         { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1602         { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1603         { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1604         { 0, }
1605 };
1606 MODULE_DEVICE_TABLE(pci, azx_ids);
1607
1608 /* pci_driver definition */
1609 static struct pci_driver driver = {
1610         .name = "HDA Intel",
1611         .owner = THIS_MODULE,
1612         .id_table = azx_ids,
1613         .probe = azx_probe,
1614         .remove = __devexit_p(azx_remove),
1615         SND_PCI_PM_CALLBACKS
1616 };
1617
1618 static int __init alsa_card_azx_init(void)
1619 {
1620         return pci_register_driver(&driver);
1621 }
1622
1623 static void __exit alsa_card_azx_exit(void)
1624 {
1625         pci_unregister_driver(&driver);
1626 }
1627
1628 module_init(alsa_card_azx_init)
1629 module_exit(alsa_card_azx_exit)