git.oblomov.eu Git - linux-2.6/blob - drivers/net/typhoon.c

   1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
   2 /*
   3         Written 2002-2004 by David Dillow <dave@thedillows.org>
   4         Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
   5         Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
   6
   7         This software may be used and distributed according to the terms of
   8         the GNU General Public License (GPL), incorporated herein by reference.
   9         Drivers based on or derived from this code fall under the GPL and must
  10         retain the authorship, copyright and license notice.  This file is not
  11         a complete program and may only be used when the entire operating
  12         system is licensed under the GPL.
  13
  14         This software is available on a public web site. It may enable
  15         cryptographic capabilities of the 3Com hardware, and may be
  16         exported from the United States under License Exception "TSU"
  17         pursuant to 15 C.F.R. Section 740.13(e).
  18
  19         This work was funded by the National Library of Medicine under
  20         the Department of Energy project number 0274DD06D1 and NLM project
  21         number Y1-LM-2015-01.
  22
  23         This driver is designed for the 3Com 3CR990 Family of cards with the
  24         3XP Processor. It has been tested on x86 and sparc64.
  25
  26         KNOWN ISSUES:
  27         *) The current firmware always strips the VLAN tag off, even if
  28                 we tell it not to. You should filter VLANs at the switch
  29                 as a workaround (good practice in any event) until we can
  30                 get this fixed.
  31         *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
  32                 issue. Hopefully 3Com will fix it.
  33         *) Waiting for a command response takes 8ms due to non-preemptable
  34                 polling. Only significant for getting stats and creating
  35                 SAs, but an ugly wart never the less.
  36
  37         TODO:
  38         *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
  39         *) Add more support for ethtool (especially for NIC stats)
  40         *) Allow disabling of RX checksum offloading
  41         *) Fix MAC changing to work while the interface is up
  42                 (Need to put commands on the TX ring, which changes
  43                 the locking)
  44         *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
  45                 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
  46 */
  47
  48 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  49  * Setting to > 1518 effectively disables this feature.
  50  */
  51 static int rx_copybreak = 200;
  52
  53 /* Should we use MMIO or Port IO?
  54  * 0: Port IO
  55  * 1: MMIO
  56  * 2: Try MMIO, fallback to Port IO
  57  */
  58 static unsigned int use_mmio = 2;
  59
  60 /* end user-configurable values */
  61
  62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  63  */
  64 static const int multicast_filter_limit = 32;
  65
  66 /* Operational parameters that are set at compile time. */
  67
  68 /* Keep the ring sizes a power of two for compile efficiency.
  69  * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  70  * Making the Tx ring too large decreases the effectiveness of channel
  71  * bonding and packet priority.
  72  * There are no ill effects from too-large receive rings.
  73  *
  74  * We don't currently use the Hi Tx ring so, don't make it very big.
  75  *
  76  * Beware that if we start using the Hi Tx ring, we will need to change
  77  * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
  78  */
  79 #define TXHI_ENTRIES            2
  80 #define TXLO_ENTRIES            128
  81 #define RX_ENTRIES              32
  82 #define COMMAND_ENTRIES         16
  83 #define RESPONSE_ENTRIES        32
  84
  85 #define COMMAND_RING_SIZE       (COMMAND_ENTRIES * sizeof(struct cmd_desc))
  86 #define RESPONSE_RING_SIZE      (RESPONSE_ENTRIES * sizeof(struct resp_desc))
  87
  88 /* The 3XP will preload and remove 64 entries from the free buffer
  89  * list, and we need one entry to keep the ring from wrapping, so
  90  * to keep this a power of two, we use 128 entries.
  91  */
  92 #define RXFREE_ENTRIES          128
  93 #define RXENT_ENTRIES           (RXFREE_ENTRIES - 1)
  94
  95 /* Operational parameters that usually are not changed. */
  96
  97 /* Time in jiffies before concluding the transmitter is hung. */
  98 #define TX_TIMEOUT  (2*HZ)
  99
 100 #define PKT_BUF_SZ              1536
 101
 102 #define DRV_MODULE_NAME         "typhoon"
 103 #define DRV_MODULE_VERSION      "1.5.8"
 104 #define DRV_MODULE_RELDATE      "06/11/09"
 105 #define PFX                     DRV_MODULE_NAME ": "
 106 #define ERR_PFX                 KERN_ERR PFX
 107
 108 #include <linux/module.h>
 109 #include <linux/kernel.h>
 110 #include <linux/string.h>
 111 #include <linux/timer.h>
 112 #include <linux/errno.h>
 113 #include <linux/ioport.h>
 114 #include <linux/slab.h>
 115 #include <linux/interrupt.h>
 116 #include <linux/pci.h>
 117 #include <linux/netdevice.h>
 118 #include <linux/etherdevice.h>
 119 #include <linux/skbuff.h>
 120 #include <linux/init.h>
 121 #include <linux/delay.h>
 122 #include <linux/ethtool.h>
 123 #include <linux/if_vlan.h>
 124 #include <linux/crc32.h>
 125 #include <linux/bitops.h>
 126 #include <asm/processor.h>
 127 #include <asm/io.h>
 128 #include <asm/uaccess.h>
 129 #include <linux/in6.h>
 130 #include <linux/version.h>
 131 #include <linux/dma-mapping.h>
 132
 133 #include "typhoon.h"
 134 #include "typhoon-firmware.h"
 135
 136 static const char version[] __devinitdata =
 137     "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 138
 139 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
 140 MODULE_VERSION(DRV_MODULE_VERSION);
 141 MODULE_LICENSE("GPL");
 142 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
 143 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
 144                                "the buffer given back to the NIC. Default "
 145                                "is 200.");
 146 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
 147                            "Default is to try MMIO and fallback to PIO.");
 148 module_param(rx_copybreak, int, 0);
 149 module_param(use_mmio, int, 0);
 150
 151 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
 152 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
 153 #undef NETIF_F_TSO
 154 #endif
 155
 156 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
 157 #error TX ring too small!
 158 #endif
 159
 160 struct typhoon_card_info {
 161         char *name;
 162         int capabilities;
 163 };
 164
 165 #define TYPHOON_CRYPTO_NONE             0x00
 166 #define TYPHOON_CRYPTO_DES              0x01
 167 #define TYPHOON_CRYPTO_3DES             0x02
 168 #define TYPHOON_CRYPTO_VARIABLE         0x04
 169 #define TYPHOON_FIBER                   0x08
 170 #define TYPHOON_WAKEUP_NEEDS_RESET      0x10
 171
 172 enum typhoon_cards {
 173         TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
 174         TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
 175         TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
 176         TYPHOON_FXM,
 177 };
 178
 179 /* directly indexed by enum typhoon_cards, above */
 180 static const struct typhoon_card_info typhoon_card_info[] __devinitdata = {
 181         { "3Com Typhoon (3C990-TX)",
 182                 TYPHOON_CRYPTO_NONE},
 183         { "3Com Typhoon (3CR990-TX-95)",
 184                 TYPHOON_CRYPTO_DES},
 185         { "3Com Typhoon (3CR990-TX-97)",
 186                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 187         { "3Com Typhoon (3C990SVR)",
 188                 TYPHOON_CRYPTO_NONE},
 189         { "3Com Typhoon (3CR990SVR95)",
 190                 TYPHOON_CRYPTO_DES},
 191         { "3Com Typhoon (3CR990SVR97)",
 192                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 193         { "3Com Typhoon2 (3C990B-TX-M)",
 194                 TYPHOON_CRYPTO_VARIABLE},
 195         { "3Com Typhoon2 (3C990BSVR)",
 196                 TYPHOON_CRYPTO_VARIABLE},
 197         { "3Com Typhoon (3CR990-FX-95)",
 198                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 199         { "3Com Typhoon (3CR990-FX-97)",
 200                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 201         { "3Com Typhoon (3CR990-FX-95 Server)",
 202                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 203         { "3Com Typhoon (3CR990-FX-97 Server)",
 204                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 205         { "3Com Typhoon2 (3C990B-FX-97)",
 206                 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
 207 };
 208
 209 /* Notes on the new subsystem numbering scheme:
 210  * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
 211  * bit 4 indicates if this card has secured firmware (we don't support it)
 212  * bit 8 indicates if this is a (0) copper or (1) fiber card
 213  * bits 12-16 indicate card type: (0) client and (1) server
 214  */
 215 static struct pci_device_id typhoon_pci_tbl[] = {
 216         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
 217           PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
 218         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
 219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
 220         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
 221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
 222         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 223           PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
 224         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 225           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
 226         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 227           PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
 228         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 229           PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
 230         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 231           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
 232         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 233           PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
 234         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 235           PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
 236         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
 237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
 238         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
 239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
 240         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
 241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
 242         { 0, }
 243 };
 244 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
 245
 246 /* Define the shared memory area
 247  * Align everything the 3XP will normally be using.
 248  * We'll need to move/align txHi if we start using that ring.
 249  */
 250 #define __3xp_aligned   ____cacheline_aligned
 251 struct typhoon_shared {
 252         struct typhoon_interface        iface;
 253         struct typhoon_indexes          indexes                 __3xp_aligned;
 254         struct tx_desc                  txLo[TXLO_ENTRIES]      __3xp_aligned;
 255         struct rx_desc                  rxLo[RX_ENTRIES]        __3xp_aligned;
 256         struct rx_desc                  rxHi[RX_ENTRIES]        __3xp_aligned;
 257         struct cmd_desc                 cmd[COMMAND_ENTRIES]    __3xp_aligned;
 258         struct resp_desc                resp[RESPONSE_ENTRIES]  __3xp_aligned;
 259         struct rx_free                  rxBuff[RXFREE_ENTRIES]  __3xp_aligned;
 260         u32                             zeroWord;
 261         struct tx_desc                  txHi[TXHI_ENTRIES];
 262 } __attribute__ ((packed));
 263
 264 struct rxbuff_ent {
 265         struct sk_buff *skb;
 266         dma_addr_t      dma_addr;
 267 };
 268
 269 struct typhoon {
 270         /* Tx cache line section */
 271         struct transmit_ring    txLoRing        ____cacheline_aligned;
 272         struct pci_dev *        tx_pdev;
 273         void __iomem            *tx_ioaddr;
 274         u32                     txlo_dma_addr;
 275
 276         /* Irq/Rx cache line section */
 277         void __iomem            *ioaddr         ____cacheline_aligned;
 278         struct typhoon_indexes *indexes;
 279         u8                      awaiting_resp;
 280         u8                      duplex;
 281         u8                      speed;
 282         u8                      card_state;
 283         struct basic_ring       rxLoRing;
 284         struct pci_dev *        pdev;
 285         struct net_device *     dev;
 286         spinlock_t              state_lock;
 287         struct vlan_group *     vlgrp;
 288         struct basic_ring       rxHiRing;
 289         struct basic_ring       rxBuffRing;
 290         struct rxbuff_ent       rxbuffers[RXENT_ENTRIES];
 291
 292         /* general section */
 293         spinlock_t              command_lock    ____cacheline_aligned;
 294         struct basic_ring       cmdRing;
 295         struct basic_ring       respRing;
 296         struct net_device_stats stats;
 297         struct net_device_stats stats_saved;
 298         const char *            name;
 299         struct typhoon_shared * shared;
 300         dma_addr_t              shared_dma;
 301         u16                     xcvr_select;
 302         u16                     wol_events;
 303         u32                     offload;
 304
 305         /* unused stuff (future use) */
 306         int                     capabilities;
 307         struct transmit_ring    txHiRing;
 308 };
 309
 310 enum completion_wait_values {
 311         NoWait = 0, WaitNoSleep, WaitSleep,
 312 };
 313
 314 /* These are the values for the typhoon.card_state variable.
 315  * These determine where the statistics will come from in get_stats().
 316  * The sleep image does not support the statistics we need.
 317  */
 318 enum state_values {
 319         Sleeping = 0, Running,
 320 };
 321
 322 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
 323  * cannot pass a read, so this forces current writes to post.
 324  */
 325 #define typhoon_post_pci_writes(x) \
 326         do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
 327
 328 /* We'll wait up to six seconds for a reset, and half a second normally.
 329  */
 330 #define TYPHOON_UDELAY                  50
 331 #define TYPHOON_RESET_TIMEOUT_SLEEP     (6 * HZ)
 332 #define TYPHOON_RESET_TIMEOUT_NOSLEEP   ((6 * 1000000) / TYPHOON_UDELAY)
 333 #define TYPHOON_WAIT_TIMEOUT            ((1000000 / 2) / TYPHOON_UDELAY)
 334
 335 #define typhoon_synchronize_irq(x) synchronize_irq(x)
 336
 337 #if defined(NETIF_F_TSO)
 338 #define skb_tso_size(x)         (skb_shinfo(x)->gso_size)
 339 #define TSO_NUM_DESCRIPTORS     2
 340 #define TSO_OFFLOAD_ON          TYPHOON_OFFLOAD_TCP_SEGMENT
 341 #else
 342 #define NETIF_F_TSO             0
 343 #define skb_tso_size(x)         0
 344 #define TSO_NUM_DESCRIPTORS     0
 345 #define TSO_OFFLOAD_ON          0
 346 #endif
 347
 348 static inline void
 349 typhoon_inc_index(u32 *index, const int count, const int num_entries)
 350 {
 351         /* Increment a ring index -- we can use this for all rings execept
 352          * the Rx rings, as they use different size descriptors
 353          * otherwise, everything is the same size as a cmd_desc
 354          */
 355         *index += count * sizeof(struct cmd_desc);
 356         *index %= num_entries * sizeof(struct cmd_desc);
 357 }
 358
 359 static inline void
 360 typhoon_inc_cmd_index(u32 *index, const int count)
 361 {
 362         typhoon_inc_index(index, count, COMMAND_ENTRIES);
 363 }
 364
 365 static inline void
 366 typhoon_inc_resp_index(u32 *index, const int count)
 367 {
 368         typhoon_inc_index(index, count, RESPONSE_ENTRIES);
 369 }
 370
 371 static inline void
 372 typhoon_inc_rxfree_index(u32 *index, const int count)
 373 {
 374         typhoon_inc_index(index, count, RXFREE_ENTRIES);
 375 }
 376
 377 static inline void
 378 typhoon_inc_tx_index(u32 *index, const int count)
 379 {
 380         /* if we start using the Hi Tx ring, this needs updateing */
 381         typhoon_inc_index(index, count, TXLO_ENTRIES);
 382 }
 383
 384 static inline void
 385 typhoon_inc_rx_index(u32 *index, const int count)
 386 {
 387         /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
 388         *index += count * sizeof(struct rx_desc);
 389         *index %= RX_ENTRIES * sizeof(struct rx_desc);
 390 }
 391
 392 static int
 393 typhoon_reset(void __iomem *ioaddr, int wait_type)
 394 {
 395         int i, err = 0;
 396         int timeout;
 397
 398         if(wait_type == WaitNoSleep)
 399                 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
 400         else
 401                 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
 402
 403         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 404         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 405
 406         iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
 407         typhoon_post_pci_writes(ioaddr);
 408         udelay(1);
 409         iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
 410
 411         if(wait_type != NoWait) {
 412                 for(i = 0; i < timeout; i++) {
 413                         if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
 414                            TYPHOON_STATUS_WAITING_FOR_HOST)
 415                                 goto out;
 416
 417                         if(wait_type == WaitSleep)
 418                                 schedule_timeout_uninterruptible(1);
 419                         else
 420                                 udelay(TYPHOON_UDELAY);
 421                 }
 422
 423                 err = -ETIMEDOUT;
 424         }
 425
 426 out:
 427         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 428         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 429
 430         /* The 3XP seems to need a little extra time to complete the load
 431          * of the sleep image before we can reliably boot it. Failure to
 432          * do this occasionally results in a hung adapter after boot in
 433          * typhoon_init_one() while trying to read the MAC address or
 434          * putting the card to sleep. 3Com's driver waits 5ms, but
 435          * that seems to be overkill. However, if we can sleep, we might
 436          * as well give it that much time. Otherwise, we'll give it 500us,
 437          * which should be enough (I've see it work well at 100us, but still
 438          * saw occasional problems.)
 439          */
 440         if(wait_type == WaitSleep)
 441                 msleep(5);
 442         else
 443                 udelay(500);
 444         return err;
 445 }
 446
 447 static int
 448 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
 449 {
 450         int i, err = 0;
 451
 452         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
 453                 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
 454                         goto out;
 455                 udelay(TYPHOON_UDELAY);
 456         }
 457
 458         err = -ETIMEDOUT;
 459
 460 out:
 461         return err;
 462 }
 463
 464 static inline void
 465 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
 466 {
 467         if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
 468                 netif_carrier_off(dev);
 469         else
 470                 netif_carrier_on(dev);
 471 }
 472
 473 static inline void
 474 typhoon_hello(struct typhoon *tp)
 475 {
 476         struct basic_ring *ring = &tp->cmdRing;
 477         struct cmd_desc *cmd;
 478
 479         /* We only get a hello request if we've not sent anything to the
 480          * card in a long while. If the lock is held, then we're in the
 481          * process of issuing a command, so we don't need to respond.
 482          */
 483         if(spin_trylock(&tp->command_lock)) {
 484                 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
 485                 typhoon_inc_cmd_index(&ring->lastWrite, 1);
 486
 487                 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
 488                 smp_wmb();
 489                 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 490                 spin_unlock(&tp->command_lock);
 491         }
 492 }
 493
 494 static int
 495 typhoon_process_response(struct typhoon *tp, int resp_size,
 496                                 struct resp_desc *resp_save)
 497 {
 498         struct typhoon_indexes *indexes = tp->indexes;
 499         struct resp_desc *resp;
 500         u8 *base = tp->respRing.ringBase;
 501         int count, len, wrap_len;
 502         u32 cleared;
 503         u32 ready;
 504
 505         cleared = le32_to_cpu(indexes->respCleared);
 506         ready = le32_to_cpu(indexes->respReady);
 507         while(cleared != ready) {
 508                 resp = (struct resp_desc *)(base + cleared);
 509                 count = resp->numDesc + 1;
 510                 if(resp_save && resp->seqNo) {
 511                         if(count > resp_size) {
 512                                 resp_save->flags = TYPHOON_RESP_ERROR;
 513                                 goto cleanup;
 514                         }
 515
 516                         wrap_len = 0;
 517                         len = count * sizeof(*resp);
 518                         if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
 519                                 wrap_len = cleared + len - RESPONSE_RING_SIZE;
 520                                 len = RESPONSE_RING_SIZE - cleared;
 521                         }
 522
 523                         memcpy(resp_save, resp, len);
 524                         if(unlikely(wrap_len)) {
 525                                 resp_save += len / sizeof(*resp);
 526                                 memcpy(resp_save, base, wrap_len);
 527                         }
 528
 529                         resp_save = NULL;
 530                 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
 531                         typhoon_media_status(tp->dev, resp);
 532                 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
 533                         typhoon_hello(tp);
 534                 } else {
 535                         printk(KERN_ERR "%s: dumping unexpected response "
 536                                "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
 537                                tp->name, le16_to_cpu(resp->cmd),
 538                                resp->numDesc, resp->flags,
 539                                le16_to_cpu(resp->parm1),
 540                                le32_to_cpu(resp->parm2),
 541                                le32_to_cpu(resp->parm3));
 542                 }
 543
 544 cleanup:
 545                 typhoon_inc_resp_index(&cleared, count);
 546         }
 547
 548         indexes->respCleared = cpu_to_le32(cleared);
 549         wmb();
 550         return (resp_save == NULL);
 551 }
 552
 553 static inline int
 554 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
 555 {
 556         /* this works for all descriptors but rx_desc, as they are a
 557          * different size than the cmd_desc -- everyone else is the same
 558          */
 559         lastWrite /= sizeof(struct cmd_desc);
 560         lastRead /= sizeof(struct cmd_desc);
 561         return (ringSize + lastRead - lastWrite - 1) % ringSize;
 562 }
 563
 564 static inline int
 565 typhoon_num_free_cmd(struct typhoon *tp)
 566 {
 567         int lastWrite = tp->cmdRing.lastWrite;
 568         int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
 569
 570         return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
 571 }
 572
 573 static inline int
 574 typhoon_num_free_resp(struct typhoon *tp)
 575 {
 576         int respReady = le32_to_cpu(tp->indexes->respReady);
 577         int respCleared = le32_to_cpu(tp->indexes->respCleared);
 578
 579         return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
 580 }
 581
 582 static inline int
 583 typhoon_num_free_tx(struct transmit_ring *ring)
 584 {
 585         /* if we start using the Hi Tx ring, this needs updating */
 586         return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
 587 }
 588
 589 static int
 590 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
 591                       int num_resp, struct resp_desc *resp)
 592 {
 593         struct typhoon_indexes *indexes = tp->indexes;
 594         struct basic_ring *ring = &tp->cmdRing;
 595         struct resp_desc local_resp;
 596         int i, err = 0;
 597         int got_resp;
 598         int freeCmd, freeResp;
 599         int len, wrap_len;
 600
 601         spin_lock(&tp->command_lock);
 602
 603         freeCmd = typhoon_num_free_cmd(tp);
 604         freeResp = typhoon_num_free_resp(tp);
 605
 606         if(freeCmd < num_cmd || freeResp < num_resp) {
 607                 printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
 608                         "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
 609                         freeResp, num_resp);
 610                 err = -ENOMEM;
 611                 goto out;
 612         }
 613
 614         if(cmd->flags & TYPHOON_CMD_RESPOND) {
 615                 /* If we're expecting a response, but the caller hasn't given
 616                  * us a place to put it, we'll provide one.
 617                  */
 618                 tp->awaiting_resp = 1;
 619                 if(resp == NULL) {
 620                         resp = &local_resp;
 621                         num_resp = 1;
 622                 }
 623         }
 624
 625         wrap_len = 0;
 626         len = num_cmd * sizeof(*cmd);
 627         if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
 628                 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
 629                 len = COMMAND_RING_SIZE - ring->lastWrite;
 630         }
 631
 632         memcpy(ring->ringBase + ring->lastWrite, cmd, len);
 633         if(unlikely(wrap_len)) {
 634                 struct cmd_desc *wrap_ptr = cmd;
 635                 wrap_ptr += len / sizeof(*cmd);
 636                 memcpy(ring->ringBase, wrap_ptr, wrap_len);
 637         }
 638
 639         typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
 640
 641         /* "I feel a presence... another warrior is on the the mesa."
 642          */
 643         wmb();
 644         iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 645         typhoon_post_pci_writes(tp->ioaddr);
 646
 647         if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
 648                 goto out;
 649
 650         /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
 651          * preempt or do anything other than take interrupts. So, don't
 652          * wait for a response unless you have to.
 653          *
 654          * I've thought about trying to sleep here, but we're called
 655          * from many contexts that don't allow that. Also, given the way
 656          * 3Com has implemented irq coalescing, we would likely timeout --
 657          * this has been observed in real life!
 658          *
 659          * The big killer is we have to wait to get stats from the card,
 660          * though we could go to a periodic refresh of those if we don't
 661          * mind them getting somewhat stale. The rest of the waiting
 662          * commands occur during open/close/suspend/resume, so they aren't
 663          * time critical. Creating SAs in the future will also have to
 664          * wait here.
 665          */
 666         got_resp = 0;
 667         for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
 668                 if(indexes->respCleared != indexes->respReady)
 669                         got_resp = typhoon_process_response(tp, num_resp,
 670                                                                 resp);
 671                 udelay(TYPHOON_UDELAY);
 672         }
 673
 674         if(!got_resp) {
 675                 err = -ETIMEDOUT;
 676                 goto out;
 677         }
 678
 679         /* Collect the error response even if we don't care about the
 680          * rest of the response
 681          */
 682         if(resp->flags & TYPHOON_RESP_ERROR)
 683                 err = -EIO;
 684
 685 out:
 686         if(tp->awaiting_resp) {
 687                 tp->awaiting_resp = 0;
 688                 smp_wmb();
 689
 690                 /* Ugh. If a response was added to the ring between
 691                  * the call to typhoon_process_response() and the clearing
 692                  * of tp->awaiting_resp, we could have missed the interrupt
 693                  * and it could hang in the ring an indeterminate amount of
 694                  * time. So, check for it, and interrupt ourselves if this
 695                  * is the case.
 696                  */
 697                 if(indexes->respCleared != indexes->respReady)
 698                         iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
 699         }
 700
 701         spin_unlock(&tp->command_lock);
 702         return err;
 703 }
 704
 705 static void
 706 typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
 707 {
 708         struct typhoon *tp = netdev_priv(dev);
 709         struct cmd_desc xp_cmd;
 710         int err;
 711
 712         spin_lock_bh(&tp->state_lock);
 713         if(!tp->vlgrp != !grp) {
 714                 /* We've either been turned on for the first time, or we've
 715                  * been turned off. Update the 3XP.
 716                  */
 717                 if(grp)
 718                         tp->offload |= TYPHOON_OFFLOAD_VLAN;
 719                 else
 720                         tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
 721
 722                 /* If the interface is up, the runtime is running -- and we
 723                  * must be up for the vlan core to call us.
 724                  *
 725                  * Do the command outside of the spin lock, as it is slow.
 726                  */
 727                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
 728                                         TYPHOON_CMD_SET_OFFLOAD_TASKS);
 729                 xp_cmd.parm2 = tp->offload;
 730                 xp_cmd.parm3 = tp->offload;
 731                 spin_unlock_bh(&tp->state_lock);
 732                 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 733                 if(err < 0)
 734                         printk("%s: vlan offload error %d\n", tp->name, -err);
 735                 spin_lock_bh(&tp->state_lock);
 736         }
 737
 738         /* now make the change visible */
 739         tp->vlgrp = grp;
 740         spin_unlock_bh(&tp->state_lock);
 741 }
 742
 743 static void
 744 typhoon_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 745 {
 746         struct typhoon *tp = netdev_priv(dev);
 747         spin_lock_bh(&tp->state_lock);
 748         if(tp->vlgrp)
 749                 tp->vlgrp->vlan_devices[vid] = NULL;
 750         spin_unlock_bh(&tp->state_lock);
 751 }
 752
 753 static inline void
 754 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
 755                         u32 ring_dma)
 756 {
 757         struct tcpopt_desc *tcpd;
 758         u32 tcpd_offset = ring_dma;
 759
 760         tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
 761         tcpd_offset += txRing->lastWrite;
 762         tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
 763         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 764
 765         tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
 766         tcpd->numDesc = 1;
 767         tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
 768         tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
 769         tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
 770         tcpd->bytesTx = cpu_to_le32(skb->len);
 771         tcpd->status = 0;
 772 }
 773
 774 static int
 775 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
 776 {
 777         struct typhoon *tp = netdev_priv(dev);
 778         struct transmit_ring *txRing;
 779         struct tx_desc *txd, *first_txd;
 780         dma_addr_t skb_dma;
 781         int numDesc;
 782
 783         /* we have two rings to choose from, but we only use txLo for now
 784          * If we start using the Hi ring as well, we'll need to update
 785          * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
 786          * and TXHI_ENTRIES to match, as well as update the TSO code below
 787          * to get the right DMA address
 788          */
 789         txRing = &tp->txLoRing;
 790
 791         /* We need one descriptor for each fragment of the sk_buff, plus the
 792          * one for the ->data area of it.
 793          *
 794          * The docs say a maximum of 16 fragment descriptors per TCP option
 795          * descriptor, then make a new packet descriptor and option descriptor
 796          * for the next 16 fragments. The engineers say just an option
 797          * descriptor is needed. I've tested up to 26 fragments with a single
 798          * packet descriptor/option descriptor combo, so I use that for now.
 799          *
 800          * If problems develop with TSO, check this first.
 801          */
 802         numDesc = skb_shinfo(skb)->nr_frags + 1;
 803         if (skb_is_gso(skb))
 804                 numDesc++;
 805
 806         /* When checking for free space in the ring, we need to also
 807          * account for the initial Tx descriptor, and we always must leave
 808          * at least one descriptor unused in the ring so that it doesn't
 809          * wrap and look empty.
 810          *
 811          * The only time we should loop here is when we hit the race
 812          * between marking the queue awake and updating the cleared index.
 813          * Just loop and it will appear. This comes from the acenic driver.
 814          */
 815         while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
 816                 smp_rmb();
 817
 818         first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 819         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 820
 821         first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
 822         first_txd->numDesc = 0;
 823         first_txd->len = 0;
 824         first_txd->addr = (u64)((unsigned long) skb) & 0xffffffff;
 825         first_txd->addrHi = (u64)((unsigned long) skb) >> 32;
 826         first_txd->processFlags = 0;
 827
 828         if(skb->ip_summed == CHECKSUM_PARTIAL) {
 829                 /* The 3XP will figure out if this is UDP/TCP */
 830                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
 831                 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
 832                 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
 833         }
 834
 835         if(vlan_tx_tag_present(skb)) {
 836                 first_txd->processFlags |=
 837                     TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
 838                 first_txd->processFlags |=
 839                     cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
 840                                 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
 841         }
 842
 843         if (skb_is_gso(skb)) {
 844                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
 845                 first_txd->numDesc++;
 846
 847                 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
 848         }
 849
 850         txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 851         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 852
 853         /* No need to worry about padding packet -- the firmware pads
 854          * it with zeros to ETH_ZLEN for us.
 855          */
 856         if(skb_shinfo(skb)->nr_frags == 0) {
 857                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
 858                                        PCI_DMA_TODEVICE);
 859                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 860                 txd->len = cpu_to_le16(skb->len);
 861                 txd->addr = cpu_to_le32(skb_dma);
 862                 txd->addrHi = 0;
 863                 first_txd->numDesc++;
 864         } else {
 865                 int i, len;
 866
 867                 len = skb_headlen(skb);
 868                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
 869                                          PCI_DMA_TODEVICE);
 870                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 871                 txd->len = cpu_to_le16(len);
 872                 txd->addr = cpu_to_le32(skb_dma);
 873                 txd->addrHi = 0;
 874                 first_txd->numDesc++;
 875
 876                 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 877                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 878                         void *frag_addr;
 879
 880                         txd = (struct tx_desc *) (txRing->ringBase +
 881                                                 txRing->lastWrite);
 882                         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 883
 884                         len = frag->size;
 885                         frag_addr = (void *) page_address(frag->page) +
 886                                                 frag->page_offset;
 887                         skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
 888                                          PCI_DMA_TODEVICE);
 889                         txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 890                         txd->len = cpu_to_le16(len);
 891                         txd->addr = cpu_to_le32(skb_dma);
 892                         txd->addrHi = 0;
 893                         first_txd->numDesc++;
 894                 }
 895         }
 896
 897         /* Kick the 3XP
 898          */
 899         wmb();
 900         iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
 901
 902         dev->trans_start = jiffies;
 903
 904         /* If we don't have room to put the worst case packet on the
 905          * queue, then we must stop the queue. We need 2 extra
 906          * descriptors -- one to prevent ring wrap, and one for the
 907          * Tx header.
 908          */
 909         numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
 910
 911         if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
 912                 netif_stop_queue(dev);
 913
 914                 /* A Tx complete IRQ could have gotten inbetween, making
 915                  * the ring free again. Only need to recheck here, since
 916                  * Tx is serialized.
 917                  */
 918                 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
 919                         netif_wake_queue(dev);
 920         }
 921
 922         return 0;
 923 }
 924
 925 static void
 926 typhoon_set_rx_mode(struct net_device *dev)
 927 {
 928         struct typhoon *tp = netdev_priv(dev);
 929         struct cmd_desc xp_cmd;
 930         u32 mc_filter[2];
 931         u16 filter;
 932
 933         filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
 934         if(dev->flags & IFF_PROMISC) {
 935                 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
 936         } else if((dev->mc_count > multicast_filter_limit) ||
 937                   (dev->flags & IFF_ALLMULTI)) {
 938                 /* Too many to match, or accept all multicasts. */
 939                 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
 940         } else if(dev->mc_count) {
 941                 struct dev_mc_list *mclist;
 942                 int i;
 943
 944                 memset(mc_filter, 0, sizeof(mc_filter));
 945                 for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
 946                     i++, mclist = mclist->next) {
 947                         int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
 948                         mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
 949                 }
 950
 951                 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
 952                                          TYPHOON_CMD_SET_MULTICAST_HASH);
 953                 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
 954                 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
 955                 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
 956                 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 957
 958                 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
 959         }
 960
 961         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
 962         xp_cmd.parm1 = filter;
 963         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 964 }
 965
 966 static int
 967 typhoon_do_get_stats(struct typhoon *tp)
 968 {
 969         struct net_device_stats *stats = &tp->stats;
 970         struct net_device_stats *saved = &tp->stats_saved;
 971         struct cmd_desc xp_cmd;
 972         struct resp_desc xp_resp[7];
 973         struct stats_resp *s = (struct stats_resp *) xp_resp;
 974         int err;
 975
 976         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
 977         err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
 978         if(err < 0)
 979                 return err;
 980
 981         /* 3Com's Linux driver uses txMultipleCollisions as it's
 982          * collisions value, but there is some other collision info as well...
 983          *
 984          * The extra status reported would be a good candidate for
 985          * ethtool_ops->get_{strings,stats}()
 986          */
 987         stats->tx_packets = le32_to_cpu(s->txPackets);
 988         stats->tx_bytes = le32_to_cpu(s->txBytes);
 989         stats->tx_errors = le32_to_cpu(s->txCarrierLost);
 990         stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
 991         stats->collisions = le32_to_cpu(s->txMultipleCollisions);
 992         stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
 993         stats->rx_bytes = le32_to_cpu(s->rxBytesGood);
 994         stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
 995         stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
 996                         le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
 997         stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
 998         stats->rx_length_errors = le32_to_cpu(s->rxOversized);
 999         tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
1000                         SPEED_100 : SPEED_10;
1001         tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
1002                         DUPLEX_FULL : DUPLEX_HALF;
1003
1004         /* add in the saved statistics
1005          */
1006         stats->tx_packets += saved->tx_packets;
1007         stats->tx_bytes += saved->tx_bytes;
1008         stats->tx_errors += saved->tx_errors;
1009         stats->collisions += saved->collisions;
1010         stats->rx_packets += saved->rx_packets;
1011         stats->rx_bytes += saved->rx_bytes;
1012         stats->rx_fifo_errors += saved->rx_fifo_errors;
1013         stats->rx_errors += saved->rx_errors;
1014         stats->rx_crc_errors += saved->rx_crc_errors;
1015         stats->rx_length_errors += saved->rx_length_errors;
1016
1017         return 0;
1018 }
1019
1020 static struct net_device_stats *
1021 typhoon_get_stats(struct net_device *dev)
1022 {
1023         struct typhoon *tp = netdev_priv(dev);
1024         struct net_device_stats *stats = &tp->stats;
1025         struct net_device_stats *saved = &tp->stats_saved;
1026
1027         smp_rmb();
1028         if(tp->card_state == Sleeping)
1029                 return saved;
1030
1031         if(typhoon_do_get_stats(tp) < 0) {
1032                 printk(KERN_ERR "%s: error getting stats\n", dev->name);
1033                 return saved;
1034         }
1035
1036         return stats;
1037 }
1038
1039 static int
1040 typhoon_set_mac_address(struct net_device *dev, void *addr)
1041 {
1042         struct sockaddr *saddr = (struct sockaddr *) addr;
1043
1044         if(netif_running(dev))
1045                 return -EBUSY;
1046
1047         memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
1048         return 0;
1049 }
1050
1051 static void
1052 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1053 {
1054         struct typhoon *tp = netdev_priv(dev);
1055         struct pci_dev *pci_dev = tp->pdev;
1056         struct cmd_desc xp_cmd;
1057         struct resp_desc xp_resp[3];
1058
1059         smp_rmb();
1060         if(tp->card_state == Sleeping) {
1061                 strcpy(info->fw_version, "Sleep image");
1062         } else {
1063                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
1064                 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
1065                         strcpy(info->fw_version, "Unknown runtime");
1066                 } else {
1067                         u32 sleep_ver = xp_resp[0].parm2;
1068                         snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1069                                  sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1070                                  sleep_ver & 0xfff);
1071                 }
1072         }
1073
1074         strcpy(info->driver, DRV_MODULE_NAME);
1075         strcpy(info->version, DRV_MODULE_VERSION);
1076         strcpy(info->bus_info, pci_name(pci_dev));
1077 }
1078
1079 static int
1080 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1081 {
1082         struct typhoon *tp = netdev_priv(dev);
1083
1084         cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1085                                 SUPPORTED_Autoneg;
1086
1087         switch (tp->xcvr_select) {
1088         case TYPHOON_XCVR_10HALF:
1089                 cmd->advertising = ADVERTISED_10baseT_Half;
1090                 break;
1091         case TYPHOON_XCVR_10FULL:
1092                 cmd->advertising = ADVERTISED_10baseT_Full;
1093                 break;
1094         case TYPHOON_XCVR_100HALF:
1095                 cmd->advertising = ADVERTISED_100baseT_Half;
1096                 break;
1097         case TYPHOON_XCVR_100FULL:
1098                 cmd->advertising = ADVERTISED_100baseT_Full;
1099                 break;
1100         case TYPHOON_XCVR_AUTONEG:
1101                 cmd->advertising = ADVERTISED_10baseT_Half |
1102                                             ADVERTISED_10baseT_Full |
1103                                             ADVERTISED_100baseT_Half |
1104                                             ADVERTISED_100baseT_Full |
1105                                             ADVERTISED_Autoneg;
1106                 break;
1107         }
1108
1109         if(tp->capabilities & TYPHOON_FIBER) {
1110                 cmd->supported |= SUPPORTED_FIBRE;
1111                 cmd->advertising |= ADVERTISED_FIBRE;
1112                 cmd->port = PORT_FIBRE;
1113         } else {
1114                 cmd->supported |= SUPPORTED_10baseT_Half |
1115                                         SUPPORTED_10baseT_Full |
1116                                         SUPPORTED_TP;
1117                 cmd->advertising |= ADVERTISED_TP;
1118                 cmd->port = PORT_TP;
1119         }
1120
1121         /* need to get stats to make these link speed/duplex valid */
1122         typhoon_do_get_stats(tp);
1123         cmd->speed = tp->speed;
1124         cmd->duplex = tp->duplex;
1125         cmd->phy_address = 0;
1126         cmd->transceiver = XCVR_INTERNAL;
1127         if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1128                 cmd->autoneg = AUTONEG_ENABLE;
1129         else
1130                 cmd->autoneg = AUTONEG_DISABLE;
1131         cmd->maxtxpkt = 1;
1132         cmd->maxrxpkt = 1;
1133
1134         return 0;
1135 }
1136
1137 static int
1138 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1139 {
1140         struct typhoon *tp = netdev_priv(dev);
1141         struct cmd_desc xp_cmd;
1142         int xcvr;
1143         int err;
1144
1145         err = -EINVAL;
1146         if(cmd->autoneg == AUTONEG_ENABLE) {
1147                 xcvr = TYPHOON_XCVR_AUTONEG;
1148         } else {
1149                 if(cmd->duplex == DUPLEX_HALF) {
1150                         if(cmd->speed == SPEED_10)
1151                                 xcvr = TYPHOON_XCVR_10HALF;
1152                         else if(cmd->speed == SPEED_100)
1153                                 xcvr = TYPHOON_XCVR_100HALF;
1154                         else
1155                                 goto out;
1156                 } else if(cmd->duplex == DUPLEX_FULL) {
1157                         if(cmd->speed == SPEED_10)
1158                                 xcvr = TYPHOON_XCVR_10FULL;
1159                         else if(cmd->speed == SPEED_100)
1160                                 xcvr = TYPHOON_XCVR_100FULL;
1161                         else
1162                                 goto out;
1163                 } else
1164                         goto out;
1165         }
1166
1167         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1168         xp_cmd.parm1 = cpu_to_le16(xcvr);
1169         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1170         if(err < 0)
1171                 goto out;
1172
1173         tp->xcvr_select = xcvr;
1174         if(cmd->autoneg == AUTONEG_ENABLE) {
1175                 tp->speed = 0xff;       /* invalid */
1176                 tp->duplex = 0xff;      /* invalid */
1177         } else {
1178                 tp->speed = cmd->speed;
1179                 tp->duplex = cmd->duplex;
1180         }
1181
1182 out:
1183         return err;
1184 }
1185
1186 static void
1187 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1188 {
1189         struct typhoon *tp = netdev_priv(dev);
1190
1191         wol->supported = WAKE_PHY | WAKE_MAGIC;
1192         wol->wolopts = 0;
1193         if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1194                 wol->wolopts |= WAKE_PHY;
1195         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1196                 wol->wolopts |= WAKE_MAGIC;
1197         memset(&wol->sopass, 0, sizeof(wol->sopass));
1198 }
1199
1200 static int
1201 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1202 {
1203         struct typhoon *tp = netdev_priv(dev);
1204
1205         if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1206                 return -EINVAL;
1207
1208         tp->wol_events = 0;
1209         if(wol->wolopts & WAKE_PHY)
1210                 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1211         if(wol->wolopts & WAKE_MAGIC)
1212                 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1213
1214         return 0;
1215 }
1216
1217 static u32
1218 typhoon_get_rx_csum(struct net_device *dev)
1219 {
1220         /* For now, we don't allow turning off RX checksums.
1221          */
1222         return 1;
1223 }
1224
1225 static void
1226 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1227 {
1228         ering->rx_max_pending = RXENT_ENTRIES;
1229         ering->rx_mini_max_pending = 0;
1230         ering->rx_jumbo_max_pending = 0;
1231         ering->tx_max_pending = TXLO_ENTRIES - 1;
1232
1233         ering->rx_pending = RXENT_ENTRIES;
1234         ering->rx_mini_pending = 0;
1235         ering->rx_jumbo_pending = 0;
1236         ering->tx_pending = TXLO_ENTRIES - 1;
1237 }
1238
1239 static const struct ethtool_ops typhoon_ethtool_ops = {
1240         .get_settings           = typhoon_get_settings,
1241         .set_settings           = typhoon_set_settings,
1242         .get_drvinfo            = typhoon_get_drvinfo,
1243         .get_wol                = typhoon_get_wol,
1244         .set_wol                = typhoon_set_wol,
1245         .get_link               = ethtool_op_get_link,
1246         .get_rx_csum            = typhoon_get_rx_csum,
1247         .get_tx_csum            = ethtool_op_get_tx_csum,
1248         .set_tx_csum            = ethtool_op_set_tx_csum,
1249         .get_sg                 = ethtool_op_get_sg,
1250         .set_sg                 = ethtool_op_set_sg,
1251         .get_tso                = ethtool_op_get_tso,
1252         .set_tso                = ethtool_op_set_tso,
1253         .get_ringparam          = typhoon_get_ringparam,
1254 };
1255
1256 static int
1257 typhoon_wait_interrupt(void __iomem *ioaddr)
1258 {
1259         int i, err = 0;
1260
1261         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1262                 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1263                    TYPHOON_INTR_BOOTCMD)
1264                         goto out;
1265                 udelay(TYPHOON_UDELAY);
1266         }
1267
1268         err = -ETIMEDOUT;
1269
1270 out:
1271         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1272         return err;
1273 }
1274
1275 #define shared_offset(x)        offsetof(struct typhoon_shared, x)
1276
1277 static void
1278 typhoon_init_interface(struct typhoon *tp)
1279 {
1280         struct typhoon_interface *iface = &tp->shared->iface;
1281         dma_addr_t shared_dma;
1282
1283         memset(tp->shared, 0, sizeof(struct typhoon_shared));
1284
1285         /* The *Hi members of iface are all init'd to zero by the memset().
1286          */
1287         shared_dma = tp->shared_dma + shared_offset(indexes);
1288         iface->ringIndex = cpu_to_le32(shared_dma);
1289
1290         shared_dma = tp->shared_dma + shared_offset(txLo);
1291         iface->txLoAddr = cpu_to_le32(shared_dma);
1292         iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1293
1294         shared_dma = tp->shared_dma + shared_offset(txHi);
1295         iface->txHiAddr = cpu_to_le32(shared_dma);
1296         iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1297
1298         shared_dma = tp->shared_dma + shared_offset(rxBuff);
1299         iface->rxBuffAddr = cpu_to_le32(shared_dma);
1300         iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1301                                         sizeof(struct rx_free));
1302
1303         shared_dma = tp->shared_dma + shared_offset(rxLo);
1304         iface->rxLoAddr = cpu_to_le32(shared_dma);
1305         iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1306
1307         shared_dma = tp->shared_dma + shared_offset(rxHi);
1308         iface->rxHiAddr = cpu_to_le32(shared_dma);
1309         iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1310
1311         shared_dma = tp->shared_dma + shared_offset(cmd);
1312         iface->cmdAddr = cpu_to_le32(shared_dma);
1313         iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1314
1315         shared_dma = tp->shared_dma + shared_offset(resp);
1316         iface->respAddr = cpu_to_le32(shared_dma);
1317         iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1318
1319         shared_dma = tp->shared_dma + shared_offset(zeroWord);
1320         iface->zeroAddr = cpu_to_le32(shared_dma);
1321
1322         tp->indexes = &tp->shared->indexes;
1323         tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1324         tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1325         tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1326         tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1327         tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1328         tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1329         tp->respRing.ringBase = (u8 *) tp->shared->resp;
1330
1331         tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1332         tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1333
1334         tp->txlo_dma_addr = iface->txLoAddr;
1335         tp->card_state = Sleeping;
1336         smp_wmb();
1337
1338         tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1339         tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1340
1341         spin_lock_init(&tp->command_lock);
1342         spin_lock_init(&tp->state_lock);
1343 }
1344
1345 static void
1346 typhoon_init_rings(struct typhoon *tp)
1347 {
1348         memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1349
1350         tp->txLoRing.lastWrite = 0;
1351         tp->txHiRing.lastWrite = 0;
1352         tp->rxLoRing.lastWrite = 0;
1353         tp->rxHiRing.lastWrite = 0;
1354         tp->rxBuffRing.lastWrite = 0;
1355         tp->cmdRing.lastWrite = 0;
1356         tp->cmdRing.lastWrite = 0;
1357
1358         tp->txLoRing.lastRead = 0;
1359         tp->txHiRing.lastRead = 0;
1360 }
1361
1362 static int
1363 typhoon_download_firmware(struct typhoon *tp)
1364 {
1365         void __iomem *ioaddr = tp->ioaddr;
1366         struct pci_dev *pdev = tp->pdev;
1367         struct typhoon_file_header *fHdr;
1368         struct typhoon_section_header *sHdr;
1369         u8 *image_data;
1370         void *dpage;
1371         dma_addr_t dpage_dma;
1372         unsigned int csum;
1373         u32 irqEnabled;
1374         u32 irqMasked;
1375         u32 numSections;
1376         u32 section_len;
1377         u32 len;
1378         u32 load_addr;
1379         u32 hmac;
1380         int i;
1381         int err;
1382
1383         err = -EINVAL;
1384         fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
1385         image_data = (u8 *) fHdr;
1386
1387         if(memcmp(fHdr->tag, "TYPHOON", 8)) {
1388                 printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
1389                 goto err_out;
1390         }
1391
1392         /* Cannot just map the firmware image using pci_map_single() as
1393          * the firmware is part of the kernel/module image, so we allocate
1394          * some consistent memory to copy the sections into, as it is simpler,
1395          * and short-lived. If we ever split out and require a userland
1396          * firmware loader, then we can revisit this.
1397          */
1398         err = -ENOMEM;
1399         dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1400         if(!dpage) {
1401                 printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
1402                 goto err_out;
1403         }
1404
1405         irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1406         iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1407                ioaddr + TYPHOON_REG_INTR_ENABLE);
1408         irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1409         iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1410                ioaddr + TYPHOON_REG_INTR_MASK);
1411
1412         err = -ETIMEDOUT;
1413         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1414                 printk(KERN_ERR "%s: card ready timeout\n", tp->name);
1415                 goto err_out_irq;
1416         }
1417
1418         numSections = le32_to_cpu(fHdr->numSections);
1419         load_addr = le32_to_cpu(fHdr->startAddr);
1420
1421         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1422         iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1423         hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1424         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1425         hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1426         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1427         hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1428         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1429         hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1430         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1431         hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1432         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1433         typhoon_post_pci_writes(ioaddr);
1434         iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1435
1436         image_data += sizeof(struct typhoon_file_header);
1437
1438         /* The ioread32() in typhoon_wait_interrupt() will force the
1439          * last write to the command register to post, so
1440          * we don't need a typhoon_post_pci_writes() after it.
1441          */
1442         for(i = 0; i < numSections; i++) {
1443                 sHdr = (struct typhoon_section_header *) image_data;
1444                 image_data += sizeof(struct typhoon_section_header);
1445                 load_addr = le32_to_cpu(sHdr->startAddr);
1446                 section_len = le32_to_cpu(sHdr->len);
1447
1448                 while(section_len) {
1449                         len = min_t(u32, section_len, PAGE_SIZE);
1450
1451                         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1452                            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1453                            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1454                                 printk(KERN_ERR "%s: segment ready timeout\n",
1455                                        tp->name);
1456                                 goto err_out_irq;
1457                         }
1458
1459                         /* Do an pseudo IPv4 checksum on the data -- first
1460                          * need to convert each u16 to cpu order before
1461                          * summing. Fortunately, due to the properties of
1462                          * the checksum, we can do this once, at the end.
1463                          */
1464                         csum = csum_partial_copy_nocheck(image_data, dpage,
1465                                                          len, 0);
1466                         csum = csum_fold(csum);
1467                         csum = le16_to_cpu(csum);
1468
1469                         iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1470                         iowrite32(csum, ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1471                         iowrite32(load_addr,
1472                                         ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1473                         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1474                         iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1475                         typhoon_post_pci_writes(ioaddr);
1476                         iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1477                                ioaddr + TYPHOON_REG_COMMAND);
1478
1479                         image_data += len;
1480                         load_addr += len;
1481                         section_len -= len;
1482                 }
1483         }
1484
1485         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1486            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1487            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1488                 printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
1489                 goto err_out_irq;
1490         }
1491
1492         iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1493
1494         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1495                 printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
1496                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1497                 goto err_out_irq;
1498         }
1499
1500         err = 0;
1501
1502 err_out_irq:
1503         iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1504         iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1505
1506         pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1507
1508 err_out:
1509         return err;
1510 }
1511
1512 static int
1513 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1514 {
1515         void __iomem *ioaddr = tp->ioaddr;
1516
1517         if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1518                 printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
1519                 goto out_timeout;
1520         }
1521
1522         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1523         iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1524         typhoon_post_pci_writes(ioaddr);
1525         iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1526                                 ioaddr + TYPHOON_REG_COMMAND);
1527
1528         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1529                 printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
1530                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1531                 goto out_timeout;
1532         }
1533
1534         /* Clear the Transmit and Command ready registers
1535          */
1536         iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1537         iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1538         iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1539         typhoon_post_pci_writes(ioaddr);
1540         iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1541
1542         return 0;
1543
1544 out_timeout:
1545         return -ETIMEDOUT;
1546 }
1547
1548 static u32
1549 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1550                         volatile u32 * index)
1551 {
1552         u32 lastRead = txRing->lastRead;
1553         struct tx_desc *tx;
1554         dma_addr_t skb_dma;
1555         int dma_len;
1556         int type;
1557
1558         while(lastRead != le32_to_cpu(*index)) {
1559                 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1560                 type = tx->flags & TYPHOON_TYPE_MASK;
1561
1562                 if(type == TYPHOON_TX_DESC) {
1563                         /* This tx_desc describes a packet.
1564                          */
1565                         unsigned long ptr = tx->addr | ((u64)tx->addrHi << 32);
1566                         struct sk_buff *skb = (struct sk_buff *) ptr;
1567                         dev_kfree_skb_irq(skb);
1568                 } else if(type == TYPHOON_FRAG_DESC) {
1569                         /* This tx_desc describes a memory mapping. Free it.
1570                          */
1571                         skb_dma = (dma_addr_t) le32_to_cpu(tx->addr);
1572                         dma_len = le16_to_cpu(tx->len);
1573                         pci_unmap_single(tp->pdev, skb_dma, dma_len,
1574                                        PCI_DMA_TODEVICE);
1575                 }
1576
1577                 tx->flags = 0;
1578                 typhoon_inc_tx_index(&lastRead, 1);
1579         }
1580
1581         return lastRead;
1582 }
1583
1584 static void
1585 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1586                         volatile u32 * index)
1587 {
1588         u32 lastRead;
1589         int numDesc = MAX_SKB_FRAGS + 1;
1590
1591         /* This will need changing if we start to use the Hi Tx ring. */
1592         lastRead = typhoon_clean_tx(tp, txRing, index);
1593         if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1594                                 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1595                 netif_wake_queue(tp->dev);
1596
1597         txRing->lastRead = lastRead;
1598         smp_wmb();
1599 }
1600
1601 static void
1602 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1603 {
1604         struct typhoon_indexes *indexes = tp->indexes;
1605         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1606         struct basic_ring *ring = &tp->rxBuffRing;
1607         struct rx_free *r;
1608
1609         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1610                                 indexes->rxBuffCleared) {
1611                 /* no room in ring, just drop the skb
1612                  */
1613                 dev_kfree_skb_any(rxb->skb);
1614                 rxb->skb = NULL;
1615                 return;
1616         }
1617
1618         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1619         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1620         r->virtAddr = idx;
1621         r->physAddr = cpu_to_le32(rxb->dma_addr);
1622
1623         /* Tell the card about it */
1624         wmb();
1625         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1626 }
1627
1628 static int
1629 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1630 {
1631         struct typhoon_indexes *indexes = tp->indexes;
1632         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1633         struct basic_ring *ring = &tp->rxBuffRing;
1634         struct rx_free *r;
1635         struct sk_buff *skb;
1636         dma_addr_t dma_addr;
1637
1638         rxb->skb = NULL;
1639
1640         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1641                                 indexes->rxBuffCleared)
1642                 return -ENOMEM;
1643
1644         skb = dev_alloc_skb(PKT_BUF_SZ);
1645         if(!skb)
1646                 return -ENOMEM;
1647
1648 #if 0
1649         /* Please, 3com, fix the firmware to allow DMA to a unaligned
1650          * address! Pretty please?
1651          */
1652         skb_reserve(skb, 2);
1653 #endif
1654
1655         skb->dev = tp->dev;
1656         dma_addr = pci_map_single(tp->pdev, skb->data,
1657                                   PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1658
1659         /* Since no card does 64 bit DAC, the high bits will never
1660          * change from zero.
1661          */
1662         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1663         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1664         r->virtAddr = idx;
1665         r->physAddr = cpu_to_le32(dma_addr);
1666         rxb->skb = skb;
1667         rxb->dma_addr = dma_addr;
1668
1669         /* Tell the card about it */
1670         wmb();
1671         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1672         return 0;
1673 }
1674
1675 static int
1676 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile u32 * ready,
1677            volatile u32 * cleared, int budget)
1678 {
1679         struct rx_desc *rx;
1680         struct sk_buff *skb, *new_skb;
1681         struct rxbuff_ent *rxb;
1682         dma_addr_t dma_addr;
1683         u32 local_ready;
1684         u32 rxaddr;
1685         int pkt_len;
1686         u32 idx;
1687         u32 csum_bits;
1688         int received;
1689
1690         received = 0;
1691         local_ready = le32_to_cpu(*ready);
1692         rxaddr = le32_to_cpu(*cleared);
1693         while(rxaddr != local_ready && budget > 0) {
1694                 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1695                 idx = rx->addr;
1696                 rxb = &tp->rxbuffers[idx];
1697                 skb = rxb->skb;
1698                 dma_addr = rxb->dma_addr;
1699
1700                 typhoon_inc_rx_index(&rxaddr, 1);
1701
1702                 if(rx->flags & TYPHOON_RX_ERROR) {
1703                         typhoon_recycle_rx_skb(tp, idx);
1704                         continue;
1705                 }
1706
1707                 pkt_len = le16_to_cpu(rx->frameLen);
1708
1709                 if(pkt_len < rx_copybreak &&
1710                    (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1711                         new_skb->dev = tp->dev;
1712                         skb_reserve(new_skb, 2);
1713                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1714                                                     PKT_BUF_SZ,
1715                                                     PCI_DMA_FROMDEVICE);
1716                         eth_copy_and_sum(new_skb, skb->data, pkt_len, 0);
1717                         pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1718                                                        PKT_BUF_SZ,
1719                                                        PCI_DMA_FROMDEVICE);
1720                         skb_put(new_skb, pkt_len);
1721                         typhoon_recycle_rx_skb(tp, idx);
1722                 } else {
1723                         new_skb = skb;
1724                         skb_put(new_skb, pkt_len);
1725                         pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1726                                        PCI_DMA_FROMDEVICE);
1727                         typhoon_alloc_rx_skb(tp, idx);
1728                 }
1729                 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1730                 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1731                         TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1732                 if(csum_bits ==
1733                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
1734                    || csum_bits ==
1735                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1736                         new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1737                 } else
1738                         new_skb->ip_summed = CHECKSUM_NONE;
1739
1740                 spin_lock(&tp->state_lock);
1741                 if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
1742                         vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
1743                                                  ntohl(rx->vlanTag) & 0xffff);
1744                 else
1745                         netif_receive_skb(new_skb);
1746                 spin_unlock(&tp->state_lock);
1747
1748                 tp->dev->last_rx = jiffies;
1749                 received++;
1750                 budget--;
1751         }
1752         *cleared = cpu_to_le32(rxaddr);
1753
1754         return received;
1755 }
1756
1757 static void
1758 typhoon_fill_free_ring(struct typhoon *tp)
1759 {
1760         u32 i;
1761
1762         for(i = 0; i < RXENT_ENTRIES; i++) {
1763                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1764                 if(rxb->skb)
1765                         continue;
1766                 if(typhoon_alloc_rx_skb(tp, i) < 0)
1767                         break;
1768         }
1769 }
1770
1771 static int
1772 typhoon_poll(struct net_device *dev, int *total_budget)
1773 {
1774         struct typhoon *tp = netdev_priv(dev);
1775         struct typhoon_indexes *indexes = tp->indexes;
1776         int orig_budget = *total_budget;
1777         int budget, work_done, done;
1778
1779         rmb();
1780         if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1781                         typhoon_process_response(tp, 0, NULL);
1782
1783         if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1784                 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1785
1786         if(orig_budget > dev->quota)
1787                 orig_budget = dev->quota;
1788
1789         budget = orig_budget;
1790         work_done = 0;
1791         done = 1;
1792
1793         if(indexes->rxHiCleared != indexes->rxHiReady) {
1794                 work_done = typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1795                                         &indexes->rxHiCleared, budget);
1796                 budget -= work_done;
1797         }
1798
1799         if(indexes->rxLoCleared != indexes->rxLoReady) {
1800                 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1801                                         &indexes->rxLoCleared, budget);
1802         }
1803
1804         if(work_done) {
1805                 *total_budget -= work_done;
1806                 dev->quota -= work_done;
1807
1808                 if(work_done >= orig_budget)
1809                         done = 0;
1810         }
1811
1812         if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1813                 /* rxBuff ring is empty, try to fill it. */
1814                 typhoon_fill_free_ring(tp);
1815         }
1816
1817         if(done) {
1818                 netif_rx_complete(dev);
1819                 iowrite32(TYPHOON_INTR_NONE,
1820                                 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1821                 typhoon_post_pci_writes(tp->ioaddr);
1822         }
1823
1824         return (done ? 0 : 1);
1825 }
1826
1827 static irqreturn_t
1828 typhoon_interrupt(int irq, void *dev_instance)
1829 {
1830         struct net_device *dev = (struct net_device *) dev_instance;
1831         struct typhoon *tp = dev->priv;
1832         void __iomem *ioaddr = tp->ioaddr;
1833         u32 intr_status;
1834
1835         intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1836         if(!(intr_status & TYPHOON_INTR_HOST_INT))
1837                 return IRQ_NONE;
1838
1839         iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1840
1841         if(netif_rx_schedule_prep(dev)) {
1842                 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1843                 typhoon_post_pci_writes(ioaddr);
1844                 __netif_rx_schedule(dev);
1845         } else {
1846                 printk(KERN_ERR "%s: Error, poll already scheduled\n",
1847                        dev->name);
1848         }
1849         return IRQ_HANDLED;
1850 }
1851
1852 static void
1853 typhoon_free_rx_rings(struct typhoon *tp)
1854 {
1855         u32 i;
1856
1857         for(i = 0; i < RXENT_ENTRIES; i++) {
1858                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1859                 if(rxb->skb) {
1860                         pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1861                                        PCI_DMA_FROMDEVICE);
1862                         dev_kfree_skb(rxb->skb);
1863                         rxb->skb = NULL;
1864                 }
1865         }
1866 }
1867
1868 static int
1869 typhoon_sleep(struct typhoon *tp, pci_power_t state, u16 events)
1870 {
1871         struct pci_dev *pdev = tp->pdev;
1872         void __iomem *ioaddr = tp->ioaddr;
1873         struct cmd_desc xp_cmd;
1874         int err;
1875
1876         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1877         xp_cmd.parm1 = events;
1878         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1879         if(err < 0) {
1880                 printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
1881                                 tp->name, err);
1882                 return err;
1883         }
1884
1885         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1886         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1887         if(err < 0) {
1888                 printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
1889                                 tp->name, err);
1890                 return err;
1891         }
1892
1893         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1894                 return -ETIMEDOUT;
1895
1896         /* Since we cannot monitor the status of the link while sleeping,
1897          * tell the world it went away.
1898          */
1899         netif_carrier_off(tp->dev);
1900
1901         pci_enable_wake(tp->pdev, state, 1);
1902         pci_disable_device(pdev);
1903         return pci_set_power_state(pdev, state);
1904 }
1905
1906 static int
1907 typhoon_wakeup(struct typhoon *tp, int wait_type)
1908 {
1909         struct pci_dev *pdev = tp->pdev;
1910         void __iomem *ioaddr = tp->ioaddr;
1911
1912         pci_set_power_state(pdev, PCI_D0);
1913         pci_restore_state(pdev);
1914
1915         /* Post 2.x.x versions of the Sleep Image require a reset before
1916          * we can download the Runtime Image. But let's not make users of
1917          * the old firmware pay for the reset.
1918          */
1919         iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1920         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1921                         (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1922                 return typhoon_reset(ioaddr, wait_type);
1923
1924         return 0;
1925 }
1926
1927 static int
1928 typhoon_start_runtime(struct typhoon *tp)
1929 {
1930         struct net_device *dev = tp->dev;
1931         void __iomem *ioaddr = tp->ioaddr;
1932         struct cmd_desc xp_cmd;
1933         int err;
1934
1935         typhoon_init_rings(tp);
1936         typhoon_fill_free_ring(tp);
1937
1938         err = typhoon_download_firmware(tp);
1939         if(err < 0) {
1940                 printk("%s: cannot load runtime on 3XP\n", tp->name);
1941                 goto error_out;
1942         }
1943
1944         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1945                 printk("%s: cannot boot 3XP\n", tp->name);
1946                 err = -EIO;
1947                 goto error_out;
1948         }
1949
1950         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1951         xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1952         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1953         if(err < 0)
1954                 goto error_out;
1955
1956         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1957         xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
1958         xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
1959         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1960         if(err < 0)
1961                 goto error_out;
1962
1963         /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1964          * us some more information on how to control it.
1965          */
1966         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1967         xp_cmd.parm1 = 0;
1968         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1969         if(err < 0)
1970                 goto error_out;
1971
1972         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1973         xp_cmd.parm1 = tp->xcvr_select;
1974         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1975         if(err < 0)
1976                 goto error_out;
1977
1978         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1979         xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q);
1980         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1981         if(err < 0)
1982                 goto error_out;
1983
1984         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1985         spin_lock_bh(&tp->state_lock);
1986         xp_cmd.parm2 = tp->offload;
1987         xp_cmd.parm3 = tp->offload;
1988         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1989         spin_unlock_bh(&tp->state_lock);
1990         if(err < 0)
1991                 goto error_out;
1992
1993         typhoon_set_rx_mode(dev);
1994
1995         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1996         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1997         if(err < 0)
1998                 goto error_out;
1999
2000         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
2001         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2002         if(err < 0)
2003                 goto error_out;
2004
2005         tp->card_state = Running;
2006         smp_wmb();
2007
2008         iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2009         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
2010         typhoon_post_pci_writes(ioaddr);
2011
2012         return 0;
2013
2014 error_out:
2015         typhoon_reset(ioaddr, WaitNoSleep);
2016         typhoon_free_rx_rings(tp);
2017         typhoon_init_rings(tp);
2018         return err;
2019 }
2020
2021 static int
2022 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
2023 {
2024         struct typhoon_indexes *indexes = tp->indexes;
2025         struct transmit_ring *txLo = &tp->txLoRing;
2026         void __iomem *ioaddr = tp->ioaddr;
2027         struct cmd_desc xp_cmd;
2028         int i;
2029
2030         /* Disable interrupts early, since we can't schedule a poll
2031          * when called with !netif_running(). This will be posted
2032          * when we force the posting of the command.
2033          */
2034         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2035
2036         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2037         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2038
2039         /* Wait 1/2 sec for any outstanding transmits to occur
2040          * We'll cleanup after the reset if this times out.
2041          */
2042         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2043                 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2044                         break;
2045                 udelay(TYPHOON_UDELAY);
2046         }
2047
2048         if(i == TYPHOON_WAIT_TIMEOUT)
2049                 printk(KERN_ERR
2050                        "%s: halt timed out waiting for Tx to complete\n",
2051                        tp->name);
2052
2053         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2054         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2055
2056         /* save the statistics so when we bring the interface up again,
2057          * the values reported to userspace are correct.
2058          */
2059         tp->card_state = Sleeping;
2060         smp_wmb();
2061         typhoon_do_get_stats(tp);
2062         memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2063
2064         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2065         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2066
2067         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2068                 printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
2069                        tp->name);
2070
2071         if(typhoon_reset(ioaddr, wait_type) < 0) {
2072                 printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
2073                 return -ETIMEDOUT;
2074         }
2075
2076         /* cleanup any outstanding Tx packets */
2077         if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2078                 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2079                 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2080         }
2081
2082         return 0;
2083 }
2084
2085 static void
2086 typhoon_tx_timeout(struct net_device *dev)
2087 {
2088         struct typhoon *tp = netdev_priv(dev);
2089
2090         if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2091                 printk(KERN_WARNING "%s: could not reset in tx timeout\n",
2092                                         dev->name);
2093                 goto truely_dead;
2094         }
2095
2096         /* If we ever start using the Hi ring, it will need cleaning too */
2097         typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2098         typhoon_free_rx_rings(tp);
2099
2100         if(typhoon_start_runtime(tp) < 0) {
2101                 printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
2102                                         dev->name);
2103                 goto truely_dead;
2104         }
2105
2106         netif_wake_queue(dev);
2107         return;
2108
2109 truely_dead:
2110         /* Reset the hardware, and turn off carrier to avoid more timeouts */
2111         typhoon_reset(tp->ioaddr, NoWait);
2112         netif_carrier_off(dev);
2113 }
2114
2115 static int
2116 typhoon_open(struct net_device *dev)
2117 {
2118         struct typhoon *tp = netdev_priv(dev);
2119         int err;
2120
2121         err = typhoon_wakeup(tp, WaitSleep);
2122         if(err < 0) {
2123                 printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
2124                 goto out_sleep;
2125         }
2126
2127         err = request_irq(dev->irq, &typhoon_interrupt, IRQF_SHARED,
2128                                 dev->name, dev);
2129         if(err < 0)
2130                 goto out_sleep;
2131
2132         err = typhoon_start_runtime(tp);
2133         if(err < 0)
2134                 goto out_irq;
2135
2136         netif_start_queue(dev);
2137         return 0;
2138
2139 out_irq:
2140         free_irq(dev->irq, dev);
2141
2142 out_sleep:
2143         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2144                 printk(KERN_ERR "%s: unable to reboot into sleep img\n",
2145                                 dev->name);
2146                 typhoon_reset(tp->ioaddr, NoWait);
2147                 goto out;
2148         }
2149
2150         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2151                 printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
2152
2153 out:
2154         return err;
2155 }
2156
2157 static int
2158 typhoon_close(struct net_device *dev)
2159 {
2160         struct typhoon *tp = netdev_priv(dev);
2161
2162         netif_stop_queue(dev);
2163
2164         if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2165                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2166
2167         /* Make sure there is no irq handler running on a different CPU. */
2168         typhoon_synchronize_irq(dev->irq);
2169         free_irq(dev->irq, dev);
2170
2171         typhoon_free_rx_rings(tp);
2172         typhoon_init_rings(tp);
2173
2174         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2175                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2176
2177         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2178                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2179
2180         return 0;
2181 }
2182
2183 #ifdef CONFIG_PM
2184 static int
2185 typhoon_resume(struct pci_dev *pdev)
2186 {
2187         struct net_device *dev = pci_get_drvdata(pdev);
2188         struct typhoon *tp = netdev_priv(dev);
2189
2190         /* If we're down, resume when we are upped.
2191          */
2192         if(!netif_running(dev))
2193                 return 0;
2194
2195         if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2196                 printk(KERN_ERR "%s: critical: could not wake up in resume\n",
2197                                 dev->name);
2198                 goto reset;
2199         }
2200
2201         if(typhoon_start_runtime(tp) < 0) {
2202                 printk(KERN_ERR "%s: critical: could not start runtime in "
2203                                 "resume\n", dev->name);
2204                 goto reset;
2205         }
2206
2207         netif_device_attach(dev);
2208         netif_start_queue(dev);
2209         return 0;
2210
2211 reset:
2212         typhoon_reset(tp->ioaddr, NoWait);
2213         return -EBUSY;
2214 }
2215
2216 static int
2217 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2218 {
2219         struct net_device *dev = pci_get_drvdata(pdev);
2220         struct typhoon *tp = netdev_priv(dev);
2221         struct cmd_desc xp_cmd;
2222
2223         /* If we're down, we're already suspended.
2224          */
2225         if(!netif_running(dev))
2226                 return 0;
2227
2228         spin_lock_bh(&tp->state_lock);
2229         if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
2230                 spin_unlock_bh(&tp->state_lock);
2231                 printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
2232                                 dev->name);
2233                 return -EBUSY;
2234         }
2235         spin_unlock_bh(&tp->state_lock);
2236
2237         netif_device_detach(dev);
2238
2239         if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2240                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2241                 goto need_resume;
2242         }
2243
2244         typhoon_free_rx_rings(tp);
2245         typhoon_init_rings(tp);
2246
2247         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2248                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2249                 goto need_resume;
2250         }
2251
2252         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2253         xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
2254         xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
2255         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2256                 printk(KERN_ERR "%s: unable to set mac address in suspend\n",
2257                                 dev->name);
2258                 goto need_resume;
2259         }
2260
2261         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2262         xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2263         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2264                 printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
2265                                 dev->name);
2266                 goto need_resume;
2267         }
2268
2269         if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2270                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2271                 goto need_resume;
2272         }
2273
2274         return 0;
2275
2276 need_resume:
2277         typhoon_resume(pdev);
2278         return -EBUSY;
2279 }
2280
2281 static int
2282 typhoon_enable_wake(struct pci_dev *pdev, pci_power_t state, int enable)
2283 {
2284         return pci_enable_wake(pdev, state, enable);
2285 }
2286 #endif
2287
2288 static int __devinit
2289 typhoon_test_mmio(struct pci_dev *pdev)
2290 {
2291         void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2292         int mode = 0;
2293         u32 val;
2294
2295         if(!ioaddr)
2296                 goto out;
2297
2298         if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2299                                 TYPHOON_STATUS_WAITING_FOR_HOST)
2300                 goto out_unmap;
2301
2302         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2303         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2304         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2305
2306         /* Ok, see if we can change our interrupt status register by
2307          * sending ourselves an interrupt. If so, then MMIO works.
2308          * The 50usec delay is arbitrary -- it could probably be smaller.
2309          */
2310         val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2311         if((val & TYPHOON_INTR_SELF) == 0) {
2312                 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2313                 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2314                 udelay(50);
2315                 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2316                 if(val & TYPHOON_INTR_SELF)
2317                         mode = 1;
2318         }
2319
2320         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2321         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2322         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2323         ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2324
2325 out_unmap:
2326         pci_iounmap(pdev, ioaddr);
2327
2328 out:
2329         if(!mode)
2330                 printk(KERN_INFO PFX "falling back to port IO\n");
2331         return mode;
2332 }
2333
2334 static int __devinit
2335 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2336 {
2337         static int did_version = 0;
2338         struct net_device *dev;
2339         struct typhoon *tp;
2340         int card_id = (int) ent->driver_data;
2341         void __iomem *ioaddr;
2342         void *shared;
2343         dma_addr_t shared_dma;
2344         struct cmd_desc xp_cmd;
2345         struct resp_desc xp_resp[3];
2346         int i;
2347         int err = 0;
2348
2349         if(!did_version++)
2350                 printk(KERN_INFO "%s", version);
2351
2352         dev = alloc_etherdev(sizeof(*tp));
2353         if(dev == NULL) {
2354                 printk(ERR_PFX "%s: unable to alloc new net device\n",
2355                        pci_name(pdev));
2356                 err = -ENOMEM;
2357                 goto error_out;
2358         }
2359         SET_MODULE_OWNER(dev);
2360         SET_NETDEV_DEV(dev, &pdev->dev);
2361
2362         err = pci_enable_device(pdev);
2363         if(err < 0) {
2364                 printk(ERR_PFX "%s: unable to enable device\n",
2365                        pci_name(pdev));
2366                 goto error_out_dev;
2367         }
2368
2369         err = pci_set_mwi(pdev);
2370         if(err < 0) {
2371                 printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
2372                 goto error_out_disable;
2373         }
2374
2375         err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2376         if(err < 0) {
2377                 printk(ERR_PFX "%s: No usable DMA configuration\n",
2378                        pci_name(pdev));
2379                 goto error_out_mwi;
2380         }
2381
2382         /* sanity checks on IO and MMIO BARs
2383          */
2384         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2385                 printk(ERR_PFX
2386                        "%s: region #1 not a PCI IO resource, aborting\n",
2387                        pci_name(pdev));
2388                 err = -ENODEV;
2389                 goto error_out_mwi;
2390         }
2391         if(pci_resource_len(pdev, 0) < 128) {
2392                 printk(ERR_PFX "%s: Invalid PCI IO region size, aborting\n",
2393                        pci_name(pdev));
2394                 err = -ENODEV;
2395                 goto error_out_mwi;
2396         }
2397         if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2398                 printk(ERR_PFX
2399                        "%s: region #1 not a PCI MMIO resource, aborting\n",
2400                        pci_name(pdev));
2401                 err = -ENODEV;
2402                 goto error_out_mwi;
2403         }
2404         if(pci_resource_len(pdev, 1) < 128) {
2405                 printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
2406                        pci_name(pdev));
2407                 err = -ENODEV;
2408                 goto error_out_mwi;
2409         }
2410
2411         err = pci_request_regions(pdev, "typhoon");
2412         if(err < 0) {
2413                 printk(ERR_PFX "%s: could not request regions\n",
2414                        pci_name(pdev));
2415                 goto error_out_mwi;
2416         }
2417
2418         /* map our registers
2419          */
2420         if(use_mmio != 0 && use_mmio != 1)
2421                 use_mmio = typhoon_test_mmio(pdev);
2422
2423         ioaddr = pci_iomap(pdev, use_mmio, 128);
2424         if (!ioaddr) {
2425                 printk(ERR_PFX "%s: cannot remap registers, aborting\n",
2426                        pci_name(pdev));
2427                 err = -EIO;
2428                 goto error_out_regions;
2429         }
2430
2431         /* allocate pci dma space for rx and tx descriptor rings
2432          */
2433         shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2434                                       &shared_dma);
2435         if(!shared) {
2436                 printk(ERR_PFX "%s: could not allocate DMA memory\n",
2437                        pci_name(pdev));
2438                 err = -ENOMEM;
2439                 goto error_out_remap;
2440         }
2441
2442         dev->irq = pdev->irq;
2443         tp = netdev_priv(dev);
2444         tp->shared = (struct typhoon_shared *) shared;
2445         tp->shared_dma = shared_dma;
2446         tp->pdev = pdev;
2447         tp->tx_pdev = pdev;
2448         tp->ioaddr = ioaddr;
2449         tp->tx_ioaddr = ioaddr;
2450         tp->dev = dev;
2451
2452         /* Init sequence:
2453          * 1) Reset the adapter to clear any bad juju
2454          * 2) Reload the sleep image
2455          * 3) Boot the sleep image
2456          * 4) Get the hardware address.
2457          * 5) Put the card to sleep.
2458          */
2459         if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2460                 printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
2461                 err = -EIO;
2462                 goto error_out_dma;
2463         }
2464
2465         /* Now that we've reset the 3XP and are sure it's not going to
2466          * write all over memory, enable bus mastering, and save our
2467          * state for resuming after a suspend.
2468          */
2469         pci_set_master(pdev);
2470         pci_save_state(pdev);
2471
2472         /* dev->name is not valid until we register, but we need to
2473          * use some common routines to initialize the card. So that those
2474          * routines print the right name, we keep our oun pointer to the name
2475          */
2476         tp->name = pci_name(pdev);
2477
2478         typhoon_init_interface(tp);
2479         typhoon_init_rings(tp);
2480
2481         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2482                 printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
2483                        pci_name(pdev));
2484                 err = -EIO;
2485                 goto error_out_reset;
2486         }
2487
2488         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2489         if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2490                 printk(ERR_PFX "%s: cannot read MAC address\n",
2491                        pci_name(pdev));
2492                 err = -EIO;
2493                 goto error_out_reset;
2494         }
2495
2496         *(u16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2497         *(u32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2498
2499         if(!is_valid_ether_addr(dev->dev_addr)) {
2500                 printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
2501                        "aborting\n", pci_name(pdev));
2502                 goto error_out_reset;
2503         }
2504
2505         /* Read the Sleep Image version last, so the response is valid
2506          * later when we print out the version reported.
2507          */
2508         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2509         if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2510                 printk(ERR_PFX "%s: Could not get Sleep Image version\n",
2511                         pci_name(pdev));
2512                 goto error_out_reset;
2513         }
2514
2515         tp->capabilities = typhoon_card_info[card_id].capabilities;
2516         tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2517
2518         /* Typhoon 1.0 Sleep Images return one response descriptor to the
2519          * READ_VERSIONS command. Those versions are OK after waking up
2520          * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2521          * seem to need a little extra help to get started. Since we don't
2522          * know how to nudge it along, just kick it.
2523          */
2524         if(xp_resp[0].numDesc != 0)
2525                 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2526
2527         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2528                 printk(ERR_PFX "%s: cannot put adapter to sleep\n",
2529                        pci_name(pdev));
2530                 err = -EIO;
2531                 goto error_out_reset;
2532         }
2533
2534         /* The chip-specific entries in the device structure. */
2535         dev->open               = typhoon_open;
2536         dev->hard_start_xmit    = typhoon_start_tx;
2537         dev->stop               = typhoon_close;
2538         dev->set_multicast_list = typhoon_set_rx_mode;
2539         dev->tx_timeout         = typhoon_tx_timeout;
2540         dev->poll               = typhoon_poll;
2541         dev->weight             = 16;
2542         dev->watchdog_timeo     = TX_TIMEOUT;
2543         dev->get_stats          = typhoon_get_stats;
2544         dev->set_mac_address    = typhoon_set_mac_address;
2545         dev->vlan_rx_register   = typhoon_vlan_rx_register;
2546         dev->vlan_rx_kill_vid   = typhoon_vlan_rx_kill_vid;
2547         SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2548
2549         /* We can handle scatter gather, up to 16 entries, and
2550          * we can do IP checksumming (only version 4, doh...)
2551          */
2552         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2553         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2554         dev->features |= NETIF_F_TSO;
2555
2556         if(register_netdev(dev) < 0)
2557                 goto error_out_reset;
2558
2559         /* fixup our local name */
2560         tp->name = dev->name;
2561
2562         pci_set_drvdata(pdev, dev);
2563
2564         printk(KERN_INFO "%s: %s at %s 0x%llx, ",
2565                dev->name, typhoon_card_info[card_id].name,
2566                use_mmio ? "MMIO" : "IO",
2567                (unsigned long long)pci_resource_start(pdev, use_mmio));
2568         for(i = 0; i < 5; i++)
2569                 printk("%2.2x:", dev->dev_addr[i]);
2570         printk("%2.2x\n", dev->dev_addr[i]);
2571
2572         /* xp_resp still contains the response to the READ_VERSIONS command.
2573          * For debugging, let the user know what version he has.
2574          */
2575         if(xp_resp[0].numDesc == 0) {
2576                 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2577                  * of version is Month/Day of build.
2578                  */
2579                 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2580                 printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
2581                         "%02u/%02u/2000\n", dev->name, monthday >> 8,
2582                         monthday & 0xff);
2583         } else if(xp_resp[0].numDesc == 2) {
2584                 /* This is the Typhoon 1.1+ type Sleep Image
2585                  */
2586                 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2587                 u8 *ver_string = (u8 *) &xp_resp[1];
2588                 ver_string[25] = 0;
2589                 printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
2590                         "%02x.%03x.%03x %s\n", dev->name, sleep_ver >> 24,
2591                         (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff,
2592                         ver_string);
2593         } else {
2594                 printk(KERN_WARNING "%s: Unknown Sleep Image version "
2595                         "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
2596                         le32_to_cpu(xp_resp[0].parm2));
2597         }
2598
2599         return 0;
2600
2601 error_out_reset:
2602         typhoon_reset(ioaddr, NoWait);
2603
2604 error_out_dma:
2605         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2606                             shared, shared_dma);
2607 error_out_remap:
2608         pci_iounmap(pdev, ioaddr);
2609 error_out_regions:
2610         pci_release_regions(pdev);
2611 error_out_mwi:
2612         pci_clear_mwi(pdev);
2613 error_out_disable:
2614         pci_disable_device(pdev);
2615 error_out_dev:
2616         free_netdev(dev);
2617 error_out:
2618         return err;
2619 }
2620
2621 static void __devexit
2622 typhoon_remove_one(struct pci_dev *pdev)
2623 {
2624         struct net_device *dev = pci_get_drvdata(pdev);
2625         struct typhoon *tp = netdev_priv(dev);
2626
2627         unregister_netdev(dev);
2628         pci_set_power_state(pdev, PCI_D0);
2629         pci_restore_state(pdev);
2630         typhoon_reset(tp->ioaddr, NoWait);
2631         pci_iounmap(pdev, tp->ioaddr);
2632         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2633                             tp->shared, tp->shared_dma);
2634         pci_release_regions(pdev);
2635         pci_clear_mwi(pdev);
2636         pci_disable_device(pdev);
2637         pci_set_drvdata(pdev, NULL);
2638         free_netdev(dev);
2639 }
2640
2641 static struct pci_driver typhoon_driver = {
2642         .name           = DRV_MODULE_NAME,
2643         .id_table       = typhoon_pci_tbl,
2644         .probe          = typhoon_init_one,
2645         .remove         = __devexit_p(typhoon_remove_one),
2646 #ifdef CONFIG_PM
2647         .suspend        = typhoon_suspend,
2648         .resume         = typhoon_resume,
2649         .enable_wake    = typhoon_enable_wake,
2650 #endif
2651 };
2652
2653 static int __init
2654 typhoon_init(void)
2655 {
2656         return pci_register_driver(&typhoon_driver);
2657 }
2658
2659 static void __exit
2660 typhoon_cleanup(void)
2661 {
2662         pci_unregister_driver(&typhoon_driver);
2663 }
2664
2665 module_init(typhoon_init);
2666 module_exit(typhoon_cleanup);