git.oblomov.eu Git - linux-2.6/blob - drivers/video/savage/savagefb_driver.c

   1 /*
   2  * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
   3  *
   4  * Copyright (c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>
   5  *                          Sven Neumann <neo@directfb.org>
   6  *
   7  *
   8  * Card specific code is based on XFree86's savage driver.
   9  * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
  10  *
  11  * This file is subject to the terms and conditions of the GNU General
  12  * Public License.  See the file COPYING in the main directory of this
  13  * archive for more details.
  14  *
  15  * 0.4.0 (neo)
  16  *  - hardware accelerated clear and move
  17  *
  18  * 0.3.2 (dok)
  19  *  - wait for vertical retrace before writing to cr67
  20  *    at the beginning of savagefb_set_par
  21  *  - use synchronization registers cr23 and cr26
  22  *
  23  * 0.3.1 (dok)
  24  *  - reset 3D engine
  25  *  - don't return alpha bits for 32bit format
  26  *
  27  * 0.3.0 (dok)
  28  *  - added WaitIdle functions for all Savage types
  29  *  - do WaitIdle before mode switching
  30  *  - code cleanup
  31  *
  32  * 0.2.0 (dok)
  33  *  - first working version
  34  *
  35  *
  36  * TODO
  37  * - clock validations in decode_var
  38  *
  39  * BUGS
  40  * - white margin on bootup
  41  *
  42  */
  43
  44 #include <linux/config.h>
  45 #include <linux/module.h>
  46 #include <linux/kernel.h>
  47 #include <linux/errno.h>
  48 #include <linux/string.h>
  49 #include <linux/mm.h>
  50 #include <linux/tty.h>
  51 #include <linux/slab.h>
  52 #include <linux/delay.h>
  53 #include <linux/fb.h>
  54 #include <linux/pci.h>
  55 #include <linux/init.h>
  56 #include <linux/console.h>
  57
  58 #include <asm/io.h>
  59 #include <asm/irq.h>
  60 #include <asm/pgtable.h>
  61 #include <asm/system.h>
  62 #include <asm/uaccess.h>
  63
  64 #ifdef CONFIG_MTRR
  65 #include <asm/mtrr.h>
  66 #endif
  67
  68 #include "savagefb.h"
  69
  70
  71 #define SAVAGEFB_VERSION "0.4.0_2.6"
  72
  73 /* --------------------------------------------------------------------- */
  74
  75
  76 static char *mode_option __initdata = NULL;
  77 static int   paletteEnabled = 0;
  78
  79 #ifdef MODULE
  80
  81 MODULE_AUTHOR("(c) 2001-2002  Denis Oliver Kropp <dok@directfb.org>");
  82 MODULE_LICENSE("GPL");
  83 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
  84
  85 #endif
  86
  87
  88 /* --------------------------------------------------------------------- */
  89
  90 static void vgaHWSeqReset (struct savagefb_par *par, int start)
  91 {
  92         if (start)
  93                 VGAwSEQ (0x00, 0x01);           /* Synchronous Reset */
  94         else
  95                 VGAwSEQ (0x00, 0x03);           /* End Reset */
  96 }
  97
  98 static void vgaHWProtect (struct savagefb_par *par, int on)
  99 {
 100         unsigned char tmp;
 101
 102         if (on) {
 103                 /*
 104                  * Turn off screen and disable sequencer.
 105                  */
 106                 tmp = VGArSEQ (0x01);
 107
 108                 vgaHWSeqReset (par, 1);         /* start synchronous reset */
 109                 VGAwSEQ (0x01, tmp | 0x20);     /* disable the display */
 110
 111                 VGAenablePalette();
 112         } else {
 113                 /*
 114                  * Reenable sequencer, then turn on screen.
 115                  */
 116
 117                 tmp = VGArSEQ (0x01);
 118
 119                 VGAwSEQ (0x01, tmp & ~0x20);    /* reenable display */
 120                 vgaHWSeqReset (par, 0);         /* clear synchronous reset */
 121
 122                 VGAdisablePalette();
 123         }
 124 }
 125
 126 static void vgaHWRestore (struct savagefb_par  *par)
 127 {
 128         int i;
 129
 130         VGAwMISC (par->MiscOutReg);
 131
 132         for (i = 1; i < 5; i++)
 133                 VGAwSEQ (i, par->Sequencer[i]);
 134
 135         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
 136            CRTC[17] */
 137         VGAwCR (17, par->CRTC[17] & ~0x80);
 138
 139         for (i = 0; i < 25; i++)
 140                 VGAwCR (i, par->CRTC[i]);
 141
 142         for (i = 0; i < 9; i++)
 143                 VGAwGR (i, par->Graphics[i]);
 144
 145         VGAenablePalette();
 146
 147         for (i = 0; i < 21; i++)
 148                 VGAwATTR (i, par->Attribute[i]);
 149
 150         VGAdisablePalette();
 151 }
 152
 153 static void vgaHWInit (struct fb_var_screeninfo *var,
 154                        struct savagefb_par            *par,
 155                        struct xtimings                *timings)
 156 {
 157         par->MiscOutReg = 0x23;
 158
 159         if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
 160                 par->MiscOutReg |= 0x40;
 161
 162         if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
 163                 par->MiscOutReg |= 0x80;
 164
 165         /*
 166          * Time Sequencer
 167          */
 168         par->Sequencer[0x00] = 0x00;
 169         par->Sequencer[0x01] = 0x01;
 170         par->Sequencer[0x02] = 0x0F;
 171         par->Sequencer[0x03] = 0x00;          /* Font select */
 172         par->Sequencer[0x04] = 0x0E;          /* Misc */
 173
 174         /*
 175          * CRTC Controller
 176          */
 177         par->CRTC[0x00] = (timings->HTotal >> 3) - 5;
 178         par->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
 179         par->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
 180         par->CRTC[0x03] = (((timings->HSyncEnd >> 3)  - 1) & 0x1f) | 0x80;
 181         par->CRTC[0x04] = (timings->HSyncStart >> 3);
 182         par->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
 183                 (((timings->HSyncEnd >> 3)) & 0x1f);
 184         par->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
 185         par->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
 186                 (((timings->VDisplay - 1) & 0x100) >> 7) |
 187                 ((timings->VSyncStart & 0x100) >> 6) |
 188                 (((timings->VSyncStart - 1) & 0x100) >> 5) |
 189                 0x10 |
 190                 (((timings->VTotal - 2) & 0x200) >> 4) |
 191                 (((timings->VDisplay - 1) & 0x200) >> 3) |
 192                 ((timings->VSyncStart & 0x200) >> 2);
 193         par->CRTC[0x08] = 0x00;
 194         par->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
 195
 196         if (timings->dblscan)
 197                 par->CRTC[0x09] |= 0x80;
 198
 199         par->CRTC[0x0a] = 0x00;
 200         par->CRTC[0x0b] = 0x00;
 201         par->CRTC[0x0c] = 0x00;
 202         par->CRTC[0x0d] = 0x00;
 203         par->CRTC[0x0e] = 0x00;
 204         par->CRTC[0x0f] = 0x00;
 205         par->CRTC[0x10] = timings->VSyncStart & 0xff;
 206         par->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
 207         par->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
 208         par->CRTC[0x13] = var->xres_virtual >> 4;
 209         par->CRTC[0x14] = 0x00;
 210         par->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
 211         par->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
 212         par->CRTC[0x17] = 0xc3;
 213         par->CRTC[0x18] = 0xff;
 214
 215         /*
 216          * are these unnecessary?
 217          * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
 218          * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
 219          */
 220
 221         /*
 222          * Graphics Display Controller
 223          */
 224         par->Graphics[0x00] = 0x00;
 225         par->Graphics[0x01] = 0x00;
 226         par->Graphics[0x02] = 0x00;
 227         par->Graphics[0x03] = 0x00;
 228         par->Graphics[0x04] = 0x00;
 229         par->Graphics[0x05] = 0x40;
 230         par->Graphics[0x06] = 0x05;   /* only map 64k VGA memory !!!! */
 231         par->Graphics[0x07] = 0x0F;
 232         par->Graphics[0x08] = 0xFF;
 233
 234
 235         par->Attribute[0x00]  = 0x00; /* standard colormap translation */
 236         par->Attribute[0x01]  = 0x01;
 237         par->Attribute[0x02]  = 0x02;
 238         par->Attribute[0x03]  = 0x03;
 239         par->Attribute[0x04]  = 0x04;
 240         par->Attribute[0x05]  = 0x05;
 241         par->Attribute[0x06]  = 0x06;
 242         par->Attribute[0x07]  = 0x07;
 243         par->Attribute[0x08]  = 0x08;
 244         par->Attribute[0x09]  = 0x09;
 245         par->Attribute[0x0a] = 0x0A;
 246         par->Attribute[0x0b] = 0x0B;
 247         par->Attribute[0x0c] = 0x0C;
 248         par->Attribute[0x0d] = 0x0D;
 249         par->Attribute[0x0e] = 0x0E;
 250         par->Attribute[0x0f] = 0x0F;
 251         par->Attribute[0x10] = 0x41;
 252         par->Attribute[0x11] = 0xFF;
 253         par->Attribute[0x12] = 0x0F;
 254         par->Attribute[0x13] = 0x00;
 255         par->Attribute[0x14] = 0x00;
 256 }
 257
 258 /* -------------------- Hardware specific routines ------------------------- */
 259
 260 /*
 261  * Hardware Acceleration for SavageFB
 262  */
 263
 264 /* Wait for fifo space */
 265 static void
 266 savage3D_waitfifo(struct savagefb_par *par, int space)
 267 {
 268         int slots = MAXFIFO - space;
 269
 270         while ((savage_in32(0x48C00) & 0x0000ffff) > slots);
 271 }
 272
 273 static void
 274 savage4_waitfifo(struct savagefb_par *par, int space)
 275 {
 276         int slots = MAXFIFO - space;
 277
 278         while ((savage_in32(0x48C60) & 0x001fffff) > slots);
 279 }
 280
 281 static void
 282 savage2000_waitfifo(struct savagefb_par *par, int space)
 283 {
 284         int slots = MAXFIFO - space;
 285
 286         while ((savage_in32(0x48C60) & 0x0000ffff) > slots);
 287 }
 288
 289 /* Wait for idle accelerator */
 290 static void
 291 savage3D_waitidle(struct savagefb_par *par)
 292 {
 293         while ((savage_in32(0x48C00) & 0x0008ffff) != 0x80000);
 294 }
 295
 296 static void
 297 savage4_waitidle(struct savagefb_par *par)
 298 {
 299         while ((savage_in32(0x48C60) & 0x00a00000) != 0x00a00000);
 300 }
 301
 302 static void
 303 savage2000_waitidle(struct savagefb_par *par)
 304 {
 305         while ((savage_in32(0x48C60) & 0x009fffff));
 306 }
 307
 308
 309 static void
 310 SavageSetup2DEngine (struct savagefb_par  *par)
 311 {
 312         unsigned long GlobalBitmapDescriptor;
 313
 314         GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
 315         BCI_BD_SET_BPP (GlobalBitmapDescriptor, par->depth);
 316         BCI_BD_SET_STRIDE (GlobalBitmapDescriptor, par->vwidth);
 317
 318         switch(par->chip) {
 319         case S3_SAVAGE3D:
 320         case S3_SAVAGE_MX:
 321                 /* Disable BCI */
 322                 savage_out32(0x48C18, savage_in32(0x48C18) & 0x3FF0);
 323                 /* Setup BCI command overflow buffer */
 324                 savage_out32(0x48C14, (par->cob_offset >> 11) | (par->cob_index << 29));
 325                 /* Program shadow status update. */
 326                 savage_out32(0x48C10, 0x78207220);
 327                 savage_out32(0x48C0C, 0);
 328                 /* Enable BCI and command overflow buffer */
 329                 savage_out32(0x48C18, savage_in32(0x48C18) | 0x0C);
 330                 break;
 331         case S3_SAVAGE4:
 332         case S3_PROSAVAGE:
 333         case S3_SUPERSAVAGE:
 334                 /* Disable BCI */
 335                 savage_out32(0x48C18, savage_in32(0x48C18) & 0x3FF0);
 336                 /* Program shadow status update */
 337                 savage_out32(0x48C10, 0x00700040);
 338                 savage_out32(0x48C0C, 0);
 339                 /* Enable BCI without the COB */
 340                 savage_out32(0x48C18, savage_in32(0x48C18) | 0x08);
 341                 break;
 342         case S3_SAVAGE2000:
 343                 /* Disable BCI */
 344                 savage_out32(0x48C18, 0);
 345                 /* Setup BCI command overflow buffer */
 346                 savage_out32(0x48C18, (par->cob_offset >> 7) | (par->cob_index));
 347                 /* Disable shadow status update */
 348                 savage_out32(0x48A30, 0);
 349                 /* Enable BCI and command overflow buffer */
 350                 savage_out32(0x48C18, savage_in32(0x48C18) | 0x00280000 );
 351                 break;
 352             default:
 353                 break;
 354         }
 355         /* Turn on 16-bit register access. */
 356         vga_out8(0x3d4, 0x31);
 357         vga_out8(0x3d5, 0x0c);
 358
 359         /* Set stride to use GBD. */
 360         vga_out8 (0x3d4, 0x50);
 361         vga_out8 (0x3d5, vga_in8 (0x3d5 ) | 0xC1);
 362
 363         /* Enable 2D engine. */
 364         vga_out8 (0x3d4, 0x40 );
 365         vga_out8 (0x3d5, 0x01 );
 366
 367         savage_out32 (MONO_PAT_0, ~0);
 368         savage_out32 (MONO_PAT_1, ~0);
 369
 370         /* Setup plane masks */
 371         savage_out32 (0x8128, ~0 ); /* enable all write planes */
 372         savage_out32 (0x812C, ~0 ); /* enable all read planes */
 373         savage_out16 (0x8134, 0x27 );
 374         savage_out16 (0x8136, 0x07 );
 375
 376         /* Now set the GBD */
 377         par->bci_ptr = 0;
 378         par->SavageWaitFifo (par, 4);
 379
 380         BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD1 );
 381         BCI_SEND( 0 );
 382         BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD2 );
 383         BCI_SEND( GlobalBitmapDescriptor );
 384 }
 385
 386
 387 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
 388                             int min_n2, int max_n2, long freq_min,
 389                             long freq_max, unsigned int *mdiv,
 390                             unsigned int *ndiv, unsigned int *r)
 391 {
 392         long diff, best_diff;
 393         unsigned int m;
 394         unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
 395
 396         if (freq < freq_min / (1 << max_n2)) {
 397                 printk (KERN_ERR "invalid frequency %ld Khz\n", freq);
 398                 freq = freq_min / (1 << max_n2);
 399         }
 400         if (freq > freq_max / (1 << min_n2)) {
 401                 printk (KERN_ERR "invalid frequency %ld Khz\n", freq);
 402                 freq = freq_max / (1 << min_n2);
 403         }
 404
 405         /* work out suitable timings */
 406         best_diff = freq;
 407
 408         for (n2=min_n2; n2<=max_n2; n2++) {
 409                 for (n1=min_n1+2; n1<=max_n1+2; n1++) {
 410                         m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
 411                                 BASE_FREQ;
 412                         if (m < min_m+2 || m > 127+2)
 413                                 continue;
 414                         if ((m * BASE_FREQ >= freq_min * n1) &&
 415                             (m * BASE_FREQ <= freq_max * n1)) {
 416                                 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
 417                                 if (diff < 0)
 418                                         diff = -diff;
 419                                 if (diff < best_diff) {
 420                                         best_diff = diff;
 421                                         best_m = m;
 422                                         best_n1 = n1;
 423                                         best_n2 = n2;
 424                                 }
 425                         }
 426                 }
 427         }
 428
 429         *ndiv = best_n1 - 2;
 430         *r = best_n2;
 431         *mdiv = best_m - 2;
 432 }
 433
 434 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
 435                              int min_n2, int max_n2, long freq_min,
 436                              long freq_max, unsigned char *mdiv,
 437                              unsigned char *ndiv)
 438 {
 439         long diff, best_diff;
 440         unsigned int m;
 441         unsigned char n1, n2;
 442         unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
 443
 444         best_diff = freq;
 445
 446         for (n2 = min_n2; n2 <= max_n2; n2++) {
 447                 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
 448                         m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
 449                                 BASE_FREQ;
 450                         if (m < min_m + 2 || m > 127+2)
 451                                 continue;
 452                         if((m * BASE_FREQ >= freq_min * n1) &&
 453                            (m * BASE_FREQ <= freq_max * n1)) {
 454                                 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
 455                                 if(diff < 0)
 456                                         diff = -diff;
 457                                 if(diff < best_diff) {
 458                                         best_diff = diff;
 459                                         best_m = m;
 460                                         best_n1 = n1;
 461                                         best_n2 = n2;
 462                                 }
 463                         }
 464                 }
 465         }
 466
 467         if(max_n1 == 63)
 468                 *ndiv = (best_n1 - 2) | (best_n2 << 6);
 469         else
 470                 *ndiv = (best_n1 - 2) | (best_n2 << 5);
 471
 472         *mdiv = best_m - 2;
 473
 474         return 0;
 475 }
 476
 477 #ifdef SAVAGEFB_DEBUG
 478 /* This function is used to debug, it prints out the contents of s3 regs */
 479
 480 static void SavagePrintRegs(void)
 481 {
 482         unsigned char i;
 483         int vgaCRIndex = 0x3d4;
 484         int vgaCRReg = 0x3d5;
 485
 486         printk(KERN_DEBUG "SR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
 487                "xF" );
 488
 489         for( i = 0; i < 0x70; i++ ) {
 490                 if( !(i % 16) )
 491                         printk(KERN_DEBUG "\nSR%xx ", i >> 4 );
 492                 vga_out8( 0x3c4, i );
 493                 printk(KERN_DEBUG " %02x", vga_in8(0x3c5) );
 494         }
 495
 496         printk(KERN_DEBUG "\n\nCR    x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
 497                "xD xE xF" );
 498
 499         for( i = 0; i < 0xB7; i++ ) {
 500                 if( !(i % 16) )
 501                         printk(KERN_DEBUG "\nCR%xx ", i >> 4 );
 502                 vga_out8( vgaCRIndex, i );
 503                 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg) );
 504         }
 505
 506         printk(KERN_DEBUG "\n\n");
 507 }
 508 #endif
 509
 510 /* --------------------------------------------------------------------- */
 511
 512 static void savage_get_default_par(struct savagefb_par *par)
 513 {
 514         unsigned char cr3a, cr53, cr66;
 515
 516         vga_out16 (0x3d4, 0x4838);
 517         vga_out16 (0x3d4, 0xa039);
 518         vga_out16 (0x3c4, 0x0608);
 519
 520         vga_out8 (0x3d4, 0x66);
 521         cr66 = vga_in8 (0x3d5);
 522         vga_out8 (0x3d5, cr66 | 0x80);
 523         vga_out8 (0x3d4, 0x3a);
 524         cr3a = vga_in8 (0x3d5);
 525         vga_out8 (0x3d5, cr3a | 0x80);
 526         vga_out8 (0x3d4, 0x53);
 527         cr53 = vga_in8 (0x3d5);
 528         vga_out8 (0x3d5, cr53 & 0x7f);
 529
 530         vga_out8 (0x3d4, 0x66);
 531         vga_out8 (0x3d5, cr66);
 532         vga_out8 (0x3d4, 0x3a);
 533         vga_out8 (0x3d5, cr3a);
 534
 535         vga_out8 (0x3d4, 0x66);
 536         vga_out8 (0x3d5, cr66);
 537         vga_out8 (0x3d4, 0x3a);
 538         vga_out8 (0x3d5, cr3a);
 539
 540         /* unlock extended seq regs */
 541         vga_out8 (0x3c4, 0x08);
 542         par->SR08 = vga_in8 (0x3c5);
 543         vga_out8 (0x3c5, 0x06);
 544
 545         /* now save all the extended regs we need */
 546         vga_out8 (0x3d4, 0x31);
 547         par->CR31 = vga_in8 (0x3d5);
 548         vga_out8 (0x3d4, 0x32);
 549         par->CR32 = vga_in8 (0x3d5);
 550         vga_out8 (0x3d4, 0x34);
 551         par->CR34 = vga_in8 (0x3d5);
 552         vga_out8 (0x3d4, 0x36);
 553         par->CR36 = vga_in8 (0x3d5);
 554         vga_out8 (0x3d4, 0x3a);
 555         par->CR3A = vga_in8 (0x3d5);
 556         vga_out8 (0x3d4, 0x40);
 557         par->CR40 = vga_in8 (0x3d5);
 558         vga_out8 (0x3d4, 0x42);
 559         par->CR42 = vga_in8 (0x3d5);
 560         vga_out8 (0x3d4, 0x45);
 561         par->CR45 = vga_in8 (0x3d5);
 562         vga_out8 (0x3d4, 0x50);
 563         par->CR50 = vga_in8 (0x3d5);
 564         vga_out8 (0x3d4, 0x51);
 565         par->CR51 = vga_in8 (0x3d5);
 566         vga_out8 (0x3d4, 0x53);
 567         par->CR53 = vga_in8 (0x3d5);
 568         vga_out8 (0x3d4, 0x58);
 569         par->CR58 = vga_in8 (0x3d5);
 570         vga_out8 (0x3d4, 0x60);
 571         par->CR60 = vga_in8 (0x3d5);
 572         vga_out8 (0x3d4, 0x66);
 573         par->CR66 = vga_in8 (0x3d5);
 574         vga_out8 (0x3d4, 0x67);
 575         par->CR67 = vga_in8 (0x3d5);
 576         vga_out8 (0x3d4, 0x68);
 577         par->CR68 = vga_in8 (0x3d5);
 578         vga_out8 (0x3d4, 0x69);
 579         par->CR69 = vga_in8 (0x3d5);
 580         vga_out8 (0x3d4, 0x6f);
 581         par->CR6F = vga_in8 (0x3d5);
 582
 583         vga_out8 (0x3d4, 0x33);
 584         par->CR33 = vga_in8 (0x3d5);
 585         vga_out8 (0x3d4, 0x86);
 586         par->CR86 = vga_in8 (0x3d5);
 587         vga_out8 (0x3d4, 0x88);
 588         par->CR88 = vga_in8 (0x3d5);
 589         vga_out8 (0x3d4, 0x90);
 590         par->CR90 = vga_in8 (0x3d5);
 591         vga_out8 (0x3d4, 0x91);
 592         par->CR91 = vga_in8 (0x3d5);
 593         vga_out8 (0x3d4, 0xb0);
 594         par->CRB0 = vga_in8 (0x3d5) | 0x80;
 595
 596         /* extended mode timing regs */
 597         vga_out8 (0x3d4, 0x3b);
 598         par->CR3B = vga_in8 (0x3d5);
 599         vga_out8 (0x3d4, 0x3c);
 600         par->CR3C = vga_in8 (0x3d5);
 601         vga_out8 (0x3d4, 0x43);
 602         par->CR43 = vga_in8 (0x3d5);
 603         vga_out8 (0x3d4, 0x5d);
 604         par->CR5D = vga_in8 (0x3d5);
 605         vga_out8 (0x3d4, 0x5e);
 606         par->CR5E = vga_in8 (0x3d5);
 607         vga_out8 (0x3d4, 0x65);
 608         par->CR65 = vga_in8 (0x3d5);
 609
 610         /* save seq extended regs for DCLK PLL programming */
 611         vga_out8 (0x3c4, 0x0e);
 612         par->SR0E = vga_in8 (0x3c5);
 613         vga_out8 (0x3c4, 0x0f);
 614         par->SR0F = vga_in8 (0x3c5);
 615         vga_out8 (0x3c4, 0x10);
 616         par->SR10 = vga_in8 (0x3c5);
 617         vga_out8 (0x3c4, 0x11);
 618         par->SR11 = vga_in8 (0x3c5);
 619         vga_out8 (0x3c4, 0x12);
 620         par->SR12 = vga_in8 (0x3c5);
 621         vga_out8 (0x3c4, 0x13);
 622         par->SR13 = vga_in8 (0x3c5);
 623         vga_out8 (0x3c4, 0x29);
 624         par->SR29 = vga_in8 (0x3c5);
 625
 626         vga_out8 (0x3c4, 0x15);
 627         par->SR15 = vga_in8 (0x3c5);
 628         vga_out8 (0x3c4, 0x30);
 629         par->SR30 = vga_in8 (0x3c5);
 630         vga_out8 (0x3c4, 0x18);
 631         par->SR18 = vga_in8 (0x3c5);
 632
 633         /* Save flat panel expansion regsters. */
 634         if (par->chip == S3_SAVAGE_MX) {
 635                 int i;
 636
 637                 for (i = 0; i < 8; i++) {
 638                         vga_out8 (0x3c4, 0x54+i);
 639                         par->SR54[i] = vga_in8 (0x3c5);
 640                 }
 641         }
 642
 643         vga_out8 (0x3d4, 0x66);
 644         cr66 = vga_in8 (0x3d5);
 645         vga_out8 (0x3d5, cr66 | 0x80);
 646         vga_out8 (0x3d4, 0x3a);
 647         cr3a = vga_in8 (0x3d5);
 648         vga_out8 (0x3d5, cr3a | 0x80);
 649
 650         /* now save MIU regs */
 651         if (par->chip != S3_SAVAGE_MX) {
 652                 par->MMPR0 = savage_in32(FIFO_CONTROL_REG);
 653                 par->MMPR1 = savage_in32(MIU_CONTROL_REG);
 654                 par->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG);
 655                 par->MMPR3 = savage_in32(MISC_TIMEOUT_REG);
 656         }
 657
 658         vga_out8 (0x3d4, 0x3a);
 659         vga_out8 (0x3d5, cr3a);
 660         vga_out8 (0x3d4, 0x66);
 661         vga_out8 (0x3d5, cr66);
 662 }
 663
 664 static void savage_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
 665 {
 666         var->xres = var->xres_virtual = modedb->xres;
 667         var->yres = modedb->yres;
 668         if (var->yres_virtual < var->yres)
 669             var->yres_virtual = var->yres;
 670         var->xoffset = var->yoffset = 0;
 671         var->pixclock = modedb->pixclock;
 672         var->left_margin = modedb->left_margin;
 673         var->right_margin = modedb->right_margin;
 674         var->upper_margin = modedb->upper_margin;
 675         var->lower_margin = modedb->lower_margin;
 676         var->hsync_len = modedb->hsync_len;
 677         var->vsync_len = modedb->vsync_len;
 678         var->sync = modedb->sync;
 679         var->vmode = modedb->vmode;
 680 }
 681
 682 static int savagefb_check_var (struct fb_var_screeninfo   *var,
 683                                struct fb_info *info)
 684 {
 685         struct savagefb_par *par = (struct savagefb_par *)info->par;
 686         int memlen, vramlen, mode_valid = 0;
 687
 688         DBG("savagefb_check_var");
 689
 690         var->transp.offset = 0;
 691         var->transp.length = 0;
 692         switch (var->bits_per_pixel) {
 693         case 8:
 694                 var->red.offset = var->green.offset =
 695                         var->blue.offset = 0;
 696                 var->red.length = var->green.length =
 697                         var->blue.length = var->bits_per_pixel;
 698                 break;
 699         case 16:
 700                 var->red.offset = 11;
 701                 var->red.length = 5;
 702                 var->green.offset = 5;
 703                 var->green.length = 6;
 704                 var->blue.offset = 0;
 705                 var->blue.length = 5;
 706                 break;
 707         case 32:
 708                 var->transp.offset = 24;
 709                 var->transp.length = 8;
 710                 var->red.offset = 16;
 711                 var->red.length = 8;
 712                 var->green.offset = 8;
 713                 var->green.length = 8;
 714                 var->blue.offset = 0;
 715                 var->blue.length = 8;
 716                 break;
 717
 718         default:
 719                 return -EINVAL;
 720         }
 721
 722         if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
 723             !info->monspecs.dclkmax || !fb_validate_mode(var, info))
 724                 mode_valid = 1;
 725
 726         /* calculate modeline if supported by monitor */
 727         if (!mode_valid && info->monspecs.gtf) {
 728                 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
 729                         mode_valid = 1;
 730         }
 731
 732         if (!mode_valid) {
 733                 struct fb_videomode *mode;
 734
 735                 mode = fb_find_best_mode(var, &info->modelist);
 736                 if (mode) {
 737                         savage_update_var(var, mode);
 738                         mode_valid = 1;
 739                 }
 740         }
 741
 742         if (!mode_valid && info->monspecs.modedb_len)
 743                 return -EINVAL;
 744
 745         /* Is the mode larger than the LCD panel? */
 746         if (par->SavagePanelWidth &&
 747             (var->xres > par->SavagePanelWidth ||
 748              var->yres > par->SavagePanelHeight)) {
 749                 printk (KERN_INFO "Mode (%dx%d) larger than the LCD panel "
 750                         "(%dx%d)\n", var->xres,  var->yres,
 751                         par->SavagePanelWidth,
 752                         par->SavagePanelHeight);
 753                 return -1;
 754         }
 755
 756         if (var->yres_virtual < var->yres)
 757                 var->yres_virtual = var->yres;
 758         if (var->xres_virtual < var->xres)
 759                 var->xres_virtual = var->xres;
 760
 761         vramlen = info->fix.smem_len;
 762
 763         memlen = var->xres_virtual * var->bits_per_pixel *
 764                 var->yres_virtual / 8;
 765         if (memlen > vramlen) {
 766                 var->yres_virtual = vramlen * 8 /
 767                         (var->xres_virtual * var->bits_per_pixel);
 768                 memlen = var->xres_virtual * var->bits_per_pixel *
 769                         var->yres_virtual / 8;
 770         }
 771
 772         /* we must round yres/xres down, we already rounded y/xres_virtual up
 773            if it was possible. We should return -EINVAL, but I disagree */
 774         if (var->yres_virtual < var->yres)
 775                 var->yres = var->yres_virtual;
 776         if (var->xres_virtual < var->xres)
 777                 var->xres = var->xres_virtual;
 778         if (var->xoffset + var->xres > var->xres_virtual)
 779                 var->xoffset = var->xres_virtual - var->xres;
 780         if (var->yoffset + var->yres > var->yres_virtual)
 781                 var->yoffset = var->yres_virtual - var->yres;
 782
 783         return 0;
 784 }
 785
 786
 787 static int savagefb_decode_var (struct fb_var_screeninfo   *var,
 788                                 struct savagefb_par        *par)
 789 {
 790         struct xtimings timings;
 791         int width, dclk, i, j; /*, refresh; */
 792         unsigned int m, n, r;
 793         unsigned char tmp = 0;
 794         unsigned int pixclock = var->pixclock;
 795
 796         DBG("savagefb_decode_var");
 797
 798         memset (&timings, 0, sizeof(timings));
 799
 800         if (!pixclock) pixclock = 10000;        /* 10ns = 100MHz */
 801         timings.Clock = 1000000000 / pixclock;
 802         if (timings.Clock < 1) timings.Clock = 1;
 803         timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
 804         timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
 805         timings.HDisplay = var->xres;
 806         timings.HSyncStart = timings.HDisplay + var->right_margin;
 807         timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
 808         timings.HTotal = timings.HSyncEnd + var->left_margin;
 809         timings.VDisplay = var->yres;
 810         timings.VSyncStart = timings.VDisplay + var->lower_margin;
 811         timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
 812         timings.VTotal = timings.VSyncEnd + var->upper_margin;
 813         timings.sync = var->sync;
 814
 815
 816         par->depth  = var->bits_per_pixel;
 817         par->vwidth = var->xres_virtual;
 818
 819         if (var->bits_per_pixel == 16  &&  par->chip == S3_SAVAGE3D) {
 820                 timings.HDisplay *= 2;
 821                 timings.HSyncStart *= 2;
 822                 timings.HSyncEnd *= 2;
 823                 timings.HTotal *= 2;
 824         }
 825
 826         /*
 827          * This will allocate the datastructure and initialize all of the
 828          * generic VGA registers.
 829          */
 830         vgaHWInit (var, par, &timings);
 831
 832         /* We need to set CR67 whether or not we use the BIOS. */
 833
 834         dclk = timings.Clock;
 835         par->CR67 = 0x00;
 836
 837         switch( var->bits_per_pixel ) {
 838         case 8:
 839                 if( (par->chip == S3_SAVAGE2000) && (dclk >= 230000) )
 840                         par->CR67 = 0x10;       /* 8bpp, 2 pixels/clock */
 841                 else
 842                         par->CR67 = 0x00;       /* 8bpp, 1 pixel/clock */
 843                 break;
 844         case 15:
 845                 if ( S3_SAVAGE_MOBILE_SERIES(par->chip) ||
 846                      ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) )
 847                         par->CR67 = 0x30;       /* 15bpp, 2 pixel/clock */
 848                 else
 849                         par->CR67 = 0x20;       /* 15bpp, 1 pixels/clock */
 850                 break;
 851         case 16:
 852                 if( S3_SAVAGE_MOBILE_SERIES(par->chip) ||
 853                     ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) )
 854                         par->CR67 = 0x50;       /* 16bpp, 2 pixel/clock */
 855                 else
 856                         par->CR67 = 0x40;       /* 16bpp, 1 pixels/clock */
 857                 break;
 858         case 24:
 859                 par->CR67 = 0x70;
 860                 break;
 861         case 32:
 862                 par->CR67 = 0xd0;
 863                 break;
 864         }
 865
 866         /*
 867          * Either BIOS use is disabled, or we failed to find a suitable
 868          * match.  Fall back to traditional register-crunching.
 869          */
 870
 871         vga_out8 (0x3d4, 0x3a);
 872         tmp = vga_in8 (0x3d5);
 873         if (1 /*FIXME:psav->pci_burst*/)
 874                 par->CR3A = (tmp & 0x7f) | 0x15;
 875         else
 876                 par->CR3A = tmp | 0x95;
 877
 878         par->CR53 = 0x00;
 879         par->CR31 = 0x8c;
 880         par->CR66 = 0x89;
 881
 882         vga_out8 (0x3d4, 0x58);
 883         par->CR58 = vga_in8 (0x3d5) & 0x80;
 884         par->CR58 |= 0x13;
 885
 886         par->SR15 = 0x03 | 0x80;
 887         par->SR18 = 0x00;
 888         par->CR43 = par->CR45 = par->CR65 = 0x00;
 889
 890         vga_out8 (0x3d4, 0x40);
 891         par->CR40 = vga_in8 (0x3d5) & ~0x01;
 892
 893         par->MMPR0 = 0x010400;
 894         par->MMPR1 = 0x00;
 895         par->MMPR2 = 0x0808;
 896         par->MMPR3 = 0x08080810;
 897
 898         SavageCalcClock (dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
 899         /* m = 107; n = 4; r = 2; */
 900
 901         if (par->MCLK <= 0) {
 902                 par->SR10 = 255;
 903                 par->SR11 = 255;
 904         } else {
 905                 common_calc_clock (par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
 906                                    &par->SR11, &par->SR10);
 907                 /*      par->SR10 = 80; // MCLK == 286000 */
 908                 /*      par->SR11 = 125; */
 909         }
 910
 911         par->SR12 = (r << 6) | (n & 0x3f);
 912         par->SR13 = m & 0xff;
 913         par->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
 914
 915         if (var->bits_per_pixel < 24)
 916                 par->MMPR0 -= 0x8000;
 917         else
 918                 par->MMPR0 -= 0x4000;
 919
 920         if (timings.interlaced)
 921                 par->CR42 = 0x20;
 922         else
 923                 par->CR42 = 0x00;
 924
 925         par->CR34 = 0x10; /* display fifo */
 926
 927         i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
 928                 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
 929                 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
 930                 ((timings.HSyncStart & 0x800) >> 7);
 931
 932         if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
 933                 i |= 0x08;
 934         if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
 935                 i |= 0x20;
 936
 937         j = (par->CRTC[0] + ((i & 0x01) << 8) +
 938              par->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
 939
 940         if (j - (par->CRTC[4] + ((i & 0x10) << 4)) < 4) {
 941                 if (par->CRTC[4] + ((i & 0x10) << 4) + 4 <=
 942                     par->CRTC[0] + ((i & 0x01) << 8))
 943                         j = par->CRTC[4] + ((i & 0x10) << 4) + 4;
 944                 else
 945                         j = par->CRTC[0] + ((i & 0x01) << 8) + 1;
 946         }
 947
 948         par->CR3B = j & 0xff;
 949         i |= (j & 0x100) >> 2;
 950         par->CR3C = (par->CRTC[0] + ((i & 0x01) << 8)) / 2;
 951         par->CR5D = i;
 952         par->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
 953                 (((timings.VDisplay - 1) & 0x400) >> 9) |
 954                 (((timings.VSyncStart) & 0x400) >> 8) |
 955                 (((timings.VSyncStart) & 0x400) >> 6) | 0x40;
 956         width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
 957         par->CR91 = par->CRTC[19] = 0xff & width;
 958         par->CR51 = (0x300 & width) >> 4;
 959         par->CR90 = 0x80 | (width >> 8);
 960         par->MiscOutReg |= 0x0c;
 961
 962         /* Set frame buffer description. */
 963
 964         if (var->bits_per_pixel <= 8)
 965                 par->CR50 = 0;
 966         else if (var->bits_per_pixel <= 16)
 967                 par->CR50 = 0x10;
 968         else
 969                 par->CR50 = 0x30;
 970
 971         if (var->xres_virtual <= 640)
 972                 par->CR50 |= 0x40;
 973         else if (var->xres_virtual == 800)
 974                 par->CR50 |= 0x80;
 975         else if (var->xres_virtual == 1024)
 976                 par->CR50 |= 0x00;
 977         else if (var->xres_virtual == 1152)
 978                 par->CR50 |= 0x01;
 979         else if (var->xres_virtual == 1280)
 980                 par->CR50 |= 0xc0;
 981         else if (var->xres_virtual == 1600)
 982                 par->CR50 |= 0x81;
 983         else
 984                 par->CR50 |= 0xc1;      /* Use GBD */
 985
 986         if( par->chip == S3_SAVAGE2000 )
 987                 par->CR33 = 0x08;
 988         else
 989                 par->CR33 = 0x20;
 990
 991         par->CRTC[0x17] = 0xeb;
 992
 993         par->CR67 |= 1;
 994
 995         vga_out8(0x3d4, 0x36);
 996         par->CR36 = vga_in8 (0x3d5);
 997         vga_out8 (0x3d4, 0x68);
 998         par->CR68 = vga_in8 (0x3d5);
 999         par->CR69 = 0;
1000         vga_out8 (0x3d4, 0x6f);
1001         par->CR6F = vga_in8 (0x3d5);
1002         vga_out8 (0x3d4, 0x86);
1003         par->CR86 = vga_in8 (0x3d5);
1004         vga_out8 (0x3d4, 0x88);
1005         par->CR88 = vga_in8 (0x3d5) | 0x08;
1006         vga_out8 (0x3d4, 0xb0);
1007         par->CRB0 = vga_in8 (0x3d5) | 0x80;
1008
1009         return 0;
1010 }
1011
1012 /* --------------------------------------------------------------------- */
1013
1014 /*
1015  *    Set a single color register. Return != 0 for invalid regno.
1016  */
1017 static int savagefb_setcolreg(unsigned        regno,
1018                               unsigned        red,
1019                               unsigned        green,
1020                               unsigned        blue,
1021                               unsigned        transp,
1022                               struct fb_info *info)
1023 {
1024         struct savagefb_par *par = (struct savagefb_par *)info->par;
1025
1026         if (regno >= NR_PALETTE)
1027                 return -EINVAL;
1028
1029         par->palette[regno].red    = red;
1030         par->palette[regno].green  = green;
1031         par->palette[regno].blue   = blue;
1032         par->palette[regno].transp = transp;
1033
1034         switch (info->var.bits_per_pixel) {
1035         case 8:
1036                 vga_out8 (0x3c8, regno);
1037
1038                 vga_out8 (0x3c9, red   >> 10);
1039                 vga_out8 (0x3c9, green >> 10);
1040                 vga_out8 (0x3c9, blue  >> 10);
1041                 break;
1042
1043         case 16:
1044                 if (regno < 16)
1045                         ((u32 *)info->pseudo_palette)[regno] =
1046                                 ((red   & 0xf800)      ) |
1047                                 ((green & 0xfc00) >>  5) |
1048                                 ((blue  & 0xf800) >> 11);
1049                 break;
1050
1051         case 24:
1052                 if (regno < 16)
1053                         ((u32 *)info->pseudo_palette)[regno] =
1054                                 ((red    & 0xff00) <<  8) |
1055                                 ((green  & 0xff00)      ) |
1056                                 ((blue   & 0xff00) >>  8);
1057                 break;
1058         case 32:
1059                 if (regno < 16)
1060                         ((u32 *)info->pseudo_palette)[regno] =
1061                                 ((transp & 0xff00) << 16) |
1062                                 ((red    & 0xff00) <<  8) |
1063                                 ((green  & 0xff00)      ) |
1064                                 ((blue   & 0xff00) >>  8);
1065                 break;
1066
1067         default:
1068                 return 1;
1069         }
1070
1071         return 0;
1072 }
1073
1074 static void savagefb_set_par_int (struct savagefb_par  *par)
1075 {
1076         unsigned char tmp, cr3a, cr66, cr67;
1077
1078         DBG ("savagefb_set_par_int");
1079
1080         par->SavageWaitIdle (par);
1081
1082         vga_out8 (0x3c2, 0x23);
1083
1084         vga_out16 (0x3d4, 0x4838);
1085         vga_out16 (0x3d4, 0xa539);
1086         vga_out16 (0x3c4, 0x0608);
1087
1088         vgaHWProtect (par, 1);
1089
1090         /*
1091          * Some Savage/MX and /IX systems go nuts when trying to exit the
1092          * server after WindowMaker has displayed a gradient background.  I
1093          * haven't been able to find what causes it, but a non-destructive
1094          * switch to mode 3 here seems to eliminate the issue.
1095          */
1096
1097         VerticalRetraceWait();
1098         vga_out8 (0x3d4, 0x67);
1099         cr67 = vga_in8 (0x3d5);
1100         vga_out8 (0x3d5, cr67/*par->CR67*/ & ~0x0c); /* no STREAMS yet */
1101
1102         vga_out8 (0x3d4, 0x23);
1103         vga_out8 (0x3d5, 0x00);
1104         vga_out8 (0x3d4, 0x26);
1105         vga_out8 (0x3d5, 0x00);
1106
1107         /* restore extended regs */
1108         vga_out8 (0x3d4, 0x66);
1109         vga_out8 (0x3d5, par->CR66);
1110         vga_out8 (0x3d4, 0x3a);
1111         vga_out8 (0x3d5, par->CR3A);
1112         vga_out8 (0x3d4, 0x31);
1113         vga_out8 (0x3d5, par->CR31);
1114         vga_out8 (0x3d4, 0x32);
1115         vga_out8 (0x3d5, par->CR32);
1116         vga_out8 (0x3d4, 0x58);
1117         vga_out8 (0x3d5, par->CR58);
1118         vga_out8 (0x3d4, 0x53);
1119         vga_out8 (0x3d5, par->CR53 & 0x7f);
1120
1121         vga_out16 (0x3c4, 0x0608);
1122
1123         /* Restore DCLK registers. */
1124
1125         vga_out8 (0x3c4, 0x0e);
1126         vga_out8 (0x3c5, par->SR0E);
1127         vga_out8 (0x3c4, 0x0f);
1128         vga_out8 (0x3c5, par->SR0F);
1129         vga_out8 (0x3c4, 0x29);
1130         vga_out8 (0x3c5, par->SR29);
1131         vga_out8 (0x3c4, 0x15);
1132         vga_out8 (0x3c5, par->SR15);
1133
1134         /* Restore flat panel expansion regsters. */
1135         if( par->chip == S3_SAVAGE_MX ) {
1136                 int i;
1137
1138                 for( i = 0; i < 8; i++ ) {
1139                         vga_out8 (0x3c4, 0x54+i);
1140                         vga_out8 (0x3c5, par->SR54[i]);
1141                 }
1142         }
1143
1144         vgaHWRestore (par);
1145
1146         /* extended mode timing registers */
1147         vga_out8 (0x3d4, 0x53);
1148         vga_out8 (0x3d5, par->CR53);
1149         vga_out8 (0x3d4, 0x5d);
1150         vga_out8 (0x3d5, par->CR5D);
1151         vga_out8 (0x3d4, 0x5e);
1152         vga_out8 (0x3d5, par->CR5E);
1153         vga_out8 (0x3d4, 0x3b);
1154         vga_out8 (0x3d5, par->CR3B);
1155         vga_out8 (0x3d4, 0x3c);
1156         vga_out8 (0x3d5, par->CR3C);
1157         vga_out8 (0x3d4, 0x43);
1158         vga_out8 (0x3d5, par->CR43);
1159         vga_out8 (0x3d4, 0x65);
1160         vga_out8 (0x3d5, par->CR65);
1161
1162         /* restore the desired video mode with cr67 */
1163         vga_out8 (0x3d4, 0x67);
1164         /* following part not present in X11 driver */
1165         cr67 = vga_in8 (0x3d5) & 0xf;
1166         vga_out8 (0x3d5, 0x50 | cr67);
1167         udelay (10000);
1168         vga_out8 (0x3d4, 0x67);
1169         /* end of part */
1170         vga_out8 (0x3d5, par->CR67 & ~0x0c);
1171
1172         /* other mode timing and extended regs */
1173         vga_out8 (0x3d4, 0x34);
1174         vga_out8 (0x3d5, par->CR34);
1175         vga_out8 (0x3d4, 0x40);
1176         vga_out8 (0x3d5, par->CR40);
1177         vga_out8 (0x3d4, 0x42);
1178         vga_out8 (0x3d5, par->CR42);
1179         vga_out8 (0x3d4, 0x45);
1180         vga_out8 (0x3d5, par->CR45);
1181         vga_out8 (0x3d4, 0x50);
1182         vga_out8 (0x3d5, par->CR50);
1183         vga_out8 (0x3d4, 0x51);
1184         vga_out8 (0x3d5, par->CR51);
1185
1186         /* memory timings */
1187         vga_out8 (0x3d4, 0x36);
1188         vga_out8 (0x3d5, par->CR36);
1189         vga_out8 (0x3d4, 0x60);
1190         vga_out8 (0x3d5, par->CR60);
1191         vga_out8 (0x3d4, 0x68);
1192         vga_out8 (0x3d5, par->CR68);
1193         vga_out8 (0x3d4, 0x69);
1194         vga_out8 (0x3d5, par->CR69);
1195         vga_out8 (0x3d4, 0x6f);
1196         vga_out8 (0x3d5, par->CR6F);
1197
1198         vga_out8 (0x3d4, 0x33);
1199         vga_out8 (0x3d5, par->CR33);
1200         vga_out8 (0x3d4, 0x86);
1201         vga_out8 (0x3d5, par->CR86);
1202         vga_out8 (0x3d4, 0x88);
1203         vga_out8 (0x3d5, par->CR88);
1204         vga_out8 (0x3d4, 0x90);
1205         vga_out8 (0x3d5, par->CR90);
1206         vga_out8 (0x3d4, 0x91);
1207         vga_out8 (0x3d5, par->CR91);
1208
1209         if (par->chip == S3_SAVAGE4) {
1210                 vga_out8 (0x3d4, 0xb0);
1211                 vga_out8 (0x3d5, par->CRB0);
1212         }
1213
1214         vga_out8 (0x3d4, 0x32);
1215         vga_out8 (0x3d5, par->CR32);
1216
1217         /* unlock extended seq regs */
1218         vga_out8 (0x3c4, 0x08);
1219         vga_out8 (0x3c5, 0x06);
1220
1221         /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1222          * that we should leave the default SR10 and SR11 values there.
1223          */
1224         if (par->SR10 != 255) {
1225                 vga_out8 (0x3c4, 0x10);
1226                 vga_out8 (0x3c5, par->SR10);
1227                 vga_out8 (0x3c4, 0x11);
1228                 vga_out8 (0x3c5, par->SR11);
1229         }
1230
1231         /* restore extended seq regs for dclk */
1232         vga_out8 (0x3c4, 0x0e);
1233         vga_out8 (0x3c5, par->SR0E);
1234         vga_out8 (0x3c4, 0x0f);
1235         vga_out8 (0x3c5, par->SR0F);
1236         vga_out8 (0x3c4, 0x12);
1237         vga_out8 (0x3c5, par->SR12);
1238         vga_out8 (0x3c4, 0x13);
1239         vga_out8 (0x3c5, par->SR13);
1240         vga_out8 (0x3c4, 0x29);
1241         vga_out8 (0x3c5, par->SR29);
1242
1243         vga_out8 (0x3c4, 0x18);
1244         vga_out8 (0x3c5, par->SR18);
1245
1246         /* load new m, n pll values for dclk & mclk */
1247         vga_out8 (0x3c4, 0x15);
1248         tmp = vga_in8 (0x3c5) & ~0x21;
1249
1250         vga_out8 (0x3c5, tmp | 0x03);
1251         vga_out8 (0x3c5, tmp | 0x23);
1252         vga_out8 (0x3c5, tmp | 0x03);
1253         vga_out8 (0x3c5, par->SR15);
1254         udelay (100);
1255
1256         vga_out8 (0x3c4, 0x30);
1257         vga_out8 (0x3c5, par->SR30);
1258         vga_out8 (0x3c4, 0x08);
1259         vga_out8 (0x3c5, par->SR08);
1260
1261         /* now write out cr67 in full, possibly starting STREAMS */
1262         VerticalRetraceWait();
1263         vga_out8 (0x3d4, 0x67);
1264         vga_out8 (0x3d5, par->CR67);
1265
1266         vga_out8 (0x3d4, 0x66);
1267         cr66 = vga_in8 (0x3d5);
1268         vga_out8 (0x3d5, cr66 | 0x80);
1269         vga_out8 (0x3d4, 0x3a);
1270         cr3a = vga_in8 (0x3d5);
1271         vga_out8 (0x3d5, cr3a | 0x80);
1272
1273         if (par->chip != S3_SAVAGE_MX) {
1274                 VerticalRetraceWait();
1275                 savage_out32 (FIFO_CONTROL_REG, par->MMPR0);
1276                 par->SavageWaitIdle (par);
1277                 savage_out32 (MIU_CONTROL_REG, par->MMPR1);
1278                 par->SavageWaitIdle (par);
1279                 savage_out32 (STREAMS_TIMEOUT_REG, par->MMPR2);
1280                 par->SavageWaitIdle (par);
1281                 savage_out32 (MISC_TIMEOUT_REG, par->MMPR3);
1282         }
1283
1284         vga_out8 (0x3d4, 0x66);
1285         vga_out8 (0x3d5, cr66);
1286         vga_out8 (0x3d4, 0x3a);
1287         vga_out8 (0x3d5, cr3a);
1288
1289         SavageSetup2DEngine (par);
1290         vgaHWProtect (par, 0);
1291 }
1292
1293 static void savagefb_update_start (struct savagefb_par      *par,
1294                                    struct fb_var_screeninfo *var)
1295 {
1296         int base;
1297
1298         base = ((var->yoffset * var->xres_virtual + (var->xoffset & ~1))
1299                 * ((var->bits_per_pixel+7) / 8)) >> 2;
1300
1301         /* now program the start address registers */
1302         vga_out16(0x3d4, (base & 0x00ff00) | 0x0c);
1303         vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d);
1304         vga_out8 (0x3d4, 0x69);
1305         vga_out8 (0x3d5, (base & 0x7f0000) >> 16);
1306 }
1307
1308
1309 static void savagefb_set_fix(struct fb_info *info)
1310 {
1311         info->fix.line_length = info->var.xres_virtual *
1312                 info->var.bits_per_pixel / 8;
1313
1314         if (info->var.bits_per_pixel == 8)
1315                 info->fix.visual      = FB_VISUAL_PSEUDOCOLOR;
1316         else
1317                 info->fix.visual      = FB_VISUAL_TRUECOLOR;
1318 }
1319
1320 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1321 static void savagefb_set_clip(struct fb_info *info)
1322 {
1323     struct savagefb_par *par = (struct savagefb_par *)info->par;
1324     int cmd;
1325
1326     cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
1327     par->bci_ptr = 0;
1328     par->SavageWaitFifo(par,3);
1329     BCI_SEND(cmd);
1330     BCI_SEND(BCI_CLIP_TL(0, 0));
1331     BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
1332 }
1333 #endif
1334
1335 static int savagefb_set_par (struct fb_info *info)
1336 {
1337         struct savagefb_par *par = (struct savagefb_par *)info->par;
1338         struct fb_var_screeninfo *var = &info->var;
1339         int err;
1340
1341         DBG("savagefb_set_par");
1342         err = savagefb_decode_var (var, par);
1343         if (err)
1344                 return err;
1345
1346         if (par->dacSpeedBpp <= 0) {
1347                 if (var->bits_per_pixel > 24)
1348                         par->dacSpeedBpp = par->clock[3];
1349                 else if (var->bits_per_pixel >= 24)
1350                         par->dacSpeedBpp = par->clock[2];
1351                 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
1352                         par->dacSpeedBpp = par->clock[1];
1353                 else if (var->bits_per_pixel <= 8)
1354                         par->dacSpeedBpp = par->clock[0];
1355         }
1356
1357         /* Set ramdac limits */
1358         par->maxClock = par->dacSpeedBpp;
1359         par->minClock = 10000;
1360
1361         savagefb_set_par_int (par);
1362         savagefb_update_start (par, var);
1363         fb_set_cmap (&info->cmap, info);
1364         savagefb_set_fix(info);
1365         savagefb_set_clip(info);
1366
1367         SavagePrintRegs();
1368         return 0;
1369 }
1370
1371 /*
1372  *    Pan or Wrap the Display
1373  */
1374 static int savagefb_pan_display (struct fb_var_screeninfo *var,
1375                                  struct fb_info           *info)
1376 {
1377         struct savagefb_par *par = (struct savagefb_par *)info->par;
1378         u_int y_bottom;
1379
1380         y_bottom = var->yoffset;
1381
1382         if (!(var->vmode & FB_VMODE_YWRAP))
1383                 y_bottom += var->yres;
1384
1385         if (var->xoffset > (var->xres_virtual - var->xres))
1386                 return -EINVAL;
1387         if (y_bottom > info->var.yres_virtual)
1388                 return -EINVAL;
1389
1390         savagefb_update_start (par, var);
1391
1392         info->var.xoffset = var->xoffset;
1393         info->var.yoffset = var->yoffset;
1394
1395         if (var->vmode & FB_VMODE_YWRAP)
1396                 info->var.vmode |= FB_VMODE_YWRAP;
1397         else
1398                 info->var.vmode &= ~FB_VMODE_YWRAP;
1399
1400         return 0;
1401 }
1402
1403 static int savagefb_blank(int blank, struct fb_info *info)
1404 {
1405         struct savagefb_par *par = info->par;
1406         u8 sr8 = 0, srd = 0;
1407
1408         if (par->display_type == DISP_CRT) {
1409                 vga_out8(0x3c4, 0x08);
1410                 sr8 = vga_in8(0x3c5);
1411                 sr8 |= 0x06;
1412                 vga_out8(0x3c5, sr8);
1413                 vga_out8(0x3c4, 0x0d);
1414                 srd = vga_in8(0x3c5);
1415                 srd &= 0x03;
1416
1417                 switch (blank) {
1418                 case FB_BLANK_UNBLANK:
1419                 case FB_BLANK_NORMAL:
1420                         break;
1421                 case FB_BLANK_VSYNC_SUSPEND:
1422                         srd |= 0x10;
1423                         break;
1424                 case FB_BLANK_HSYNC_SUSPEND:
1425                         srd |= 0x40;
1426                         break;
1427                 case FB_BLANK_POWERDOWN:
1428                         srd |= 0x50;
1429                         break;
1430                 }
1431
1432                 vga_out8(0x3c4, 0x0d);
1433                 vga_out8(0x3c5, srd);
1434         }
1435
1436         if (par->display_type == DISP_LCD ||
1437             par->display_type == DISP_DFP) {
1438                 switch(blank) {
1439                 case FB_BLANK_UNBLANK:
1440                 case FB_BLANK_NORMAL:
1441                         vga_out8(0x3c4, 0x31); /* SR31 bit 4 - FP enable */
1442                         vga_out8(0x3c5, vga_in8(0x3c5) | 0x10);
1443                         break;
1444                 case FB_BLANK_VSYNC_SUSPEND:
1445                 case FB_BLANK_HSYNC_SUSPEND:
1446                 case FB_BLANK_POWERDOWN:
1447                         vga_out8(0x3c4, 0x31); /* SR31 bit 4 - FP enable */
1448                         vga_out8(0x3c5, vga_in8(0x3c5) & ~0x10);
1449                         break;
1450                 }
1451         }
1452
1453         return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1454 }
1455
1456 static struct fb_ops savagefb_ops = {
1457         .owner          = THIS_MODULE,
1458         .fb_check_var   = savagefb_check_var,
1459         .fb_set_par     = savagefb_set_par,
1460         .fb_setcolreg   = savagefb_setcolreg,
1461         .fb_pan_display = savagefb_pan_display,
1462         .fb_blank       = savagefb_blank,
1463 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1464         .fb_fillrect    = savagefb_fillrect,
1465         .fb_copyarea    = savagefb_copyarea,
1466         .fb_imageblit   = savagefb_imageblit,
1467         .fb_sync        = savagefb_sync,
1468 #else
1469         .fb_fillrect    = cfb_fillrect,
1470         .fb_copyarea    = cfb_copyarea,
1471         .fb_imageblit   = cfb_imageblit,
1472 #endif
1473         .fb_cursor      = soft_cursor,
1474 };
1475
1476 /* --------------------------------------------------------------------- */
1477
1478 static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = {
1479         .accel_flags =  FB_ACCELF_TEXT,
1480         .xres =         800,
1481         .yres =         600,
1482         .xres_virtual =  800,
1483         .yres_virtual =  600,
1484         .bits_per_pixel = 8,
1485         .pixclock =     25000,
1486         .left_margin =  88,
1487         .right_margin = 40,
1488         .upper_margin = 23,
1489         .lower_margin = 1,
1490         .hsync_len =    128,
1491         .vsync_len =    4,
1492         .sync =         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1493         .vmode =        FB_VMODE_NONINTERLACED
1494 };
1495
1496 static void savage_enable_mmio (struct savagefb_par *par)
1497 {
1498         unsigned char val;
1499
1500         DBG ("savage_enable_mmio\n");
1501
1502         val = vga_in8 (0x3c3);
1503         vga_out8 (0x3c3, val | 0x01);
1504         val = vga_in8 (0x3cc);
1505         vga_out8 (0x3c2, val | 0x01);
1506
1507         if (par->chip >= S3_SAVAGE4) {
1508                 vga_out8 (0x3d4, 0x40);
1509                 val = vga_in8 (0x3d5);
1510                 vga_out8 (0x3d5, val | 1);
1511         }
1512 }
1513
1514
1515 static void savage_disable_mmio (struct savagefb_par *par)
1516 {
1517         unsigned char val;
1518
1519         DBG ("savage_disable_mmio\n");
1520
1521         if(par->chip >= S3_SAVAGE4 ) {
1522                 vga_out8 (0x3d4, 0x40);
1523                 val = vga_in8 (0x3d5);
1524                 vga_out8 (0x3d5, val | 1);
1525         }
1526 }
1527
1528
1529 static int __devinit savage_map_mmio (struct fb_info *info)
1530 {
1531         struct savagefb_par *par = (struct savagefb_par *)info->par;
1532         DBG ("savage_map_mmio");
1533
1534         if (S3_SAVAGE3D_SERIES (par->chip))
1535                 par->mmio.pbase = pci_resource_start (par->pcidev, 0) +
1536                         SAVAGE_NEWMMIO_REGBASE_S3;
1537         else
1538                 par->mmio.pbase = pci_resource_start (par->pcidev, 0) +
1539                         SAVAGE_NEWMMIO_REGBASE_S4;
1540
1541         par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1542
1543         par->mmio.vbase = ioremap (par->mmio.pbase, par->mmio.len);
1544         if (!par->mmio.vbase) {
1545                 printk ("savagefb: unable to map memory mapped IO\n");
1546                 return -ENOMEM;
1547         } else
1548                 printk (KERN_INFO "savagefb: mapped io at %p\n",
1549                         par->mmio.vbase);
1550
1551         info->fix.mmio_start = par->mmio.pbase;
1552         info->fix.mmio_len   = par->mmio.len;
1553
1554         par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1555         par->bci_ptr  = 0;
1556
1557         savage_enable_mmio (par);
1558
1559         return 0;
1560 }
1561
1562 static void __devinit savage_unmap_mmio (struct fb_info *info)
1563 {
1564         struct savagefb_par *par = (struct savagefb_par *)info->par;
1565         DBG ("savage_unmap_mmio");
1566
1567         savage_disable_mmio(par);
1568
1569         if (par->mmio.vbase) {
1570                 iounmap(par->mmio.vbase);
1571                 par->mmio.vbase = NULL;
1572         }
1573 }
1574
1575 static int __devinit savage_map_video (struct fb_info *info,
1576                                        int video_len)
1577 {
1578         struct savagefb_par *par = (struct savagefb_par *)info->par;
1579         int resource;
1580
1581         DBG("savage_map_video");
1582
1583         if (S3_SAVAGE3D_SERIES (par->chip))
1584                 resource = 0;
1585         else
1586                 resource = 1;
1587
1588         par->video.pbase = pci_resource_start (par->pcidev, resource);
1589         par->video.len   = video_len;
1590         par->video.vbase = ioremap (par->video.pbase, par->video.len);
1591
1592         if (!par->video.vbase) {
1593                 printk ("savagefb: unable to map screen memory\n");
1594                 return -ENOMEM;
1595         } else
1596                 printk (KERN_INFO "savagefb: mapped framebuffer at %p, "
1597                         "pbase == %x\n", par->video.vbase, par->video.pbase);
1598
1599         info->fix.smem_start = par->video.pbase;
1600         info->fix.smem_len   = par->video.len - par->cob_size;
1601         info->screen_base    = par->video.vbase;
1602
1603 #ifdef CONFIG_MTRR
1604         par->video.mtrr = mtrr_add (par->video.pbase, video_len,
1605                                      MTRR_TYPE_WRCOMB, 1);
1606 #endif
1607
1608         /* Clear framebuffer, it's all white in memory after boot */
1609         memset_io (par->video.vbase, 0, par->video.len);
1610
1611         return 0;
1612 }
1613
1614 static void __devinit savage_unmap_video (struct fb_info *info)
1615 {
1616         struct savagefb_par *par = (struct savagefb_par *)info->par;
1617
1618         DBG("savage_unmap_video");
1619
1620         if (par->video.vbase) {
1621 #ifdef CONFIG_MTRR
1622                 mtrr_del (par->video.mtrr, par->video.pbase, par->video.len);
1623 #endif
1624
1625                 iounmap (par->video.vbase);
1626                 par->video.vbase = NULL;
1627                 info->screen_base = NULL;
1628         }
1629 }
1630
1631 static int __devinit savage_init_hw (struct savagefb_par *par)
1632 {
1633         unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
1634
1635         static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
1636         static unsigned char RamSavage4[] =  { 2, 4, 8, 12, 16, 32, 64, 32 };
1637         static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1638         static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1639         int videoRam, videoRambytes, dvi;
1640
1641         DBG("savage_init_hw");
1642
1643         /* unprotect CRTC[0-7] */
1644         vga_out8(0x3d4, 0x11);
1645         tmp = vga_in8(0x3d5);
1646         vga_out8(0x3d5, tmp & 0x7f);
1647
1648         /* unlock extended regs */
1649         vga_out16(0x3d4, 0x4838);
1650         vga_out16(0x3d4, 0xa039);
1651         vga_out16(0x3c4, 0x0608);
1652
1653         vga_out8(0x3d4, 0x40);
1654         tmp = vga_in8(0x3d5);
1655         vga_out8(0x3d5, tmp & ~0x01);
1656
1657         /* unlock sys regs */
1658         vga_out8(0x3d4, 0x38);
1659         vga_out8(0x3d5, 0x48);
1660
1661         /* Unlock system registers. */
1662         vga_out16(0x3d4, 0x4838);
1663
1664         /* Next go on to detect amount of installed ram */
1665
1666         vga_out8(0x3d4, 0x36);            /* for register CR36 (CONFG_REG1), */
1667         config1 = vga_in8(0x3d5);           /* get amount of vram installed */
1668
1669         /* Compute the amount of video memory and offscreen memory. */
1670
1671         switch  (par->chip) {
1672         case S3_SAVAGE3D:
1673                 videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024;
1674                 break;
1675
1676         case S3_SAVAGE4:
1677                 /*
1678                  * The Savage4 has one ugly special case to consider.  On
1679                  * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1680                  * when it really means 8MB.  Why do it the same when you
1681                  * can do it different...
1682                  */
1683                 vga_out8(0x3d4, 0x68);  /* memory control 1 */
1684                 if( (vga_in8(0x3d5) & 0xC0) == (0x01 << 6) )
1685                         RamSavage4[1] = 8;
1686
1687                 /*FALLTHROUGH*/
1688
1689         case S3_SAVAGE2000:
1690                 videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024;
1691                 break;
1692
1693         case S3_SAVAGE_MX:
1694         case S3_SUPERSAVAGE:
1695                 videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024;
1696                 break;
1697
1698         case S3_PROSAVAGE:
1699                 videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024;
1700                 break;
1701
1702         default:
1703                 /* How did we get here? */
1704                 videoRam = 0;
1705                 break;
1706         }
1707
1708         videoRambytes = videoRam * 1024;
1709
1710         printk (KERN_INFO "savagefb: probed videoram:  %dk\n", videoRam);
1711
1712         /* reset graphics engine to avoid memory corruption */
1713         vga_out8 (0x3d4, 0x66);
1714         cr66 = vga_in8 (0x3d5);
1715         vga_out8 (0x3d5, cr66 | 0x02);
1716         udelay (10000);
1717
1718         vga_out8 (0x3d4, 0x66);
1719         vga_out8 (0x3d5, cr66 & ~0x02); /* clear reset flag */
1720         udelay (10000);
1721
1722
1723         /*
1724          * reset memory interface, 3D engine, AGP master, PCI master,
1725          * master engine unit, motion compensation/LPB
1726          */
1727         vga_out8 (0x3d4, 0x3f);
1728         cr3f = vga_in8 (0x3d5);
1729         vga_out8 (0x3d5, cr3f | 0x08);
1730         udelay (10000);
1731
1732         vga_out8 (0x3d4, 0x3f);
1733         vga_out8 (0x3d5, cr3f & ~0x08); /* clear reset flags */
1734         udelay (10000);
1735
1736         /* Savage ramdac speeds */
1737         par->numClocks = 4;
1738         par->clock[0] = 250000;
1739         par->clock[1] = 250000;
1740         par->clock[2] = 220000;
1741         par->clock[3] = 220000;
1742
1743         /* detect current mclk */
1744         vga_out8(0x3c4, 0x08);
1745         sr8 = vga_in8(0x3c5);
1746         vga_out8(0x3c5, 0x06);
1747         vga_out8(0x3c4, 0x10);
1748         n = vga_in8(0x3c5);
1749         vga_out8(0x3c4, 0x11);
1750         m = vga_in8(0x3c5);
1751         vga_out8(0x3c4, 0x08);
1752         vga_out8(0x3c5, sr8);
1753         m &= 0x7f;
1754         n1 = n & 0x1f;
1755         n2 = (n >> 5) & 0x03;
1756         par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1757         printk (KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
1758                 par->MCLK);
1759
1760         /* check for DVI/flat panel */
1761         dvi = 0;
1762
1763         if (par->chip == S3_SAVAGE4) {
1764                 unsigned char sr30 = 0x00;
1765
1766                 vga_out8(0x3c4, 0x30);
1767                 /* clear bit 1 */
1768                 vga_out8(0x3c5, vga_in8(0x3c5) & ~0x02);
1769                 sr30 = vga_in8(0x3c5);
1770                 if (sr30 & 0x02 /*0x04 */) {
1771                         dvi = 1;
1772                         printk("savagefb: Digital Flat Panel Detected\n");
1773                 }
1774         }
1775
1776         if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1777             (S3_MOBILE_TWISTER_SERIES(par->chip) && !par->crtonly))
1778                 par->display_type = DISP_LCD;
1779         else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1780                 par->display_type = DISP_DFP;
1781         else
1782                 par->display_type = DISP_CRT;
1783
1784         /* Check LCD panel parrmation */
1785
1786         if (par->chip == S3_SAVAGE_MX) {
1787                 unsigned char cr6b = VGArCR( 0x6b );
1788
1789                 int panelX = (VGArSEQ (0x61) +
1790                               ((VGArSEQ (0x66) & 0x02) << 7) + 1) * 8;
1791                 int panelY = (VGArSEQ (0x69) +
1792                               ((VGArSEQ (0x6e) & 0x70) << 4) + 1);
1793
1794                 char * sTechnology = "Unknown";
1795
1796                 /* OK, I admit it.  I don't know how to limit the max dot clock
1797                  * for LCD panels of various sizes.  I thought I copied the
1798                  * formula from the BIOS, but many users have parrmed me of
1799                  * my folly.
1800                  *
1801                  * Instead, I'll abandon any attempt to automatically limit the
1802                  * clock, and add an LCDClock option to XF86Config.  Some day,
1803                  * I should come back to this.
1804                  */
1805
1806                 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
1807                         ActiveCRT = 0x01,
1808                         ActiveLCD = 0x02,
1809                         ActiveTV = 0x04,
1810                         ActiveCRT2 = 0x20,
1811                         ActiveDUO = 0x80
1812                 };
1813
1814                 if ((VGArSEQ (0x39) & 0x03) == 0) {
1815                         sTechnology = "TFT";
1816                 } else if ((VGArSEQ (0x30) & 0x01) == 0) {
1817                         sTechnology = "DSTN";
1818                 } else  {
1819                         sTechnology = "STN";
1820                 }
1821
1822                 printk (KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
1823                         panelX, panelY, sTechnology,
1824                         cr6b & ActiveLCD ? "and active" : "but not active");
1825
1826                 if( cr6b & ActiveLCD )  {
1827                         /*
1828                          * If the LCD is active and panel expansion is enabled,
1829                          * we probably want to kill the HW cursor.
1830                          */
1831
1832                         printk (KERN_INFO "savagefb: Limiting video mode to "
1833                                 "%dx%d\n", panelX, panelY );
1834
1835                         par->SavagePanelWidth = panelX;
1836                         par->SavagePanelHeight = panelY;
1837
1838                 } else
1839                         par->display_type = DISP_CRT;
1840         }
1841
1842         savage_get_default_par (par);
1843
1844         if( S3_SAVAGE4_SERIES(par->chip) ) {
1845                 /*
1846                  * The Savage4 and ProSavage have COB coherency bugs which
1847                  * render the buffer useless.  We disable it.
1848                  */
1849                 par->cob_index = 2;
1850                 par->cob_size = 0x8000 << par->cob_index;
1851                 par->cob_offset = videoRambytes;
1852         } else {
1853                 /* We use 128kB for the COB on all chips. */
1854
1855                 par->cob_index  = 7;
1856                 par->cob_size   = 0x400 << par->cob_index;
1857                 par->cob_offset = videoRambytes - par->cob_size;
1858         }
1859
1860         return videoRambytes;
1861 }
1862
1863 static int __devinit savage_init_fb_info (struct fb_info *info,
1864                                           struct pci_dev *dev,
1865                                           const struct pci_device_id *id)
1866 {
1867         struct savagefb_par *par = (struct savagefb_par *)info->par;
1868         int err = 0;
1869
1870         par->pcidev  = dev;
1871
1872         info->fix.type     = FB_TYPE_PACKED_PIXELS;
1873         info->fix.type_aux         = 0;
1874         info->fix.xpanstep         = 2;
1875         info->fix.ypanstep         = 1;
1876         info->fix.ywrapstep   = 0;
1877         info->fix.accel       = id->driver_data;
1878
1879         switch (info->fix.accel) {
1880         case FB_ACCEL_SUPERSAVAGE:
1881                 par->chip = S3_SUPERSAVAGE;
1882                 snprintf (info->fix.id, 16, "SuperSavage");
1883                 break;
1884         case FB_ACCEL_SAVAGE4:
1885                 par->chip = S3_SAVAGE4;
1886                 snprintf (info->fix.id, 16, "Savage4");
1887                 break;
1888         case FB_ACCEL_SAVAGE3D:
1889                 par->chip = S3_SAVAGE3D;
1890                 snprintf (info->fix.id, 16, "Savage3D");
1891                 break;
1892         case FB_ACCEL_SAVAGE3D_MV:
1893                 par->chip = S3_SAVAGE3D;
1894                 snprintf (info->fix.id, 16, "Savage3D-MV");
1895                 break;
1896         case FB_ACCEL_SAVAGE2000:
1897                 par->chip = S3_SAVAGE2000;
1898                 snprintf (info->fix.id, 16, "Savage2000");
1899                 break;
1900         case FB_ACCEL_SAVAGE_MX_MV:
1901                 par->chip = S3_SAVAGE_MX;
1902                 snprintf (info->fix.id, 16, "Savage/MX-MV");
1903                 break;
1904         case FB_ACCEL_SAVAGE_MX:
1905                 par->chip = S3_SAVAGE_MX;
1906                 snprintf (info->fix.id, 16, "Savage/MX");
1907                 break;
1908         case FB_ACCEL_SAVAGE_IX_MV:
1909                 par->chip = S3_SAVAGE_MX;
1910                 snprintf (info->fix.id, 16, "Savage/IX-MV");
1911                 break;
1912         case FB_ACCEL_SAVAGE_IX:
1913                 par->chip = S3_SAVAGE_MX;
1914                 snprintf (info->fix.id, 16, "Savage/IX");
1915                 break;
1916         case FB_ACCEL_PROSAVAGE_PM:
1917                 par->chip = S3_PROSAVAGE;
1918                 snprintf (info->fix.id, 16, "ProSavagePM");
1919                 break;
1920         case FB_ACCEL_PROSAVAGE_KM:
1921                 par->chip = S3_PROSAVAGE;
1922                 snprintf (info->fix.id, 16, "ProSavageKM");
1923                 break;
1924         case FB_ACCEL_S3TWISTER_P:
1925                 par->chip = S3_TWISTER;
1926                 snprintf (info->fix.id, 16, "TwisterP");
1927                 break;
1928         case FB_ACCEL_S3TWISTER_K:
1929                 par->chip = S3_TWISTER;
1930                 snprintf (info->fix.id, 16, "TwisterK");
1931                 break;
1932         case FB_ACCEL_PROSAVAGE_DDR:
1933                 par->chip = S3_PROSAVAGEDDR;
1934                 snprintf (info->fix.id, 16, "ProSavageDDR");
1935                 break;
1936         case FB_ACCEL_PROSAVAGE_DDRK:
1937                 par->chip = S3_PROSAVAGE;
1938                 snprintf (info->fix.id, 16, "ProSavage8");
1939                 break;
1940         }
1941
1942         if (S3_SAVAGE3D_SERIES(par->chip)) {
1943                 par->SavageWaitIdle = savage3D_waitidle;
1944                 par->SavageWaitFifo = savage3D_waitfifo;
1945         } else if (S3_SAVAGE4_SERIES(par->chip) ||
1946                    S3_SUPERSAVAGE == par->chip) {
1947                 par->SavageWaitIdle = savage4_waitidle;
1948                 par->SavageWaitFifo = savage4_waitfifo;
1949         } else {
1950                 par->SavageWaitIdle = savage2000_waitidle;
1951                 par->SavageWaitFifo = savage2000_waitfifo;
1952         }
1953
1954         info->var.nonstd      = 0;
1955         info->var.activate    = FB_ACTIVATE_NOW;
1956         info->var.width       = -1;
1957         info->var.height      = -1;
1958         info->var.accel_flags = 0;
1959
1960         info->fbops          = &savagefb_ops;
1961         info->flags          = FBINFO_DEFAULT |
1962                                FBINFO_HWACCEL_YPAN |
1963                                FBINFO_HWACCEL_XPAN;
1964
1965         info->pseudo_palette = par->pseudo_palette;
1966
1967 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1968         /* FIFO size + padding for commands */
1969         info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL);
1970
1971         err = -ENOMEM;
1972         if (info->pixmap.addr) {
1973                 memset(info->pixmap.addr, 0, 8*1024);
1974                 info->pixmap.size = 8*1024;
1975                 info->pixmap.scan_align = 4;
1976                 info->pixmap.buf_align = 4;
1977                 info->pixmap.access_align = 32;
1978
1979                 err = fb_alloc_cmap (&info->cmap, NR_PALETTE, 0);
1980                 if (!err)
1981                 info->flags |= FBINFO_HWACCEL_COPYAREA |
1982                                FBINFO_HWACCEL_FILLRECT |
1983                                FBINFO_HWACCEL_IMAGEBLIT;
1984         }
1985 #endif
1986         return err;
1987 }
1988
1989 /* --------------------------------------------------------------------- */
1990
1991 static int __devinit savagefb_probe (struct pci_dev* dev,
1992                                      const struct pci_device_id* id)
1993 {
1994         struct fb_info *info;
1995         struct savagefb_par *par;
1996         u_int h_sync, v_sync;
1997         int err, lpitch;
1998         int video_len;
1999
2000         DBG("savagefb_probe");
2001         SavagePrintRegs();
2002
2003         info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
2004         if (!info)
2005                 return -ENOMEM;
2006         par = info->par;
2007         err = pci_enable_device(dev);
2008         if (err)
2009                 goto failed_enable;
2010
2011         if ((err = pci_request_regions(dev, "savagefb"))) {
2012                 printk(KERN_ERR "cannot request PCI regions\n");
2013                 goto failed_enable;
2014         }
2015
2016         err = -ENOMEM;
2017
2018         if ((err = savage_init_fb_info(info, dev, id)))
2019                 goto failed_init;
2020
2021         err = savage_map_mmio(info);
2022         if (err)
2023                 goto failed_mmio;
2024
2025         video_len = savage_init_hw(par);
2026         /* FIXME: cant be negative */
2027         if (video_len < 0) {
2028                 err = video_len;
2029                 goto failed_mmio;
2030         }
2031
2032         err = savage_map_video(info, video_len);
2033         if (err)
2034                 goto failed_video;
2035
2036         INIT_LIST_HEAD(&info->modelist);
2037 #if defined(CONFIG_FB_SAVAGE_I2C)
2038         savagefb_create_i2c_busses(info);
2039         savagefb_probe_i2c_connector(info, &par->edid);
2040         kfree(par->edid);
2041         fb_edid_to_monspecs(par->edid, &info->monspecs);
2042         fb_videomode_to_modelist(info->monspecs.modedb,
2043                                  info->monspecs.modedb_len,
2044                                  &info->modelist);
2045 #endif
2046         info->var = savagefb_var800x600x8;
2047
2048         if (mode_option) {
2049                 fb_find_mode(&info->var, info, mode_option,
2050                              info->monspecs.modedb, info->monspecs.modedb_len,
2051                              NULL, 8);
2052         } else if (info->monspecs.modedb != NULL) {
2053                 struct fb_monspecs *specs = &info->monspecs;
2054                 struct fb_videomode modedb;
2055
2056                 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
2057                         int i;
2058
2059                         for (i = 0; i < specs->modedb_len; i++) {
2060                                 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
2061                                         modedb = specs->modedb[i];
2062                                         break;
2063                                 }
2064                         }
2065                 } else {
2066                         /* otherwise, get first mode in database */
2067                         modedb = specs->modedb[0];
2068                 }
2069
2070                 savage_update_var(&info->var, &modedb);
2071         }
2072
2073         /* maximize virtual vertical length */
2074         lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
2075         info->var.yres_virtual = info->fix.smem_len/lpitch;
2076
2077         if (info->var.yres_virtual < info->var.yres)
2078                 goto failed;
2079
2080 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2081         /*
2082          * The clipping coordinates are masked with 0xFFF, so limit our
2083          * virtual resolutions to these sizes.
2084          */
2085         if (info->var.yres_virtual > 0x1000)
2086                 info->var.yres_virtual = 0x1000;
2087
2088         if (info->var.xres_virtual > 0x1000)
2089                 info->var.xres_virtual = 0x1000;
2090 #endif
2091         savagefb_check_var(&info->var, info);
2092         savagefb_set_fix(info);
2093
2094         /*
2095          * Calculate the hsync and vsync frequencies.  Note that
2096          * we split the 1e12 constant up so that we can preserve
2097          * the precision and fit the results into 32-bit registers.
2098          *  (1953125000 * 512 = 1e12)
2099          */
2100         h_sync = 1953125000 / info->var.pixclock;
2101         h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
2102                                  info->var.right_margin +
2103                                  info->var.hsync_len);
2104         v_sync = h_sync / (info->var.yres + info->var.upper_margin +
2105                            info->var.lower_margin + info->var.vsync_len);
2106
2107         printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
2108                "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2109                info->fix.smem_len >> 10,
2110                info->var.xres, info->var.yres,
2111                h_sync / 1000, h_sync % 1000, v_sync);
2112
2113
2114         fb_destroy_modedb(info->monspecs.modedb);
2115         info->monspecs.modedb = NULL;
2116
2117         err = register_framebuffer (info);
2118         if (err < 0)
2119                 goto failed;
2120
2121         printk (KERN_INFO "fb: S3 %s frame buffer device\n",
2122                 info->fix.id);
2123
2124         /*
2125          * Our driver data
2126          */
2127         pci_set_drvdata(dev, info);
2128
2129         return 0;
2130
2131  failed:
2132 #ifdef CONFIG_FB_SAVAGE_I2C
2133         savagefb_delete_i2c_busses(info);
2134 #endif
2135         fb_alloc_cmap (&info->cmap, 0, 0);
2136         savage_unmap_video(info);
2137  failed_video:
2138         savage_unmap_mmio (info);
2139  failed_mmio:
2140         kfree(info->pixmap.addr);
2141  failed_init:
2142         pci_release_regions(dev);
2143  failed_enable:
2144         framebuffer_release(info);
2145
2146         return err;
2147 }
2148
2149 static void __devexit savagefb_remove (struct pci_dev *dev)
2150 {
2151         struct fb_info *info =
2152                 (struct fb_info *)pci_get_drvdata(dev);
2153
2154         DBG("savagefb_remove");
2155
2156         if (info) {
2157                 /*
2158                  * If unregister_framebuffer fails, then
2159                  * we will be leaving hooks that could cause
2160                  * oopsen laying around.
2161                  */
2162                 if (unregister_framebuffer (info))
2163                         printk (KERN_WARNING "savagefb: danger danger! "
2164                                 "Oopsen imminent!\n");
2165
2166 #ifdef CONFIG_FB_SAVAGE_I2C
2167                 savagefb_delete_i2c_busses(info);
2168 #endif
2169                 fb_alloc_cmap (&info->cmap, 0, 0);
2170                 savage_unmap_video (info);
2171                 savage_unmap_mmio (info);
2172                 kfree(info->pixmap.addr);
2173                 pci_release_regions(dev);
2174                 framebuffer_release(info);
2175
2176                 /*
2177                  * Ensure that the driver data is no longer
2178                  * valid.
2179                  */
2180                 pci_set_drvdata(dev, NULL);
2181         }
2182 }
2183
2184 static int savagefb_suspend (struct pci_dev* dev, pm_message_t state)
2185 {
2186         struct fb_info *info =
2187                 (struct fb_info *)pci_get_drvdata(dev);
2188         struct savagefb_par *par = (struct savagefb_par *)info->par;
2189
2190         DBG("savagefb_suspend");
2191
2192
2193         par->pm_state = state.event;
2194
2195         /*
2196          * For PM_EVENT_FREEZE, do not power down so the console
2197          * can remain active.
2198          */
2199         if (state.event == PM_EVENT_FREEZE) {
2200                 dev->dev.power.power_state = state;
2201                 return 0;
2202         }
2203
2204         acquire_console_sem();
2205         fb_set_suspend(info, 1);
2206
2207         if (info->fbops->fb_sync)
2208                 info->fbops->fb_sync(info);
2209
2210         savagefb_blank(FB_BLANK_POWERDOWN, info);
2211         savage_disable_mmio(par);
2212         pci_save_state(dev);
2213         pci_disable_device(dev);
2214         pci_set_power_state(dev, pci_choose_state(dev, state));
2215         release_console_sem();
2216
2217         return 0;
2218 }
2219
2220 static int savagefb_resume (struct pci_dev* dev)
2221 {
2222         struct fb_info *info =
2223                 (struct fb_info *)pci_get_drvdata(dev);
2224         struct savagefb_par *par = (struct savagefb_par *)info->par;
2225         int cur_state = par->pm_state;
2226
2227         DBG("savage_resume");
2228
2229         par->pm_state = PM_EVENT_ON;
2230
2231         /*
2232          * The adapter was not powered down coming back from a
2233          * PM_EVENT_FREEZE.
2234          */
2235         if (cur_state == PM_EVENT_FREEZE) {
2236                 pci_set_power_state(dev, PCI_D0);
2237                 return 0;
2238         }
2239
2240         acquire_console_sem();
2241
2242         pci_set_power_state(dev, PCI_D0);
2243         pci_restore_state(dev);
2244
2245         if(pci_enable_device(dev))
2246                 DBG("err");
2247
2248         pci_set_master(dev);
2249         savage_enable_mmio(par);
2250         savage_init_hw(par);
2251         savagefb_set_par (info);
2252         savagefb_blank(FB_BLANK_UNBLANK, info);
2253         fb_set_suspend (info, 0);
2254         release_console_sem();
2255
2256         return 0;
2257 }
2258
2259
2260 static struct pci_device_id savagefb_devices[] __devinitdata = {
2261         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
2262          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2263
2264         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
2265          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2266
2267         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
2268          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2269
2270         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
2271          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2272
2273         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
2274          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2275
2276         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
2277          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2278
2279         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
2280          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2281
2282         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
2283          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2284
2285         {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
2286          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2287
2288         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
2289          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
2290
2291         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
2292          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
2293
2294         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
2295          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
2296
2297         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
2298          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
2299
2300         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
2301          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
2302
2303         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
2304          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
2305
2306         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
2307          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
2308
2309         {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
2310          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
2311
2312         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
2313          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
2314
2315         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
2316          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
2317
2318         {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
2319          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
2320
2321         {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
2322          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
2323
2324         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
2325          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
2326
2327         {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
2328          PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
2329
2330         {0, 0, 0, 0, 0, 0, 0}
2331 };
2332
2333 MODULE_DEVICE_TABLE(pci, savagefb_devices);
2334
2335 static struct pci_driver savagefb_driver = {
2336         .name =     "savagefb",
2337         .id_table = savagefb_devices,
2338         .probe =    savagefb_probe,
2339         .suspend =  savagefb_suspend,
2340         .resume =   savagefb_resume,
2341         .remove =   __devexit_p(savagefb_remove)
2342 };
2343
2344 /* **************************** exit-time only **************************** */
2345
2346 static void __exit savage_done (void)
2347 {
2348         DBG("savage_done");
2349         pci_unregister_driver (&savagefb_driver);
2350 }
2351
2352
2353 /* ************************* init in-kernel code ************************** */
2354
2355 static int __init savagefb_setup(char *options)
2356 {
2357 #ifndef MODULE
2358         char *this_opt;
2359
2360         if (!options || !*options)
2361                 return 0;
2362
2363         while ((this_opt = strsep(&options, ",")) != NULL) {
2364                 mode_option = this_opt;
2365         }
2366 #endif /* !MODULE */
2367         return 0;
2368 }
2369
2370 static int __init savagefb_init(void)
2371 {
2372         char *option;
2373
2374         DBG("savagefb_init");
2375
2376         if (fb_get_options("savagefb", &option))
2377                 return -ENODEV;
2378
2379         savagefb_setup(option);
2380         return pci_register_driver (&savagefb_driver);
2381
2382 }
2383
2384 module_init(savagefb_init);
2385 module_exit(savage_done);
2386
2387 module_param(mode_option, charp, 0);
2388 MODULE_PARM_DESC(mode_option, "Specify initial video mode");