git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 /*
  15 /memreserve/    00000000 1000000;
  16 */
  17
  18 / {
  19         model = "MPC8568EMDS";
  20         compatible = "MPC8568EMDS", "MPC85xxMDS";
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         aliases {
  25                 ethernet0 = &enet0;
  26                 ethernet1 = &enet1;
  27                 ethernet2 = &enet2;
  28                 ethernet3 = &enet3;
  29                 serial0 = &serial0;
  30                 serial1 = &serial1;
  31                 pci0 = &pci0;
  32                 pci1 = &pci1;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 PowerPC,8568@0 {
  40                         device_type = "cpu";
  41                         reg = <0x0>;
  42                         d-cache-line-size = <32>;       // 32 bytes
  43                         i-cache-line-size = <32>;       // 32 bytes
  44                         d-cache-size = <0x8000>;                // L1, 32K
  45                         i-cache-size = <0x8000>;                // L1, 32K
  46                         timebase-frequency = <0>;
  47                         bus-frequency = <0>;
  48                         clock-frequency = <0>;
  49                 };
  50         };
  51
  52         memory {
  53                 device_type = "memory";
  54                 reg = <0x0 0x10000000>;
  55         };
  56
  57         bcsr@f8000000 {
  58                 device_type = "board-control";
  59                 reg = <0xf8000000 0x8000>;
  60         };
  61
  62         soc8568@e0000000 {
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 device_type = "soc";
  66                 ranges = <0x0 0xe0000000 0x100000>;
  67                 reg = <0xe0000000 0x1000>;
  68                 bus-frequency = <0>;
  69
  70                 memory-controller@2000 {
  71                         compatible = "fsl,8568-memory-controller";
  72                         reg = <0x2000 0x1000>;
  73                         interrupt-parent = <&mpic>;
  74                         interrupts = <18 2>;
  75                 };
  76
  77                 l2-cache-controller@20000 {
  78                         compatible = "fsl,8568-l2-cache-controller";
  79                         reg = <0x20000 0x1000>;
  80                         cache-line-size = <32>; // 32 bytes
  81                         cache-size = <0x80000>; // L2, 512K
  82                         interrupt-parent = <&mpic>;
  83                         interrupts = <16 2>;
  84                 };
  85
  86                 i2c@3000 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         cell-index = <0>;
  90                         compatible = "fsl-i2c";
  91                         reg = <0x3000 0x100>;
  92                         interrupts = <43 2>;
  93                         interrupt-parent = <&mpic>;
  94                         dfsrr;
  95
  96                         rtc@68 {
  97                                 compatible = "dallas,ds1374";
  98                                 reg = <0x68>;
  99                         };
 100                 };
 101
 102                 i2c@3100 {
 103                         #address-cells = <1>;
 104                         #size-cells = <0>;
 105                         cell-index = <1>;
 106                         compatible = "fsl-i2c";
 107                         reg = <0x3100 0x100>;
 108                         interrupts = <43 2>;
 109                         interrupt-parent = <&mpic>;
 110                         dfsrr;
 111                 };
 112
 113                 mdio@24520 {
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                         compatible = "fsl,gianfar-mdio";
 117                         reg = <0x24520 0x20>;
 118
 119                         phy0: ethernet-phy@7 {
 120                                 interrupt-parent = <&mpic>;
 121                                 interrupts = <1 1>;
 122                                 reg = <0x7>;
 123                                 device_type = "ethernet-phy";
 124                         };
 125                         phy1: ethernet-phy@1 {
 126                                 interrupt-parent = <&mpic>;
 127                                 interrupts = <2 1>;
 128                                 reg = <0x1>;
 129                                 device_type = "ethernet-phy";
 130                         };
 131                         phy2: ethernet-phy@2 {
 132                                 interrupt-parent = <&mpic>;
 133                                 interrupts = <1 1>;
 134                                 reg = <0x2>;
 135                                 device_type = "ethernet-phy";
 136                         };
 137                         phy3: ethernet-phy@3 {
 138                                 interrupt-parent = <&mpic>;
 139                                 interrupts = <2 1>;
 140                                 reg = <0x3>;
 141                                 device_type = "ethernet-phy";
 142                         };
 143                 };
 144
 145                 enet0: ethernet@24000 {
 146                         cell-index = <0>;
 147                         device_type = "network";
 148                         model = "eTSEC";
 149                         compatible = "gianfar";
 150                         reg = <0x24000 0x1000>;
 151                         local-mac-address = [ 00 00 00 00 00 00 ];
 152                         interrupts = <29 2 30 2 34 2>;
 153                         interrupt-parent = <&mpic>;
 154                         phy-handle = <&phy2>;
 155                 };
 156
 157                 enet1: ethernet@25000 {
 158                         cell-index = <1>;
 159                         device_type = "network";
 160                         model = "eTSEC";
 161                         compatible = "gianfar";
 162                         reg = <0x25000 0x1000>;
 163                         local-mac-address = [ 00 00 00 00 00 00 ];
 164                         interrupts = <35 2 36 2 40 2>;
 165                         interrupt-parent = <&mpic>;
 166                         phy-handle = <&phy3>;
 167                 };
 168
 169                 serial0: serial@4500 {
 170                         cell-index = <0>;
 171                         device_type = "serial";
 172                         compatible = "ns16550";
 173                         reg = <0x4500 0x100>;
 174                         clock-frequency = <0>;
 175                         interrupts = <42 2>;
 176                         interrupt-parent = <&mpic>;
 177                 };
 178
 179                 global-utilities@e0000 {        //global utilities block
 180                         compatible = "fsl,mpc8548-guts";
 181                         reg = <0xe0000 0x1000>;
 182                         fsl,has-rstcr;
 183                 };
 184
 185                 serial1: serial@4600 {
 186                         cell-index = <1>;
 187                         device_type = "serial";
 188                         compatible = "ns16550";
 189                         reg = <0x4600 0x100>;
 190                         clock-frequency = <0>;
 191                         interrupts = <42 2>;
 192                         interrupt-parent = <&mpic>;
 193                 };
 194
 195                 crypto@30000 {
 196                         device_type = "crypto";
 197                         model = "SEC2";
 198                         compatible = "talitos";
 199                         reg = <0x30000 0xf000>;
 200                         interrupts = <45 2>;
 201                         interrupt-parent = <&mpic>;
 202                         num-channels = <4>;
 203                         channel-fifo-len = <24>;
 204                         exec-units-mask = <0xfe>;
 205                         descriptor-types-mask = <0x12b0ebf>;
 206                 };
 207
 208                 mpic: pic@40000 {
 209                         clock-frequency = <0>;
 210                         interrupt-controller;
 211                         #address-cells = <0>;
 212                         #interrupt-cells = <2>;
 213                         reg = <0x40000 0x40000>;
 214                         compatible = "chrp,open-pic";
 215                         device_type = "open-pic";
 216                         big-endian;
 217                 };
 218
 219                 par_io@e0100 {
 220                         reg = <0xe0100 0x100>;
 221                         device_type = "par_io";
 222                         num-ports = <7>;
 223
 224                         pio1: ucc_pin@01 {
 225                                 pio-map = <
 226                         /* port  pin  dir  open_drain  assignment  has_irq */
 227                                         0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
 228                                         0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
 229                                         0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
 230                                         0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
 231                                         0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
 232                                         0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
 233                                         0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
 234                                         0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
 235                                         0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
 236                                         0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
 237                                         0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
 238                                         0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
 239                                         0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
 240                                         0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
 241                                         0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
 242                                         0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
 243                                         0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
 244                                         0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
 245                                         0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
 246                                         0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
 247                                         0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
 248                                         0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
 249                                         0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
 250                         };
 251
 252                         pio2: ucc_pin@02 {
 253                                 pio-map = <
 254                         /* port  pin  dir  open_drain  assignment  has_irq */
 255                                         0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
 256                                         0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
 257                                         0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
 258                                         0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
 259                                         0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
 260                                         0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
 261                                         0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
 262                                         0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
 263                                         0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
 264                                         0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
 265                                         0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
 266                                         0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
 267                                         0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
 268                                         0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
 269                                         0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
 270                                         0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
 271                                         0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
 272                                         0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
 273                                         0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
 274                                         0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
 275                                         0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
 276                                         0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
 277                                         0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
 278                                         0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
 279                                         0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
 280                         };
 281                 };
 282         };
 283
 284         qe@e0080000 {
 285                 #address-cells = <1>;
 286                 #size-cells = <1>;
 287                 device_type = "qe";
 288                 compatible = "fsl,qe";
 289                 ranges = <0x0 0xe0080000 0x40000>;
 290                 reg = <0xe0080000 0x480>;
 291                 brg-frequency = <0>;
 292                 bus-frequency = <396000000>;
 293
 294                 muram@10000 {
 295                         #address-cells = <1>;
 296                         #size-cells = <1>;
 297                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 298                         ranges = <0x0 0x10000 0xc000>;
 299
 300                         data-only@0 {
 301                                 compatible = "fsl,qe-muram-data",
 302                                              "fsl,cpm-muram-data";
 303                                 reg = <0x0 0xc000>;
 304                         };
 305                 };
 306
 307                 spi@4c0 {
 308                         cell-index = <0>;
 309                         compatible = "fsl,spi";
 310                         reg = <0x4c0 0x40>;
 311                         interrupts = <2>;
 312                         interrupt-parent = <&qeic>;
 313                         mode = "cpu";
 314                 };
 315
 316                 spi@500 {
 317                         cell-index = <1>;
 318                         compatible = "fsl,spi";
 319                         reg = <0x500 0x40>;
 320                         interrupts = <1>;
 321                         interrupt-parent = <&qeic>;
 322                         mode = "cpu";
 323                 };
 324
 325                 enet2: ucc@2000 {
 326                         device_type = "network";
 327                         compatible = "ucc_geth";
 328                         cell-index = <1>;
 329                         reg = <0x2000 0x200>;
 330                         interrupts = <32>;
 331                         interrupt-parent = <&qeic>;
 332                         local-mac-address = [ 00 00 00 00 00 00 ];
 333                         rx-clock-name = "none";
 334                         tx-clock-name = "clk16";
 335                         pio-handle = <&pio1>;
 336                         phy-handle = <&phy0>;
 337                         phy-connection-type = "rgmii-id";
 338                 };
 339
 340                 enet3: ucc@3000 {
 341                         device_type = "network";
 342                         compatible = "ucc_geth";
 343                         cell-index = <2>;
 344                         reg = <0x3000 0x200>;
 345                         interrupts = <33>;
 346                         interrupt-parent = <&qeic>;
 347                         local-mac-address = [ 00 00 00 00 00 00 ];
 348                         rx-clock-name = "none";
 349                         tx-clock-name = "clk16";
 350                         pio-handle = <&pio2>;
 351                         phy-handle = <&phy1>;
 352                         phy-connection-type = "rgmii-id";
 353                 };
 354
 355                 mdio@2120 {
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         reg = <0x2120 0x18>;
 359                         compatible = "fsl,ucc-mdio";
 360
 361                         /* These are the same PHYs as on
 362                          * gianfar's MDIO bus */
 363                         qe_phy0: ethernet-phy@07 {
 364                                 interrupt-parent = <&mpic>;
 365                                 interrupts = <1 1>;
 366                                 reg = <0x7>;
 367                                 device_type = "ethernet-phy";
 368                         };
 369                         qe_phy1: ethernet-phy@01 {
 370                                 interrupt-parent = <&mpic>;
 371                                 interrupts = <2 1>;
 372                                 reg = <0x1>;
 373                                 device_type = "ethernet-phy";
 374                         };
 375                         qe_phy2: ethernet-phy@02 {
 376                                 interrupt-parent = <&mpic>;
 377                                 interrupts = <1 1>;
 378                                 reg = <0x2>;
 379                                 device_type = "ethernet-phy";
 380                         };
 381                         qe_phy3: ethernet-phy@03 {
 382                                 interrupt-parent = <&mpic>;
 383                                 interrupts = <2 1>;
 384                                 reg = <0x3>;
 385                                 device_type = "ethernet-phy";
 386                         };
 387                 };
 388
 389                 qeic: interrupt-controller@80 {
 390                         interrupt-controller;
 391                         compatible = "fsl,qe-ic";
 392                         #address-cells = <0>;
 393                         #interrupt-cells = <1>;
 394                         reg = <0x80 0x80>;
 395                         big-endian;
 396                         interrupts = <46 2 46 2>; //high:30 low:30
 397                         interrupt-parent = <&mpic>;
 398                 };
 399
 400         };
 401
 402         pci0: pci@e0008000 {
 403                 cell-index = <0>;
 404                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 405                 interrupt-map = <
 406                         /* IDSEL 0x12 AD18 */
 407                         0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
 408                         0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
 409                         0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
 410                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 411
 412                         /* IDSEL 0x13 AD19 */
 413                         0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
 414                         0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
 415                         0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
 416                         0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 417
 418                 interrupt-parent = <&mpic>;
 419                 interrupts = <24 2>;
 420                 bus-range = <0 255>;
 421                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 422                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 423                 clock-frequency = <66666666>;
 424                 #interrupt-cells = <1>;
 425                 #size-cells = <2>;
 426                 #address-cells = <3>;
 427                 reg = <0xe0008000 0x1000>;
 428                 compatible = "fsl,mpc8540-pci";
 429                 device_type = "pci";
 430         };
 431
 432         /* PCI Express */
 433         pci1: pcie@e000a000 {
 434                 cell-index = <2>;
 435                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 436                 interrupt-map = <
 437
 438                         /* IDSEL 0x0 (PEX) */
 439                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 440                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 441                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 442                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 443
 444                 interrupt-parent = <&mpic>;
 445                 interrupts = <26 2>;
 446                 bus-range = <0 255>;
 447                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 448                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 449                 clock-frequency = <33333333>;
 450                 #interrupt-cells = <1>;
 451                 #size-cells = <2>;
 452                 #address-cells = <3>;
 453                 reg = <0xe000a000 0x1000>;
 454                 compatible = "fsl,mpc8548-pcie";
 455                 device_type = "pci";
 456                 pcie@0 {
 457                         reg = <0x0 0x0 0x0 0x0 0x0>;
 458                         #size-cells = <2>;
 459                         #address-cells = <3>;
 460                         device_type = "pci";
 461                         ranges = <0x2000000 0x0 0xa0000000
 462                                   0x2000000 0x0 0xa0000000
 463                                   0x0 0x10000000
 464
 465                                   0x1000000 0x0 0x0
 466                                   0x1000000 0x0 0x0
 467                                   0x0 0x800000>;
 468                 };
 469         };
 470 };