2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
44 #define ROOT_SIZE VTD_PAGE_SIZE
45 #define CONTEXT_SIZE VTD_PAGE_SIZE
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
50 #define IOAPIC_RANGE_START (0xfee00000)
51 #define IOAPIC_RANGE_END (0xfeefffff)
52 #define IOVA_START_ADDR (0x1000)
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
56 #define MAX_AGAW_WIDTH 64
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
59 #define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
61 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
62 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
63 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
66 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67 are never going to work. */
68 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
70 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
73 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
75 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
77 static inline unsigned long page_to_dma_pfn(struct page *pg)
79 return mm_to_dma_pfn(page_to_pfn(pg));
81 static inline unsigned long virt_to_dma_pfn(void *p)
83 return page_to_dma_pfn(virt_to_page(p));
86 /* global iommu list, set NULL for ignored DMAR units */
87 static struct intel_iommu **g_iommus;
89 static int rwbf_quirk;
94 * 12-63: Context Ptr (12 - (haw-1))
101 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102 static inline bool root_present(struct root_entry *root)
104 return (root->val & 1);
106 static inline void set_root_present(struct root_entry *root)
110 static inline void set_root_value(struct root_entry *root, unsigned long value)
112 root->val |= value & VTD_PAGE_MASK;
115 static inline struct context_entry *
116 get_context_addr_from_root(struct root_entry *root)
118 return (struct context_entry *)
119 (root_present(root)?phys_to_virt(
120 root->val & VTD_PAGE_MASK) :
127 * 1: fault processing disable
128 * 2-3: translation type
129 * 12-63: address space root
135 struct context_entry {
140 static inline bool context_present(struct context_entry *context)
142 return (context->lo & 1);
144 static inline void context_set_present(struct context_entry *context)
149 static inline void context_set_fault_enable(struct context_entry *context)
151 context->lo &= (((u64)-1) << 2) | 1;
154 static inline void context_set_translation_type(struct context_entry *context,
157 context->lo &= (((u64)-1) << 4) | 3;
158 context->lo |= (value & 3) << 2;
161 static inline void context_set_address_root(struct context_entry *context,
164 context->lo |= value & VTD_PAGE_MASK;
167 static inline void context_set_address_width(struct context_entry *context,
170 context->hi |= value & 7;
173 static inline void context_set_domain_id(struct context_entry *context,
176 context->hi |= (value & ((1 << 16) - 1)) << 8;
179 static inline void context_clear_entry(struct context_entry *context)
192 * 12-63: Host physcial address
198 static inline void dma_clear_pte(struct dma_pte *pte)
203 static inline void dma_set_pte_readable(struct dma_pte *pte)
205 pte->val |= DMA_PTE_READ;
208 static inline void dma_set_pte_writable(struct dma_pte *pte)
210 pte->val |= DMA_PTE_WRITE;
213 static inline void dma_set_pte_snp(struct dma_pte *pte)
215 pte->val |= DMA_PTE_SNP;
218 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
220 pte->val = (pte->val & ~3) | (prot & 3);
223 static inline u64 dma_pte_addr(struct dma_pte *pte)
226 return pte->val & VTD_PAGE_MASK;
228 /* Must have a full atomic 64-bit read */
229 return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
233 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
235 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
238 static inline bool dma_pte_present(struct dma_pte *pte)
240 return (pte->val & 3) != 0;
243 static inline int first_pte_in_page(struct dma_pte *pte)
245 return !((unsigned long)pte & ~VTD_PAGE_MASK);
249 * This domain is a statically identity mapping domain.
250 * 1. This domain creats a static 1:1 mapping to all usable memory.
251 * 2. It maps to each iommu if successful.
252 * 3. Each iommu mapps to this domain if successful.
254 struct dmar_domain *si_domain;
256 /* devices under the same p2p bridge are owned in one domain */
257 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
259 /* domain represents a virtual machine, more than one devices
260 * across iommus may be owned in one domain, e.g. kvm guest.
262 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
264 /* si_domain contains mulitple devices */
265 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
268 int id; /* domain id */
269 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
271 struct list_head devices; /* all devices' list */
272 struct iova_domain iovad; /* iova's that belong to this domain */
274 struct dma_pte *pgd; /* virtual address */
275 int gaw; /* max guest address width */
277 /* adjusted guest address width, 0 is level 2 30-bit */
280 int flags; /* flags to find out type of domain */
282 int iommu_coherency;/* indicate coherency of iommu access */
283 int iommu_snooping; /* indicate snooping control feature*/
284 int iommu_count; /* reference count of iommu */
285 spinlock_t iommu_lock; /* protect iommu set in domain */
286 u64 max_addr; /* maximum mapped address */
289 /* PCI domain-device relationship */
290 struct device_domain_info {
291 struct list_head link; /* link to domain siblings */
292 struct list_head global; /* link to global list */
293 int segment; /* PCI domain */
294 u8 bus; /* PCI bus number */
295 u8 devfn; /* PCI devfn number */
296 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
297 struct intel_iommu *iommu; /* IOMMU used by this device */
298 struct dmar_domain *domain; /* pointer to domain */
301 static void flush_unmaps_timeout(unsigned long data);
303 DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
305 #define HIGH_WATER_MARK 250
306 struct deferred_flush_tables {
308 struct iova *iova[HIGH_WATER_MARK];
309 struct dmar_domain *domain[HIGH_WATER_MARK];
312 static struct deferred_flush_tables *deferred_flush;
314 /* bitmap for indexing intel_iommus */
315 static int g_num_of_iommus;
317 static DEFINE_SPINLOCK(async_umap_flush_lock);
318 static LIST_HEAD(unmaps_to_do);
321 static long list_size;
323 static void domain_remove_dev_info(struct dmar_domain *domain);
325 #ifdef CONFIG_DMAR_DEFAULT_ON
326 int dmar_disabled = 0;
328 int dmar_disabled = 1;
329 #endif /*CONFIG_DMAR_DEFAULT_ON*/
331 static int __initdata dmar_map_gfx = 1;
332 static int dmar_forcedac;
333 static int intel_iommu_strict;
335 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
336 static DEFINE_SPINLOCK(device_domain_lock);
337 static LIST_HEAD(device_domain_list);
339 static struct iommu_ops intel_iommu_ops;
341 static int __init intel_iommu_setup(char *str)
346 if (!strncmp(str, "on", 2)) {
348 printk(KERN_INFO "Intel-IOMMU: enabled\n");
349 } else if (!strncmp(str, "off", 3)) {
351 printk(KERN_INFO "Intel-IOMMU: disabled\n");
352 } else if (!strncmp(str, "igfx_off", 8)) {
355 "Intel-IOMMU: disable GFX device mapping\n");
356 } else if (!strncmp(str, "forcedac", 8)) {
358 "Intel-IOMMU: Forcing DAC for PCI devices\n");
360 } else if (!strncmp(str, "strict", 6)) {
362 "Intel-IOMMU: disable batched IOTLB flush\n");
363 intel_iommu_strict = 1;
366 str += strcspn(str, ",");
372 __setup("intel_iommu=", intel_iommu_setup);
374 static struct kmem_cache *iommu_domain_cache;
375 static struct kmem_cache *iommu_devinfo_cache;
376 static struct kmem_cache *iommu_iova_cache;
378 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
383 /* trying to avoid low memory issues */
384 flags = current->flags & PF_MEMALLOC;
385 current->flags |= PF_MEMALLOC;
386 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
387 current->flags &= (~PF_MEMALLOC | flags);
392 static inline void *alloc_pgtable_page(void)
397 /* trying to avoid low memory issues */
398 flags = current->flags & PF_MEMALLOC;
399 current->flags |= PF_MEMALLOC;
400 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
401 current->flags &= (~PF_MEMALLOC | flags);
405 static inline void free_pgtable_page(void *vaddr)
407 free_page((unsigned long)vaddr);
410 static inline void *alloc_domain_mem(void)
412 return iommu_kmem_cache_alloc(iommu_domain_cache);
415 static void free_domain_mem(void *vaddr)
417 kmem_cache_free(iommu_domain_cache, vaddr);
420 static inline void * alloc_devinfo_mem(void)
422 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
425 static inline void free_devinfo_mem(void *vaddr)
427 kmem_cache_free(iommu_devinfo_cache, vaddr);
430 struct iova *alloc_iova_mem(void)
432 return iommu_kmem_cache_alloc(iommu_iova_cache);
435 void free_iova_mem(struct iova *iova)
437 kmem_cache_free(iommu_iova_cache, iova);
441 static inline int width_to_agaw(int width);
443 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
448 sagaw = cap_sagaw(iommu->cap);
449 for (agaw = width_to_agaw(max_gaw);
451 if (test_bit(agaw, &sagaw))
459 * Calculate max SAGAW for each iommu.
461 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
463 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
467 * calculate agaw for each iommu.
468 * "SAGAW" may be different across iommus, use a default agaw, and
469 * get a supported less agaw for iommus that don't support the default agaw.
471 int iommu_calculate_agaw(struct intel_iommu *iommu)
473 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
476 /* This functionin only returns single iommu in a domain */
477 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
481 /* si_domain and vm domain should not get here. */
482 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
483 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
485 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
486 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
489 return g_iommus[iommu_id];
492 static void domain_update_iommu_coherency(struct dmar_domain *domain)
496 domain->iommu_coherency = 1;
498 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
499 for (; i < g_num_of_iommus; ) {
500 if (!ecap_coherent(g_iommus[i]->ecap)) {
501 domain->iommu_coherency = 0;
504 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
508 static void domain_update_iommu_snooping(struct dmar_domain *domain)
512 domain->iommu_snooping = 1;
514 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
515 for (; i < g_num_of_iommus; ) {
516 if (!ecap_sc_support(g_iommus[i]->ecap)) {
517 domain->iommu_snooping = 0;
520 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
524 /* Some capabilities may be different across iommus */
525 static void domain_update_iommu_cap(struct dmar_domain *domain)
527 domain_update_iommu_coherency(domain);
528 domain_update_iommu_snooping(domain);
531 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
533 struct dmar_drhd_unit *drhd = NULL;
536 for_each_drhd_unit(drhd) {
539 if (segment != drhd->segment)
542 for (i = 0; i < drhd->devices_cnt; i++) {
543 if (drhd->devices[i] &&
544 drhd->devices[i]->bus->number == bus &&
545 drhd->devices[i]->devfn == devfn)
547 if (drhd->devices[i] &&
548 drhd->devices[i]->subordinate &&
549 drhd->devices[i]->subordinate->number <= bus &&
550 drhd->devices[i]->subordinate->subordinate >= bus)
554 if (drhd->include_all)
561 static void domain_flush_cache(struct dmar_domain *domain,
562 void *addr, int size)
564 if (!domain->iommu_coherency)
565 clflush_cache_range(addr, size);
568 /* Gets context entry for a given bus and devfn */
569 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
572 struct root_entry *root;
573 struct context_entry *context;
574 unsigned long phy_addr;
577 spin_lock_irqsave(&iommu->lock, flags);
578 root = &iommu->root_entry[bus];
579 context = get_context_addr_from_root(root);
581 context = (struct context_entry *)alloc_pgtable_page();
583 spin_unlock_irqrestore(&iommu->lock, flags);
586 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
587 phy_addr = virt_to_phys((void *)context);
588 set_root_value(root, phy_addr);
589 set_root_present(root);
590 __iommu_flush_cache(iommu, root, sizeof(*root));
592 spin_unlock_irqrestore(&iommu->lock, flags);
593 return &context[devfn];
596 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
598 struct root_entry *root;
599 struct context_entry *context;
603 spin_lock_irqsave(&iommu->lock, flags);
604 root = &iommu->root_entry[bus];
605 context = get_context_addr_from_root(root);
610 ret = context_present(&context[devfn]);
612 spin_unlock_irqrestore(&iommu->lock, flags);
616 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
618 struct root_entry *root;
619 struct context_entry *context;
622 spin_lock_irqsave(&iommu->lock, flags);
623 root = &iommu->root_entry[bus];
624 context = get_context_addr_from_root(root);
626 context_clear_entry(&context[devfn]);
627 __iommu_flush_cache(iommu, &context[devfn], \
630 spin_unlock_irqrestore(&iommu->lock, flags);
633 static void free_context_table(struct intel_iommu *iommu)
635 struct root_entry *root;
638 struct context_entry *context;
640 spin_lock_irqsave(&iommu->lock, flags);
641 if (!iommu->root_entry) {
644 for (i = 0; i < ROOT_ENTRY_NR; i++) {
645 root = &iommu->root_entry[i];
646 context = get_context_addr_from_root(root);
648 free_pgtable_page(context);
650 free_pgtable_page(iommu->root_entry);
651 iommu->root_entry = NULL;
653 spin_unlock_irqrestore(&iommu->lock, flags);
656 /* page table handling */
657 #define LEVEL_STRIDE (9)
658 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
660 static inline int agaw_to_level(int agaw)
665 static inline int agaw_to_width(int agaw)
667 return 30 + agaw * LEVEL_STRIDE;
671 static inline int width_to_agaw(int width)
673 return (width - 30) / LEVEL_STRIDE;
676 static inline unsigned int level_to_offset_bits(int level)
678 return (level - 1) * LEVEL_STRIDE;
681 static inline int pfn_level_offset(unsigned long pfn, int level)
683 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
686 static inline unsigned long level_mask(int level)
688 return -1UL << level_to_offset_bits(level);
691 static inline unsigned long level_size(int level)
693 return 1UL << level_to_offset_bits(level);
696 static inline unsigned long align_to_level(unsigned long pfn, int level)
698 return (pfn + level_size(level) - 1) & level_mask(level);
701 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
704 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
705 struct dma_pte *parent, *pte = NULL;
706 int level = agaw_to_level(domain->agaw);
709 BUG_ON(!domain->pgd);
710 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
711 parent = domain->pgd;
716 offset = pfn_level_offset(pfn, level);
717 pte = &parent[offset];
721 if (!dma_pte_present(pte)) {
724 tmp_page = alloc_pgtable_page();
729 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
730 pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
731 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
732 /* Someone else set it while we were thinking; use theirs. */
733 free_pgtable_page(tmp_page);
736 domain_flush_cache(domain, pte, sizeof(*pte));
739 parent = phys_to_virt(dma_pte_addr(pte));
746 /* return address's pte at specific level */
747 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
751 struct dma_pte *parent, *pte = NULL;
752 int total = agaw_to_level(domain->agaw);
755 parent = domain->pgd;
756 while (level <= total) {
757 offset = pfn_level_offset(pfn, total);
758 pte = &parent[offset];
762 if (!dma_pte_present(pte))
764 parent = phys_to_virt(dma_pte_addr(pte));
770 /* clear last level pte, a tlb flush should be followed */
771 static void dma_pte_clear_range(struct dmar_domain *domain,
772 unsigned long start_pfn,
773 unsigned long last_pfn)
775 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
776 struct dma_pte *first_pte, *pte;
778 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
779 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
781 /* we don't need lock here; nobody else touches the iova range */
782 while (start_pfn <= last_pfn) {
783 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
785 start_pfn = align_to_level(start_pfn + 1, 2);
792 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
794 domain_flush_cache(domain, first_pte,
795 (void *)pte - (void *)first_pte);
799 /* free page table pages. last level pte should already be cleared */
800 static void dma_pte_free_pagetable(struct dmar_domain *domain,
801 unsigned long start_pfn,
802 unsigned long last_pfn)
804 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
805 struct dma_pte *first_pte, *pte;
806 int total = agaw_to_level(domain->agaw);
810 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
811 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
813 /* We don't need lock here; nobody else touches the iova range */
815 while (level <= total) {
816 tmp = align_to_level(start_pfn, level);
818 /* If we can't even clear one PTE at this level, we're done */
819 if (tmp + level_size(level) - 1 > last_pfn)
822 while (tmp + level_size(level) - 1 <= last_pfn) {
823 first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
825 tmp = align_to_level(tmp + 1, level + 1);
829 if (dma_pte_present(pte)) {
830 free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
834 tmp += level_size(level);
835 } while (!first_pte_in_page(pte) &&
836 tmp + level_size(level) - 1 <= last_pfn);
838 domain_flush_cache(domain, first_pte,
839 (void *)pte - (void *)first_pte);
845 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
846 free_pgtable_page(domain->pgd);
852 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
854 struct root_entry *root;
857 root = (struct root_entry *)alloc_pgtable_page();
861 __iommu_flush_cache(iommu, root, ROOT_SIZE);
863 spin_lock_irqsave(&iommu->lock, flags);
864 iommu->root_entry = root;
865 spin_unlock_irqrestore(&iommu->lock, flags);
870 static void iommu_set_root_entry(struct intel_iommu *iommu)
876 addr = iommu->root_entry;
878 spin_lock_irqsave(&iommu->register_lock, flag);
879 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
881 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
883 /* Make sure hardware complete it */
884 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
885 readl, (sts & DMA_GSTS_RTPS), sts);
887 spin_unlock_irqrestore(&iommu->register_lock, flag);
890 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
895 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
898 spin_lock_irqsave(&iommu->register_lock, flag);
899 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
901 /* Make sure hardware complete it */
902 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
903 readl, (!(val & DMA_GSTS_WBFS)), val);
905 spin_unlock_irqrestore(&iommu->register_lock, flag);
908 /* return value determine if we need a write buffer flush */
909 static void __iommu_flush_context(struct intel_iommu *iommu,
910 u16 did, u16 source_id, u8 function_mask,
917 case DMA_CCMD_GLOBAL_INVL:
918 val = DMA_CCMD_GLOBAL_INVL;
920 case DMA_CCMD_DOMAIN_INVL:
921 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
923 case DMA_CCMD_DEVICE_INVL:
924 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
925 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
932 spin_lock_irqsave(&iommu->register_lock, flag);
933 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
935 /* Make sure hardware complete it */
936 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
937 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
939 spin_unlock_irqrestore(&iommu->register_lock, flag);
942 /* return value determine if we need a write buffer flush */
943 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
944 u64 addr, unsigned int size_order, u64 type)
946 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
947 u64 val = 0, val_iva = 0;
951 case DMA_TLB_GLOBAL_FLUSH:
952 /* global flush doesn't need set IVA_REG */
953 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
955 case DMA_TLB_DSI_FLUSH:
956 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
958 case DMA_TLB_PSI_FLUSH:
959 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
960 /* Note: always flush non-leaf currently */
961 val_iva = size_order | addr;
966 /* Note: set drain read/write */
969 * This is probably to be super secure.. Looks like we can
970 * ignore it without any impact.
972 if (cap_read_drain(iommu->cap))
973 val |= DMA_TLB_READ_DRAIN;
975 if (cap_write_drain(iommu->cap))
976 val |= DMA_TLB_WRITE_DRAIN;
978 spin_lock_irqsave(&iommu->register_lock, flag);
979 /* Note: Only uses first TLB reg currently */
981 dmar_writeq(iommu->reg + tlb_offset, val_iva);
982 dmar_writeq(iommu->reg + tlb_offset + 8, val);
984 /* Make sure hardware complete it */
985 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
986 dmar_readq, (!(val & DMA_TLB_IVT)), val);
988 spin_unlock_irqrestore(&iommu->register_lock, flag);
990 /* check IOTLB invalidation granularity */
991 if (DMA_TLB_IAIG(val) == 0)
992 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
993 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
994 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
995 (unsigned long long)DMA_TLB_IIRG(type),
996 (unsigned long long)DMA_TLB_IAIG(val));
999 static struct device_domain_info *iommu_support_dev_iotlb(
1000 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1003 unsigned long flags;
1004 struct device_domain_info *info;
1005 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1007 if (!ecap_dev_iotlb_support(iommu->ecap))
1013 spin_lock_irqsave(&device_domain_lock, flags);
1014 list_for_each_entry(info, &domain->devices, link)
1015 if (info->bus == bus && info->devfn == devfn) {
1019 spin_unlock_irqrestore(&device_domain_lock, flags);
1021 if (!found || !info->dev)
1024 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1027 if (!dmar_find_matched_atsr_unit(info->dev))
1030 info->iommu = iommu;
1035 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1040 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1043 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1045 if (!info->dev || !pci_ats_enabled(info->dev))
1048 pci_disable_ats(info->dev);
1051 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1052 u64 addr, unsigned mask)
1055 unsigned long flags;
1056 struct device_domain_info *info;
1058 spin_lock_irqsave(&device_domain_lock, flags);
1059 list_for_each_entry(info, &domain->devices, link) {
1060 if (!info->dev || !pci_ats_enabled(info->dev))
1063 sid = info->bus << 8 | info->devfn;
1064 qdep = pci_ats_queue_depth(info->dev);
1065 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1067 spin_unlock_irqrestore(&device_domain_lock, flags);
1070 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1071 unsigned long pfn, unsigned int pages)
1073 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1074 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1079 * Fallback to domain selective flush if no PSI support or the size is
1081 * PSI requires page size to be 2 ^ x, and the base address is naturally
1082 * aligned to the size
1084 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1085 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1088 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1092 * In caching mode, domain ID 0 is reserved for non-present to present
1093 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1095 if (!cap_caching_mode(iommu->cap) || did)
1096 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1099 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1102 unsigned long flags;
1104 spin_lock_irqsave(&iommu->register_lock, flags);
1105 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1106 pmen &= ~DMA_PMEN_EPM;
1107 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1109 /* wait for the protected region status bit to clear */
1110 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1111 readl, !(pmen & DMA_PMEN_PRS), pmen);
1113 spin_unlock_irqrestore(&iommu->register_lock, flags);
1116 static int iommu_enable_translation(struct intel_iommu *iommu)
1119 unsigned long flags;
1121 spin_lock_irqsave(&iommu->register_lock, flags);
1122 iommu->gcmd |= DMA_GCMD_TE;
1123 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1125 /* Make sure hardware complete it */
1126 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1127 readl, (sts & DMA_GSTS_TES), sts);
1129 spin_unlock_irqrestore(&iommu->register_lock, flags);
1133 static int iommu_disable_translation(struct intel_iommu *iommu)
1138 spin_lock_irqsave(&iommu->register_lock, flag);
1139 iommu->gcmd &= ~DMA_GCMD_TE;
1140 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1142 /* Make sure hardware complete it */
1143 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1144 readl, (!(sts & DMA_GSTS_TES)), sts);
1146 spin_unlock_irqrestore(&iommu->register_lock, flag);
1151 static int iommu_init_domains(struct intel_iommu *iommu)
1153 unsigned long ndomains;
1154 unsigned long nlongs;
1156 ndomains = cap_ndoms(iommu->cap);
1157 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1158 nlongs = BITS_TO_LONGS(ndomains);
1160 /* TBD: there might be 64K domains,
1161 * consider other allocation for future chip
1163 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1164 if (!iommu->domain_ids) {
1165 printk(KERN_ERR "Allocating domain id array failed\n");
1168 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1170 if (!iommu->domains) {
1171 printk(KERN_ERR "Allocating domain array failed\n");
1172 kfree(iommu->domain_ids);
1176 spin_lock_init(&iommu->lock);
1179 * if Caching mode is set, then invalid translations are tagged
1180 * with domainid 0. Hence we need to pre-allocate it.
1182 if (cap_caching_mode(iommu->cap))
1183 set_bit(0, iommu->domain_ids);
1188 static void domain_exit(struct dmar_domain *domain);
1189 static void vm_domain_exit(struct dmar_domain *domain);
1191 void free_dmar_iommu(struct intel_iommu *iommu)
1193 struct dmar_domain *domain;
1195 unsigned long flags;
1197 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1198 for (; i < cap_ndoms(iommu->cap); ) {
1199 domain = iommu->domains[i];
1200 clear_bit(i, iommu->domain_ids);
1202 spin_lock_irqsave(&domain->iommu_lock, flags);
1203 if (--domain->iommu_count == 0) {
1204 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1205 vm_domain_exit(domain);
1207 domain_exit(domain);
1209 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1211 i = find_next_bit(iommu->domain_ids,
1212 cap_ndoms(iommu->cap), i+1);
1215 if (iommu->gcmd & DMA_GCMD_TE)
1216 iommu_disable_translation(iommu);
1219 set_irq_data(iommu->irq, NULL);
1220 /* This will mask the irq */
1221 free_irq(iommu->irq, iommu);
1222 destroy_irq(iommu->irq);
1225 kfree(iommu->domains);
1226 kfree(iommu->domain_ids);
1228 g_iommus[iommu->seq_id] = NULL;
1230 /* if all iommus are freed, free g_iommus */
1231 for (i = 0; i < g_num_of_iommus; i++) {
1236 if (i == g_num_of_iommus)
1239 /* free context mapping */
1240 free_context_table(iommu);
1243 static struct dmar_domain *alloc_domain(void)
1245 struct dmar_domain *domain;
1247 domain = alloc_domain_mem();
1251 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1257 static int iommu_attach_domain(struct dmar_domain *domain,
1258 struct intel_iommu *iommu)
1261 unsigned long ndomains;
1262 unsigned long flags;
1264 ndomains = cap_ndoms(iommu->cap);
1266 spin_lock_irqsave(&iommu->lock, flags);
1268 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1269 if (num >= ndomains) {
1270 spin_unlock_irqrestore(&iommu->lock, flags);
1271 printk(KERN_ERR "IOMMU: no free domain ids\n");
1276 set_bit(num, iommu->domain_ids);
1277 set_bit(iommu->seq_id, &domain->iommu_bmp);
1278 iommu->domains[num] = domain;
1279 spin_unlock_irqrestore(&iommu->lock, flags);
1284 static void iommu_detach_domain(struct dmar_domain *domain,
1285 struct intel_iommu *iommu)
1287 unsigned long flags;
1291 spin_lock_irqsave(&iommu->lock, flags);
1292 ndomains = cap_ndoms(iommu->cap);
1293 num = find_first_bit(iommu->domain_ids, ndomains);
1294 for (; num < ndomains; ) {
1295 if (iommu->domains[num] == domain) {
1299 num = find_next_bit(iommu->domain_ids,
1300 cap_ndoms(iommu->cap), num+1);
1304 clear_bit(num, iommu->domain_ids);
1305 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1306 iommu->domains[num] = NULL;
1308 spin_unlock_irqrestore(&iommu->lock, flags);
1311 static struct iova_domain reserved_iova_list;
1312 static struct lock_class_key reserved_alloc_key;
1313 static struct lock_class_key reserved_rbtree_key;
1315 static void dmar_init_reserved_ranges(void)
1317 struct pci_dev *pdev = NULL;
1321 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1323 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1324 &reserved_alloc_key);
1325 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1326 &reserved_rbtree_key);
1328 /* IOAPIC ranges shouldn't be accessed by DMA */
1329 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1330 IOVA_PFN(IOAPIC_RANGE_END));
1332 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1334 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1335 for_each_pci_dev(pdev) {
1338 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1339 r = &pdev->resource[i];
1340 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1342 iova = reserve_iova(&reserved_iova_list,
1346 printk(KERN_ERR "Reserve iova failed\n");
1352 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1354 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1357 static inline int guestwidth_to_adjustwidth(int gaw)
1360 int r = (gaw - 12) % 9;
1371 static int domain_init(struct dmar_domain *domain, int guest_width)
1373 struct intel_iommu *iommu;
1374 int adjust_width, agaw;
1375 unsigned long sagaw;
1377 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1378 spin_lock_init(&domain->iommu_lock);
1380 domain_reserve_special_ranges(domain);
1382 /* calculate AGAW */
1383 iommu = domain_get_iommu(domain);
1384 if (guest_width > cap_mgaw(iommu->cap))
1385 guest_width = cap_mgaw(iommu->cap);
1386 domain->gaw = guest_width;
1387 adjust_width = guestwidth_to_adjustwidth(guest_width);
1388 agaw = width_to_agaw(adjust_width);
1389 sagaw = cap_sagaw(iommu->cap);
1390 if (!test_bit(agaw, &sagaw)) {
1391 /* hardware doesn't support it, choose a bigger one */
1392 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1393 agaw = find_next_bit(&sagaw, 5, agaw);
1397 domain->agaw = agaw;
1398 INIT_LIST_HEAD(&domain->devices);
1400 if (ecap_coherent(iommu->ecap))
1401 domain->iommu_coherency = 1;
1403 domain->iommu_coherency = 0;
1405 if (ecap_sc_support(iommu->ecap))
1406 domain->iommu_snooping = 1;
1408 domain->iommu_snooping = 0;
1410 domain->iommu_count = 1;
1412 /* always allocate the top pgd */
1413 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1416 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1420 static void domain_exit(struct dmar_domain *domain)
1422 struct dmar_drhd_unit *drhd;
1423 struct intel_iommu *iommu;
1425 /* Domain 0 is reserved, so dont process it */
1429 domain_remove_dev_info(domain);
1431 put_iova_domain(&domain->iovad);
1434 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1436 /* free page tables */
1437 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1439 for_each_active_iommu(iommu, drhd)
1440 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1441 iommu_detach_domain(domain, iommu);
1443 free_domain_mem(domain);
1446 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1447 u8 bus, u8 devfn, int translation)
1449 struct context_entry *context;
1450 unsigned long flags;
1451 struct intel_iommu *iommu;
1452 struct dma_pte *pgd;
1454 unsigned long ndomains;
1457 struct device_domain_info *info = NULL;
1459 pr_debug("Set context mapping for %02x:%02x.%d\n",
1460 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1462 BUG_ON(!domain->pgd);
1463 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1464 translation != CONTEXT_TT_MULTI_LEVEL);
1466 iommu = device_to_iommu(segment, bus, devfn);
1470 context = device_to_context_entry(iommu, bus, devfn);
1473 spin_lock_irqsave(&iommu->lock, flags);
1474 if (context_present(context)) {
1475 spin_unlock_irqrestore(&iommu->lock, flags);
1482 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1483 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1486 /* find an available domain id for this device in iommu */
1487 ndomains = cap_ndoms(iommu->cap);
1488 num = find_first_bit(iommu->domain_ids, ndomains);
1489 for (; num < ndomains; ) {
1490 if (iommu->domains[num] == domain) {
1495 num = find_next_bit(iommu->domain_ids,
1496 cap_ndoms(iommu->cap), num+1);
1500 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1501 if (num >= ndomains) {
1502 spin_unlock_irqrestore(&iommu->lock, flags);
1503 printk(KERN_ERR "IOMMU: no free domain ids\n");
1507 set_bit(num, iommu->domain_ids);
1508 set_bit(iommu->seq_id, &domain->iommu_bmp);
1509 iommu->domains[num] = domain;
1513 /* Skip top levels of page tables for
1514 * iommu which has less agaw than default.
1516 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1517 pgd = phys_to_virt(dma_pte_addr(pgd));
1518 if (!dma_pte_present(pgd)) {
1519 spin_unlock_irqrestore(&iommu->lock, flags);
1525 context_set_domain_id(context, id);
1527 if (translation != CONTEXT_TT_PASS_THROUGH) {
1528 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1529 translation = info ? CONTEXT_TT_DEV_IOTLB :
1530 CONTEXT_TT_MULTI_LEVEL;
1533 * In pass through mode, AW must be programmed to indicate the largest
1534 * AGAW value supported by hardware. And ASR is ignored by hardware.
1536 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1537 context_set_address_width(context, iommu->msagaw);
1539 context_set_address_root(context, virt_to_phys(pgd));
1540 context_set_address_width(context, iommu->agaw);
1543 context_set_translation_type(context, translation);
1544 context_set_fault_enable(context);
1545 context_set_present(context);
1546 domain_flush_cache(domain, context, sizeof(*context));
1549 * It's a non-present to present mapping. If hardware doesn't cache
1550 * non-present entry we only need to flush the write-buffer. If the
1551 * _does_ cache non-present entries, then it does so in the special
1552 * domain #0, which we have to flush:
1554 if (cap_caching_mode(iommu->cap)) {
1555 iommu->flush.flush_context(iommu, 0,
1556 (((u16)bus) << 8) | devfn,
1557 DMA_CCMD_MASK_NOBIT,
1558 DMA_CCMD_DEVICE_INVL);
1559 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1561 iommu_flush_write_buffer(iommu);
1563 iommu_enable_dev_iotlb(info);
1564 spin_unlock_irqrestore(&iommu->lock, flags);
1566 spin_lock_irqsave(&domain->iommu_lock, flags);
1567 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1568 domain->iommu_count++;
1569 domain_update_iommu_cap(domain);
1571 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1576 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1580 struct pci_dev *tmp, *parent;
1582 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1583 pdev->bus->number, pdev->devfn,
1588 /* dependent device mapping */
1589 tmp = pci_find_upstream_pcie_bridge(pdev);
1592 /* Secondary interface's bus number and devfn 0 */
1593 parent = pdev->bus->self;
1594 while (parent != tmp) {
1595 ret = domain_context_mapping_one(domain,
1596 pci_domain_nr(parent->bus),
1597 parent->bus->number,
1598 parent->devfn, translation);
1601 parent = parent->bus->self;
1603 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1604 return domain_context_mapping_one(domain,
1605 pci_domain_nr(tmp->subordinate),
1606 tmp->subordinate->number, 0,
1608 else /* this is a legacy PCI bridge */
1609 return domain_context_mapping_one(domain,
1610 pci_domain_nr(tmp->bus),
1616 static int domain_context_mapped(struct pci_dev *pdev)
1619 struct pci_dev *tmp, *parent;
1620 struct intel_iommu *iommu;
1622 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1627 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1630 /* dependent device mapping */
1631 tmp = pci_find_upstream_pcie_bridge(pdev);
1634 /* Secondary interface's bus number and devfn 0 */
1635 parent = pdev->bus->self;
1636 while (parent != tmp) {
1637 ret = device_context_mapped(iommu, parent->bus->number,
1641 parent = parent->bus->self;
1644 return device_context_mapped(iommu, tmp->subordinate->number,
1647 return device_context_mapped(iommu, tmp->bus->number,
1651 /* Returns a number of VTD pages, but aligned to MM page size */
1652 static inline unsigned long aligned_nrpages(unsigned long host_addr,
1655 host_addr &= ~PAGE_MASK;
1656 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1659 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1660 struct scatterlist *sg, unsigned long phys_pfn,
1661 unsigned long nr_pages, int prot)
1663 struct dma_pte *first_pte = NULL, *pte = NULL;
1664 phys_addr_t uninitialized_var(pteval);
1665 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1666 unsigned long sg_res;
1668 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1670 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1673 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1678 sg_res = nr_pages + 1;
1679 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1682 while (nr_pages--) {
1686 sg_res = aligned_nrpages(sg->offset, sg->length);
1687 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1688 sg->dma_length = sg->length;
1689 pteval = page_to_phys(sg_page(sg)) | prot;
1692 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1696 /* We don't need lock here, nobody else
1697 * touches the iova range
1699 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1701 static int dumps = 5;
1702 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1703 iov_pfn, tmp, (unsigned long long)pteval);
1706 debug_dma_dump_mappings(NULL);
1711 if (!nr_pages || first_pte_in_page(pte)) {
1712 domain_flush_cache(domain, first_pte,
1713 (void *)pte - (void *)first_pte);
1717 pteval += VTD_PAGE_SIZE;
1725 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1726 struct scatterlist *sg, unsigned long nr_pages,
1729 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1732 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1733 unsigned long phys_pfn, unsigned long nr_pages,
1736 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1739 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1744 clear_context_table(iommu, bus, devfn);
1745 iommu->flush.flush_context(iommu, 0, 0, 0,
1746 DMA_CCMD_GLOBAL_INVL);
1747 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1750 static void domain_remove_dev_info(struct dmar_domain *domain)
1752 struct device_domain_info *info;
1753 unsigned long flags;
1754 struct intel_iommu *iommu;
1756 spin_lock_irqsave(&device_domain_lock, flags);
1757 while (!list_empty(&domain->devices)) {
1758 info = list_entry(domain->devices.next,
1759 struct device_domain_info, link);
1760 list_del(&info->link);
1761 list_del(&info->global);
1763 info->dev->dev.archdata.iommu = NULL;
1764 spin_unlock_irqrestore(&device_domain_lock, flags);
1766 iommu_disable_dev_iotlb(info);
1767 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1768 iommu_detach_dev(iommu, info->bus, info->devfn);
1769 free_devinfo_mem(info);
1771 spin_lock_irqsave(&device_domain_lock, flags);
1773 spin_unlock_irqrestore(&device_domain_lock, flags);
1778 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1780 static struct dmar_domain *
1781 find_domain(struct pci_dev *pdev)
1783 struct device_domain_info *info;
1785 /* No lock here, assumes no domain exit in normal case */
1786 info = pdev->dev.archdata.iommu;
1788 return info->domain;
1792 /* domain is initialized */
1793 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1795 struct dmar_domain *domain, *found = NULL;
1796 struct intel_iommu *iommu;
1797 struct dmar_drhd_unit *drhd;
1798 struct device_domain_info *info, *tmp;
1799 struct pci_dev *dev_tmp;
1800 unsigned long flags;
1801 int bus = 0, devfn = 0;
1805 domain = find_domain(pdev);
1809 segment = pci_domain_nr(pdev->bus);
1811 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1813 if (dev_tmp->is_pcie) {
1814 bus = dev_tmp->subordinate->number;
1817 bus = dev_tmp->bus->number;
1818 devfn = dev_tmp->devfn;
1820 spin_lock_irqsave(&device_domain_lock, flags);
1821 list_for_each_entry(info, &device_domain_list, global) {
1822 if (info->segment == segment &&
1823 info->bus == bus && info->devfn == devfn) {
1824 found = info->domain;
1828 spin_unlock_irqrestore(&device_domain_lock, flags);
1829 /* pcie-pci bridge already has a domain, uses it */
1836 domain = alloc_domain();
1840 /* Allocate new domain for the device */
1841 drhd = dmar_find_matched_drhd_unit(pdev);
1843 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1847 iommu = drhd->iommu;
1849 ret = iommu_attach_domain(domain, iommu);
1851 domain_exit(domain);
1855 if (domain_init(domain, gaw)) {
1856 domain_exit(domain);
1860 /* register pcie-to-pci device */
1862 info = alloc_devinfo_mem();
1864 domain_exit(domain);
1867 info->segment = segment;
1869 info->devfn = devfn;
1871 info->domain = domain;
1872 /* This domain is shared by devices under p2p bridge */
1873 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1875 /* pcie-to-pci bridge already has a domain, uses it */
1877 spin_lock_irqsave(&device_domain_lock, flags);
1878 list_for_each_entry(tmp, &device_domain_list, global) {
1879 if (tmp->segment == segment &&
1880 tmp->bus == bus && tmp->devfn == devfn) {
1881 found = tmp->domain;
1886 free_devinfo_mem(info);
1887 domain_exit(domain);
1890 list_add(&info->link, &domain->devices);
1891 list_add(&info->global, &device_domain_list);
1893 spin_unlock_irqrestore(&device_domain_lock, flags);
1897 info = alloc_devinfo_mem();
1900 info->segment = segment;
1901 info->bus = pdev->bus->number;
1902 info->devfn = pdev->devfn;
1904 info->domain = domain;
1905 spin_lock_irqsave(&device_domain_lock, flags);
1906 /* somebody is fast */
1907 found = find_domain(pdev);
1908 if (found != NULL) {
1909 spin_unlock_irqrestore(&device_domain_lock, flags);
1910 if (found != domain) {
1911 domain_exit(domain);
1914 free_devinfo_mem(info);
1917 list_add(&info->link, &domain->devices);
1918 list_add(&info->global, &device_domain_list);
1919 pdev->dev.archdata.iommu = info;
1920 spin_unlock_irqrestore(&device_domain_lock, flags);
1923 /* recheck it here, maybe others set it */
1924 return find_domain(pdev);
1927 static int iommu_identity_mapping;
1929 static int iommu_domain_identity_map(struct dmar_domain *domain,
1930 unsigned long long start,
1931 unsigned long long end)
1933 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1934 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1936 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1937 dma_to_mm_pfn(last_vpfn))) {
1938 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1942 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1943 start, end, domain->id);
1945 * RMRR range might have overlap with physical memory range,
1948 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1950 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1951 last_vpfn - first_vpfn + 1,
1952 DMA_PTE_READ|DMA_PTE_WRITE);
1955 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1956 unsigned long long start,
1957 unsigned long long end)
1959 struct dmar_domain *domain;
1963 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1964 pci_name(pdev), start, end);
1966 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1970 ret = iommu_domain_identity_map(domain, start, end);
1974 /* context entry init */
1975 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1982 domain_exit(domain);
1986 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1987 struct pci_dev *pdev)
1989 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1991 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1992 rmrr->end_address + 1);
1995 #ifdef CONFIG_DMAR_FLOPPY_WA
1996 static inline void iommu_prepare_isa(void)
1998 struct pci_dev *pdev;
2001 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2005 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2006 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
2009 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2010 "floppy might not work\n");
2014 static inline void iommu_prepare_isa(void)
2018 #endif /* !CONFIG_DMAR_FLPY_WA */
2020 /* Initialize each context entry as pass through.*/
2021 static int __init init_context_pass_through(void)
2023 struct pci_dev *pdev = NULL;
2024 struct dmar_domain *domain;
2027 for_each_pci_dev(pdev) {
2028 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2029 ret = domain_context_mapping(domain, pdev,
2030 CONTEXT_TT_PASS_THROUGH);
2037 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2039 static int __init si_domain_work_fn(unsigned long start_pfn,
2040 unsigned long end_pfn, void *datax)
2044 *ret = iommu_domain_identity_map(si_domain,
2045 (uint64_t)start_pfn << PAGE_SHIFT,
2046 (uint64_t)end_pfn << PAGE_SHIFT);
2051 static int si_domain_init(void)
2053 struct dmar_drhd_unit *drhd;
2054 struct intel_iommu *iommu;
2057 si_domain = alloc_domain();
2061 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2063 for_each_active_iommu(iommu, drhd) {
2064 ret = iommu_attach_domain(si_domain, iommu);
2066 domain_exit(si_domain);
2071 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2072 domain_exit(si_domain);
2076 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2078 for_each_online_node(nid) {
2079 work_with_active_regions(nid, si_domain_work_fn, &ret);
2087 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2088 struct pci_dev *pdev);
2089 static int identity_mapping(struct pci_dev *pdev)
2091 struct device_domain_info *info;
2093 if (likely(!iommu_identity_mapping))
2097 list_for_each_entry(info, &si_domain->devices, link)
2098 if (info->dev == pdev)
2103 static int domain_add_dev_info(struct dmar_domain *domain,
2104 struct pci_dev *pdev)
2106 struct device_domain_info *info;
2107 unsigned long flags;
2109 info = alloc_devinfo_mem();
2113 info->segment = pci_domain_nr(pdev->bus);
2114 info->bus = pdev->bus->number;
2115 info->devfn = pdev->devfn;
2117 info->domain = domain;
2119 spin_lock_irqsave(&device_domain_lock, flags);
2120 list_add(&info->link, &domain->devices);
2121 list_add(&info->global, &device_domain_list);
2122 pdev->dev.archdata.iommu = info;
2123 spin_unlock_irqrestore(&device_domain_lock, flags);
2128 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2130 if (iommu_identity_mapping == 2)
2131 return IS_GFX_DEVICE(pdev);
2134 * We want to start off with all devices in the 1:1 domain, and
2135 * take them out later if we find they can't access all of memory.
2137 * However, we can't do this for PCI devices behind bridges,
2138 * because all PCI devices behind the same bridge will end up
2139 * with the same source-id on their transactions.
2141 * Practically speaking, we can't change things around for these
2142 * devices at run-time, because we can't be sure there'll be no
2143 * DMA transactions in flight for any of their siblings.
2145 * So PCI devices (unless they're on the root bus) as well as
2146 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2147 * the 1:1 domain, just in _case_ one of their siblings turns out
2148 * not to be able to map all of memory.
2150 if (!pdev->is_pcie) {
2151 if (!pci_is_root_bus(pdev->bus))
2153 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2155 } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2159 * At boot time, we don't yet know if devices will be 64-bit capable.
2160 * Assume that they will -- if they turn out not to be, then we can
2161 * take them out of the 1:1 domain later.
2164 return pdev->dma_mask > DMA_BIT_MASK(32);
2169 static int iommu_prepare_static_identity_mapping(void)
2171 struct pci_dev *pdev = NULL;
2174 ret = si_domain_init();
2178 for_each_pci_dev(pdev) {
2179 if (iommu_should_identity_map(pdev, 1)) {
2180 printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2183 ret = domain_context_mapping(si_domain, pdev,
2184 CONTEXT_TT_MULTI_LEVEL);
2187 ret = domain_add_dev_info(si_domain, pdev);
2196 int __init init_dmars(void)
2198 struct dmar_drhd_unit *drhd;
2199 struct dmar_rmrr_unit *rmrr;
2200 struct pci_dev *pdev;
2201 struct intel_iommu *iommu;
2203 int pass_through = 1;
2206 * In case pass through can not be enabled, iommu tries to use identity
2209 if (iommu_pass_through)
2210 iommu_identity_mapping = 1;
2215 * initialize and program root entry to not present
2218 for_each_drhd_unit(drhd) {
2221 * lock not needed as this is only incremented in the single
2222 * threaded kernel __init code path all other access are read
2227 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2230 printk(KERN_ERR "Allocating global iommu array failed\n");
2235 deferred_flush = kzalloc(g_num_of_iommus *
2236 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2237 if (!deferred_flush) {
2243 for_each_drhd_unit(drhd) {
2247 iommu = drhd->iommu;
2248 g_iommus[iommu->seq_id] = iommu;
2250 ret = iommu_init_domains(iommu);
2256 * we could share the same root & context tables
2257 * amoung all IOMMU's. Need to Split it later.
2259 ret = iommu_alloc_root_entry(iommu);
2261 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2264 if (!ecap_pass_through(iommu->ecap))
2267 if (iommu_pass_through)
2268 if (!pass_through) {
2270 "Pass Through is not supported by hardware.\n");
2271 iommu_pass_through = 0;
2275 * Start from the sane iommu hardware state.
2277 for_each_drhd_unit(drhd) {
2281 iommu = drhd->iommu;
2284 * If the queued invalidation is already initialized by us
2285 * (for example, while enabling interrupt-remapping) then
2286 * we got the things already rolling from a sane state.
2292 * Clear any previous faults.
2294 dmar_fault(-1, iommu);
2296 * Disable queued invalidation if supported and already enabled
2297 * before OS handover.
2299 dmar_disable_qi(iommu);
2302 for_each_drhd_unit(drhd) {
2306 iommu = drhd->iommu;
2308 if (dmar_enable_qi(iommu)) {
2310 * Queued Invalidate not enabled, use Register Based
2313 iommu->flush.flush_context = __iommu_flush_context;
2314 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2315 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2317 (unsigned long long)drhd->reg_base_addr);
2319 iommu->flush.flush_context = qi_flush_context;
2320 iommu->flush.flush_iotlb = qi_flush_iotlb;
2321 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2323 (unsigned long long)drhd->reg_base_addr);
2328 * If pass through is set and enabled, context entries of all pci
2329 * devices are intialized by pass through translation type.
2331 if (iommu_pass_through) {
2332 ret = init_context_pass_through();
2334 printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2335 iommu_pass_through = 0;
2340 * If pass through is not set or not enabled, setup context entries for
2341 * identity mappings for rmrr, gfx, and isa and may fall back to static
2342 * identity mapping if iommu_identity_mapping is set.
2344 if (!iommu_pass_through) {
2345 #ifdef CONFIG_DMAR_BROKEN_GFX_WA
2346 if (!iommu_identity_mapping)
2347 iommu_identity_mapping = 2;
2349 if (iommu_identity_mapping)
2350 iommu_prepare_static_identity_mapping();
2353 * for each dev attached to rmrr
2355 * locate drhd for dev, alloc domain for dev
2356 * allocate free domain
2357 * allocate page table entries for rmrr
2358 * if context not allocated for bus
2359 * allocate and init context
2360 * set present in root table for this bus
2361 * init context with domain, translation etc
2365 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2366 for_each_rmrr_units(rmrr) {
2367 for (i = 0; i < rmrr->devices_cnt; i++) {
2368 pdev = rmrr->devices[i];
2370 * some BIOS lists non-exist devices in DMAR
2375 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2378 "IOMMU: mapping reserved region failed\n");
2382 iommu_prepare_isa();
2388 * global invalidate context cache
2389 * global invalidate iotlb
2390 * enable translation
2392 for_each_drhd_unit(drhd) {
2395 iommu = drhd->iommu;
2397 iommu_flush_write_buffer(iommu);
2399 ret = dmar_set_interrupt(iommu);
2403 iommu_set_root_entry(iommu);
2405 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2406 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2407 iommu_disable_protect_mem_regions(iommu);
2409 ret = iommu_enable_translation(iommu);
2416 for_each_drhd_unit(drhd) {
2419 iommu = drhd->iommu;
2426 /* This takes a number of _MM_ pages, not VTD pages */
2427 static struct iova *intel_alloc_iova(struct device *dev,
2428 struct dmar_domain *domain,
2429 unsigned long nrpages, uint64_t dma_mask)
2431 struct pci_dev *pdev = to_pci_dev(dev);
2432 struct iova *iova = NULL;
2434 /* Restrict dma_mask to the width that the iommu can handle */
2435 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2437 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2439 * First try to allocate an io virtual address in
2440 * DMA_BIT_MASK(32) and if that fails then try allocating
2443 iova = alloc_iova(&domain->iovad, nrpages,
2444 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2448 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2449 if (unlikely(!iova)) {
2450 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2451 nrpages, pci_name(pdev));
2458 static struct dmar_domain *
2459 get_valid_domain_for_dev(struct pci_dev *pdev)
2461 struct dmar_domain *domain;
2464 domain = get_domain_for_dev(pdev,
2465 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2468 "Allocating domain for %s failed", pci_name(pdev));
2472 /* make sure context mapping is ok */
2473 if (unlikely(!domain_context_mapped(pdev))) {
2474 ret = domain_context_mapping(domain, pdev,
2475 CONTEXT_TT_MULTI_LEVEL);
2478 "Domain context map for %s failed",
2487 static int iommu_dummy(struct pci_dev *pdev)
2489 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2492 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2493 static int iommu_no_mapping(struct device *dev)
2495 struct pci_dev *pdev;
2498 if (unlikely(dev->bus != &pci_bus_type))
2501 pdev = to_pci_dev(dev);
2502 if (iommu_dummy(pdev))
2505 if (!iommu_identity_mapping)
2508 found = identity_mapping(pdev);
2510 if (iommu_should_identity_map(pdev, 0))
2514 * 32 bit DMA is removed from si_domain and fall back
2515 * to non-identity mapping.
2517 domain_remove_one_dev_info(si_domain, pdev);
2518 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2524 * In case of a detached 64 bit DMA device from vm, the device
2525 * is put into si_domain for identity mapping.
2527 if (iommu_should_identity_map(pdev, 0)) {
2529 ret = domain_add_dev_info(si_domain, pdev);
2532 ret = domain_context_mapping(si_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2534 printk(KERN_INFO "64bit %s uses identity mapping\n",
2544 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2545 size_t size, int dir, u64 dma_mask)
2547 struct pci_dev *pdev = to_pci_dev(hwdev);
2548 struct dmar_domain *domain;
2549 phys_addr_t start_paddr;
2553 struct intel_iommu *iommu;
2554 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2556 BUG_ON(dir == DMA_NONE);
2558 if (iommu_no_mapping(hwdev))
2561 domain = get_valid_domain_for_dev(pdev);
2565 iommu = domain_get_iommu(domain);
2566 size = aligned_nrpages(paddr, size);
2568 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2574 * Check if DMAR supports zero-length reads on write only
2577 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2578 !cap_zlr(iommu->cap))
2579 prot |= DMA_PTE_READ;
2580 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2581 prot |= DMA_PTE_WRITE;
2583 * paddr - (paddr + size) might be partial page, we should map the whole
2584 * page. Note: if two part of one page are separately mapped, we
2585 * might have two guest_addr mapping to the same host paddr, but this
2586 * is not a big problem
2588 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2589 mm_to_dma_pfn(paddr_pfn), size, prot);
2593 /* it's a non-present to present mapping. Only flush if caching mode */
2594 if (cap_caching_mode(iommu->cap))
2595 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2597 iommu_flush_write_buffer(iommu);
2599 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2600 start_paddr += paddr & ~PAGE_MASK;
2605 __free_iova(&domain->iovad, iova);
2606 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2607 pci_name(pdev), size, (unsigned long long)paddr, dir);
2611 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2612 unsigned long offset, size_t size,
2613 enum dma_data_direction dir,
2614 struct dma_attrs *attrs)
2616 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2617 dir, to_pci_dev(dev)->dma_mask);
2620 static void flush_unmaps(void)
2626 /* just flush them all */
2627 for (i = 0; i < g_num_of_iommus; i++) {
2628 struct intel_iommu *iommu = g_iommus[i];
2632 if (!deferred_flush[i].next)
2635 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2636 DMA_TLB_GLOBAL_FLUSH);
2637 for (j = 0; j < deferred_flush[i].next; j++) {
2639 struct iova *iova = deferred_flush[i].iova[j];
2641 mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2642 mask = ilog2(mask >> VTD_PAGE_SHIFT);
2643 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2644 iova->pfn_lo << PAGE_SHIFT, mask);
2645 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2647 deferred_flush[i].next = 0;
2653 static void flush_unmaps_timeout(unsigned long data)
2655 unsigned long flags;
2657 spin_lock_irqsave(&async_umap_flush_lock, flags);
2659 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2662 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2664 unsigned long flags;
2666 struct intel_iommu *iommu;
2668 spin_lock_irqsave(&async_umap_flush_lock, flags);
2669 if (list_size == HIGH_WATER_MARK)
2672 iommu = domain_get_iommu(dom);
2673 iommu_id = iommu->seq_id;
2675 next = deferred_flush[iommu_id].next;
2676 deferred_flush[iommu_id].domain[next] = dom;
2677 deferred_flush[iommu_id].iova[next] = iova;
2678 deferred_flush[iommu_id].next++;
2681 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2685 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2688 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2689 size_t size, enum dma_data_direction dir,
2690 struct dma_attrs *attrs)
2692 struct pci_dev *pdev = to_pci_dev(dev);
2693 struct dmar_domain *domain;
2694 unsigned long start_pfn, last_pfn;
2696 struct intel_iommu *iommu;
2698 if (iommu_no_mapping(dev))
2701 domain = find_domain(pdev);
2704 iommu = domain_get_iommu(domain);
2706 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2707 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2708 (unsigned long long)dev_addr))
2711 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2712 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2714 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2715 pci_name(pdev), start_pfn, last_pfn);
2717 /* clear the whole page */
2718 dma_pte_clear_range(domain, start_pfn, last_pfn);
2720 /* free page tables */
2721 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2723 if (intel_iommu_strict) {
2724 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2725 last_pfn - start_pfn + 1);
2727 __free_iova(&domain->iovad, iova);
2729 add_unmap(domain, iova);
2731 * queue up the release of the unmap to save the 1/6th of the
2732 * cpu used up by the iotlb flush operation...
2737 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2740 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2743 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2744 dma_addr_t *dma_handle, gfp_t flags)
2749 size = PAGE_ALIGN(size);
2750 order = get_order(size);
2751 flags &= ~(GFP_DMA | GFP_DMA32);
2753 vaddr = (void *)__get_free_pages(flags, order);
2756 memset(vaddr, 0, size);
2758 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2760 hwdev->coherent_dma_mask);
2763 free_pages((unsigned long)vaddr, order);
2767 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2768 dma_addr_t dma_handle)
2772 size = PAGE_ALIGN(size);
2773 order = get_order(size);
2775 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2776 free_pages((unsigned long)vaddr, order);
2779 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2780 int nelems, enum dma_data_direction dir,
2781 struct dma_attrs *attrs)
2783 struct pci_dev *pdev = to_pci_dev(hwdev);
2784 struct dmar_domain *domain;
2785 unsigned long start_pfn, last_pfn;
2787 struct intel_iommu *iommu;
2789 if (iommu_no_mapping(hwdev))
2792 domain = find_domain(pdev);
2795 iommu = domain_get_iommu(domain);
2797 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2798 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2799 (unsigned long long)sglist[0].dma_address))
2802 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2803 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2805 /* clear the whole page */
2806 dma_pte_clear_range(domain, start_pfn, last_pfn);
2808 /* free page tables */
2809 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2811 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2812 (last_pfn - start_pfn + 1));
2815 __free_iova(&domain->iovad, iova);
2818 static int intel_nontranslate_map_sg(struct device *hddev,
2819 struct scatterlist *sglist, int nelems, int dir)
2822 struct scatterlist *sg;
2824 for_each_sg(sglist, sg, nelems, i) {
2825 BUG_ON(!sg_page(sg));
2826 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2827 sg->dma_length = sg->length;
2832 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2833 enum dma_data_direction dir, struct dma_attrs *attrs)
2836 struct pci_dev *pdev = to_pci_dev(hwdev);
2837 struct dmar_domain *domain;
2840 size_t offset_pfn = 0;
2841 struct iova *iova = NULL;
2843 struct scatterlist *sg;
2844 unsigned long start_vpfn;
2845 struct intel_iommu *iommu;
2847 BUG_ON(dir == DMA_NONE);
2848 if (iommu_no_mapping(hwdev))
2849 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2851 domain = get_valid_domain_for_dev(pdev);
2855 iommu = domain_get_iommu(domain);
2857 for_each_sg(sglist, sg, nelems, i)
2858 size += aligned_nrpages(sg->offset, sg->length);
2860 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2863 sglist->dma_length = 0;
2868 * Check if DMAR supports zero-length reads on write only
2871 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2872 !cap_zlr(iommu->cap))
2873 prot |= DMA_PTE_READ;
2874 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2875 prot |= DMA_PTE_WRITE;
2877 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2879 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
2880 if (unlikely(ret)) {
2881 /* clear the page */
2882 dma_pte_clear_range(domain, start_vpfn,
2883 start_vpfn + size - 1);
2884 /* free page tables */
2885 dma_pte_free_pagetable(domain, start_vpfn,
2886 start_vpfn + size - 1);
2888 __free_iova(&domain->iovad, iova);
2892 /* it's a non-present to present mapping. Only flush if caching mode */
2893 if (cap_caching_mode(iommu->cap))
2894 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2896 iommu_flush_write_buffer(iommu);
2901 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2906 struct dma_map_ops intel_dma_ops = {
2907 .alloc_coherent = intel_alloc_coherent,
2908 .free_coherent = intel_free_coherent,
2909 .map_sg = intel_map_sg,
2910 .unmap_sg = intel_unmap_sg,
2911 .map_page = intel_map_page,
2912 .unmap_page = intel_unmap_page,
2913 .mapping_error = intel_mapping_error,
2916 static inline int iommu_domain_cache_init(void)
2920 iommu_domain_cache = kmem_cache_create("iommu_domain",
2921 sizeof(struct dmar_domain),
2926 if (!iommu_domain_cache) {
2927 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2934 static inline int iommu_devinfo_cache_init(void)
2938 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2939 sizeof(struct device_domain_info),
2943 if (!iommu_devinfo_cache) {
2944 printk(KERN_ERR "Couldn't create devinfo cache\n");
2951 static inline int iommu_iova_cache_init(void)
2955 iommu_iova_cache = kmem_cache_create("iommu_iova",
2956 sizeof(struct iova),
2960 if (!iommu_iova_cache) {
2961 printk(KERN_ERR "Couldn't create iova cache\n");
2968 static int __init iommu_init_mempool(void)
2971 ret = iommu_iova_cache_init();
2975 ret = iommu_domain_cache_init();
2979 ret = iommu_devinfo_cache_init();
2983 kmem_cache_destroy(iommu_domain_cache);
2985 kmem_cache_destroy(iommu_iova_cache);
2990 static void __init iommu_exit_mempool(void)
2992 kmem_cache_destroy(iommu_devinfo_cache);
2993 kmem_cache_destroy(iommu_domain_cache);
2994 kmem_cache_destroy(iommu_iova_cache);
2998 static void __init init_no_remapping_devices(void)
3000 struct dmar_drhd_unit *drhd;
3002 for_each_drhd_unit(drhd) {
3003 if (!drhd->include_all) {
3005 for (i = 0; i < drhd->devices_cnt; i++)
3006 if (drhd->devices[i] != NULL)
3008 /* ignore DMAR unit if no pci devices exist */
3009 if (i == drhd->devices_cnt)
3017 for_each_drhd_unit(drhd) {
3019 if (drhd->ignored || drhd->include_all)
3022 for (i = 0; i < drhd->devices_cnt; i++)
3023 if (drhd->devices[i] &&
3024 !IS_GFX_DEVICE(drhd->devices[i]))
3027 if (i < drhd->devices_cnt)
3030 /* bypass IOMMU if it is just for gfx devices */
3032 for (i = 0; i < drhd->devices_cnt; i++) {
3033 if (!drhd->devices[i])
3035 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3040 #ifdef CONFIG_SUSPEND
3041 static int init_iommu_hw(void)
3043 struct dmar_drhd_unit *drhd;
3044 struct intel_iommu *iommu = NULL;
3046 for_each_active_iommu(iommu, drhd)
3048 dmar_reenable_qi(iommu);
3050 for_each_active_iommu(iommu, drhd) {
3051 iommu_flush_write_buffer(iommu);
3053 iommu_set_root_entry(iommu);
3055 iommu->flush.flush_context(iommu, 0, 0, 0,
3056 DMA_CCMD_GLOBAL_INVL);
3057 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3058 DMA_TLB_GLOBAL_FLUSH);
3059 iommu_disable_protect_mem_regions(iommu);
3060 iommu_enable_translation(iommu);
3066 static void iommu_flush_all(void)
3068 struct dmar_drhd_unit *drhd;
3069 struct intel_iommu *iommu;
3071 for_each_active_iommu(iommu, drhd) {
3072 iommu->flush.flush_context(iommu, 0, 0, 0,
3073 DMA_CCMD_GLOBAL_INVL);
3074 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3075 DMA_TLB_GLOBAL_FLUSH);
3079 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3081 struct dmar_drhd_unit *drhd;
3082 struct intel_iommu *iommu = NULL;
3085 for_each_active_iommu(iommu, drhd) {
3086 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3088 if (!iommu->iommu_state)
3094 for_each_active_iommu(iommu, drhd) {
3095 iommu_disable_translation(iommu);
3097 spin_lock_irqsave(&iommu->register_lock, flag);
3099 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3100 readl(iommu->reg + DMAR_FECTL_REG);
3101 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3102 readl(iommu->reg + DMAR_FEDATA_REG);
3103 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3104 readl(iommu->reg + DMAR_FEADDR_REG);
3105 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3106 readl(iommu->reg + DMAR_FEUADDR_REG);
3108 spin_unlock_irqrestore(&iommu->register_lock, flag);
3113 for_each_active_iommu(iommu, drhd)
3114 kfree(iommu->iommu_state);
3119 static int iommu_resume(struct sys_device *dev)
3121 struct dmar_drhd_unit *drhd;
3122 struct intel_iommu *iommu = NULL;
3125 if (init_iommu_hw()) {
3126 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3130 for_each_active_iommu(iommu, drhd) {
3132 spin_lock_irqsave(&iommu->register_lock, flag);
3134 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3135 iommu->reg + DMAR_FECTL_REG);
3136 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3137 iommu->reg + DMAR_FEDATA_REG);
3138 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3139 iommu->reg + DMAR_FEADDR_REG);
3140 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3141 iommu->reg + DMAR_FEUADDR_REG);
3143 spin_unlock_irqrestore(&iommu->register_lock, flag);
3146 for_each_active_iommu(iommu, drhd)
3147 kfree(iommu->iommu_state);
3152 static struct sysdev_class iommu_sysclass = {
3154 .resume = iommu_resume,
3155 .suspend = iommu_suspend,
3158 static struct sys_device device_iommu = {
3159 .cls = &iommu_sysclass,
3162 static int __init init_iommu_sysfs(void)
3166 error = sysdev_class_register(&iommu_sysclass);
3170 error = sysdev_register(&device_iommu);
3172 sysdev_class_unregister(&iommu_sysclass);
3178 static int __init init_iommu_sysfs(void)
3182 #endif /* CONFIG_PM */
3184 int __init intel_iommu_init(void)
3188 if (dmar_table_init())
3191 if (dmar_dev_scope_init())
3195 * Check the need for DMA-remapping initialization now.
3196 * Above initialization will also be used by Interrupt-remapping.
3198 if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3201 iommu_init_mempool();
3202 dmar_init_reserved_ranges();
3204 init_no_remapping_devices();
3208 printk(KERN_ERR "IOMMU: dmar init failed\n");
3209 put_iova_domain(&reserved_iova_list);
3210 iommu_exit_mempool();
3214 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3216 init_timer(&unmap_timer);
3219 if (!iommu_pass_through) {
3221 "Multi-level page-table translation for DMAR.\n");
3222 dma_ops = &intel_dma_ops;
3225 "DMAR: Pass through translation for DMAR.\n");
3229 register_iommu(&intel_iommu_ops);
3234 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3235 struct pci_dev *pdev)
3237 struct pci_dev *tmp, *parent;
3239 if (!iommu || !pdev)
3242 /* dependent device detach */
3243 tmp = pci_find_upstream_pcie_bridge(pdev);
3244 /* Secondary interface's bus number and devfn 0 */
3246 parent = pdev->bus->self;
3247 while (parent != tmp) {
3248 iommu_detach_dev(iommu, parent->bus->number,
3250 parent = parent->bus->self;
3252 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3253 iommu_detach_dev(iommu,
3254 tmp->subordinate->number, 0);
3255 else /* this is a legacy PCI bridge */
3256 iommu_detach_dev(iommu, tmp->bus->number,
3261 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3262 struct pci_dev *pdev)
3264 struct device_domain_info *info;
3265 struct intel_iommu *iommu;
3266 unsigned long flags;
3268 struct list_head *entry, *tmp;
3270 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3275 spin_lock_irqsave(&device_domain_lock, flags);
3276 list_for_each_safe(entry, tmp, &domain->devices) {
3277 info = list_entry(entry, struct device_domain_info, link);
3278 /* No need to compare PCI domain; it has to be the same */
3279 if (info->bus == pdev->bus->number &&
3280 info->devfn == pdev->devfn) {
3281 list_del(&info->link);
3282 list_del(&info->global);
3284 info->dev->dev.archdata.iommu = NULL;
3285 spin_unlock_irqrestore(&device_domain_lock, flags);
3287 iommu_disable_dev_iotlb(info);
3288 iommu_detach_dev(iommu, info->bus, info->devfn);
3289 iommu_detach_dependent_devices(iommu, pdev);
3290 free_devinfo_mem(info);
3292 spin_lock_irqsave(&device_domain_lock, flags);
3300 /* if there is no other devices under the same iommu
3301 * owned by this domain, clear this iommu in iommu_bmp
3302 * update iommu count and coherency
3304 if (iommu == device_to_iommu(info->segment, info->bus,
3310 unsigned long tmp_flags;
3311 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3312 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3313 domain->iommu_count--;
3314 domain_update_iommu_cap(domain);
3315 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3318 spin_unlock_irqrestore(&device_domain_lock, flags);
3321 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3323 struct device_domain_info *info;
3324 struct intel_iommu *iommu;
3325 unsigned long flags1, flags2;
3327 spin_lock_irqsave(&device_domain_lock, flags1);
3328 while (!list_empty(&domain->devices)) {
3329 info = list_entry(domain->devices.next,
3330 struct device_domain_info, link);
3331 list_del(&info->link);
3332 list_del(&info->global);
3334 info->dev->dev.archdata.iommu = NULL;
3336 spin_unlock_irqrestore(&device_domain_lock, flags1);
3338 iommu_disable_dev_iotlb(info);
3339 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3340 iommu_detach_dev(iommu, info->bus, info->devfn);
3341 iommu_detach_dependent_devices(iommu, info->dev);
3343 /* clear this iommu in iommu_bmp, update iommu count
3346 spin_lock_irqsave(&domain->iommu_lock, flags2);
3347 if (test_and_clear_bit(iommu->seq_id,
3348 &domain->iommu_bmp)) {
3349 domain->iommu_count--;
3350 domain_update_iommu_cap(domain);
3352 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3354 free_devinfo_mem(info);
3355 spin_lock_irqsave(&device_domain_lock, flags1);
3357 spin_unlock_irqrestore(&device_domain_lock, flags1);
3360 /* domain id for virtual machine, it won't be set in context */
3361 static unsigned long vm_domid;
3363 static int vm_domain_min_agaw(struct dmar_domain *domain)
3366 int min_agaw = domain->agaw;
3368 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3369 for (; i < g_num_of_iommus; ) {
3370 if (min_agaw > g_iommus[i]->agaw)
3371 min_agaw = g_iommus[i]->agaw;
3373 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3379 static struct dmar_domain *iommu_alloc_vm_domain(void)
3381 struct dmar_domain *domain;
3383 domain = alloc_domain_mem();
3387 domain->id = vm_domid++;
3388 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3389 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3394 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3398 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3399 spin_lock_init(&domain->iommu_lock);
3401 domain_reserve_special_ranges(domain);
3403 /* calculate AGAW */
3404 domain->gaw = guest_width;
3405 adjust_width = guestwidth_to_adjustwidth(guest_width);
3406 domain->agaw = width_to_agaw(adjust_width);
3408 INIT_LIST_HEAD(&domain->devices);
3410 domain->iommu_count = 0;
3411 domain->iommu_coherency = 0;
3412 domain->max_addr = 0;
3414 /* always allocate the top pgd */
3415 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3418 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3422 static void iommu_free_vm_domain(struct dmar_domain *domain)
3424 unsigned long flags;
3425 struct dmar_drhd_unit *drhd;
3426 struct intel_iommu *iommu;
3428 unsigned long ndomains;
3430 for_each_drhd_unit(drhd) {
3433 iommu = drhd->iommu;
3435 ndomains = cap_ndoms(iommu->cap);
3436 i = find_first_bit(iommu->domain_ids, ndomains);
3437 for (; i < ndomains; ) {
3438 if (iommu->domains[i] == domain) {
3439 spin_lock_irqsave(&iommu->lock, flags);
3440 clear_bit(i, iommu->domain_ids);
3441 iommu->domains[i] = NULL;
3442 spin_unlock_irqrestore(&iommu->lock, flags);
3445 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3450 static void vm_domain_exit(struct dmar_domain *domain)
3452 /* Domain 0 is reserved, so dont process it */
3456 vm_domain_remove_all_dev_info(domain);
3458 put_iova_domain(&domain->iovad);
3461 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3463 /* free page tables */
3464 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3466 iommu_free_vm_domain(domain);
3467 free_domain_mem(domain);
3470 static int intel_iommu_domain_init(struct iommu_domain *domain)
3472 struct dmar_domain *dmar_domain;
3474 dmar_domain = iommu_alloc_vm_domain();
3477 "intel_iommu_domain_init: dmar_domain == NULL\n");
3480 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3482 "intel_iommu_domain_init() failed\n");
3483 vm_domain_exit(dmar_domain);
3486 domain->priv = dmar_domain;
3491 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3493 struct dmar_domain *dmar_domain = domain->priv;
3495 domain->priv = NULL;
3496 vm_domain_exit(dmar_domain);
3499 static int intel_iommu_attach_device(struct iommu_domain *domain,
3502 struct dmar_domain *dmar_domain = domain->priv;
3503 struct pci_dev *pdev = to_pci_dev(dev);
3504 struct intel_iommu *iommu;
3509 /* normally pdev is not mapped */
3510 if (unlikely(domain_context_mapped(pdev))) {
3511 struct dmar_domain *old_domain;
3513 old_domain = find_domain(pdev);
3515 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3516 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3517 domain_remove_one_dev_info(old_domain, pdev);
3519 domain_remove_dev_info(old_domain);
3523 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3528 /* check if this iommu agaw is sufficient for max mapped address */
3529 addr_width = agaw_to_width(iommu->agaw);
3530 end = DOMAIN_MAX_ADDR(addr_width);
3531 end = end & VTD_PAGE_MASK;
3532 if (end < dmar_domain->max_addr) {
3533 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3534 "sufficient for the mapped address (%llx)\n",
3535 __func__, iommu->agaw, dmar_domain->max_addr);
3539 ret = domain_add_dev_info(dmar_domain, pdev);
3543 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3547 static void intel_iommu_detach_device(struct iommu_domain *domain,
3550 struct dmar_domain *dmar_domain = domain->priv;
3551 struct pci_dev *pdev = to_pci_dev(dev);
3553 domain_remove_one_dev_info(dmar_domain, pdev);
3556 static int intel_iommu_map_range(struct iommu_domain *domain,
3557 unsigned long iova, phys_addr_t hpa,
3558 size_t size, int iommu_prot)
3560 struct dmar_domain *dmar_domain = domain->priv;
3566 if (iommu_prot & IOMMU_READ)
3567 prot |= DMA_PTE_READ;
3568 if (iommu_prot & IOMMU_WRITE)
3569 prot |= DMA_PTE_WRITE;
3570 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3571 prot |= DMA_PTE_SNP;
3573 max_addr = iova + size;
3574 if (dmar_domain->max_addr < max_addr) {
3578 /* check if minimum agaw is sufficient for mapped address */
3579 min_agaw = vm_domain_min_agaw(dmar_domain);
3580 addr_width = agaw_to_width(min_agaw);
3581 end = DOMAIN_MAX_ADDR(addr_width);
3582 end = end & VTD_PAGE_MASK;
3583 if (end < max_addr) {
3584 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3585 "sufficient for the mapped address (%llx)\n",
3586 __func__, min_agaw, max_addr);
3589 dmar_domain->max_addr = max_addr;
3591 /* Round up size to next multiple of PAGE_SIZE, if it and
3592 the low bits of hpa would take us onto the next page */
3593 size = aligned_nrpages(hpa, size);
3594 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3595 hpa >> VTD_PAGE_SHIFT, size, prot);
3599 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3600 unsigned long iova, size_t size)
3602 struct dmar_domain *dmar_domain = domain->priv;
3607 dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3608 (iova + size - 1) >> VTD_PAGE_SHIFT);
3610 if (dmar_domain->max_addr == iova + size)
3611 dmar_domain->max_addr = iova;
3614 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3617 struct dmar_domain *dmar_domain = domain->priv;
3618 struct dma_pte *pte;
3621 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3623 phys = dma_pte_addr(pte);
3628 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3631 struct dmar_domain *dmar_domain = domain->priv;
3633 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3634 return dmar_domain->iommu_snooping;
3639 static struct iommu_ops intel_iommu_ops = {
3640 .domain_init = intel_iommu_domain_init,
3641 .domain_destroy = intel_iommu_domain_destroy,
3642 .attach_dev = intel_iommu_attach_device,
3643 .detach_dev = intel_iommu_detach_device,
3644 .map = intel_iommu_map_range,
3645 .unmap = intel_iommu_unmap_range,
3646 .iova_to_phys = intel_iommu_iova_to_phys,
3647 .domain_has_cap = intel_iommu_domain_has_cap,
3650 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3653 * Mobile 4 Series Chipset neglects to set RWBF capability,
3656 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);