Automatic merge with /usr/src/ntfs-2.6.git.
[linux-2.6] / drivers / video / aty / radeon_base.c
1 /*
2  *      drivers/video/aty/radeon_base.c
3  *
4  *      framebuffer driver for ATI Radeon chipset video boards
5  *
6  *      Copyright 2003  Ben. Herrenschmidt <benh@kernel.crashing.org>
7  *      Copyright 2000  Ani Joshi <ajoshi@kernel.crashing.org>
8  *
9  *      i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10  *      
11  *      Special thanks to ATI DevRel team for their hardware donations.
12  *
13  *      ...Insert GPL boilerplate here...
14  *
15  *      Significant portions of this driver apdated from XFree86 Radeon
16  *      driver which has the following copyright notice:
17  *
18  *      Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19  *                     VA Linux Systems Inc., Fremont, California.
20  *
21  *      All Rights Reserved.
22  *
23  *      Permission is hereby granted, free of charge, to any person obtaining
24  *      a copy of this software and associated documentation files (the
25  *      "Software"), to deal in the Software without restriction, including
26  *      without limitation on the rights to use, copy, modify, merge,
27  *      publish, distribute, sublicense, and/or sell copies of the Software,
28  *      and to permit persons to whom the Software is furnished to do so,
29  *      subject to the following conditions:
30  *
31  *      The above copyright notice and this permission notice (including the
32  *      next paragraph) shall be included in all copies or substantial
33  *      portions of the Software.
34  *
35  *      THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36  *      EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37  *      MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38  *      NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39  *      THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40  *      WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41  *      OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42  *      DEALINGS IN THE SOFTWARE.
43  *
44  *      XFree86 driver authors:
45  *
46  *         Kevin E. Martin <martin@xfree86.org>
47  *         Rickard E. Faith <faith@valinux.com>
48  *         Alan Hourihane <alanh@fairlite.demon.co.uk>
49  *
50  */
51
52
53 #define RADEON_VERSION  "0.2.0"
54
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/errno.h>
60 #include <linux/string.h>
61 #include <linux/mm.h>
62 #include <linux/tty.h>
63 #include <linux/slab.h>
64 #include <linux/delay.h>
65 #include <linux/time.h>
66 #include <linux/fb.h>
67 #include <linux/ioport.h>
68 #include <linux/init.h>
69 #include <linux/pci.h>
70 #include <linux/vmalloc.h>
71 #include <linux/device.h>
72 #include <linux/i2c.h>
73
74 #include <asm/io.h>
75 #include <asm/uaccess.h>
76
77 #ifdef CONFIG_PPC_OF
78
79 #include <asm/pci-bridge.h>
80 #include "../macmodes.h"
81
82 #ifdef CONFIG_PMAC_BACKLIGHT
83 #include <asm/backlight.h>
84 #endif
85
86 #ifdef CONFIG_BOOTX_TEXT
87 #include <asm/btext.h>
88 #endif
89
90 #endif /* CONFIG_PPC_OF */
91
92 #ifdef CONFIG_MTRR
93 #include <asm/mtrr.h>
94 #endif
95
96 #include <video/radeon.h>
97 #include <linux/radeonfb.h>
98
99 #include "../edid.h" // MOVE THAT TO include/video
100 #include "ati_ids.h"
101 #include "radeonfb.h"               
102
103 #define MAX_MAPPED_VRAM (2048*2048*4)
104 #define MIN_MAPPED_VRAM (1024*768*1)
105
106 #define CHIP_DEF(id, family, flags)                                     \
107         { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
108
109 static struct pci_device_id radeonfb_pci_table[] = {
110         /* Mobility M6 */
111         CHIP_DEF(PCI_CHIP_RADEON_LY,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
112         CHIP_DEF(PCI_CHIP_RADEON_LZ,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
113         /* Radeon VE/7000 */
114         CHIP_DEF(PCI_CHIP_RV100_QY,     RV100,  CHIP_HAS_CRTC2),
115         CHIP_DEF(PCI_CHIP_RV100_QZ,     RV100,  CHIP_HAS_CRTC2),
116         /* Radeon IGP320M (U1) */
117         CHIP_DEF(PCI_CHIP_RS100_4336,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
118         /* Radeon IGP320 (A3) */
119         CHIP_DEF(PCI_CHIP_RS100_4136,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP), 
120         /* IGP330M/340M/350M (U2) */
121         CHIP_DEF(PCI_CHIP_RS200_4337,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
122         /* IGP330/340/350 (A4) */
123         CHIP_DEF(PCI_CHIP_RS200_4137,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
124         /* Mobility 7000 IGP */
125         CHIP_DEF(PCI_CHIP_RS250_4437,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
126         /* 7000 IGP (A4+) */
127         CHIP_DEF(PCI_CHIP_RS250_4237,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
128         /* 8500 AIW */
129         CHIP_DEF(PCI_CHIP_R200_BB,      R200,   CHIP_HAS_CRTC2),
130         CHIP_DEF(PCI_CHIP_R200_BC,      R200,   CHIP_HAS_CRTC2),
131         /* 8700/8800 */
132         CHIP_DEF(PCI_CHIP_R200_QH,      R200,   CHIP_HAS_CRTC2),
133         /* 8500 */
134         CHIP_DEF(PCI_CHIP_R200_QL,      R200,   CHIP_HAS_CRTC2),
135         /* 9100 */
136         CHIP_DEF(PCI_CHIP_R200_QM,      R200,   CHIP_HAS_CRTC2),
137         /* Mobility M7 */
138         CHIP_DEF(PCI_CHIP_RADEON_LW,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139         CHIP_DEF(PCI_CHIP_RADEON_LX,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140         /* 7500 */
141         CHIP_DEF(PCI_CHIP_RV200_QW,     RV200,  CHIP_HAS_CRTC2),
142         CHIP_DEF(PCI_CHIP_RV200_QX,     RV200,  CHIP_HAS_CRTC2),
143         /* Mobility M9 */
144         CHIP_DEF(PCI_CHIP_RV250_Ld,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145         CHIP_DEF(PCI_CHIP_RV250_Le,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146         CHIP_DEF(PCI_CHIP_RV250_Lf,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147         CHIP_DEF(PCI_CHIP_RV250_Lg,     RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
148         /* 9000/Pro */
149         CHIP_DEF(PCI_CHIP_RV250_If,     RV250,  CHIP_HAS_CRTC2),
150         CHIP_DEF(PCI_CHIP_RV250_Ig,     RV250,  CHIP_HAS_CRTC2),
151         /* Mobility 9100 IGP (U3) */
152         CHIP_DEF(PCI_CHIP_RS300_5835,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
153         CHIP_DEF(PCI_CHIP_RS350_7835,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154         /* 9100 IGP (A5) */
155         CHIP_DEF(PCI_CHIP_RS300_5834,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
156         CHIP_DEF(PCI_CHIP_RS350_7834,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157         /* Mobility 9200 (M9+) */
158         CHIP_DEF(PCI_CHIP_RV280_5C61,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
159         CHIP_DEF(PCI_CHIP_RV280_5C63,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160         /* 9200 */
161         CHIP_DEF(PCI_CHIP_RV280_5960,   RV280,  CHIP_HAS_CRTC2),
162         CHIP_DEF(PCI_CHIP_RV280_5961,   RV280,  CHIP_HAS_CRTC2),
163         CHIP_DEF(PCI_CHIP_RV280_5962,   RV280,  CHIP_HAS_CRTC2),
164         CHIP_DEF(PCI_CHIP_RV280_5964,   RV280,  CHIP_HAS_CRTC2),
165         /* 9500 */
166         CHIP_DEF(PCI_CHIP_R300_AD,      R300,   CHIP_HAS_CRTC2),
167         CHIP_DEF(PCI_CHIP_R300_AE,      R300,   CHIP_HAS_CRTC2),
168         /* 9600TX / FireGL Z1 */
169         CHIP_DEF(PCI_CHIP_R300_AF,      R300,   CHIP_HAS_CRTC2),
170         CHIP_DEF(PCI_CHIP_R300_AG,      R300,   CHIP_HAS_CRTC2),
171         /* 9700/9500/Pro/FireGL X1 */
172         CHIP_DEF(PCI_CHIP_R300_ND,      R300,   CHIP_HAS_CRTC2),
173         CHIP_DEF(PCI_CHIP_R300_NE,      R300,   CHIP_HAS_CRTC2),
174         CHIP_DEF(PCI_CHIP_R300_NF,      R300,   CHIP_HAS_CRTC2),
175         CHIP_DEF(PCI_CHIP_R300_NG,      R300,   CHIP_HAS_CRTC2),
176         /* Mobility M10/M11 */
177         CHIP_DEF(PCI_CHIP_RV350_NP,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178         CHIP_DEF(PCI_CHIP_RV350_NQ,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179         CHIP_DEF(PCI_CHIP_RV350_NR,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180         CHIP_DEF(PCI_CHIP_RV350_NS,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181         CHIP_DEF(PCI_CHIP_RV350_NT,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182         CHIP_DEF(PCI_CHIP_RV350_NV,     RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183         /* 9600/FireGL T2 */
184         CHIP_DEF(PCI_CHIP_RV350_AP,     RV350,  CHIP_HAS_CRTC2),
185         CHIP_DEF(PCI_CHIP_RV350_AQ,     RV350,  CHIP_HAS_CRTC2),
186         CHIP_DEF(PCI_CHIP_RV360_AR,     RV350,  CHIP_HAS_CRTC2),
187         CHIP_DEF(PCI_CHIP_RV350_AS,     RV350,  CHIP_HAS_CRTC2),
188         CHIP_DEF(PCI_CHIP_RV350_AT,     RV350,  CHIP_HAS_CRTC2),
189         CHIP_DEF(PCI_CHIP_RV350_AV,     RV350,  CHIP_HAS_CRTC2),
190         /* 9800/Pro/FileGL X2 */
191         CHIP_DEF(PCI_CHIP_R350_AH,      R350,   CHIP_HAS_CRTC2),
192         CHIP_DEF(PCI_CHIP_R350_AI,      R350,   CHIP_HAS_CRTC2),
193         CHIP_DEF(PCI_CHIP_R350_AJ,      R350,   CHIP_HAS_CRTC2),
194         CHIP_DEF(PCI_CHIP_R350_AK,      R350,   CHIP_HAS_CRTC2),
195         CHIP_DEF(PCI_CHIP_R350_NH,      R350,   CHIP_HAS_CRTC2),
196         CHIP_DEF(PCI_CHIP_R350_NI,      R350,   CHIP_HAS_CRTC2),
197         CHIP_DEF(PCI_CHIP_R360_NJ,      R350,   CHIP_HAS_CRTC2),
198         CHIP_DEF(PCI_CHIP_R350_NK,      R350,   CHIP_HAS_CRTC2),
199         /* Newer stuff */
200         CHIP_DEF(PCI_CHIP_RV380_3E50,   RV380,  CHIP_HAS_CRTC2),
201         CHIP_DEF(PCI_CHIP_RV380_3E54,   RV380,  CHIP_HAS_CRTC2),
202         CHIP_DEF(PCI_CHIP_RV380_3150,   RV380,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203         CHIP_DEF(PCI_CHIP_RV380_3154,   RV380,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204         CHIP_DEF(PCI_CHIP_RV370_5B60,   RV380,  CHIP_HAS_CRTC2),
205         CHIP_DEF(PCI_CHIP_RV370_5B62,   RV380,  CHIP_HAS_CRTC2),
206         CHIP_DEF(PCI_CHIP_RV370_5B64,   RV380,  CHIP_HAS_CRTC2),
207         CHIP_DEF(PCI_CHIP_RV370_5B65,   RV380,  CHIP_HAS_CRTC2),
208         CHIP_DEF(PCI_CHIP_RV370_5460,   RV380,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
209         CHIP_DEF(PCI_CHIP_RV370_5464,   RV380,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
210         CHIP_DEF(PCI_CHIP_R420_JH,      R420,   CHIP_HAS_CRTC2),
211         CHIP_DEF(PCI_CHIP_R420_JI,      R420,   CHIP_HAS_CRTC2),
212         CHIP_DEF(PCI_CHIP_R420_JJ,      R420,   CHIP_HAS_CRTC2),
213         CHIP_DEF(PCI_CHIP_R420_JK,      R420,   CHIP_HAS_CRTC2),
214         CHIP_DEF(PCI_CHIP_R420_JL,      R420,   CHIP_HAS_CRTC2),
215         CHIP_DEF(PCI_CHIP_R420_JM,      R420,   CHIP_HAS_CRTC2),
216         CHIP_DEF(PCI_CHIP_R420_JN,      R420,   CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
217         CHIP_DEF(PCI_CHIP_R420_JP,      R420,   CHIP_HAS_CRTC2),
218         CHIP_DEF(PCI_CHIP_R423_UH,      R420,   CHIP_HAS_CRTC2),
219         CHIP_DEF(PCI_CHIP_R423_UI,      R420,   CHIP_HAS_CRTC2),
220         CHIP_DEF(PCI_CHIP_R423_UJ,      R420,   CHIP_HAS_CRTC2),
221         CHIP_DEF(PCI_CHIP_R423_UK,      R420,   CHIP_HAS_CRTC2),
222         CHIP_DEF(PCI_CHIP_R423_UQ,      R420,   CHIP_HAS_CRTC2),
223         CHIP_DEF(PCI_CHIP_R423_UR,      R420,   CHIP_HAS_CRTC2),
224         CHIP_DEF(PCI_CHIP_R423_UT,      R420,   CHIP_HAS_CRTC2),
225         CHIP_DEF(PCI_CHIP_R423_5D57,    R420,   CHIP_HAS_CRTC2),
226         /* Original Radeon/7200 */
227         CHIP_DEF(PCI_CHIP_RADEON_QD,    RADEON, 0),
228         CHIP_DEF(PCI_CHIP_RADEON_QE,    RADEON, 0),
229         CHIP_DEF(PCI_CHIP_RADEON_QF,    RADEON, 0),
230         CHIP_DEF(PCI_CHIP_RADEON_QG,    RADEON, 0),
231         { 0, }
232 };
233 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
234
235
236 typedef struct {
237         u16 reg;
238         u32 val;
239 } reg_val;
240
241
242 /* these common regs are cleared before mode setting so they do not
243  * interfere with anything
244  */
245 static reg_val common_regs[] = {
246         { OVR_CLR, 0 }, 
247         { OVR_WID_LEFT_RIGHT, 0 },
248         { OVR_WID_TOP_BOTTOM, 0 },
249         { OV0_SCALE_CNTL, 0 },
250         { SUBPIC_CNTL, 0 },
251         { VIPH_CONTROL, 0 },
252         { I2C_CNTL_1, 0 },
253         { GEN_INT_CNTL, 0 },
254         { CAP0_TRIG_CNTL, 0 },
255         { CAP1_TRIG_CNTL, 0 },
256 };
257
258 /*
259  * globals
260  */
261         
262 static char *mode_option;
263 static char *monitor_layout;
264 static int noaccel = 0;
265 static int default_dynclk = -2;
266 static int nomodeset = 0;
267 static int ignore_edid = 0;
268 static int mirror = 0;
269 static int panel_yres = 0;
270 static int force_dfp = 0;
271 static int force_measure_pll = 0;
272 #ifdef CONFIG_MTRR
273 static int nomtrr = 0;
274 #endif
275
276 /*
277  * prototypes
278  */
279
280
281 #ifdef CONFIG_PPC_OF
282
283 #ifdef CONFIG_PMAC_BACKLIGHT
284 static int radeon_set_backlight_enable(int on, int level, void *data);
285 static int radeon_set_backlight_level(int level, void *data);
286 static struct backlight_controller radeon_backlight_controller = {
287         radeon_set_backlight_enable,
288         radeon_set_backlight_level
289 };
290 #endif /* CONFIG_PMAC_BACKLIGHT */
291
292 #endif /* CONFIG_PPC_OF */
293
294 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
295 {
296         if (!rinfo->bios_seg)
297                 return;
298         pci_unmap_rom(dev, rinfo->bios_seg);
299 }
300
301 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
302 {
303         void __iomem *rom;
304         u16 dptr;
305         u8 rom_type;
306         size_t rom_size;
307
308         /* If this is a primary card, there is a shadow copy of the
309          * ROM somewhere in the first meg. We will just ignore the copy
310          * and use the ROM directly.
311          */
312     
313         /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
314         unsigned int temp;
315         temp = INREG(MPP_TB_CONFIG);
316         temp &= 0x00ffffffu;
317         temp |= 0x04 << 24;
318         OUTREG(MPP_TB_CONFIG, temp);
319         temp = INREG(MPP_TB_CONFIG);
320                                                                                                           
321         rom = pci_map_rom(dev, &rom_size);
322         if (!rom) {
323                 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
324                        pci_name(rinfo->pdev));
325                 return -ENOMEM;
326         }
327         
328         rinfo->bios_seg = rom;
329
330         /* Very simple test to make sure it appeared */
331         if (BIOS_IN16(0) != 0xaa55) {
332                 printk(KERN_ERR "radeonfb (%s): Invalid ROM signature %x should be"
333                        "0xaa55\n", pci_name(rinfo->pdev), BIOS_IN16(0));
334                 goto failed;
335         }
336         /* Look for the PCI data to check the ROM type */
337         dptr = BIOS_IN16(0x18);
338
339         /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
340          * for now, until I've verified this works everywhere. The goal here is more
341          * to phase out Open Firmware images.
342          *
343          * Currently, we only look at the first PCI data, we could iteratre and deal with
344          * them all, and we should use fb_bios_start relative to start of image and not
345          * relative start of ROM, but so far, I never found a dual-image ATI card
346          *
347          * typedef struct {
348          *      u32     signature;      + 0x00
349          *      u16     vendor;         + 0x04
350          *      u16     device;         + 0x06
351          *      u16     reserved_1;     + 0x08
352          *      u16     dlen;           + 0x0a
353          *      u8      drevision;      + 0x0c
354          *      u8      class_hi;       + 0x0d
355          *      u16     class_lo;       + 0x0e
356          *      u16     ilen;           + 0x10
357          *      u16     irevision;      + 0x12
358          *      u8      type;           + 0x14
359          *      u8      indicator;      + 0x15
360          *      u16     reserved_2;     + 0x16
361          * } pci_data_t;
362          */
363         if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
364                 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
365                        "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
366                 goto anyway;
367         }
368         rom_type = BIOS_IN8(dptr + 0x14);
369         switch(rom_type) {
370         case 0:
371                 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
372                 break;
373         case 1:
374                 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
375                 goto failed;
376         case 2:
377                 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
378                 goto failed;
379         default:
380                 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
381                 goto failed;
382         }
383  anyway:
384         /* Locate the flat panel infos, do some sanity checking !!! */
385         rinfo->fp_bios_start = BIOS_IN16(0x48);
386         return 0;
387
388  failed:
389         rinfo->bios_seg = NULL;
390         radeon_unmap_ROM(rinfo, dev);
391         return -ENXIO;
392 }
393
394 #ifdef CONFIG_X86
395 static int  __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
396 {
397         /* I simplified this code as we used to miss the signatures in
398          * a lot of case. It's now closer to XFree, we just don't check
399          * for signatures at all... Something better will have to be done
400          * if we end up having conflicts
401          */
402         u32  segstart;
403         void __iomem *rom_base = NULL;
404                                                 
405         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
406                 rom_base = ioremap(segstart, 0x10000);
407                 if (rom_base == NULL)
408                         return -ENOMEM;
409                 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
410                         break;
411                 iounmap(rom_base);
412                 rom_base = NULL;
413         }
414         if (rom_base == NULL)
415                 return -ENXIO;
416
417         /* Locate the flat panel infos, do some sanity checking !!! */
418         rinfo->bios_seg = rom_base;
419         rinfo->fp_bios_start = BIOS_IN16(0x48);
420
421         return 0;
422 }
423 #endif
424
425 #ifdef CONFIG_PPC_OF
426 /*
427  * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
428  * tree. Hopefully, ATI OF driver is kind enough to fill these
429  */
430 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
431 {
432         struct device_node *dp = rinfo->of_node;
433         u32 *val;
434
435         if (dp == NULL)
436                 return -ENODEV;
437         val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
438         if (!val || !*val) {
439                 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
440                 return -EINVAL;
441         }
442
443         rinfo->pll.ref_clk = (*val) / 10;
444
445         val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
446         if (val && *val)
447                 rinfo->pll.sclk = (*val) / 10;
448
449         val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
450         if (val && *val)
451                 rinfo->pll.mclk = (*val) / 10;
452
453         return 0;
454 }
455 #endif /* CONFIG_PPC_OF */
456
457 /*
458  * Read PLL infos from chip registers
459  */
460 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
461 {
462         unsigned char ppll_div_sel;
463         unsigned Ns, Nm, M;
464         unsigned sclk, mclk, tmp, ref_div;
465         int hTotal, vTotal, num, denom, m, n;
466         unsigned long long hz, vclk;
467         long xtal;
468         struct timeval start_tv, stop_tv;
469         long total_secs, total_usecs;
470         int i;
471
472         /* Ugh, we cut interrupts, bad bad bad, but we want some precision
473          * here, so... --BenH
474          */
475
476         /* Flush PCI buffers ? */
477         tmp = INREG(DEVICE_ID);
478
479         local_irq_disable();
480
481         for(i=0; i<1000000; i++)
482                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
483                         break;
484
485         do_gettimeofday(&start_tv);
486
487         for(i=0; i<1000000; i++)
488                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
489                         break;
490
491         for(i=0; i<1000000; i++)
492                 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
493                         break;
494         
495         do_gettimeofday(&stop_tv);
496         
497         local_irq_enable();
498
499         total_secs = stop_tv.tv_sec - start_tv.tv_sec;
500         if (total_secs > 10)
501                 return -1;
502         total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
503         total_usecs += total_secs * 1000000;
504         if (total_usecs < 0)
505                 total_usecs = -total_usecs;
506         hz = 1000000/total_usecs;
507  
508         hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
509         vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
510         vclk = (long long)hTotal * (long long)vTotal * hz;
511
512         switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
513         case 0:
514         default:
515                 num = 1;
516                 denom = 1;
517                 break;
518         case 1:
519                 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
520                 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
521                 num = 2*n;
522                 denom = 2*m;
523                 break;
524         case 2:
525                 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
526                 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
527                 num = 2*n;
528                 denom = 2*m;
529         break;
530         }
531
532         ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
533         radeon_pll_errata_after_index(rinfo);
534
535         n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
536         m = (INPLL(PPLL_REF_DIV) & 0x3ff);
537
538         num *= n;
539         denom *= m;
540
541         switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
542         case 1:
543                 denom *= 2;
544                 break;
545         case 2:
546                 denom *= 4;
547                 break;
548         case 3:
549                 denom *= 8;
550                 break;
551         case 4:
552                 denom *= 3;
553                 break;
554         case 6:
555                 denom *= 6;   
556                 break;
557         case 7:
558                 denom *= 12;
559                 break;
560         }
561
562         vclk *= denom;
563         do_div(vclk, 1000 * num);
564         xtal = vclk;
565
566         if ((xtal > 26900) && (xtal < 27100))
567                 xtal = 2700;
568         else if ((xtal > 14200) && (xtal < 14400))
569                 xtal = 1432;
570         else if ((xtal > 29400) && (xtal < 29600))
571                 xtal = 2950;
572         else {
573                 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
574                 return -1;
575         }
576
577         tmp = INPLL(M_SPLL_REF_FB_DIV);
578         ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
579
580         Ns = (tmp & 0xff0000) >> 16;
581         Nm = (tmp & 0xff00) >> 8;
582         M = (tmp & 0xff);
583         sclk = round_div((2 * Ns * xtal), (2 * M));
584         mclk = round_div((2 * Nm * xtal), (2 * M));
585
586         /* we're done, hopefully these are sane values */
587         rinfo->pll.ref_clk = xtal;
588         rinfo->pll.ref_div = ref_div;
589         rinfo->pll.sclk = sclk;
590         rinfo->pll.mclk = mclk;
591
592         return 0;
593 }
594
595 /*
596  * Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)
597  */
598 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
599 {
600         /*
601          * In the case nothing works, these are defaults; they are mostly
602          * incomplete, however.  It does provide ppll_max and _min values
603          * even for most other methods, however.
604          */
605         switch (rinfo->chipset) {
606         case PCI_DEVICE_ID_ATI_RADEON_QW:
607         case PCI_DEVICE_ID_ATI_RADEON_QX:
608                 rinfo->pll.ppll_max = 35000;
609                 rinfo->pll.ppll_min = 12000;
610                 rinfo->pll.mclk = 23000;
611                 rinfo->pll.sclk = 23000;
612                 rinfo->pll.ref_clk = 2700;
613                 break;
614         case PCI_DEVICE_ID_ATI_RADEON_QL:
615         case PCI_DEVICE_ID_ATI_RADEON_QN:
616         case PCI_DEVICE_ID_ATI_RADEON_QO:
617         case PCI_DEVICE_ID_ATI_RADEON_Ql:
618         case PCI_DEVICE_ID_ATI_RADEON_BB:
619                 rinfo->pll.ppll_max = 35000;
620                 rinfo->pll.ppll_min = 12000;
621                 rinfo->pll.mclk = 27500;
622                 rinfo->pll.sclk = 27500;
623                 rinfo->pll.ref_clk = 2700;
624                 break;
625         case PCI_DEVICE_ID_ATI_RADEON_Id:
626         case PCI_DEVICE_ID_ATI_RADEON_Ie:
627         case PCI_DEVICE_ID_ATI_RADEON_If:
628         case PCI_DEVICE_ID_ATI_RADEON_Ig:
629                 rinfo->pll.ppll_max = 35000;
630                 rinfo->pll.ppll_min = 12000;
631                 rinfo->pll.mclk = 25000;
632                 rinfo->pll.sclk = 25000;
633                 rinfo->pll.ref_clk = 2700;
634                 break;
635         case PCI_DEVICE_ID_ATI_RADEON_ND:
636         case PCI_DEVICE_ID_ATI_RADEON_NE:
637         case PCI_DEVICE_ID_ATI_RADEON_NF:
638         case PCI_DEVICE_ID_ATI_RADEON_NG:
639                 rinfo->pll.ppll_max = 40000;
640                 rinfo->pll.ppll_min = 20000;
641                 rinfo->pll.mclk = 27000;
642                 rinfo->pll.sclk = 27000;
643                 rinfo->pll.ref_clk = 2700;
644                 break;
645         case PCI_DEVICE_ID_ATI_RADEON_QD:
646         case PCI_DEVICE_ID_ATI_RADEON_QE:
647         case PCI_DEVICE_ID_ATI_RADEON_QF:
648         case PCI_DEVICE_ID_ATI_RADEON_QG:
649         default:
650                 rinfo->pll.ppll_max = 35000;
651                 rinfo->pll.ppll_min = 12000;
652                 rinfo->pll.mclk = 16600;
653                 rinfo->pll.sclk = 16600;
654                 rinfo->pll.ref_clk = 2700;
655                 break;
656         }
657         rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
658
659
660 #ifdef CONFIG_PPC_OF
661         /*
662          * Retreive PLL infos from Open Firmware first
663          */
664         if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
665                 printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");
666                 goto found;
667         }
668 #endif /* CONFIG_PPC_OF */
669
670         /*
671          * Check out if we have an X86 which gave us some PLL informations
672          * and if yes, retreive them
673          */
674         if (!force_measure_pll && rinfo->bios_seg) {
675                 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
676
677                 rinfo->pll.sclk         = BIOS_IN16(pll_info_block + 0x08);
678                 rinfo->pll.mclk         = BIOS_IN16(pll_info_block + 0x0a);
679                 rinfo->pll.ref_clk      = BIOS_IN16(pll_info_block + 0x0e);
680                 rinfo->pll.ref_div      = BIOS_IN16(pll_info_block + 0x10);
681                 rinfo->pll.ppll_min     = BIOS_IN32(pll_info_block + 0x12);
682                 rinfo->pll.ppll_max     = BIOS_IN32(pll_info_block + 0x16);
683
684                 printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");
685                 goto found;
686         }
687
688         /*
689          * We didn't get PLL parameters from either OF or BIOS, we try to
690          * probe them
691          */
692         if (radeon_probe_pll_params(rinfo) == 0) {
693                 printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");
694                 goto found;
695         }
696
697         /*
698          * Fall back to already-set defaults...
699          */
700         printk(KERN_INFO "radeonfb: Used default PLL infos\n");
701
702 found:
703         /*
704          * Some methods fail to retreive SCLK and MCLK values, we apply default
705          * settings in this case (200Mhz). If that really happne often, we could
706          * fetch from registers instead...
707          */
708         if (rinfo->pll.mclk == 0)
709                 rinfo->pll.mclk = 20000;
710         if (rinfo->pll.sclk == 0)
711                 rinfo->pll.sclk = 20000;
712
713         printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
714                rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
715                rinfo->pll.ref_div,
716                rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
717                rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
718         printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
719 }
720
721 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
722 {
723         struct radeonfb_info *rinfo = info->par;
724         struct fb_var_screeninfo v;
725         int nom, den;
726         unsigned int pitch;
727
728         if (radeon_match_mode(rinfo, &v, var))
729                 return -EINVAL;
730
731         switch (v.bits_per_pixel) {
732                 case 0 ... 8:
733                         v.bits_per_pixel = 8;
734                         break;
735                 case 9 ... 16:
736                         v.bits_per_pixel = 16;
737                         break;
738                 case 17 ... 24:
739 #if 0 /* Doesn't seem to work */
740                         v.bits_per_pixel = 24;
741                         break;
742 #endif                  
743                         return -EINVAL;
744                 case 25 ... 32:
745                         v.bits_per_pixel = 32;
746                         break;
747                 default:
748                         return -EINVAL;
749         }
750
751         switch (var_to_depth(&v)) {
752                 case 8:
753                         nom = den = 1;
754                         v.red.offset = v.green.offset = v.blue.offset = 0;
755                         v.red.length = v.green.length = v.blue.length = 8;
756                         v.transp.offset = v.transp.length = 0;
757                         break;
758                 case 15:
759                         nom = 2;
760                         den = 1;
761                         v.red.offset = 10;
762                         v.green.offset = 5;
763                         v.blue.offset = 0;
764                         v.red.length = v.green.length = v.blue.length = 5;
765                         v.transp.offset = v.transp.length = 0;
766                         break;
767                 case 16:
768                         nom = 2;
769                         den = 1;
770                         v.red.offset = 11;
771                         v.green.offset = 5;
772                         v.blue.offset = 0;
773                         v.red.length = 5;
774                         v.green.length = 6;
775                         v.blue.length = 5;
776                         v.transp.offset = v.transp.length = 0;
777                         break;                          
778                 case 24:
779                         nom = 4;
780                         den = 1;
781                         v.red.offset = 16;
782                         v.green.offset = 8;
783                         v.blue.offset = 0;
784                         v.red.length = v.blue.length = v.green.length = 8;
785                         v.transp.offset = v.transp.length = 0;
786                         break;
787                 case 32:
788                         nom = 4;
789                         den = 1;
790                         v.red.offset = 16;
791                         v.green.offset = 8;
792                         v.blue.offset = 0;
793                         v.red.length = v.blue.length = v.green.length = 8;
794                         v.transp.offset = 24;
795                         v.transp.length = 8;
796                         break;
797                 default:
798                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
799                                 var->xres, var->yres, var->bits_per_pixel);
800                         return -EINVAL;
801         }
802
803         if (v.yres_virtual < v.yres)
804                 v.yres_virtual = v.yres;
805         if (v.xres_virtual < v.xres)
806                 v.xres_virtual = v.xres;
807                 
808
809         /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
810          * with some panels, though I don't quite like this solution
811          */
812         if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
813                 v.xres_virtual = v.xres_virtual & ~7ul;
814         } else {
815                 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
816                                 & ~(0x3f)) >> 6;
817                 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
818         }
819
820         if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
821                 return -EINVAL;
822
823         if (v.xres_virtual < v.xres)
824                 v.xres = v.xres_virtual;
825
826         if (v.xoffset < 0)
827                 v.xoffset = 0;
828         if (v.yoffset < 0)
829                 v.yoffset = 0;
830          
831         if (v.xoffset > v.xres_virtual - v.xres)
832                 v.xoffset = v.xres_virtual - v.xres - 1;
833                         
834         if (v.yoffset > v.yres_virtual - v.yres)
835                 v.yoffset = v.yres_virtual - v.yres - 1;
836          
837         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
838                           v.transp.offset = v.transp.length =
839                           v.transp.msb_right = 0;
840         
841         memcpy(var, &v, sizeof(v));
842
843         return 0;
844 }
845
846
847 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
848                                  struct fb_info *info)
849 {
850         struct radeonfb_info *rinfo = info->par;
851
852         if ((var->xoffset + var->xres > var->xres_virtual)
853             || (var->yoffset + var->yres > var->yres_virtual))
854                return -EINVAL;
855                 
856         if (rinfo->asleep)
857                 return 0;
858
859         radeon_fifo_wait(2);
860         OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
861                              * var->bits_per_pixel / 8) & ~7);
862         return 0;
863 }
864
865
866 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
867                            unsigned long arg, struct fb_info *info)
868 {
869         struct radeonfb_info *rinfo = info->par;
870         unsigned int tmp;
871         u32 value = 0;
872         int rc;
873
874         switch (cmd) {
875                 /*
876                  * TODO:  set mirror accordingly for non-Mobility chipsets with 2 CRTC's
877                  *        and do something better using 2nd CRTC instead of just hackish
878                  *        routing to second output
879                  */
880                 case FBIO_RADEON_SET_MIRROR:
881                         if (!rinfo->is_mobility)
882                                 return -EINVAL;
883
884                         rc = get_user(value, (__u32 __user *)arg);
885
886                         if (rc)
887                                 return rc;
888
889                         radeon_fifo_wait(2);
890                         if (value & 0x01) {
891                                 tmp = INREG(LVDS_GEN_CNTL);
892
893                                 tmp |= (LVDS_ON | LVDS_BLON);
894                         } else {
895                                 tmp = INREG(LVDS_GEN_CNTL);
896
897                                 tmp &= ~(LVDS_ON | LVDS_BLON);
898                         }
899
900                         OUTREG(LVDS_GEN_CNTL, tmp);
901
902                         if (value & 0x02) {
903                                 tmp = INREG(CRTC_EXT_CNTL);
904                                 tmp |= CRTC_CRT_ON;
905
906                                 mirror = 1;
907                         } else {
908                                 tmp = INREG(CRTC_EXT_CNTL);
909                                 tmp &= ~CRTC_CRT_ON;
910
911                                 mirror = 0;
912                         }
913
914                         OUTREG(CRTC_EXT_CNTL, tmp);
915
916                         return 0;
917                 case FBIO_RADEON_GET_MIRROR:
918                         if (!rinfo->is_mobility)
919                                 return -EINVAL;
920
921                         tmp = INREG(LVDS_GEN_CNTL);
922                         if ((LVDS_ON | LVDS_BLON) & tmp)
923                                 value |= 0x01;
924
925                         tmp = INREG(CRTC_EXT_CNTL);
926                         if (CRTC_CRT_ON & tmp)
927                                 value |= 0x02;
928
929                         return put_user(value, (__u32 __user *)arg);
930                 default:
931                         return -EINVAL;
932         }
933
934         return -EINVAL;
935 }
936
937
938 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
939 {
940         u32 val;
941         u32 tmp_pix_clks;
942         int unblank = 0;
943
944         if (rinfo->lock_blank)
945                 return 0;
946
947         radeon_engine_idle();
948
949         val = INREG(CRTC_EXT_CNTL);
950         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
951                  CRTC_VSYNC_DIS);
952         switch (blank) {
953         case FB_BLANK_VSYNC_SUSPEND:
954                 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
955                 break;
956         case FB_BLANK_HSYNC_SUSPEND:
957                 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
958                 break;
959         case FB_BLANK_POWERDOWN:
960                 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
961                         CRTC_HSYNC_DIS);
962                 break;
963         case FB_BLANK_NORMAL:
964                 val |= CRTC_DISPLAY_DIS;
965                 break;
966         case FB_BLANK_UNBLANK:
967         default:
968                 unblank = 1;
969         }
970         OUTREG(CRTC_EXT_CNTL, val);
971
972
973         switch (rinfo->mon1_type) {
974         case MT_DFP:
975                 if (unblank)
976                         OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
977                                 ~(FP_FPON | FP_TMDS_EN));
978                 else {
979                         if (mode_switch || blank == FB_BLANK_NORMAL)
980                                 break;
981                         OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
982                 }
983                 break;
984         case MT_LCD:
985                 del_timer_sync(&rinfo->lvds_timer);
986                 val = INREG(LVDS_GEN_CNTL);
987                 if (unblank) {
988                         u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
989                                 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
990                                              & (LVDS_DIGON | LVDS_BL_MOD_EN));
991                         if ((val ^ target_val) == LVDS_DISPLAY_DIS)
992                                 OUTREG(LVDS_GEN_CNTL, target_val);
993                         else if ((val ^ target_val) != 0) {
994                                 OUTREG(LVDS_GEN_CNTL, target_val
995                                        & ~(LVDS_ON | LVDS_BL_MOD_EN));
996                                 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
997                                 rinfo->init_state.lvds_gen_cntl |=
998                                         target_val & LVDS_STATE_MASK;
999                                 if (mode_switch) {
1000                                         radeon_msleep(rinfo->panel_info.pwr_delay);
1001                                         OUTREG(LVDS_GEN_CNTL, target_val);
1002                                 }
1003                                 else {
1004                                         rinfo->pending_lvds_gen_cntl = target_val;
1005                                         mod_timer(&rinfo->lvds_timer,
1006                                            jiffies +
1007                                            msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1008                                 }
1009                         }
1010                 } else {
1011                         val |= LVDS_DISPLAY_DIS;
1012                         OUTREG(LVDS_GEN_CNTL, val);
1013
1014                         /* We don't do a full switch-off on a simple mode switch */
1015                         if (mode_switch || blank == FB_BLANK_NORMAL)
1016                                 break;
1017
1018                         /* Asic bug, when turning off LVDS_ON, we have to make sure
1019                          * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1020                          */
1021                         tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1022                         if (rinfo->is_mobility || rinfo->is_IGP)
1023                                 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1024                         val &= ~(LVDS_BL_MOD_EN);
1025                         OUTREG(LVDS_GEN_CNTL, val);
1026                         udelay(100);
1027                         val &= ~(LVDS_ON | LVDS_EN);
1028                         OUTREG(LVDS_GEN_CNTL, val);
1029                         val &= ~LVDS_DIGON;
1030                         rinfo->pending_lvds_gen_cntl = val;
1031                         mod_timer(&rinfo->lvds_timer,
1032                                   jiffies +
1033                                   msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1034                         rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1035                         rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1036                         if (rinfo->is_mobility || rinfo->is_IGP)
1037                                 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1038                 }
1039                 break;
1040         case MT_CRT:
1041                 // todo: powerdown DAC
1042         default:
1043                 break;
1044         }
1045
1046         /* let fbcon do a soft blank for us */
1047         return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
1048 }
1049
1050 static int radeonfb_blank (int blank, struct fb_info *info)
1051 {
1052         struct radeonfb_info *rinfo = info->par;
1053
1054         if (rinfo->asleep)
1055                 return 0;
1056                 
1057         return radeon_screen_blank(rinfo, blank, 0);
1058 }
1059
1060 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1061                              unsigned blue, unsigned transp,
1062                              struct radeonfb_info *rinfo)
1063 {
1064         u32 pindex;
1065         unsigned int i;
1066
1067
1068         if (regno > 255)
1069                 return 1;
1070
1071         red >>= 8;
1072         green >>= 8;
1073         blue >>= 8;
1074         rinfo->palette[regno].red = red;
1075         rinfo->palette[regno].green = green;
1076         rinfo->palette[regno].blue = blue;
1077
1078         /* default */
1079         pindex = regno;
1080
1081         if (!rinfo->asleep) {
1082                 radeon_fifo_wait(9);
1083
1084                 if (rinfo->bpp == 16) {
1085                         pindex = regno * 8;
1086
1087                         if (rinfo->depth == 16 && regno > 63)
1088                                 return 1;
1089                         if (rinfo->depth == 15 && regno > 31)
1090                                 return 1;
1091
1092                         /* For 565, the green component is mixed one order
1093                          * below
1094                          */
1095                         if (rinfo->depth == 16) {
1096                                 OUTREG(PALETTE_INDEX, pindex>>1);
1097                                 OUTREG(PALETTE_DATA,
1098                                        (rinfo->palette[regno>>1].red << 16) |
1099                                         (green << 8) |
1100                                        (rinfo->palette[regno>>1].blue));
1101                                 green = rinfo->palette[regno<<1].green;
1102                         }
1103                 }
1104
1105                 if (rinfo->depth != 16 || regno < 32) {
1106                         OUTREG(PALETTE_INDEX, pindex);
1107                         OUTREG(PALETTE_DATA, (red << 16) |
1108                                (green << 8) | blue);
1109                 }
1110         }
1111         if (regno < 16) {
1112                 u32 *pal = rinfo->info->pseudo_palette;
1113                 switch (rinfo->depth) {
1114                 case 15:
1115                         pal[regno] = (regno << 10) | (regno << 5) | regno;
1116                         break;
1117                 case 16:
1118                         pal[regno] = (regno << 11) | (regno << 5) | regno;
1119                         break;
1120                 case 24:
1121                         pal[regno] = (regno << 16) | (regno << 8) | regno;
1122                         break;
1123                 case 32:
1124                         i = (regno << 8) | regno;
1125                         pal[regno] = (i << 16) | i;
1126                         break;
1127                 }
1128         }
1129         return 0;
1130 }
1131
1132 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1133                                unsigned blue, unsigned transp,
1134                                struct fb_info *info)
1135 {
1136         struct radeonfb_info *rinfo = info->par;
1137         u32 dac_cntl2, vclk_cntl = 0;
1138         int rc;
1139
1140         if (!rinfo->asleep) {
1141                 if (rinfo->is_mobility) {
1142                         vclk_cntl = INPLL(VCLK_ECP_CNTL);
1143                         OUTPLL(VCLK_ECP_CNTL,
1144                                vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1145                 }
1146
1147                 /* Make sure we are on first palette */
1148                 if (rinfo->has_CRTC2) {
1149                         dac_cntl2 = INREG(DAC_CNTL2);
1150                         dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1151                         OUTREG(DAC_CNTL2, dac_cntl2);
1152                 }
1153         }
1154
1155         rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1156
1157         if (!rinfo->asleep && rinfo->is_mobility)
1158                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1159
1160         return rc;
1161 }
1162
1163 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1164 {
1165         struct radeonfb_info *rinfo = info->par;
1166         u16 *red, *green, *blue, *transp;
1167         u32 dac_cntl2, vclk_cntl = 0;
1168         int i, start, rc = 0;
1169
1170         if (!rinfo->asleep) {
1171                 if (rinfo->is_mobility) {
1172                         vclk_cntl = INPLL(VCLK_ECP_CNTL);
1173                         OUTPLL(VCLK_ECP_CNTL,
1174                                vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1175                 }
1176
1177                 /* Make sure we are on first palette */
1178                 if (rinfo->has_CRTC2) {
1179                         dac_cntl2 = INREG(DAC_CNTL2);
1180                         dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1181                         OUTREG(DAC_CNTL2, dac_cntl2);
1182                 }
1183         }
1184
1185         red = cmap->red;
1186         green = cmap->green;
1187         blue = cmap->blue;
1188         transp = cmap->transp;
1189         start = cmap->start;
1190
1191         for (i = 0; i < cmap->len; i++) {
1192                 u_int hred, hgreen, hblue, htransp = 0xffff;
1193
1194                 hred = *red++;
1195                 hgreen = *green++;
1196                 hblue = *blue++;
1197                 if (transp)
1198                         htransp = *transp++;
1199                 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1200                                        rinfo);
1201                 if (rc)
1202                         break;
1203         }
1204
1205         if (!rinfo->asleep && rinfo->is_mobility)
1206                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1207
1208         return rc;
1209 }
1210
1211 static void radeon_save_state (struct radeonfb_info *rinfo,
1212                                struct radeon_regs *save)
1213 {
1214         /* CRTC regs */
1215         save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1216         save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1217         save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1218         save->dac_cntl = INREG(DAC_CNTL);
1219         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1220         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1221         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1222         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1223         save->crtc_pitch = INREG(CRTC_PITCH);
1224         save->surface_cntl = INREG(SURFACE_CNTL);
1225
1226         /* FP regs */
1227         save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1228         save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1229         save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1230         save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1231         save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1232         save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1233         save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1234         save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1235         save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1236         save->tmds_crc = INREG(TMDS_CRC);
1237         save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1238         save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1239
1240         /* PLL regs */
1241         save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1242         radeon_pll_errata_after_index(rinfo);
1243         save->ppll_div_3 = INPLL(PPLL_DIV_3);
1244         save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1245 }
1246
1247
1248 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1249 {
1250         int i;
1251
1252         radeon_fifo_wait(20);
1253
1254         /* Workaround from XFree */
1255         if (rinfo->is_mobility) {
1256                 /* A temporal workaround for the occational blanking on certain laptop
1257                  * panels. This appears to related to the PLL divider registers
1258                  * (fail to lock?). It occurs even when all dividers are the same
1259                  * with their old settings. In this case we really don't need to
1260                  * fiddle with PLL registers. By doing this we can avoid the blanking
1261                  * problem with some panels.
1262                  */
1263                 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1264                     (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1265                                           (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1266                         /* We still have to force a switch to selected PPLL div thanks to
1267                          * an XFree86 driver bug which will switch it away in some cases
1268                          * even when using UseFDev */
1269                         OUTREGP(CLOCK_CNTL_INDEX,
1270                                 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1271                                 ~PPLL_DIV_SEL_MASK);
1272                         radeon_pll_errata_after_index(rinfo);
1273                         radeon_pll_errata_after_data(rinfo);
1274                         return;
1275                 }
1276         }
1277
1278         /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1279         OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1280
1281         /* Reset PPLL & enable atomic update */
1282         OUTPLLP(PPLL_CNTL,
1283                 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1284                 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1285
1286         /* Switch to selected PPLL divider */
1287         OUTREGP(CLOCK_CNTL_INDEX,
1288                 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1289                 ~PPLL_DIV_SEL_MASK);
1290         radeon_pll_errata_after_index(rinfo);
1291         radeon_pll_errata_after_data(rinfo);
1292
1293         /* Set PPLL ref. div */
1294         if (rinfo->family == CHIP_FAMILY_R300 ||
1295             rinfo->family == CHIP_FAMILY_RS300 ||
1296             rinfo->family == CHIP_FAMILY_R350 ||
1297             rinfo->family == CHIP_FAMILY_RV350) {
1298                 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1299                         /* When restoring console mode, use saved PPLL_REF_DIV
1300                          * setting.
1301                          */
1302                         OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1303                 } else {
1304                         /* R300 uses ref_div_acc field as real ref divider */
1305                         OUTPLLP(PPLL_REF_DIV,
1306                                 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 
1307                                 ~R300_PPLL_REF_DIV_ACC_MASK);
1308                 }
1309         } else
1310                 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1311
1312         /* Set PPLL divider 3 & post divider*/
1313         OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1314         OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1315
1316         /* Write update */
1317         while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1318                 ;
1319         OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1320
1321         /* Wait read update complete */
1322         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
1323            the cause yet, but this workaround will mask the problem for now.
1324            Other chips usually will pass at the very first test, so the
1325            workaround shouldn't have any effect on them. */
1326         for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1327                 ;
1328         
1329         OUTPLL(HTOTAL_CNTL, 0);
1330
1331         /* Clear reset & atomic update */
1332         OUTPLLP(PPLL_CNTL, 0,
1333                 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1334
1335         /* We may want some locking ... oh well */
1336         radeon_msleep(5);
1337
1338         /* Switch back VCLK source to PPLL */
1339         OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1340 }
1341
1342 /*
1343  * Timer function for delayed LVDS panel power up/down
1344  */
1345 static void radeon_lvds_timer_func(unsigned long data)
1346 {
1347         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1348
1349         radeon_engine_idle();
1350
1351         OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1352 }
1353
1354 /*
1355  * Apply a video mode. This will apply the whole register set, including
1356  * the PLL registers, to the card
1357  */
1358 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1359                         int regs_only)
1360 {
1361         int i;
1362         int primary_mon = PRIMARY_MONITOR(rinfo);
1363
1364         if (nomodeset)
1365                 return;
1366
1367         if (!regs_only)
1368                 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1369
1370         radeon_fifo_wait(31);
1371         for (i=0; i<10; i++)
1372                 OUTREG(common_regs[i].reg, common_regs[i].val);
1373
1374         /* Apply surface registers */
1375         for (i=0; i<8; i++) {
1376                 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1377                 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1378                 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1379         }
1380
1381         OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1382         OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1383                 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1384         OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1385         OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1386         OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1387         OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1388         OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1389         OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1390         OUTREG(CRTC_OFFSET, 0);
1391         OUTREG(CRTC_OFFSET_CNTL, 0);
1392         OUTREG(CRTC_PITCH, mode->crtc_pitch);
1393         OUTREG(SURFACE_CNTL, mode->surface_cntl);
1394
1395         radeon_write_pll_regs(rinfo, mode);
1396
1397         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1398                 radeon_fifo_wait(10);
1399                 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1400                 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1401                 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1402                 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1403                 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1404                 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1405                 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1406                 OUTREG(TMDS_CRC, mode->tmds_crc);
1407                 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1408         }
1409
1410         if (!regs_only)
1411                 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1412
1413         radeon_fifo_wait(2);
1414         OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1415         
1416         return;
1417 }
1418
1419 /*
1420  * Calculate the PLL values for a given mode
1421  */
1422 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1423                                  unsigned long freq)
1424 {
1425         const struct {
1426                 int divider;
1427                 int bitvalue;
1428         } *post_div,
1429           post_divs[] = {
1430                 { 1,  0 },
1431                 { 2,  1 },
1432                 { 4,  2 },
1433                 { 8,  3 },
1434                 { 3,  4 },
1435                 { 16, 5 },
1436                 { 6,  6 },
1437                 { 12, 7 },
1438                 { 0,  0 },
1439         };
1440         int fb_div, pll_output_freq = 0;
1441         int uses_dvo = 0;
1442
1443         /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1444          * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1445          * recent than an r(v)100...
1446          */
1447 #if 1
1448         /* XXX I had reports of flicker happening with the cinema display
1449          * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1450          * this case. This could just be a bandwidth calculation issue, I
1451          * haven't implemented the bandwidth code yet, but in the meantime,
1452          * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1453          * I haven't seen a case were were absolutely needed an odd PLL
1454          * divider. I'll find a better fix once I have more infos on the
1455          * real cause of the problem.
1456          */
1457         while (rinfo->has_CRTC2) {
1458                 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1459                 u32 disp_output_cntl;
1460                 int source;
1461
1462                 /* FP2 path not enabled */
1463                 if ((fp2_gen_cntl & FP2_ON) == 0)
1464                         break;
1465                 /* Not all chip revs have the same format for this register,
1466                  * extract the source selection
1467                  */
1468                 if (rinfo->family == CHIP_FAMILY_R200 ||
1469                     rinfo->family == CHIP_FAMILY_R300 ||
1470                     rinfo->family == CHIP_FAMILY_R350 ||
1471                     rinfo->family == CHIP_FAMILY_RV350) {
1472                         source = (fp2_gen_cntl >> 10) & 0x3;
1473                         /* sourced from transform unit, check for transform unit
1474                          * own source
1475                          */
1476                         if (source == 3) {
1477                                 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1478                                 source = (disp_output_cntl >> 12) & 0x3;
1479                         }
1480                 } else
1481                         source = (fp2_gen_cntl >> 13) & 0x1;
1482                 /* sourced from CRTC2 -> exit */
1483                 if (source == 1)
1484                         break;
1485
1486                 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1487                 uses_dvo = 1;
1488                 break;
1489         }
1490 #else
1491         uses_dvo = 1;
1492 #endif
1493         if (freq > rinfo->pll.ppll_max)
1494                 freq = rinfo->pll.ppll_max;
1495         if (freq*12 < rinfo->pll.ppll_min)
1496                 freq = rinfo->pll.ppll_min / 12;
1497         RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1498                freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1499
1500         for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1501                 pll_output_freq = post_div->divider * freq;
1502                 /* If we output to the DVO port (external TMDS), we don't allow an
1503                  * odd PLL divider as those aren't supported on this path
1504                  */
1505                 if (uses_dvo && (post_div->divider & 1))
1506                         continue;
1507                 if (pll_output_freq >= rinfo->pll.ppll_min  &&
1508                     pll_output_freq <= rinfo->pll.ppll_max)
1509                         break;
1510         }
1511
1512         /* If we fall through the bottom, try the "default value"
1513            given by the terminal post_div->bitvalue */
1514         if ( !post_div->divider ) {
1515                 post_div = &post_divs[post_div->bitvalue];
1516                 pll_output_freq = post_div->divider * freq;
1517         }
1518         RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1519                rinfo->pll.ref_div, rinfo->pll.ref_clk,
1520                pll_output_freq);
1521
1522         /* If we fall through the bottom, try the "default value"
1523            given by the terminal post_div->bitvalue */
1524         if ( !post_div->divider ) {
1525                 post_div = &post_divs[post_div->bitvalue];
1526                 pll_output_freq = post_div->divider * freq;
1527         }
1528         RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1529                rinfo->pll.ref_div, rinfo->pll.ref_clk,
1530                pll_output_freq);
1531
1532         fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1533                                   rinfo->pll.ref_clk);
1534         regs->ppll_ref_div = rinfo->pll.ref_div;
1535         regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1536
1537         RTRACE("post div = 0x%x\n", post_div->bitvalue);
1538         RTRACE("fb_div = 0x%x\n", fb_div);
1539         RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1540 }
1541
1542 static int radeonfb_set_par(struct fb_info *info)
1543 {
1544         struct radeonfb_info *rinfo = info->par;
1545         struct fb_var_screeninfo *mode = &info->var;
1546         struct radeon_regs *newmode;
1547         int hTotal, vTotal, hSyncStart, hSyncEnd,
1548             hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1549         u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1550         u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1551         u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1552         int i, freq;
1553         int format = 0;
1554         int nopllcalc = 0;
1555         int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1556         int primary_mon = PRIMARY_MONITOR(rinfo);
1557         int depth = var_to_depth(mode);
1558         int use_rmx = 0;
1559
1560         newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1561         if (!newmode)
1562                 return -ENOMEM;
1563
1564         /* We always want engine to be idle on a mode switch, even
1565          * if we won't actually change the mode
1566          */
1567         radeon_engine_idle();
1568
1569         hSyncStart = mode->xres + mode->right_margin;
1570         hSyncEnd = hSyncStart + mode->hsync_len;
1571         hTotal = hSyncEnd + mode->left_margin;
1572
1573         vSyncStart = mode->yres + mode->lower_margin;
1574         vSyncEnd = vSyncStart + mode->vsync_len;
1575         vTotal = vSyncEnd + mode->upper_margin;
1576         pixClock = mode->pixclock;
1577
1578         sync = mode->sync;
1579         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1580         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1581
1582         if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1583                 if (rinfo->panel_info.xres < mode->xres)
1584                         mode->xres = rinfo->panel_info.xres;
1585                 if (rinfo->panel_info.yres < mode->yres)
1586                         mode->yres = rinfo->panel_info.yres;
1587
1588                 hTotal = mode->xres + rinfo->panel_info.hblank;
1589                 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1590                 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1591
1592                 vTotal = mode->yres + rinfo->panel_info.vblank;
1593                 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1594                 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1595
1596                 h_sync_pol = !rinfo->panel_info.hAct_high;
1597                 v_sync_pol = !rinfo->panel_info.vAct_high;
1598
1599                 pixClock = 100000000 / rinfo->panel_info.clock;
1600
1601                 if (rinfo->panel_info.use_bios_dividers) {
1602                         nopllcalc = 1;
1603                         newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1604                                 (rinfo->panel_info.post_divider << 16);
1605                         newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1606                 }
1607         }
1608         dotClock = 1000000000 / pixClock;
1609         freq = dotClock / 10; /* x100 */
1610
1611         RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1612                 hSyncStart, hSyncEnd, hTotal);
1613         RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1614                 vSyncStart, vSyncEnd, vTotal);
1615
1616         hsync_wid = (hSyncEnd - hSyncStart) / 8;
1617         vsync_wid = vSyncEnd - vSyncStart;
1618         if (hsync_wid == 0)
1619                 hsync_wid = 1;
1620         else if (hsync_wid > 0x3f)      /* max */
1621                 hsync_wid = 0x3f;
1622
1623         if (vsync_wid == 0)
1624                 vsync_wid = 1;
1625         else if (vsync_wid > 0x1f)      /* max */
1626                 vsync_wid = 0x1f;
1627
1628         hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1629         vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1630
1631         cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1632
1633         format = radeon_get_dstbpp(depth);
1634         bytpp = mode->bits_per_pixel >> 3;
1635
1636         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1637                 hsync_fudge = hsync_fudge_fp[format-1];
1638         else
1639                 hsync_fudge = hsync_adj_tab[format-1];
1640
1641         hsync_start = hSyncStart - 8 + hsync_fudge;
1642
1643         newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1644                                 (format << 8);
1645
1646         /* Clear auto-center etc... */
1647         newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1648         newmode->crtc_more_cntl &= 0xfffffff0;
1649         
1650         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1651                 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1652                 if (mirror)
1653                         newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1654
1655                 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1656                                            CRTC_INTERLACE_EN);
1657         } else {
1658                 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1659                                         CRTC_CRT_ON;
1660         }
1661
1662         newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1663                            DAC_8BIT_EN;
1664
1665         newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1666                                      (((mode->xres / 8) - 1) << 16));
1667
1668         newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1669                                         (hsync_wid << 16) | (h_sync_pol << 23));
1670
1671         newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1672                                     ((mode->yres - 1) << 16);
1673
1674         newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1675                                          (vsync_wid << 16) | (v_sync_pol  << 23));
1676
1677         if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1678                 /* We first calculate the engine pitch */
1679                 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1680                                 & ~(0x3f)) >> 6;
1681
1682                 /* Then, re-multiply it to get the CRTC pitch */
1683                 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1684         } else
1685                 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1686
1687         newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1688
1689         /*
1690          * It looks like recent chips have a problem with SURFACE_CNTL,
1691          * setting SURF_TRANSLATION_DIS completely disables the
1692          * swapper as well, so we leave it unset now.
1693          */
1694         newmode->surface_cntl = 0;
1695
1696 #if defined(__BIG_ENDIAN)
1697
1698         /* Setup swapping on both apertures, though we currently
1699          * only use aperture 0, enabling swapper on aperture 1
1700          * won't harm
1701          */
1702         switch (mode->bits_per_pixel) {
1703                 case 16:
1704                         newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1705                         newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1706                         break;
1707                 case 24:        
1708                 case 32:
1709                         newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1710                         newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1711                         break;
1712         }
1713 #endif
1714
1715         /* Clear surface registers */
1716         for (i=0; i<8; i++) {
1717                 newmode->surf_lower_bound[i] = 0;
1718                 newmode->surf_upper_bound[i] = 0x1f;
1719                 newmode->surf_info[i] = 0;
1720         }
1721
1722         RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
1723                 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1724         RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
1725                 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1726
1727         rinfo->bpp = mode->bits_per_pixel;
1728         rinfo->depth = depth;
1729
1730         RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1731         RTRACE("freq = %lu\n", (unsigned long)freq);
1732
1733         /* We use PPLL_DIV_3 */
1734         newmode->clk_cntl_index = 0x300;
1735
1736         /* Calculate PPLL value if necessary */
1737         if (!nopllcalc)
1738                 radeon_calc_pll_regs(rinfo, newmode, freq);
1739
1740         newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1741
1742         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1743                 unsigned int hRatio, vRatio;
1744
1745                 if (mode->xres > rinfo->panel_info.xres)
1746                         mode->xres = rinfo->panel_info.xres;
1747                 if (mode->yres > rinfo->panel_info.yres)
1748                         mode->yres = rinfo->panel_info.yres;
1749
1750                 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1751                                            << HORZ_PANEL_SHIFT);
1752                 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1753                                            << VERT_PANEL_SHIFT);
1754
1755                 if (mode->xres != rinfo->panel_info.xres) {
1756                         hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1757                                            rinfo->panel_info.xres);
1758                         newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1759                                                    (newmode->fp_horz_stretch &
1760                                                     (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1761                                                      HORZ_AUTO_RATIO_INC)));
1762                         newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1763                                                     HORZ_STRETCH_ENABLE);
1764                         use_rmx = 1;
1765                 }
1766                 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1767
1768                 if (mode->yres != rinfo->panel_info.yres) {
1769                         vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1770                                            rinfo->panel_info.yres);
1771                         newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1772                                                    (newmode->fp_vert_stretch &
1773                                                    (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1774                         newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1775                                                     VERT_STRETCH_ENABLE);
1776                         use_rmx = 1;
1777                 }
1778                 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1779
1780                 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1781                                        ~(FP_SEL_CRTC2 |
1782                                          FP_RMX_HVSYNC_CONTROL_EN |
1783                                          FP_DFP_SYNC_SEL |
1784                                          FP_CRT_SYNC_SEL |
1785                                          FP_CRTC_LOCK_8DOT |
1786                                          FP_USE_SHADOW_EN |
1787                                          FP_CRTC_USE_SHADOW_VEND |
1788                                          FP_CRT_SYNC_ALT));
1789
1790                 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1791                                         FP_CRTC_DONT_SHADOW_HEND |
1792                                         FP_PANEL_FORMAT);
1793
1794                 if (IS_R300_VARIANT(rinfo) ||
1795                     (rinfo->family == CHIP_FAMILY_R200)) {
1796                         newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1797                         if (use_rmx)
1798                                 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1799                         else
1800                                 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1801                 } else
1802                         newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1803
1804                 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1805                 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1806                 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1807                 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1808
1809                 if (primary_mon == MT_LCD) {
1810                         newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1811                         newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1812                 } else {
1813                         /* DFP */
1814                         newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1815                         newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1816                         /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1817                         if (IS_R300_VARIANT(rinfo) ||
1818                             (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1819                                 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1820                         else
1821                                 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1822                         newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1823                 }
1824
1825                 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1826                                 (((mode->xres / 8) - 1) << 16));
1827                 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1828                                 ((mode->yres - 1) << 16);
1829                 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1830                                 (hsync_wid << 16) | (h_sync_pol << 23));
1831                 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1832                                 (vsync_wid << 16) | (v_sync_pol  << 23));
1833         }
1834
1835         /* do it! */
1836         if (!rinfo->asleep) {
1837                 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1838                 radeon_write_mode (rinfo, newmode, 0);
1839                 /* (re)initialize the engine */
1840                 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1841                         radeonfb_engine_init (rinfo);
1842         }
1843         /* Update fix */
1844         if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1845                 info->fix.line_length = rinfo->pitch*64;
1846         else
1847                 info->fix.line_length = mode->xres_virtual
1848                         * ((mode->bits_per_pixel + 1) / 8);
1849         info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1850                 : FB_VISUAL_DIRECTCOLOR;
1851
1852 #ifdef CONFIG_BOOTX_TEXT
1853         /* Update debug text engine */
1854         btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1855                              rinfo->depth, info->fix.line_length);
1856 #endif
1857
1858         kfree(newmode);
1859         return 0;
1860 }
1861
1862
1863 static struct fb_ops radeonfb_ops = {
1864         .owner                  = THIS_MODULE,
1865         .fb_check_var           = radeonfb_check_var,
1866         .fb_set_par             = radeonfb_set_par,
1867         .fb_setcolreg           = radeonfb_setcolreg,
1868         .fb_setcmap             = radeonfb_setcmap,
1869         .fb_pan_display         = radeonfb_pan_display,
1870         .fb_blank               = radeonfb_blank,
1871         .fb_ioctl               = radeonfb_ioctl,
1872         .fb_sync                = radeonfb_sync,
1873         .fb_fillrect            = radeonfb_fillrect,
1874         .fb_copyarea            = radeonfb_copyarea,
1875         .fb_imageblit           = radeonfb_imageblit,
1876         .fb_cursor              = soft_cursor,
1877 };
1878
1879
1880 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1881 {
1882         struct fb_info *info = rinfo->info;
1883
1884         info->par = rinfo;
1885         info->pseudo_palette = rinfo->pseudo_palette;
1886         info->flags = FBINFO_DEFAULT
1887                     | FBINFO_HWACCEL_COPYAREA
1888                     | FBINFO_HWACCEL_FILLRECT
1889                     | FBINFO_HWACCEL_XPAN
1890                     | FBINFO_HWACCEL_YPAN;
1891         info->fbops = &radeonfb_ops;
1892         info->screen_base = rinfo->fb_base;
1893         info->screen_size = rinfo->mapped_vram;
1894         /* Fill fix common fields */
1895         strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1896         info->fix.smem_start = rinfo->fb_base_phys;
1897         info->fix.smem_len = rinfo->video_ram;
1898         info->fix.type = FB_TYPE_PACKED_PIXELS;
1899         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1900         info->fix.xpanstep = 8;
1901         info->fix.ypanstep = 1;
1902         info->fix.ywrapstep = 0;
1903         info->fix.type_aux = 0;
1904         info->fix.mmio_start = rinfo->mmio_base_phys;
1905         info->fix.mmio_len = RADEON_REGSIZE;
1906         info->fix.accel = FB_ACCEL_ATI_RADEON;
1907
1908         fb_alloc_cmap(&info->cmap, 256, 0);
1909
1910         if (noaccel)
1911                 info->flags |= FBINFO_HWACCEL_DISABLED;
1912
1913         return 0;
1914 }
1915
1916
1917 #ifdef CONFIG_PMAC_BACKLIGHT
1918
1919 /* TODO: Dbl check these tables, we don't go up to full ON backlight
1920  * in these, possibly because we noticed MacOS doesn't, but I'd prefer
1921  * having some more official numbers from ATI
1922  */
1923 static int backlight_conv_m6[] = {
1924         0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
1925         0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
1926 };
1927 static int backlight_conv_m7[] = {
1928         0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
1929         0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
1930 };
1931
1932 #define BACKLIGHT_LVDS_OFF
1933 #undef BACKLIGHT_DAC_OFF
1934
1935 /* We turn off the LCD completely instead of just dimming the backlight.
1936  * This provides some greater power saving and the display is useless
1937  * without backlight anyway.
1938  */
1939 static int radeon_set_backlight_enable(int on, int level, void *data)
1940 {
1941         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1942         u32 lvds_gen_cntl, tmpPixclksCntl;
1943         int* conv_table;
1944
1945         if (rinfo->mon1_type != MT_LCD)
1946                 return 0;
1947
1948         /* Pardon me for that hack... maybe some day we can figure
1949          * out in what direction backlight should work on a given
1950          * panel ?
1951          */
1952         if ((rinfo->family == CHIP_FAMILY_RV200 ||
1953              rinfo->family == CHIP_FAMILY_RV250 ||
1954              rinfo->family == CHIP_FAMILY_RV280 ||
1955              rinfo->family == CHIP_FAMILY_RV350) &&
1956             !machine_is_compatible("PowerBook4,3") &&
1957             !machine_is_compatible("PowerBook6,3") &&
1958             !machine_is_compatible("PowerBook6,5"))
1959                 conv_table = backlight_conv_m7;
1960         else
1961                 conv_table = backlight_conv_m6;
1962
1963         del_timer_sync(&rinfo->lvds_timer);
1964         radeon_engine_idle();
1965
1966         lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1967         if (on && (level > BACKLIGHT_OFF)) {
1968                 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
1969                 if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {
1970                         lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);
1971                         lvds_gen_cntl |= LVDS_BLON | LVDS_EN;
1972                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1973                         lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1974                         lvds_gen_cntl |= (conv_table[level] <<
1975                                           LVDS_BL_MOD_LEVEL_SHIFT);
1976                         lvds_gen_cntl |= LVDS_ON;
1977                         lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);
1978                         rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
1979                         mod_timer(&rinfo->lvds_timer,
1980                                   jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1981                 } else {
1982                         lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1983                         lvds_gen_cntl |= (conv_table[level] <<
1984                                           LVDS_BL_MOD_LEVEL_SHIFT);
1985                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1986                 }
1987                 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1988                 rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl
1989                         & LVDS_STATE_MASK;
1990         } else {
1991                 /* Asic bug, when turning off LVDS_ON, we have to make sure
1992                    RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1993                 */
1994                 tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
1995                 if (rinfo->is_mobility || rinfo->is_IGP)
1996                         OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1997                 lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);
1998                 lvds_gen_cntl |= (conv_table[0] <<
1999                                   LVDS_BL_MOD_LEVEL_SHIFT);
2000                 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2001                 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2002                 udelay(100);
2003                 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);
2004                 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2005                 lvds_gen_cntl &= ~(LVDS_DIGON);
2006                 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
2007                 mod_timer(&rinfo->lvds_timer,
2008                           jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
2009                 if (rinfo->is_mobility || rinfo->is_IGP)
2010                         OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
2011         }
2012         rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2013         rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2014
2015         return 0;
2016 }
2017
2018
2019 static int radeon_set_backlight_level(int level, void *data)
2020 {
2021         return radeon_set_backlight_enable(1, level, data);
2022 }
2023 #endif /* CONFIG_PMAC_BACKLIGHT */
2024
2025
2026 /*
2027  * This reconfigure the card's internal memory map. In theory, we'd like
2028  * to setup the card's memory at the same address as it's PCI bus address,
2029  * and the AGP aperture right after that so that system RAM on 32 bits
2030  * machines at least, is directly accessible. However, doing so would
2031  * conflict with the current XFree drivers...
2032  * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
2033  * on the proper way to set this up and duplicate this here. In the meantime,
2034  * I put the card's memory at 0 in card space and AGP at some random high
2035  * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
2036  */
2037 #ifdef CONFIG_PPC_OF
2038 #undef SET_MC_FB_FROM_APERTURE
2039 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
2040 {
2041         u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
2042         u32 save_crtc_ext_cntl;
2043         u32 aper_base, aper_size;
2044         u32 agp_base;
2045
2046         /* First, we disable display to avoid interfering */
2047         if (rinfo->has_CRTC2) {
2048                 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
2049                 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
2050         }
2051         save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
2052         save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
2053         
2054         OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
2055         OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
2056         mdelay(100);
2057
2058         aper_base = INREG(CONFIG_APER_0_BASE);
2059         aper_size = INREG(CONFIG_APER_SIZE);
2060
2061 #ifdef SET_MC_FB_FROM_APERTURE
2062         /* Set framebuffer to be at the same address as set in PCI BAR */
2063         OUTREG(MC_FB_LOCATION, 
2064                 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
2065         rinfo->fb_local_base = aper_base;
2066 #else
2067         OUTREG(MC_FB_LOCATION, 0x7fff0000);
2068         rinfo->fb_local_base = 0;
2069 #endif
2070         agp_base = aper_base + aper_size;
2071         if (agp_base & 0xf0000000)
2072                 agp_base = (aper_base | 0x0fffffff) + 1;
2073
2074         /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
2075          * assumes the FB isn't mapped to 0xf0000000 or above, but this is
2076          * always the case on PPCs afaik.
2077          */
2078 #ifdef SET_MC_FB_FROM_APERTURE
2079         OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
2080 #else
2081         OUTREG(MC_AGP_LOCATION, 0xffffe000);
2082 #endif
2083
2084         /* Fixup the display base addresses & engine offsets while we
2085          * are at it as well
2086          */
2087 #ifdef SET_MC_FB_FROM_APERTURE
2088         OUTREG(DISPLAY_BASE_ADDR, aper_base);
2089         if (rinfo->has_CRTC2)
2090                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
2091         OUTREG(OV0_BASE_ADDR, aper_base);
2092 #else
2093         OUTREG(DISPLAY_BASE_ADDR, 0);
2094         if (rinfo->has_CRTC2)
2095                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
2096         OUTREG(OV0_BASE_ADDR, 0);
2097 #endif
2098         mdelay(100);
2099
2100         /* Restore display settings */
2101         OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
2102         OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2103         if (rinfo->has_CRTC2)
2104                 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);    
2105
2106         RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2107                 aper_base,
2108                 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2109                 0xffff0000 | (agp_base >> 16));
2110 }
2111 #endif /* CONFIG_PPC_OF */
2112
2113
2114 static void radeon_identify_vram(struct radeonfb_info *rinfo)
2115 {
2116         u32 tmp;
2117
2118         /* framebuffer size */
2119         if ((rinfo->family == CHIP_FAMILY_RS100) ||
2120             (rinfo->family == CHIP_FAMILY_RS200) ||
2121             (rinfo->family == CHIP_FAMILY_RS300)) {
2122           u32 tom = INREG(NB_TOM);
2123           tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2124
2125                 radeon_fifo_wait(6);
2126           OUTREG(MC_FB_LOCATION, tom);
2127           OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2128           OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2129           OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2130
2131           /* This is supposed to fix the crtc2 noise problem. */
2132           OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2133
2134           if ((rinfo->family == CHIP_FAMILY_RS100) ||
2135               (rinfo->family == CHIP_FAMILY_RS200)) {
2136              /* This is to workaround the asic bug for RMX, some versions
2137                 of BIOS dosen't have this register initialized correctly.
2138              */
2139              OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2140                      ~CRTC_H_CUTOFF_ACTIVE_EN);
2141           }
2142         } else {
2143           tmp = INREG(CONFIG_MEMSIZE);
2144         }
2145
2146         /* mem size is bits [28:0], mask off the rest */
2147         rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2148
2149         /*
2150          * Hack to get around some busted production M6's
2151          * reporting no ram
2152          */
2153         if (rinfo->video_ram == 0) {
2154                 switch (rinfo->pdev->device) {
2155                 case PCI_CHIP_RADEON_LY:
2156                 case PCI_CHIP_RADEON_LZ:
2157                         rinfo->video_ram = 8192 * 1024;
2158                         break;
2159                 default:
2160                         break;
2161                 }
2162         }
2163
2164
2165         /*
2166          * Now try to identify VRAM type
2167          */
2168         if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2169             (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2170                 rinfo->vram_ddr = 1;
2171         else
2172                 rinfo->vram_ddr = 0;
2173
2174         tmp = INREG(MEM_CNTL);
2175         if (IS_R300_VARIANT(rinfo)) {
2176                 tmp &=  R300_MEM_NUM_CHANNELS_MASK;
2177                 switch (tmp) {
2178                 case 0:  rinfo->vram_width = 64; break;
2179                 case 1:  rinfo->vram_width = 128; break;
2180                 case 2:  rinfo->vram_width = 256; break;
2181                 default: rinfo->vram_width = 128; break;
2182                 }
2183         } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2184                    (rinfo->family == CHIP_FAMILY_RS100) ||
2185                    (rinfo->family == CHIP_FAMILY_RS200)){
2186                 if (tmp & RV100_MEM_HALF_MODE)
2187                         rinfo->vram_width = 32;
2188                 else
2189                         rinfo->vram_width = 64;
2190         } else {
2191                 if (tmp & MEM_NUM_CHANNELS_MASK)
2192                         rinfo->vram_width = 128;
2193                 else
2194                         rinfo->vram_width = 64;
2195         }
2196
2197         /* This may not be correct, as some cards can have half of channel disabled
2198          * ToDo: identify these cases
2199          */
2200
2201         RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2202                pci_name(rinfo->pdev),
2203                rinfo->video_ram / 1024,
2204                rinfo->vram_ddr ? "DDR" : "SDRAM",
2205                rinfo->vram_width);
2206 }
2207
2208 /*
2209  * Sysfs
2210  */
2211
2212 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2213 {
2214         if (off > EDID_LENGTH)
2215                 return 0;
2216
2217         if (off + count > EDID_LENGTH)
2218                 count = EDID_LENGTH - off;
2219
2220         memcpy(buf, edid + off, count);
2221
2222         return count;
2223 }
2224
2225
2226 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2227 {
2228         struct device *dev = container_of(kobj, struct device, kobj);
2229         struct pci_dev *pdev = to_pci_dev(dev);
2230         struct fb_info *info = pci_get_drvdata(pdev);
2231         struct radeonfb_info *rinfo = info->par;
2232
2233         return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2234 }
2235
2236
2237 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2238 {
2239         struct device *dev = container_of(kobj, struct device, kobj);
2240         struct pci_dev *pdev = to_pci_dev(dev);
2241         struct fb_info *info = pci_get_drvdata(pdev);
2242         struct radeonfb_info *rinfo = info->par;
2243
2244         return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2245 }
2246
2247 static struct bin_attribute edid1_attr = {
2248         .attr   = {
2249                 .name   = "edid1",
2250                 .owner  = THIS_MODULE,
2251                 .mode   = 0444,
2252         },
2253         .size   = EDID_LENGTH,
2254         .read   = radeon_show_edid1,
2255 };
2256
2257 static struct bin_attribute edid2_attr = {
2258         .attr   = {
2259                 .name   = "edid2",
2260                 .owner  = THIS_MODULE,
2261                 .mode   = 0444,
2262         },
2263         .size   = EDID_LENGTH,
2264         .read   = radeon_show_edid2,
2265 };
2266
2267
2268 static int radeonfb_pci_register (struct pci_dev *pdev,
2269                                   const struct pci_device_id *ent)
2270 {
2271         struct fb_info *info;
2272         struct radeonfb_info *rinfo;
2273         int ret;
2274
2275         RTRACE("radeonfb_pci_register BEGIN\n");
2276         
2277         /* Enable device in PCI config */
2278         ret = pci_enable_device(pdev);
2279         if (ret < 0) {
2280                 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2281                        pci_name(pdev));
2282                 goto err_out;
2283         }
2284
2285         info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2286         if (!info) {
2287                 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2288                         pci_name(pdev));
2289                 ret = -ENOMEM;
2290                 goto err_disable;
2291         }
2292         rinfo = info->par;
2293         rinfo->info = info;     
2294         rinfo->pdev = pdev;
2295         
2296         spin_lock_init(&rinfo->reg_lock);
2297         init_timer(&rinfo->lvds_timer);
2298         rinfo->lvds_timer.function = radeon_lvds_timer_func;
2299         rinfo->lvds_timer.data = (unsigned long)rinfo;
2300
2301         strcpy(rinfo->name, "ATI Radeon XX ");
2302         rinfo->name[11] = ent->device >> 8;
2303         rinfo->name[12] = ent->device & 0xFF;
2304         rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2305         rinfo->chipset = pdev->device;
2306         rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2307         rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2308         rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2309
2310         /* Set base addrs */
2311         rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2312         rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2313
2314         /* request the mem regions */
2315         ret = pci_request_regions(pdev, "radeonfb");
2316         if (ret < 0) {
2317                 printk( KERN_ERR "radeonfb (%s): cannot reserve PCI regions."
2318                         "  Someone already got them?\n", pci_name(rinfo->pdev));
2319                 goto err_release_fb;
2320         }
2321
2322         /* map the regions */
2323         rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2324         if (!rinfo->mmio_base) {
2325                 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n", pci_name(rinfo->pdev));
2326                 ret = -EIO;
2327                 goto err_release_pci;
2328         }
2329
2330         rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2331
2332         /*
2333          * Check for errata
2334          */
2335         rinfo->errata = 0;
2336         if (rinfo->family == CHIP_FAMILY_R300 &&
2337             (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2338             == CFG_ATI_REV_A11)
2339                 rinfo->errata |= CHIP_ERRATA_R300_CG;
2340
2341         if (rinfo->family == CHIP_FAMILY_RV200 ||
2342             rinfo->family == CHIP_FAMILY_RS200)
2343                 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2344
2345         if (rinfo->family == CHIP_FAMILY_RV100 ||
2346             rinfo->family == CHIP_FAMILY_RS100 ||
2347             rinfo->family == CHIP_FAMILY_RS200)
2348                 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2349
2350 #ifdef CONFIG_PPC_OF
2351         /* On PPC, we obtain the OF device-node pointer to the firmware
2352          * data for this chip
2353          */
2354         rinfo->of_node = pci_device_to_OF_node(pdev);
2355         if (rinfo->of_node == NULL)
2356                 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2357                        pci_name(rinfo->pdev));
2358
2359         /* On PPC, the firmware sets up a memory mapping that tends
2360          * to cause lockups when enabling the engine. We reconfigure
2361          * the card internal memory mappings properly
2362          */
2363         fixup_memory_mappings(rinfo);
2364 #endif /* CONFIG_PPC_OF */
2365
2366         /* Get VRAM size and type */
2367         radeon_identify_vram(rinfo);
2368
2369         rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2370
2371         do {
2372                 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2373                                           rinfo->mapped_vram);
2374         } while (   rinfo->fb_base == 0 &&
2375                   ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2376
2377         if (rinfo->fb_base == NULL) {
2378                 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2379                         pci_name(rinfo->pdev));
2380                 ret = -EIO;
2381                 goto err_unmap_rom;
2382         }
2383
2384         RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2385                rinfo->mapped_vram/1024);
2386
2387         /*
2388          * Map the BIOS ROM if any and retreive PLL parameters from
2389          * the BIOS. We skip that on mobility chips as the real panel
2390          * values we need aren't in the ROM but in the BIOS image in
2391          * memory. This is definitely not the best meacnism though,
2392          * we really need the arch code to tell us which is the "primary"
2393          * video adapter to use the memory image (or better, the arch
2394          * should provide us a copy of the BIOS image to shield us from
2395          * archs who would store that elsewhere and/or could initialize
2396          * more than one adapter during boot).
2397          */
2398         if (!rinfo->is_mobility)
2399                 radeon_map_ROM(rinfo, pdev);
2400
2401         /*
2402          * On x86, the primary display on laptop may have it's BIOS
2403          * ROM elsewhere, try to locate it at the legacy memory hole.
2404          * We probably need to make sure this is the primary display,
2405          * but that is difficult without some arch support.
2406          */
2407 #ifdef CONFIG_X86
2408         if (rinfo->bios_seg == NULL)
2409                 radeon_find_mem_vbios(rinfo);
2410 #endif
2411
2412         /* If both above failed, try the BIOS ROM again for mobility
2413          * chips
2414          */
2415         if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2416                 radeon_map_ROM(rinfo, pdev);
2417
2418         /* Get informations about the board's PLL */
2419         radeon_get_pllinfo(rinfo);
2420
2421 #ifdef CONFIG_FB_RADEON_I2C
2422         /* Register I2C bus */
2423         radeon_create_i2c_busses(rinfo);
2424 #endif
2425
2426         /* set all the vital stuff */
2427         radeon_set_fbinfo (rinfo);
2428
2429         /* Probe screen types */
2430         radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2431
2432         /* Build mode list, check out panel native model */
2433         radeon_check_modes(rinfo, mode_option);
2434
2435         /* Register some sysfs stuff (should be done better) */
2436         if (rinfo->mon1_EDID)
2437                 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2438         if (rinfo->mon2_EDID)
2439                 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2440
2441         /* save current mode regs before we switch into the new one
2442          * so we can restore this upon __exit
2443          */
2444         radeon_save_state (rinfo, &rinfo->init_state);
2445         memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2446
2447         /* Setup Power Management capabilities */
2448         if (default_dynclk < -1) {
2449                 /* -2 is special: means  ON on mobility chips and do not
2450                  * change on others
2451                  */
2452                 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);
2453         } else
2454                 radeonfb_pm_init(rinfo, default_dynclk);
2455
2456         pci_set_drvdata(pdev, info);
2457
2458         /* Register with fbdev layer */
2459         ret = register_framebuffer(info);
2460         if (ret < 0) {
2461                 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2462                         pci_name(rinfo->pdev));
2463                 goto err_unmap_fb;
2464         }
2465
2466 #ifdef CONFIG_MTRR
2467         rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2468                                                  rinfo->video_ram,
2469                                                  MTRR_TYPE_WRCOMB, 1);
2470 #endif
2471
2472 #ifdef CONFIG_PMAC_BACKLIGHT
2473         if (rinfo->mon1_type == MT_LCD) {
2474                 register_backlight_controller(&radeon_backlight_controller,
2475                                               rinfo, "ati");
2476                 register_backlight_controller(&radeon_backlight_controller,
2477                                               rinfo, "mnca");
2478         }
2479 #endif
2480
2481         printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2482
2483         if (rinfo->bios_seg)
2484                 radeon_unmap_ROM(rinfo, pdev);
2485         RTRACE("radeonfb_pci_register END\n");
2486
2487         return 0;
2488 err_unmap_fb:
2489         iounmap(rinfo->fb_base);
2490 err_unmap_rom:
2491         kfree(rinfo->mon1_EDID);
2492         kfree(rinfo->mon2_EDID);
2493         if (rinfo->mon1_modedb)
2494                 fb_destroy_modedb(rinfo->mon1_modedb);
2495         fb_dealloc_cmap(&info->cmap);
2496 #ifdef CONFIG_FB_RADEON_I2C
2497         radeon_delete_i2c_busses(rinfo);
2498 #endif
2499         if (rinfo->bios_seg)
2500                 radeon_unmap_ROM(rinfo, pdev);
2501         iounmap(rinfo->mmio_base);
2502 err_release_pci:
2503         pci_release_regions(pdev);
2504 err_release_fb:
2505         framebuffer_release(info);
2506 err_disable:
2507         pci_disable_device(pdev);
2508 err_out:
2509         return ret;
2510 }
2511
2512
2513
2514 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2515 {
2516         struct fb_info *info = pci_get_drvdata(pdev);
2517         struct radeonfb_info *rinfo = info->par;
2518  
2519         if (!rinfo)
2520                 return;
2521  
2522         radeonfb_pm_exit(rinfo);
2523
2524 #if 0
2525         /* restore original state
2526          * 
2527          * Doesn't quite work yet, I suspect if we come from a legacy
2528          * VGA mode (or worse, text mode), we need to do some VGA black
2529          * magic here that I know nothing about. --BenH
2530          */
2531         radeon_write_mode (rinfo, &rinfo->init_state, 1);
2532  #endif
2533
2534         del_timer_sync(&rinfo->lvds_timer);
2535
2536 #ifdef CONFIG_MTRR
2537         if (rinfo->mtrr_hdl >= 0)
2538                 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2539 #endif
2540
2541         unregister_framebuffer(info);
2542
2543         iounmap(rinfo->mmio_base);
2544         iounmap(rinfo->fb_base);
2545  
2546         pci_release_regions(pdev);
2547
2548         kfree(rinfo->mon1_EDID);
2549         kfree(rinfo->mon2_EDID);
2550         if (rinfo->mon1_modedb)
2551                 fb_destroy_modedb(rinfo->mon1_modedb);
2552 #ifdef CONFIG_FB_RADEON_I2C
2553         radeon_delete_i2c_busses(rinfo);
2554 #endif        
2555         fb_dealloc_cmap(&info->cmap);
2556         framebuffer_release(info);
2557         pci_disable_device(pdev);
2558 }
2559
2560
2561 static struct pci_driver radeonfb_driver = {
2562         .name           = "radeonfb",
2563         .id_table       = radeonfb_pci_table,
2564         .probe          = radeonfb_pci_register,
2565         .remove         = __devexit_p(radeonfb_pci_unregister),
2566 #ifdef CONFIG_PM
2567         .suspend        = radeonfb_pci_suspend,
2568         .resume         = radeonfb_pci_resume,
2569 #endif /* CONFIG_PM */
2570 };
2571
2572 #ifndef MODULE
2573 static int __init radeonfb_setup (char *options)
2574 {
2575         char *this_opt;
2576
2577         if (!options || !*options)
2578                 return 0;
2579
2580         while ((this_opt = strsep (&options, ",")) != NULL) {
2581                 if (!*this_opt)
2582                         continue;
2583
2584                 if (!strncmp(this_opt, "noaccel", 7)) {
2585                         noaccel = 1;
2586                 } else if (!strncmp(this_opt, "mirror", 6)) {
2587                         mirror = 1;
2588                 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2589                         force_dfp = 1;
2590                 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2591                         panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2592 #ifdef CONFIG_MTRR
2593                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2594                         nomtrr = 1;
2595 #endif
2596                 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2597                         nomodeset = 1;
2598                 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2599                         force_measure_pll = 1;
2600                 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2601                         ignore_edid = 1;
2602                 } else
2603                         mode_option = this_opt;
2604         }
2605         return 0;
2606 }
2607 #endif  /*  MODULE  */
2608
2609 static int __init radeonfb_init (void)
2610 {
2611 #ifndef MODULE
2612         char *option = NULL;
2613
2614         if (fb_get_options("radeonfb", &option))
2615                 return -ENODEV;
2616         radeonfb_setup(option);
2617 #endif
2618         return pci_register_driver (&radeonfb_driver);
2619 }
2620
2621
2622 static void __exit radeonfb_exit (void)
2623 {
2624         pci_unregister_driver (&radeonfb_driver);
2625 }
2626
2627 module_init(radeonfb_init);
2628 module_exit(radeonfb_exit);
2629
2630 MODULE_AUTHOR("Ani Joshi");
2631 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2632 MODULE_LICENSE("GPL");
2633 module_param(noaccel, bool, 0);
2634 module_param(default_dynclk, int, 0);
2635 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2636 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2637 module_param(nomodeset, bool, 0);
2638 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2639 module_param(mirror, bool, 0);
2640 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2641 module_param(force_dfp, bool, 0);
2642 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2643 module_param(ignore_edid, bool, 0);
2644 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2645 module_param(monitor_layout, charp, 0);
2646 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2647 module_param(force_measure_pll, bool, 0);
2648 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2649 #ifdef CONFIG_MTRR
2650 module_param(nomtrr, bool, 0);
2651 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2652 #endif
2653 module_param(panel_yres, int, 0);
2654 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2655 module_param(mode_option, charp, 0);
2656 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");