2 * arch/sparc/kernel/sun4m_irq.c:
4 * djhr: Hacked out of irq.c into a CPU dependent version.
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
12 #include <linux/errno.h>
13 #include <linux/linkage.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
16 #include <linux/sched.h>
17 #include <linux/ptrace.h>
18 #include <linux/smp.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
24 #include <asm/ptrace.h>
25 #include <asm/processor.h>
26 #include <asm/system.h>
28 #include <asm/vaddrs.h>
29 #include <asm/timer.h>
30 #include <asm/openprom.h>
31 #include <asm/oplib.h>
32 #include <asm/traps.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
39 #include <asm/cacheflush.h>
43 /* On the sun4m, just like the timers, we have both per-cpu and master
44 * interrupt registers.
47 /* These registers are used for sending/receiving irqs from/to
50 struct sun4m_intreg_percpu {
51 unsigned int tbt; /* Interrupts still pending for this cpu. */
53 /* These next two registers are WRITE-ONLY and are only
54 * "on bit" sensitive, "off bits" written have NO affect.
56 unsigned int clear; /* Clear this cpus irqs here. */
57 unsigned int set; /* Set this cpus irqs here. */
58 unsigned char space[PAGE_SIZE - 12];
63 * Actually the clear and set fields in this struct are misleading..
64 * according to the SLAVIO manual (and the same applies for the SEC)
65 * the clear field clears bits in the mask which will ENABLE that IRQ
66 * the set field sets bits in the mask to DISABLE the IRQ.
68 * Also the undirected_xx address in the SLAVIO is defined as
69 * RESERVED and write only..
71 * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
72 * sun4m machines, for MP the layout makes more sense.
74 struct sun4m_intregs {
75 struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
76 unsigned int tbt; /* IRQ's that are still pending. */
77 unsigned int irqs; /* Master IRQ bits. */
79 /* Again, like the above, two these registers are WRITE-ONLY. */
80 unsigned int clear; /* Clear master IRQ's by setting bits here. */
81 unsigned int set; /* Set master IRQ's by setting bits here. */
83 /* This register is both READ and WRITE. */
84 unsigned int undirected_target; /* Which cpu gets undirected irqs. */
87 static unsigned long dummy;
89 struct sun4m_intregs *sun4m_interrupts;
90 unsigned long *irq_rcvreg = &dummy;
92 /* Dave Redman (djhr@tadpole.co.uk)
93 * The sun4m interrupt registers.
95 #define SUN4M_INT_ENABLE 0x80000000
96 #define SUN4M_INT_E14 0x00000080
97 #define SUN4M_INT_E10 0x00080000
99 #define SUN4M_HARD_INT(x) (0x000000001 << (x))
100 #define SUN4M_SOFT_INT(x) (0x000010000 << (x))
102 #define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
103 #define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
104 #define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
105 #define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
106 #define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
107 #define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
108 #define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
109 #define SUN4M_INT_REALTIME 0x00080000 /* system timer */
110 #define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
111 #define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
112 #define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
113 #define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
114 #define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
115 #define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
117 #define SUN4M_INT_SBUS(x) (1 << (x+7))
118 #define SUN4M_INT_VME(x) (1 << (x))
120 /* These tables only apply for interrupts greater than 15..
122 * any intr value below 0x10 is considered to be a soft-int
123 * this may be useful or it may not.. but that's how I've done it.
124 * and it won't clash with what OBP is telling us about devices.
126 * take an encoded intr value and lookup if it's valid
127 * then get the mask bits that match from irq_mask
129 * P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
131 static unsigned char irq_xlate[32] = {
132 /* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f */
133 0, 0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 5, 6, 14, 0, 7,
134 0, 0, 8, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 0
137 static unsigned long irq_mask[] = {
138 0, /* illegal index */
139 SUN4M_INT_SCSI, /* 1 irq 4 */
140 SUN4M_INT_ETHERNET, /* 2 irq 6 */
141 SUN4M_INT_VIDEO, /* 3 irq 8 */
142 SUN4M_INT_REALTIME, /* 4 irq 10 */
143 SUN4M_INT_FLOPPY, /* 5 irq 11 */
144 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS), /* 6 irq 12 */
145 SUN4M_INT_MODULE_ERR, /* 7 irq 15 */
146 SUN4M_INT_SBUS(0), /* 8 irq 2 */
147 SUN4M_INT_SBUS(1), /* 9 irq 3 */
148 SUN4M_INT_SBUS(2), /* 10 irq 5 */
149 SUN4M_INT_SBUS(3), /* 11 irq 7 */
150 SUN4M_INT_SBUS(4), /* 12 irq 9 */
151 SUN4M_INT_SBUS(5), /* 13 irq 11 */
152 SUN4M_INT_SBUS(6) /* 14 irq 13 */
155 static unsigned long sun4m_get_irqmask(unsigned int irq)
160 /* OBIO/SBUS interrupts */
162 mask = irq_mask[irq_xlate[irq]];
164 printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
166 /* Soft Interrupts will come here.
167 * Currently there is no way to trigger them but I'm sure
168 * something could be cooked up.
171 mask = SUN4M_SOFT_INT(irq);
176 static void sun4m_disable_irq(unsigned int irq_nr)
178 unsigned long mask, flags;
179 int cpu = smp_processor_id();
181 mask = sun4m_get_irqmask(irq_nr);
182 local_irq_save(flags);
184 sun4m_interrupts->set = mask;
186 sun4m_interrupts->cpu_intregs[cpu].set = mask;
187 local_irq_restore(flags);
190 static void sun4m_enable_irq(unsigned int irq_nr)
192 unsigned long mask, flags;
193 int cpu = smp_processor_id();
195 /* Dreadful floppy hack. When we use 0x2b instead of
196 * 0x0b the system blows (it starts to whistle!).
197 * So we continue to use 0x0b. Fixme ASAP. --P3
199 if (irq_nr != 0x0b) {
200 mask = sun4m_get_irqmask(irq_nr);
201 local_irq_save(flags);
203 sun4m_interrupts->clear = mask;
205 sun4m_interrupts->cpu_intregs[cpu].clear = mask;
206 local_irq_restore(flags);
208 local_irq_save(flags);
209 sun4m_interrupts->clear = SUN4M_INT_FLOPPY;
210 local_irq_restore(flags);
214 static unsigned long cpu_pil_to_imask[16] = {
217 /*2*/ SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
218 /*3*/ SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
219 /*4*/ SUN4M_INT_SCSI,
220 /*5*/ SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
221 /*6*/ SUN4M_INT_ETHERNET,
222 /*7*/ SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
223 /*8*/ SUN4M_INT_VIDEO,
224 /*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
225 /*10*/ SUN4M_INT_REALTIME,
226 /*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
227 /*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
228 /*13*/ SUN4M_INT_AUDIO,
229 /*14*/ SUN4M_INT_E14,
233 /* We assume the caller has disabled local interrupts when these are called,
234 * or else very bizarre behavior will result.
236 static void sun4m_disable_pil_irq(unsigned int pil)
238 sun4m_interrupts->set = cpu_pil_to_imask[pil];
241 static void sun4m_enable_pil_irq(unsigned int pil)
243 sun4m_interrupts->clear = cpu_pil_to_imask[pil];
247 static void sun4m_send_ipi(int cpu, int level)
251 mask = sun4m_get_irqmask(level);
252 sun4m_interrupts->cpu_intregs[cpu].set = mask;
255 static void sun4m_clear_ipi(int cpu, int level)
259 mask = sun4m_get_irqmask(level);
260 sun4m_interrupts->cpu_intregs[cpu].clear = mask;
263 static void sun4m_set_udt(int cpu)
265 sun4m_interrupts->undirected_target = cpu;
269 #define OBIO_INTR 0x20
270 #define TIMER_IRQ (OBIO_INTR | 10)
271 #define PROFILE_IRQ (OBIO_INTR | 14)
273 static struct sun4m_timer_regs *sun4m_timers;
274 unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
276 static void sun4m_clear_clock_irq(void)
278 volatile unsigned int clear_intr;
279 clear_intr = sun4m_timers->l10_timer_limit;
282 static void sun4m_clear_profile_irq(int cpu)
284 volatile unsigned int clear;
286 clear = sun4m_timers->cpu_timers[cpu].l14_timer_limit;
289 static void sun4m_load_profile_irq(int cpu, unsigned int limit)
291 sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit;
294 static void __init sun4m_init_timers(irq_handler_t counter_fn)
296 int reg_count, irq, cpu;
297 struct linux_prom_registers cnt_regs[PROMREG_MAX];
298 int obio_node, cnt_node;
303 prom_searchsiblings (prom_getchild(prom_root_node), "obio")) == 0 ||
304 (obio_node = prom_getchild (obio_node)) == 0 ||
305 (cnt_node = prom_searchsiblings (obio_node, "counter")) == 0) {
306 prom_printf("Cannot find /obio/counter node\n");
309 reg_count = prom_getproperty(cnt_node, "reg",
310 (void *) cnt_regs, sizeof(cnt_regs));
311 reg_count = (reg_count/sizeof(struct linux_prom_registers));
313 /* Apply the obio ranges to the timer registers. */
314 prom_apply_obio_ranges(cnt_regs, reg_count);
316 cnt_regs[4].phys_addr = cnt_regs[reg_count-1].phys_addr;
317 cnt_regs[4].reg_size = cnt_regs[reg_count-1].reg_size;
318 cnt_regs[4].which_io = cnt_regs[reg_count-1].which_io;
319 for(obio_node = 1; obio_node < 4; obio_node++) {
320 cnt_regs[obio_node].phys_addr =
321 cnt_regs[obio_node-1].phys_addr + PAGE_SIZE;
322 cnt_regs[obio_node].reg_size = cnt_regs[obio_node-1].reg_size;
323 cnt_regs[obio_node].which_io = cnt_regs[obio_node-1].which_io;
326 memset((char*)&r, 0, sizeof(struct resource));
327 /* Map the per-cpu Counter registers. */
328 r.flags = cnt_regs[0].which_io;
329 r.start = cnt_regs[0].phys_addr;
330 sun4m_timers = (struct sun4m_timer_regs *) sbus_ioremap(&r, 0,
331 PAGE_SIZE*SUN4M_NCPUS, "sun4m_cpu_cnt");
332 /* Map the system Counter register. */
333 /* XXX Here we expect consequent calls to yeld adjusent maps. */
334 r.flags = cnt_regs[4].which_io;
335 r.start = cnt_regs[4].phys_addr;
336 sbus_ioremap(&r, 0, cnt_regs[4].reg_size, "sun4m_sys_cnt");
338 sun4m_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10);
339 master_l10_counter = &sun4m_timers->l10_cur_count;
340 master_l10_limit = &sun4m_timers->l10_timer_limit;
342 irq = request_irq(TIMER_IRQ,
344 (IRQF_DISABLED | SA_STATIC_ALLOC),
347 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
351 if (!cpu_find_by_instance(1, NULL, NULL)) {
352 for(cpu = 0; cpu < 4; cpu++)
353 sun4m_timers->cpu_timers[cpu].l14_timer_limit = 0;
354 sun4m_interrupts->set = SUN4M_INT_E14;
356 sun4m_timers->cpu_timers[0].l14_timer_limit = 0;
361 extern unsigned long lvl14_save[4];
362 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
364 /* For SMP we use the level 14 ticker, however the bootup code
365 * has copied the firmware's level 14 vector into the boot cpu's
366 * trap table, we must fix this now or we get squashed.
368 local_irq_save(flags);
369 trap_table->inst_one = lvl14_save[0];
370 trap_table->inst_two = lvl14_save[1];
371 trap_table->inst_three = lvl14_save[2];
372 trap_table->inst_four = lvl14_save[3];
373 local_flush_cache_all();
374 local_irq_restore(flags);
379 void __init sun4m_init_IRQ(void)
382 struct linux_prom_registers int_regs[PROMREG_MAX];
388 if((ie_node = prom_searchsiblings(prom_getchild(prom_root_node), "obio")) == 0 ||
389 (ie_node = prom_getchild (ie_node)) == 0 ||
390 (ie_node = prom_searchsiblings (ie_node, "interrupt")) == 0) {
391 prom_printf("Cannot find /obio/interrupt node\n");
394 num_regs = prom_getproperty(ie_node, "reg", (char *) int_regs,
396 num_regs = (num_regs/sizeof(struct linux_prom_registers));
398 /* Apply the obio ranges to these registers. */
399 prom_apply_obio_ranges(int_regs, num_regs);
401 int_regs[4].phys_addr = int_regs[num_regs-1].phys_addr;
402 int_regs[4].reg_size = int_regs[num_regs-1].reg_size;
403 int_regs[4].which_io = int_regs[num_regs-1].which_io;
404 for(ie_node = 1; ie_node < 4; ie_node++) {
405 int_regs[ie_node].phys_addr = int_regs[ie_node-1].phys_addr + PAGE_SIZE;
406 int_regs[ie_node].reg_size = int_regs[ie_node-1].reg_size;
407 int_regs[ie_node].which_io = int_regs[ie_node-1].which_io;
410 memset((char *)&r, 0, sizeof(struct resource));
411 /* Map the interrupt registers for all possible cpus. */
412 r.flags = int_regs[0].which_io;
413 r.start = int_regs[0].phys_addr;
414 sun4m_interrupts = (struct sun4m_intregs *) sbus_ioremap(&r, 0,
415 PAGE_SIZE*SUN4M_NCPUS, "interrupts_percpu");
417 /* Map the system interrupt control registers. */
418 r.flags = int_regs[4].which_io;
419 r.start = int_regs[4].phys_addr;
420 sbus_ioremap(&r, 0, int_regs[4].reg_size, "interrupts_system");
422 sun4m_interrupts->set = ~SUN4M_INT_MASKALL;
423 for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
424 sun4m_interrupts->cpu_intregs[mid].clear = ~0x17fff;
426 if (!cpu_find_by_instance(1, NULL, NULL)) {
427 /* system wide interrupts go to cpu 0, this should always
428 * be safe because it is guaranteed to be fitted or OBP doesn't
431 * Not sure, but writing here on SLAVIO systems may puke
432 * so I don't do it unless there is more than 1 cpu.
434 irq_rcvreg = (unsigned long *)
435 &sun4m_interrupts->undirected_target;
436 sun4m_interrupts->undirected_target = 0;
438 BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
439 BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
440 BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
441 BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
442 BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
443 BTFIXUPSET_CALL(clear_profile_irq, sun4m_clear_profile_irq, BTFIXUPCALL_NORM);
444 BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
445 sparc_init_timers = sun4m_init_timers;
447 BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
448 BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
449 BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
451 /* Cannot enable interrupts until OBP ticker is disabled. */