Merge branch 'for-linus' of git://oss.sgi.com:8090/xfs/xfs-2.6
[linux-2.6] / drivers / ide / mips / au1xxx-ide.c
1 /*
2  * linux/drivers/ide/mips/au1xxx-ide.c  version 01.30.00        Aug. 02 2005
3  *
4  * BRIEF MODULE DESCRIPTION
5  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
6  *
7  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
8  *
9  * This program is free software; you can redistribute it and/or modify it under
10  * the terms of the GNU General Public License as published by the Free Software
11  * Foundation; either version 2 of the License, or (at your option) any later
12  * version.
13  *
14  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23  * POSSIBILITY OF SUCH DAMAGE.
24  *
25  * You should have received a copy of the GNU General Public License along with
26  * this program; if not, write to the Free Software Foundation, Inc.,
27  * 675 Mass Ave, Cambridge, MA 02139, USA.
28  *
29  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30  *       Interface and Linux Device Driver" Application Note.
31  */
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/platform_device.h>
37
38 #include <linux/init.h>
39 #include <linux/ide.h>
40 #include <linux/sysdev.h>
41
42 #include <linux/dma-mapping.h>
43
44 #include "ide-timing.h"
45
46 #include <asm/io.h>
47 #include <asm/mach-au1x00/au1xxx.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
49
50 #include <asm/mach-au1x00/au1xxx_ide.h>
51
52 #define DRV_NAME        "au1200-ide"
53 #define DRV_VERSION     "1.0"
54 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
55
56 /* enable the burstmode in the dbdma */
57 #define IDE_AU1XXX_BURSTMODE    1
58
59 static _auide_hwif auide_hwif;
60 static int dbdma_init_done;
61
62 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
63
64 void auide_insw(unsigned long port, void *addr, u32 count)
65 {
66         _auide_hwif *ahwif = &auide_hwif;
67         chan_tab_t *ctp;
68         au1x_ddma_desc_t *dp;
69
70         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1, 
71                            DDMA_FLAGS_NOIE)) {
72                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
73                 return;
74         }
75         ctp = *((chan_tab_t **)ahwif->rx_chan);
76         dp = ctp->cur_ptr;
77         while (dp->dscr_cmd0 & DSCR_CMD0_V)
78                 ;
79         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
80 }
81
82 void auide_outsw(unsigned long port, void *addr, u32 count)
83 {
84         _auide_hwif *ahwif = &auide_hwif;
85         chan_tab_t *ctp;
86         au1x_ddma_desc_t *dp;
87
88         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
89                              count << 1, DDMA_FLAGS_NOIE)) {
90                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
91                 return;
92         }
93         ctp = *((chan_tab_t **)ahwif->tx_chan);
94         dp = ctp->cur_ptr;
95         while (dp->dscr_cmd0 & DSCR_CMD0_V)
96                 ;
97         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
98 }
99
100 #endif
101
102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
103 {
104         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
105
106         /* set pio mode! */
107         switch(pio) {
108         case 0:
109                 mem_sttime = SBC_IDE_TIMING(PIO0);
110
111                 /* set configuration for RCS2# */
112                 mem_stcfg |= TS_MASK;
113                 mem_stcfg &= ~TCSOE_MASK;
114                 mem_stcfg &= ~TOECS_MASK;
115                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
116                 break;
117
118         case 1:
119                 mem_sttime = SBC_IDE_TIMING(PIO1);
120
121                 /* set configuration for RCS2# */
122                 mem_stcfg |= TS_MASK;
123                 mem_stcfg &= ~TCSOE_MASK;
124                 mem_stcfg &= ~TOECS_MASK;
125                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
126                 break;
127
128         case 2:
129                 mem_sttime = SBC_IDE_TIMING(PIO2);
130
131                 /* set configuration for RCS2# */
132                 mem_stcfg &= ~TS_MASK;
133                 mem_stcfg &= ~TCSOE_MASK;
134                 mem_stcfg &= ~TOECS_MASK;
135                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
136                 break;
137
138         case 3:
139                 mem_sttime = SBC_IDE_TIMING(PIO3);
140
141                 /* set configuration for RCS2# */
142                 mem_stcfg &= ~TS_MASK;
143                 mem_stcfg &= ~TCSOE_MASK;
144                 mem_stcfg &= ~TOECS_MASK;
145                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
146
147                 break;
148
149         case 4:
150                 mem_sttime = SBC_IDE_TIMING(PIO4);
151
152                 /* set configuration for RCS2# */
153                 mem_stcfg &= ~TS_MASK;
154                 mem_stcfg &= ~TCSOE_MASK;
155                 mem_stcfg &= ~TOECS_MASK;
156                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
157                 break;
158         }
159
160         au_writel(mem_sttime,MEM_STTIME2);
161         au_writel(mem_stcfg,MEM_STCFG2);
162 }
163
164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
165 {
166         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
167
168         switch(speed) {
169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
170         case XFER_MW_DMA_2:
171                 mem_sttime = SBC_IDE_TIMING(MDMA2);
172
173                 /* set configuration for RCS2# */
174                 mem_stcfg &= ~TS_MASK;
175                 mem_stcfg &= ~TCSOE_MASK;
176                 mem_stcfg &= ~TOECS_MASK;
177                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
178
179                 break;
180         case XFER_MW_DMA_1:
181                 mem_sttime = SBC_IDE_TIMING(MDMA1);
182
183                 /* set configuration for RCS2# */
184                 mem_stcfg &= ~TS_MASK;
185                 mem_stcfg &= ~TCSOE_MASK;
186                 mem_stcfg &= ~TOECS_MASK;
187                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
188
189                 break;
190         case XFER_MW_DMA_0:
191                 mem_sttime = SBC_IDE_TIMING(MDMA0);
192
193                 /* set configuration for RCS2# */
194                 mem_stcfg |= TS_MASK;
195                 mem_stcfg &= ~TCSOE_MASK;
196                 mem_stcfg &= ~TOECS_MASK;
197                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
198
199                 break;
200 #endif
201         default:
202                 return;
203         }
204
205         au_writel(mem_sttime,MEM_STTIME2);
206         au_writel(mem_stcfg,MEM_STCFG2);
207 }
208
209 /*
210  * Multi-Word DMA + DbDMA functions
211  */
212
213 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
214
215 static int auide_build_sglist(ide_drive_t *drive,  struct request *rq)
216 {
217         ide_hwif_t *hwif = drive->hwif;
218         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
219         struct scatterlist *sg = hwif->sg_table;
220
221         ide_map_sg(drive, rq);
222
223         if (rq_data_dir(rq) == READ)
224                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
225         else
226                 hwif->sg_dma_direction = DMA_TO_DEVICE;
227
228         return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
229                           hwif->sg_dma_direction);
230 }
231
232 static int auide_build_dmatable(ide_drive_t *drive)
233 {
234         int i, iswrite, count = 0;
235         ide_hwif_t *hwif = HWIF(drive);
236
237         struct request *rq = HWGROUP(drive)->rq;
238
239         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
240         struct scatterlist *sg;
241
242         iswrite = (rq_data_dir(rq) == WRITE);
243         /* Save for interrupt context */
244         ahwif->drive = drive;
245
246         /* Build sglist */
247         hwif->sg_nents = i = auide_build_sglist(drive, rq);
248
249         if (!i)
250                 return 0;
251
252         /* fill the descriptors */
253         sg = hwif->sg_table;
254         while (i && sg_dma_len(sg)) {
255                 u32 cur_addr;
256                 u32 cur_len;
257
258                 cur_addr = sg_dma_address(sg);
259                 cur_len = sg_dma_len(sg);
260
261                 while (cur_len) {
262                         u32 flags = DDMA_FLAGS_NOIE;
263                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
264
265                         if (++count >= PRD_ENTRIES) {
266                                 printk(KERN_WARNING "%s: DMA table too small\n",
267                                        drive->name);
268                                 goto use_pio_instead;
269                         }
270
271                         /* Lets enable intr for the last descriptor only */
272                         if (1==i)
273                                 flags = DDMA_FLAGS_IE;
274                         else
275                                 flags = DDMA_FLAGS_NOIE;
276
277                         if (iswrite) {
278                                 if(!put_source_flags(ahwif->tx_chan, 
279                                                      (void*)(page_address(sg->page) 
280                                                              + sg->offset), 
281                                                      tc, flags)) { 
282                                         printk(KERN_ERR "%s failed %d\n", 
283                                                __FUNCTION__, __LINE__);
284                                 }
285                         } else 
286                         {
287                                 if(!put_dest_flags(ahwif->rx_chan, 
288                                                    (void*)(page_address(sg->page) 
289                                                            + sg->offset), 
290                                                    tc, flags)) { 
291                                         printk(KERN_ERR "%s failed %d\n", 
292                                                __FUNCTION__, __LINE__);
293                                 }
294                         }
295
296                         cur_addr += tc;
297                         cur_len -= tc;
298                 }
299                 sg = sg_next(sg);
300                 i--;
301         }
302
303         if (count)
304                 return 1;
305
306  use_pio_instead:
307         dma_unmap_sg(ahwif->dev,
308                      hwif->sg_table,
309                      hwif->sg_nents,
310                      hwif->sg_dma_direction);
311
312         return 0; /* revert to PIO for this request */
313 }
314
315 static int auide_dma_end(ide_drive_t *drive)
316 {
317         ide_hwif_t *hwif = HWIF(drive);
318         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
319
320         if (hwif->sg_nents) {
321                 dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
322                              hwif->sg_dma_direction);
323                 hwif->sg_nents = 0;
324         }
325
326         return 0;
327 }
328
329 static void auide_dma_start(ide_drive_t *drive )
330 {
331 }
332
333
334 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
335 {
336         /* issue cmd to drive */
337         ide_execute_command(drive, command, &ide_dma_intr,
338                             (2*WAIT_CMD), NULL);
339 }
340
341 static int auide_dma_setup(ide_drive_t *drive)
342 {               
343         struct request *rq = HWGROUP(drive)->rq;
344
345         if (!auide_build_dmatable(drive)) {
346                 ide_map_sg(drive, rq);
347                 return 1;
348         }
349
350         drive->waiting_for_dma = 1;
351         return 0;
352 }
353
354 static u8 auide_mdma_filter(ide_drive_t *drive)
355 {
356         /*
357          * FIXME: ->white_list and ->black_list are based on completely bogus
358          * ->ide_dma_check implementation which didn't set neither the host
359          * controller timings nor the device for the desired transfer mode.
360          *
361          * They should be either removed or 0x00 MWDMA mask should be
362          * returned for devices on the ->black_list.
363          */
364
365         if (dbdma_init_done == 0) {
366                 auide_hwif.white_list = ide_in_drive_list(drive->id,
367                                                           dma_white_list);
368                 auide_hwif.black_list = ide_in_drive_list(drive->id,
369                                                           dma_black_list);
370                 auide_hwif.drive = drive;
371                 auide_ddma_init(&auide_hwif);
372                 dbdma_init_done = 1;
373         }
374
375         /* Is the drive in our DMA black list? */
376         if (auide_hwif.black_list)
377                 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
378                                     drive->name, drive->id->model);
379
380         return drive->hwif->mwdma_mask;
381 }
382
383 static int auide_dma_test_irq(ide_drive_t *drive)
384 {       
385         if (drive->waiting_for_dma == 0)
386                 printk(KERN_WARNING "%s: ide_dma_test_irq \
387                                      called while not waiting\n", drive->name);
388
389         /* If dbdma didn't execute the STOP command yet, the
390          * active bit is still set
391          */
392         drive->waiting_for_dma++;
393         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
394                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
395                                      complete\n", drive->name);
396                 return 1;
397         }
398         udelay(10);
399         return 0;
400 }
401
402 static void auide_dma_host_on(ide_drive_t *drive)
403 {
404 }
405
406 static int auide_dma_on(ide_drive_t *drive)
407 {
408         drive->using_dma = 1;
409
410         return 0;
411 }
412
413 static void auide_dma_host_off(ide_drive_t *drive)
414 {
415 }
416
417 static void auide_dma_off_quietly(ide_drive_t *drive)
418 {
419         drive->using_dma = 0;
420 }
421
422 static void auide_dma_lost_irq(ide_drive_t *drive)
423 {
424         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
425 }
426
427 static void auide_ddma_tx_callback(int irq, void *param)
428 {
429         _auide_hwif *ahwif = (_auide_hwif*)param;
430         ahwif->drive->waiting_for_dma = 0;
431 }
432
433 static void auide_ddma_rx_callback(int irq, void *param)
434 {
435         _auide_hwif *ahwif = (_auide_hwif*)param;
436         ahwif->drive->waiting_for_dma = 0;
437 }
438
439 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
440
441 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
442 {
443         dev->dev_id          = dev_id;
444         dev->dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
445         dev->dev_intlevel    = 0;
446         dev->dev_intpolarity = 0;
447         dev->dev_tsize       = tsize;
448         dev->dev_devwidth    = devwidth;
449         dev->dev_flags       = flags;
450 }
451   
452 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
453
454 static void auide_dma_timeout(ide_drive_t *drive)
455 {
456         ide_hwif_t *hwif = HWIF(drive);
457
458         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
459
460         if (hwif->ide_dma_test_irq(drive))
461                 return;
462
463         hwif->ide_dma_end(drive);
464 }
465                                         
466
467 static int auide_ddma_init(_auide_hwif *auide) {
468         
469         dbdev_tab_t source_dev_tab, target_dev_tab;
470         u32 dev_id, tsize, devwidth, flags;
471         ide_hwif_t *hwif = auide->hwif;
472
473         dev_id   = AU1XXX_ATA_DDMA_REQ;
474
475         if (auide->white_list || auide->black_list) {
476                 tsize    = 8;
477                 devwidth = 32;
478         }
479         else { 
480                 tsize    = 1;
481                 devwidth = 16;
482                 
483                 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
484                 printk(KERN_ERR "            please read 'Documentation/mips/AU1xxx_IDE.README'");
485         }
486
487 #ifdef IDE_AU1XXX_BURSTMODE 
488         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
489 #else
490         flags = DEV_FLAGS_SYNC;
491 #endif
492
493         /* setup dev_tab for tx channel */
494         auide_init_dbdma_dev( &source_dev_tab,
495                               dev_id,
496                               tsize, devwidth, DEV_FLAGS_OUT | flags);
497         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
498
499         auide_init_dbdma_dev( &source_dev_tab,
500                               dev_id,
501                               tsize, devwidth, DEV_FLAGS_IN | flags);
502         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
503         
504         /* We also need to add a target device for the DMA */
505         auide_init_dbdma_dev( &target_dev_tab,
506                               (u32)DSCR_CMD0_ALWAYS,
507                               tsize, devwidth, DEV_FLAGS_ANYUSE);
508         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); 
509  
510         /* Get a channel for TX */
511         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
512                                                  auide->tx_dev_id,
513                                                  auide_ddma_tx_callback,
514                                                  (void*)auide);
515  
516         /* Get a channel for RX */
517         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
518                                                  auide->target_dev_id,
519                                                  auide_ddma_rx_callback,
520                                                  (void*)auide);
521
522         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
523                                                              NUM_DESCRIPTORS);
524         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
525                                                              NUM_DESCRIPTORS);
526  
527         hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
528                                                 PRD_ENTRIES * PRD_BYTES,        /* 1 Page */
529                                                 &hwif->dmatable_dma, GFP_KERNEL);
530         
531         au1xxx_dbdma_start( auide->tx_chan );
532         au1xxx_dbdma_start( auide->rx_chan );
533  
534         return 0;
535
536 #else
537  
538 static int auide_ddma_init( _auide_hwif *auide )
539 {
540         dbdev_tab_t source_dev_tab;
541         int flags;
542
543 #ifdef IDE_AU1XXX_BURSTMODE 
544         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
545 #else
546         flags = DEV_FLAGS_SYNC;
547 #endif
548
549         /* setup dev_tab for tx channel */
550         auide_init_dbdma_dev( &source_dev_tab,
551                               (u32)DSCR_CMD0_ALWAYS,
552                               8, 32, DEV_FLAGS_OUT | flags);
553         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
554
555         auide_init_dbdma_dev( &source_dev_tab,
556                               (u32)DSCR_CMD0_ALWAYS,
557                               8, 32, DEV_FLAGS_IN | flags);
558         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
559         
560         /* Get a channel for TX */
561         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
562                                                  auide->tx_dev_id,
563                                                  NULL,
564                                                  (void*)auide);
565  
566         /* Get a channel for RX */
567         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
568                                                  DSCR_CMD0_ALWAYS,
569                                                  NULL,
570                                                  (void*)auide);
571  
572         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
573                                                              NUM_DESCRIPTORS);
574         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
575                                                              NUM_DESCRIPTORS);
576  
577         au1xxx_dbdma_start( auide->tx_chan );
578         au1xxx_dbdma_start( auide->rx_chan );
579         
580         return 0;
581 }
582 #endif
583
584 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
585 {
586         int i;
587         unsigned long *ata_regs = hw->io_ports;
588
589         /* FIXME? */
590         for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
591                 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
592         }
593
594         /* set the Alternative Status register */
595         *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
596 }
597
598 static int au_ide_probe(struct device *dev)
599 {
600         struct platform_device *pdev = to_platform_device(dev);
601         _auide_hwif *ahwif = &auide_hwif;
602         ide_hwif_t *hwif;
603         struct resource *res;
604         hw_regs_t *hw;
605         int ret = 0;
606
607 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
608         char *mode = "MWDMA2";
609 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
610         char *mode = "PIO+DDMA(offload)";
611 #endif
612
613         memset(&auide_hwif, 0, sizeof(_auide_hwif));
614         auide_hwif.dev                  = 0;
615
616         ahwif->dev = dev;
617         ahwif->irq = platform_get_irq(pdev, 0);
618
619         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
620
621         if (res == NULL) {
622                 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
623                 ret = -ENODEV;
624                 goto out;
625         }
626         if (ahwif->irq < 0) {
627                 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
628                 ret = -ENODEV;
629                 goto out;
630         }
631
632         if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
633                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
634                 ret =  -EBUSY;
635                 goto out;
636         }
637
638         ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
639         if (ahwif->regbase == 0) {
640                 ret = -ENOMEM;
641                 goto out;
642         }
643
644         /* FIXME:  This might possibly break PCMCIA IDE devices */
645
646         hwif                            = &ide_hwifs[pdev->id];
647         hw                              = &hwif->hw;
648         hwif->irq = hw->irq             = ahwif->irq;
649         hwif->chipset                   = ide_au1xxx;
650
651         auide_setup_ports(hw, ahwif);
652         memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
653
654         hwif->ultra_mask                = 0x0;  /* Disable Ultra DMA */
655 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
656         hwif->mwdma_mask                = 0x07; /* Multimode-2 DMA  */
657         hwif->swdma_mask                = 0x00;
658 #else
659         hwif->mwdma_mask                = 0x0;
660         hwif->swdma_mask                = 0x0;
661 #endif
662
663         hwif->pio_mask = ATA_PIO4;
664         hwif->host_flags = IDE_HFLAG_POST_SET_MODE;
665
666         hwif->noprobe = 0;
667         hwif->drives[0].unmask          = 1;
668         hwif->drives[1].unmask          = 1;
669
670         /* hold should be on in all cases */
671         hwif->hold                      = 1;
672
673         hwif->mmio  = 1;
674
675         /* If the user has selected DDMA assisted copies,
676            then set up a few local I/O function entry points 
677         */
678
679 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA      
680         hwif->INSW                      = auide_insw;
681         hwif->OUTSW                     = auide_outsw;
682 #endif
683
684         hwif->set_pio_mode              = &au1xxx_set_pio_mode;
685         hwif->set_dma_mode              = &auide_set_dma_mode;
686
687 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
688         hwif->dma_off_quietly           = &auide_dma_off_quietly;
689         hwif->dma_timeout               = &auide_dma_timeout;
690
691         hwif->mdma_filter               = &auide_mdma_filter;
692
693         hwif->dma_exec_cmd              = &auide_dma_exec_cmd;
694         hwif->dma_start                 = &auide_dma_start;
695         hwif->ide_dma_end               = &auide_dma_end;
696         hwif->dma_setup                 = &auide_dma_setup;
697         hwif->ide_dma_test_irq          = &auide_dma_test_irq;
698         hwif->dma_host_off              = &auide_dma_host_off;
699         hwif->dma_host_on               = &auide_dma_host_on;
700         hwif->dma_lost_irq              = &auide_dma_lost_irq;
701         hwif->ide_dma_on                = &auide_dma_on;
702
703         hwif->atapi_dma                 = 1;
704
705 #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
706         hwif->channel                   = 0;
707         hwif->hold                      = 1;
708         hwif->select_data               = 0;    /* no chipset-specific code */
709         hwif->config_data               = 0;    /* no chipset-specific code */
710
711         hwif->drives[0].autotune        = 1;    /* 1=autotune, 2=noautotune, 0=default */
712 #endif
713         hwif->drives[0].no_io_32bit     = 1;   
714
715         auide_hwif.hwif                 = hwif;
716         hwif->hwif_data                 = &auide_hwif;
717
718 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA           
719         auide_ddma_init(&auide_hwif);
720         dbdma_init_done = 1;
721 #endif
722
723         probe_hwif_init(hwif);
724
725         ide_proc_register_port(hwif);
726
727         dev_set_drvdata(dev, hwif);
728
729         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
730
731  out:
732         return ret;
733 }
734
735 static int au_ide_remove(struct device *dev)
736 {
737         struct platform_device *pdev = to_platform_device(dev);
738         struct resource *res;
739         ide_hwif_t *hwif = dev_get_drvdata(dev);
740         _auide_hwif *ahwif = &auide_hwif;
741
742         ide_unregister(hwif - ide_hwifs);
743
744         iounmap((void *)ahwif->regbase);
745
746         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
747         release_mem_region(res->start, res->end - res->start);
748
749         return 0;
750 }
751
752 static struct device_driver au1200_ide_driver = {
753         .name           = "au1200-ide",
754         .bus            = &platform_bus_type,
755         .probe          = au_ide_probe,
756         .remove         = au_ide_remove,
757 };
758
759 static int __init au_ide_init(void)
760 {
761         return driver_register(&au1200_ide_driver);
762 }
763
764 static void __exit au_ide_exit(void)
765 {
766         driver_unregister(&au1200_ide_driver);
767 }
768
769 MODULE_LICENSE("GPL");
770 MODULE_DESCRIPTION("AU1200 IDE driver");
771
772 module_init(au_ide_init);
773 module_exit(au_ide_exit);