git.oblomov.eu Git - linux-2.6/blob - drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.51    Jul 27, 2007
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
   7  *
   8  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   9  *  compiled into the kernel if you have more than one card installed.
  10  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  11  *  safe chipset tuning, including this support is harmless
  12  *
  13  *  Promise Ultra66 cards with BIOS v1.11 this
  14  *  compiled into the kernel if you have more than one card installed.
  15  *
  16  *  Promise Ultra100 cards.
  17  *
  18  *  The latest chipset code will support the following ::
  19  *  Three Ultra33 controllers and 12 drives.
  20  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  21  *  The 8/4 ratio is a BIOS code limit by promise.
  22  *
  23  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  24  *
  25  */
  26
  27 /*
  28  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  29  *  Author: Frank Tiernan (frankt@promise.com)
  30  *  Released under terms of General Public License
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/delay.h>
  37 #include <linux/timer.h>
  38 #include <linux/mm.h>
  39 #include <linux/ioport.h>
  40 #include <linux/blkdev.h>
  41 #include <linux/hdreg.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/init.h>
  45 #include <linux/ide.h>
  46
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
  65
  66 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  67 {
  68         ide_hwif_t *hwif        = HWIF(drive);
  69         struct pci_dev *dev     = hwif->pci_dev;
  70         u8 drive_pci            = 0x60 + (drive->dn << 2);
  71
  72         u8                      AP = 0, BP = 0, CP = 0;
  73         u8                      TA = 0, TB = 0, TC = 0;
  74
  75 #if PDC202XX_DEBUG_DRIVE_INFO
  76         u32                     drive_conf = 0;
  77         pci_read_config_dword(dev, drive_pci, &drive_conf);
  78 #endif
  79
  80         /*
  81          * TODO: do this once per channel
  82          */
  83         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
  84                 pdc_old_disable_66MHz_clock(hwif);
  85
  86         pci_read_config_byte(dev, drive_pci,     &AP);
  87         pci_read_config_byte(dev, drive_pci + 1, &BP);
  88         pci_read_config_byte(dev, drive_pci + 2, &CP);
  89
  90         switch(speed) {
  91                 case XFER_UDMA_5:
  92                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  93                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  94                 case XFER_UDMA_3:
  95                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  96                 case XFER_UDMA_0:
  97                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  98                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  99                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
 100                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 101                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 102                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 103                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 104                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 105                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 106                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 107                 case XFER_PIO_0:
 108                 default:                TA = 0x09; TB = 0x13; break;
 109         }
 110
 111         if (speed < XFER_SW_DMA_0) {
 112                 /*
 113                  * preserve SYNC_INT / ERDDY_EN bits while clearing
 114                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
 115                  */
 116                 AP &= ~0x3f;
 117                 if (drive->id->capability & 4)
 118                         AP |= 0x20;     /* set IORDY_EN bit */
 119                 if (drive->media == ide_disk)
 120                         AP |= 0x10;     /* set Prefetch_EN bit */
 121                 /* clear PB[4:0] bits of register B */
 122                 BP &= ~0x1f;
 123                 pci_write_config_byte(dev, drive_pci,     AP | TA);
 124                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 125         } else {
 126                 /* clear MB[2:0] bits of register B */
 127                 BP &= ~0xe0;
 128                 /* clear MC[3:0] bits of register C */
 129                 CP &= ~0x0f;
 130                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 131                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
 132         }
 133
 134 #if PDC202XX_DEBUG_DRIVE_INFO
 135         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 136                 drive->name, ide_xfer_verbose(speed),
 137                 drive->dn, drive_conf);
 138         pci_read_config_dword(dev, drive_pci, &drive_conf);
 139         printk("0x%08x\n", drive_conf);
 140 #endif
 141 }
 142
 143 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 144 {
 145         pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
 146 }
 147
 148 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 149 {
 150         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 151
 152         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 153
 154         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 155 }
 156
 157 /*
 158  * Set the control register to use the 66MHz system
 159  * clock for UDMA 3/4/5 mode operation when necessary.
 160  *
 161  * FIXME: this register is shared by both channels, some locking is needed
 162  *
 163  * It may also be possible to leave the 66MHz clock on
 164  * and readjust the timing parameters.
 165  */
 166 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 167 {
 168         unsigned long clock_reg = hwif->dma_master + 0x11;
 169         u8 clock = inb(clock_reg);
 170
 171         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 172 }
 173
 174 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 175 {
 176         unsigned long clock_reg = hwif->dma_master + 0x11;
 177         u8 clock = inb(clock_reg);
 178
 179         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 180 }
 181
 182 static int pdc202xx_quirkproc (ide_drive_t *drive)
 183 {
 184         const char **list, *model = drive->id->model;
 185
 186         for (list = pdc_quirk_drives; *list != NULL; list++)
 187                 if (strstr(model, *list) != NULL)
 188                         return 2;
 189         return 0;
 190 }
 191
 192 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 193 {
 194         if (drive->current_speed > XFER_UDMA_2)
 195                 pdc_old_enable_66MHz_clock(drive->hwif);
 196         if (drive->media != ide_disk || drive->addressing == 1) {
 197                 struct request *rq      = HWGROUP(drive)->rq;
 198                 ide_hwif_t *hwif        = HWIF(drive);
 199                 unsigned long high_16   = hwif->dma_master;
 200                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 201                 u32 word_count  = 0;
 202                 u8 clock = inb(high_16 + 0x11);
 203
 204                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 205                 word_count = (rq->nr_sectors << 8);
 206                 word_count = (rq_data_dir(rq) == READ) ?
 207                                         word_count | 0x05000000 :
 208                                         word_count | 0x06000000;
 209                 outl(word_count, atapi_reg);
 210         }
 211         ide_dma_start(drive);
 212 }
 213
 214 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 215 {
 216         if (drive->media != ide_disk || drive->addressing == 1) {
 217                 ide_hwif_t *hwif        = HWIF(drive);
 218                 unsigned long high_16   = hwif->dma_master;
 219                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 220                 u8 clock                = 0;
 221
 222                 outl(0, atapi_reg); /* zero out extra */
 223                 clock = inb(high_16 + 0x11);
 224                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 225         }
 226         if (drive->current_speed > XFER_UDMA_2)
 227                 pdc_old_disable_66MHz_clock(drive->hwif);
 228         return __ide_dma_end(drive);
 229 }
 230
 231 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 232 {
 233         ide_hwif_t *hwif        = HWIF(drive);
 234         unsigned long high_16   = hwif->dma_master;
 235         u8 dma_stat             = inb(hwif->dma_status);
 236         u8 sc1d                 = inb(high_16 + 0x001d);
 237
 238         if (hwif->channel) {
 239                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 240                 if ((sc1d & 0x50) == 0x50)
 241                         goto somebody_else;
 242                 else if ((sc1d & 0x40) == 0x40)
 243                         return (dma_stat & 4) == 4;
 244         } else {
 245                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 246                 if ((sc1d & 0x05) == 0x05)
 247                         goto somebody_else;
 248                 else if ((sc1d & 0x04) == 0x04)
 249                         return (dma_stat & 4) == 4;
 250         }
 251 somebody_else:
 252         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 253 }
 254
 255 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
 256 {
 257         ide_hwif_t *hwif = HWIF(drive);
 258
 259         if (hwif->resetproc != NULL)
 260                 hwif->resetproc(drive);
 261
 262         ide_dma_lost_irq(drive);
 263 }
 264
 265 static void pdc202xx_dma_timeout(ide_drive_t *drive)
 266 {
 267         ide_hwif_t *hwif = HWIF(drive);
 268
 269         if (hwif->resetproc != NULL)
 270                 hwif->resetproc(drive);
 271
 272         ide_dma_timeout(drive);
 273 }
 274
 275 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 276 {
 277         unsigned long high_16   = hwif->dma_master;
 278         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 279
 280         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 281         mdelay(100);
 282         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 283         mdelay(2000);   /* 2 seconds ?! */
 284
 285         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 286                 hwif->channel ? "Secondary" : "Primary");
 287 }
 288
 289 static void pdc202xx_reset (ide_drive_t *drive)
 290 {
 291         ide_hwif_t *hwif        = HWIF(drive);
 292         ide_hwif_t *mate        = hwif->mate;
 293
 294         pdc202xx_reset_host(hwif);
 295         pdc202xx_reset_host(mate);
 296
 297         ide_set_max_pio(drive);
 298 }
 299
 300 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 301                                                         const char *name)
 302 {
 303         return dev->irq;
 304 }
 305
 306 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 307 {
 308         struct pci_dev *dev = hwif->pci_dev;
 309
 310         /* PDC20265 has problems with large LBA48 requests */
 311         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 312             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 313                 hwif->rqsize = 256;
 314
 315         hwif->set_pio_mode = &pdc202xx_set_pio_mode;
 316         hwif->set_dma_mode = &pdc202xx_set_mode;
 317
 318         hwif->quirkproc = &pdc202xx_quirkproc;
 319
 320         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 321                 hwif->resetproc = &pdc202xx_reset;
 322
 323         hwif->err_stops_fifo = 1;
 324
 325         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 326
 327         if (hwif->dma_base == 0)
 328                 return;
 329
 330         hwif->ultra_mask = hwif->cds->udma_mask;
 331         hwif->mwdma_mask = 0x07;
 332         hwif->swdma_mask = 0x07;
 333         hwif->atapi_dma = 1;
 334
 335         hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
 336         hwif->dma_timeout = &pdc202xx_dma_timeout;
 337
 338         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 339                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 340                         hwif->cbl = pdc202xx_old_cable_detect(hwif);
 341
 342                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 343                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 344         }
 345         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 346 }
 347
 348 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 349 {
 350         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 351
 352         if (hwif->channel) {
 353                 ide_setup_dma(hwif, dmabase, 8);
 354                 return;
 355         }
 356
 357         udma_speed_flag = inb(dmabase | 0x1f);
 358         primary_mode    = inb(dmabase | 0x1a);
 359         secondary_mode  = inb(dmabase | 0x1b);
 360         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 361                 "Primary %s Mode " \
 362                 "Secondary %s Mode.\n", hwif->cds->name,
 363                 (udma_speed_flag & 1) ? "EN" : "DIS",
 364                 (primary_mode & 1) ? "MASTER" : "PCI",
 365                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 366
 367 #ifdef CONFIG_PDC202XX_BURST
 368         if (!(udma_speed_flag & 1)) {
 369                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 370                         hwif->cds->name, udma_speed_flag,
 371                         (udma_speed_flag|1));
 372                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 373                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 374         }
 375 #endif /* CONFIG_PDC202XX_BURST */
 376
 377         ide_setup_dma(hwif, dmabase, 8);
 378 }
 379
 380 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 381                                            ide_pci_device_t *d)
 382 {
 383         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 384                 u8 irq = 0, irq2 = 0;
 385                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 386                 /* 0xbc */
 387                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 388                 if (irq != irq2) {
 389                         pci_write_config_byte(dev,
 390                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 391                         printk(KERN_INFO "%s: pci-config space interrupt "
 392                                 "mirror fixed.\n", d->name);
 393                 }
 394         }
 395         return ide_setup_pci_device(dev, d);
 396 }
 397
 398 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 399                                          ide_pci_device_t *d)
 400 {
 401         if ((dev->bus->self) &&
 402             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 403             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 404              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 405                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 406                         "attached to I2O RAID controller.\n");
 407                 return -ENODEV;
 408         }
 409         return ide_setup_pci_device(dev, d);
 410 }
 411
 412 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 413                                          ide_pci_device_t *d)
 414 {
 415         return ide_setup_pci_device(dev, d);
 416 }
 417
 418 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 419         {       /* 0 */
 420                 .name           = "PDC20246",
 421                 .init_setup     = init_setup_pdc202ata4,
 422                 .init_chipset   = init_chipset_pdc202xx,
 423                 .init_hwif      = init_hwif_pdc202xx,
 424                 .init_dma       = init_dma_pdc202xx,
 425                 .autodma        = AUTODMA,
 426                 .bootable       = OFF_BOARD,
 427                 .extra          = 16,
 428                 .pio_mask       = ATA_PIO4,
 429                 .udma_mask      = 0x07, /* udma0-2 */
 430         },{     /* 1 */
 431                 .name           = "PDC20262",
 432                 .init_setup     = init_setup_pdc202ata4,
 433                 .init_chipset   = init_chipset_pdc202xx,
 434                 .init_hwif      = init_hwif_pdc202xx,
 435                 .init_dma       = init_dma_pdc202xx,
 436                 .autodma        = AUTODMA,
 437                 .bootable       = OFF_BOARD,
 438                 .extra          = 48,
 439                 .pio_mask       = ATA_PIO4,
 440                 .udma_mask      = 0x1f, /* udma0-4 */
 441         },{     /* 2 */
 442                 .name           = "PDC20263",
 443                 .init_setup     = init_setup_pdc202ata4,
 444                 .init_chipset   = init_chipset_pdc202xx,
 445                 .init_hwif      = init_hwif_pdc202xx,
 446                 .init_dma       = init_dma_pdc202xx,
 447                 .autodma        = AUTODMA,
 448                 .bootable       = OFF_BOARD,
 449                 .extra          = 48,
 450                 .pio_mask       = ATA_PIO4,
 451                 .udma_mask      = 0x1f, /* udma0-4 */
 452         },{     /* 3 */
 453                 .name           = "PDC20265",
 454                 .init_setup     = init_setup_pdc20265,
 455                 .init_chipset   = init_chipset_pdc202xx,
 456                 .init_hwif      = init_hwif_pdc202xx,
 457                 .init_dma       = init_dma_pdc202xx,
 458                 .autodma        = AUTODMA,
 459                 .bootable       = OFF_BOARD,
 460                 .extra          = 48,
 461                 .pio_mask       = ATA_PIO4,
 462                 .udma_mask      = 0x3f, /* udma0-5 */
 463         },{     /* 4 */
 464                 .name           = "PDC20267",
 465                 .init_setup     = init_setup_pdc202xx,
 466                 .init_chipset   = init_chipset_pdc202xx,
 467                 .init_hwif      = init_hwif_pdc202xx,
 468                 .init_dma       = init_dma_pdc202xx,
 469                 .autodma        = AUTODMA,
 470                 .bootable       = OFF_BOARD,
 471                 .extra          = 48,
 472                 .pio_mask       = ATA_PIO4,
 473                 .udma_mask      = 0x3f, /* udma0-5 */
 474         }
 475 };
 476
 477 /**
 478  *      pdc202xx_init_one       -       called when a PDC202xx is found
 479  *      @dev: the pdc202xx device
 480  *      @id: the matching pci id
 481  *
 482  *      Called when the PCI registration layer (or the IDE initialization)
 483  *      finds a device matching our IDE device tables.
 484  */
 485
 486 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 487 {
 488         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 489
 490         return d->init_setup(dev, d);
 491 }
 492
 493 static const struct pci_device_id pdc202xx_pci_tbl[] = {
 494         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
 495         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
 496         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
 497         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
 498         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
 499         { 0, },
 500 };
 501 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 502
 503 static struct pci_driver driver = {
 504         .name           = "Promise_Old_IDE",
 505         .id_table       = pdc202xx_pci_tbl,
 506         .probe          = pdc202xx_init_one,
 507 };
 508
 509 static int __init pdc202xx_ide_init(void)
 510 {
 511         return ide_pci_register_driver(&driver);
 512 }
 513
 514 module_init(pdc202xx_ide_init);
 515
 516 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 517 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 518 MODULE_LICENSE("GPL");