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   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/smp_lock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/cache.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/profile.h>
  24 #include <linux/bootmem.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/ptrace.h>
  28 #include <asm/atomic.h>
  29 #include <asm/tlbflush.h>
  30 #include <asm/mmu_context.h>
  31 #include <asm/cpudata.h>
  32
  33 #include <asm/irq.h>
  34 #include <asm/page.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/oplib.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/timer.h>
  39 #include <asm/starfire.h>
  40 #include <asm/tlb.h>
  41 #include <asm/sections.h>
  42
  43 extern void calibrate_delay(void);
  44
  45 /* Please don't make this stuff initdata!!!  --DaveM */
  46 static unsigned char boot_cpu_id;
  47
  48 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
  49 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
  50 static cpumask_t smp_commenced_mask;
  51 static cpumask_t cpu_callout_map;
  52
  53 void smp_info(struct seq_file *m)
  54 {
  55         int i;
  56
  57         seq_printf(m, "State:\n");
  58         for (i = 0; i < NR_CPUS; i++) {
  59                 if (cpu_online(i))
  60                         seq_printf(m,
  61                                    "CPU%d:\t\tonline\n", i);
  62         }
  63 }
  64
  65 void smp_bogo(struct seq_file *m)
  66 {
  67         int i;
  68
  69         for (i = 0; i < NR_CPUS; i++)
  70                 if (cpu_online(i))
  71                         seq_printf(m,
  72                                    "Cpu%dBogo\t: %lu.%02lu\n"
  73                                    "Cpu%dClkTck\t: %016lx\n",
  74                                    i, cpu_data(i).udelay_val / (500000/HZ),
  75                                    (cpu_data(i).udelay_val / (5000/HZ)) % 100,
  76                                    i, cpu_data(i).clock_tick);
  77 }
  78
  79 void __init smp_store_cpu_info(int id)
  80 {
  81         int cpu_node;
  82
  83         /* multiplier and counter set by
  84            smp_setup_percpu_timer()  */
  85         cpu_data(id).udelay_val                 = loops_per_jiffy;
  86
  87         cpu_find_by_mid(id, &cpu_node);
  88         cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
  89                                                      "clock-frequency", 0);
  90
  91         cpu_data(id).idle_volume                = 1;
  92
  93         cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
  94                                                       16 * 1024);
  95         cpu_data(id).dcache_line_size =
  96                 prom_getintdefault(cpu_node, "dcache-line-size", 32);
  97         cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
  98                                                       16 * 1024);
  99         cpu_data(id).icache_line_size =
 100                 prom_getintdefault(cpu_node, "icache-line-size", 32);
 101         cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
 102                                                       4 * 1024 * 1024);
 103         cpu_data(id).ecache_line_size =
 104                 prom_getintdefault(cpu_node, "ecache-line-size", 64);
 105         printk("CPU[%d]: Caches "
 106                "D[sz(%d):line_sz(%d)] "
 107                "I[sz(%d):line_sz(%d)] "
 108                "E[sz(%d):line_sz(%d)]\n",
 109                id,
 110                cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
 111                cpu_data(id).icache_size, cpu_data(id).icache_line_size,
 112                cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
 113 }
 114
 115 static void smp_setup_percpu_timer(void);
 116
 117 static volatile unsigned long callin_flag = 0;
 118
 119 void __init smp_callin(void)
 120 {
 121         int cpuid = hard_smp_processor_id();
 122
 123         __local_per_cpu_offset = __per_cpu_offset(cpuid);
 124
 125         __flush_tlb_all();
 126
 127         smp_setup_percpu_timer();
 128
 129         if (cheetah_pcache_forced_on)
 130                 cheetah_enable_pcache();
 131
 132         local_irq_enable();
 133
 134         calibrate_delay();
 135         smp_store_cpu_info(cpuid);
 136         callin_flag = 1;
 137         __asm__ __volatile__("membar #Sync\n\t"
 138                              "flush  %%g6" : : : "memory");
 139
 140         /* Clear this or we will die instantly when we
 141          * schedule back to this idler...
 142          */
 143         current_thread_info()->new_child = 0;
 144
 145         /* Attach to the address space of init_task. */
 146         atomic_inc(&init_mm.mm_count);
 147         current->active_mm = &init_mm;
 148
 149         while (!cpu_isset(cpuid, smp_commenced_mask))
 150                 rmb();
 151
 152         cpu_set(cpuid, cpu_online_map);
 153
 154         /* idle thread is expected to have preempt disabled */
 155         preempt_disable();
 156 }
 157
 158 void cpu_panic(void)
 159 {
 160         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 161         panic("SMP bolixed\n");
 162 }
 163
 164 static unsigned long current_tick_offset __read_mostly;
 165
 166 /* This tick register synchronization scheme is taken entirely from
 167  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 168  *
 169  * The only change I've made is to rework it so that the master
 170  * initiates the synchonization instead of the slave. -DaveM
 171  */
 172
 173 #define MASTER  0
 174 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 175
 176 #define NUM_ROUNDS      64      /* magic value */
 177 #define NUM_ITERS       5       /* likewise */
 178
 179 static DEFINE_SPINLOCK(itc_sync_lock);
 180 static unsigned long go[SLAVE + 1];
 181
 182 #define DEBUG_TICK_SYNC 0
 183
 184 static inline long get_delta (long *rt, long *master)
 185 {
 186         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 187         unsigned long tcenter, t0, t1, tm;
 188         unsigned long i;
 189
 190         for (i = 0; i < NUM_ITERS; i++) {
 191                 t0 = tick_ops->get_tick();
 192                 go[MASTER] = 1;
 193                 membar_storeload();
 194                 while (!(tm = go[SLAVE]))
 195                         rmb();
 196                 go[SLAVE] = 0;
 197                 wmb();
 198                 t1 = tick_ops->get_tick();
 199
 200                 if (t1 - t0 < best_t1 - best_t0)
 201                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 202         }
 203
 204         *rt = best_t1 - best_t0;
 205         *master = best_tm - best_t0;
 206
 207         /* average best_t0 and best_t1 without overflow: */
 208         tcenter = (best_t0/2 + best_t1/2);
 209         if (best_t0 % 2 + best_t1 % 2 == 2)
 210                 tcenter++;
 211         return tcenter - best_tm;
 212 }
 213
 214 void smp_synchronize_tick_client(void)
 215 {
 216         long i, delta, adj, adjust_latency = 0, done = 0;
 217         unsigned long flags, rt, master_time_stamp, bound;
 218 #if DEBUG_TICK_SYNC
 219         struct {
 220                 long rt;        /* roundtrip time */
 221                 long master;    /* master's timestamp */
 222                 long diff;      /* difference between midpoint and master's timestamp */
 223                 long lat;       /* estimate of itc adjustment latency */
 224         } t[NUM_ROUNDS];
 225 #endif
 226
 227         go[MASTER] = 1;
 228
 229         while (go[MASTER])
 230                 rmb();
 231
 232         local_irq_save(flags);
 233         {
 234                 for (i = 0; i < NUM_ROUNDS; i++) {
 235                         delta = get_delta(&rt, &master_time_stamp);
 236                         if (delta == 0) {
 237                                 done = 1;       /* let's lock on to this... */
 238                                 bound = rt;
 239                         }
 240
 241                         if (!done) {
 242                                 if (i > 0) {
 243                                         adjust_latency += -delta;
 244                                         adj = -delta + adjust_latency/4;
 245                                 } else
 246                                         adj = -delta;
 247
 248                                 tick_ops->add_tick(adj, current_tick_offset);
 249                         }
 250 #if DEBUG_TICK_SYNC
 251                         t[i].rt = rt;
 252                         t[i].master = master_time_stamp;
 253                         t[i].diff = delta;
 254                         t[i].lat = adjust_latency/4;
 255 #endif
 256                 }
 257         }
 258         local_irq_restore(flags);
 259
 260 #if DEBUG_TICK_SYNC
 261         for (i = 0; i < NUM_ROUNDS; i++)
 262                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 263                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 264 #endif
 265
 266         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
 267                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
 268 }
 269
 270 static void smp_start_sync_tick_client(int cpu);
 271
 272 static void smp_synchronize_one_tick(int cpu)
 273 {
 274         unsigned long flags, i;
 275
 276         go[MASTER] = 0;
 277
 278         smp_start_sync_tick_client(cpu);
 279
 280         /* wait for client to be ready */
 281         while (!go[MASTER])
 282                 rmb();
 283
 284         /* now let the client proceed into his loop */
 285         go[MASTER] = 0;
 286         membar_storeload();
 287
 288         spin_lock_irqsave(&itc_sync_lock, flags);
 289         {
 290                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 291                         while (!go[MASTER])
 292                                 rmb();
 293                         go[MASTER] = 0;
 294                         wmb();
 295                         go[SLAVE] = tick_ops->get_tick();
 296                         membar_storeload();
 297                 }
 298         }
 299         spin_unlock_irqrestore(&itc_sync_lock, flags);
 300 }
 301
 302 extern unsigned long sparc64_cpu_startup;
 303
 304 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 305  * 32-bits (I think) so to be safe we have it read the pointer
 306  * contained here so we work on >4GB machines. -DaveM
 307  */
 308 static struct thread_info *cpu_new_thread = NULL;
 309
 310 static int __devinit smp_boot_one_cpu(unsigned int cpu)
 311 {
 312         unsigned long entry =
 313                 (unsigned long)(&sparc64_cpu_startup);
 314         unsigned long cookie =
 315                 (unsigned long)(&cpu_new_thread);
 316         struct task_struct *p;
 317         int timeout, ret, cpu_node;
 318
 319         p = fork_idle(cpu);
 320         callin_flag = 0;
 321         cpu_new_thread = task_thread_info(p);
 322         cpu_set(cpu, cpu_callout_map);
 323
 324         cpu_find_by_mid(cpu, &cpu_node);
 325         prom_startcpu(cpu_node, entry, cookie);
 326
 327         for (timeout = 0; timeout < 5000000; timeout++) {
 328                 if (callin_flag)
 329                         break;
 330                 udelay(100);
 331         }
 332         if (callin_flag) {
 333                 ret = 0;
 334         } else {
 335                 printk("Processor %d is stuck.\n", cpu);
 336                 cpu_clear(cpu, cpu_callout_map);
 337                 ret = -ENODEV;
 338         }
 339         cpu_new_thread = NULL;
 340
 341         return ret;
 342 }
 343
 344 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 345 {
 346         u64 result, target;
 347         int stuck, tmp;
 348
 349         if (this_is_starfire) {
 350                 /* map to real upaid */
 351                 cpu = (((cpu & 0x3c) << 1) |
 352                         ((cpu & 0x40) >> 4) |
 353                         (cpu & 0x3));
 354         }
 355
 356         target = (cpu << 14) | 0x70;
 357 again:
 358         /* Ok, this is the real Spitfire Errata #54.
 359          * One must read back from a UDB internal register
 360          * after writes to the UDB interrupt dispatch, but
 361          * before the membar Sync for that write.
 362          * So we use the high UDB control register (ASI 0x7f,
 363          * ADDR 0x20) for the dummy read. -DaveM
 364          */
 365         tmp = 0x40;
 366         __asm__ __volatile__(
 367         "wrpr   %1, %2, %%pstate\n\t"
 368         "stxa   %4, [%0] %3\n\t"
 369         "stxa   %5, [%0+%8] %3\n\t"
 370         "add    %0, %8, %0\n\t"
 371         "stxa   %6, [%0+%8] %3\n\t"
 372         "membar #Sync\n\t"
 373         "stxa   %%g0, [%7] %3\n\t"
 374         "membar #Sync\n\t"
 375         "mov    0x20, %%g1\n\t"
 376         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 377         "membar #Sync"
 378         : "=r" (tmp)
 379         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 380           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 381           "r" (0x10), "0" (tmp)
 382         : "g1");
 383
 384         /* NOTE: PSTATE_IE is still clear. */
 385         stuck = 100000;
 386         do {
 387                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 388                         : "=r" (result)
 389                         : "i" (ASI_INTR_DISPATCH_STAT));
 390                 if (result == 0) {
 391                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 392                                              : : "r" (pstate));
 393                         return;
 394                 }
 395                 stuck -= 1;
 396                 if (stuck == 0)
 397                         break;
 398         } while (result & 0x1);
 399         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 400                              : : "r" (pstate));
 401         if (stuck == 0) {
 402                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 403                        smp_processor_id(), result);
 404         } else {
 405                 udelay(2);
 406                 goto again;
 407         }
 408 }
 409
 410 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 411 {
 412         u64 pstate;
 413         int i;
 414
 415         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 416         for_each_cpu_mask(i, mask)
 417                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
 418 }
 419
 420 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 421  * packet, but we have no use for that.  However we do take advantage of
 422  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 423  */
 424 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 425 {
 426         u64 pstate, ver;
 427         int nack_busy_id, is_jalapeno;
 428
 429         if (cpus_empty(mask))
 430                 return;
 431
 432         /* Unfortunately, someone at Sun had the brilliant idea to make the
 433          * busy/nack fields hard-coded by ITID number for this Ultra-III
 434          * derivative processor.
 435          */
 436         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 437         is_jalapeno = ((ver >> 32) == 0x003e0016);
 438
 439         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 440
 441 retry:
 442         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 443                              : : "r" (pstate), "i" (PSTATE_IE));
 444
 445         /* Setup the dispatch data registers. */
 446         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 447                              "stxa      %1, [%4] %6\n\t"
 448                              "stxa      %2, [%5] %6\n\t"
 449                              "membar    #Sync\n\t"
 450                              : /* no outputs */
 451                              : "r" (data0), "r" (data1), "r" (data2),
 452                                "r" (0x40), "r" (0x50), "r" (0x60),
 453                                "i" (ASI_INTR_W));
 454
 455         nack_busy_id = 0;
 456         {
 457                 int i;
 458
 459                 for_each_cpu_mask(i, mask) {
 460                         u64 target = (i << 14) | 0x70;
 461
 462                         if (!is_jalapeno)
 463                                 target |= (nack_busy_id << 24);
 464                         __asm__ __volatile__(
 465                                 "stxa   %%g0, [%0] %1\n\t"
 466                                 "membar #Sync\n\t"
 467                                 : /* no outputs */
 468                                 : "r" (target), "i" (ASI_INTR_W));
 469                         nack_busy_id++;
 470                 }
 471         }
 472
 473         /* Now, poll for completion. */
 474         {
 475                 u64 dispatch_stat;
 476                 long stuck;
 477
 478                 stuck = 100000 * nack_busy_id;
 479                 do {
 480                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 481                                              : "=r" (dispatch_stat)
 482                                              : "i" (ASI_INTR_DISPATCH_STAT));
 483                         if (dispatch_stat == 0UL) {
 484                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 485                                                      : : "r" (pstate));
 486                                 return;
 487                         }
 488                         if (!--stuck)
 489                                 break;
 490                 } while (dispatch_stat & 0x5555555555555555UL);
 491
 492                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 493                                      : : "r" (pstate));
 494
 495                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
 496                         /* Busy bits will not clear, continue instead
 497                          * of freezing up on this cpu.
 498                          */
 499                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 500                                smp_processor_id(), dispatch_stat);
 501                 } else {
 502                         int i, this_busy_nack = 0;
 503
 504                         /* Delay some random time with interrupts enabled
 505                          * to prevent deadlock.
 506                          */
 507                         udelay(2 * nack_busy_id);
 508
 509                         /* Clear out the mask bits for cpus which did not
 510                          * NACK us.
 511                          */
 512                         for_each_cpu_mask(i, mask) {
 513                                 u64 check_mask;
 514
 515                                 if (is_jalapeno)
 516                                         check_mask = (0x2UL << (2*i));
 517                                 else
 518                                         check_mask = (0x2UL <<
 519                                                       this_busy_nack);
 520                                 if ((dispatch_stat & check_mask) == 0)
 521                                         cpu_clear(i, mask);
 522                                 this_busy_nack += 2;
 523                         }
 524
 525                         goto retry;
 526                 }
 527         }
 528 }
 529
 530 /* Send cross call to all processors mentioned in MASK
 531  * except self.
 532  */
 533 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
 534 {
 535         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 536         int this_cpu = get_cpu();
 537
 538         cpus_and(mask, mask, cpu_online_map);
 539         cpu_clear(this_cpu, mask);
 540
 541         if (tlb_type == spitfire)
 542                 spitfire_xcall_deliver(data0, data1, data2, mask);
 543         else
 544                 cheetah_xcall_deliver(data0, data1, data2, mask);
 545         /* NOTE: Caller runs local copy on master. */
 546
 547         put_cpu();
 548 }
 549
 550 extern unsigned long xcall_sync_tick;
 551
 552 static void smp_start_sync_tick_client(int cpu)
 553 {
 554         cpumask_t mask = cpumask_of_cpu(cpu);
 555
 556         smp_cross_call_masked(&xcall_sync_tick,
 557                               0, 0, 0, mask);
 558 }
 559
 560 /* Send cross call to all processors except self. */
 561 #define smp_cross_call(func, ctx, data1, data2) \
 562         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
 563
 564 struct call_data_struct {
 565         void (*func) (void *info);
 566         void *info;
 567         atomic_t finished;
 568         int wait;
 569 };
 570
 571 static DEFINE_SPINLOCK(call_lock);
 572 static struct call_data_struct *call_data;
 573
 574 extern unsigned long xcall_call_function;
 575
 576 /*
 577  * You must not call this function with disabled interrupts or from a
 578  * hardware interrupt handler or from a bottom half handler.
 579  */
 580 static int smp_call_function_mask(void (*func)(void *info), void *info,
 581                                   int nonatomic, int wait, cpumask_t mask)
 582 {
 583         struct call_data_struct data;
 584         int cpus = cpus_weight(mask) - 1;
 585         long timeout;
 586
 587         if (!cpus)
 588                 return 0;
 589
 590         /* Can deadlock when called with interrupts disabled */
 591         WARN_ON(irqs_disabled());
 592
 593         data.func = func;
 594         data.info = info;
 595         atomic_set(&data.finished, 0);
 596         data.wait = wait;
 597
 598         spin_lock(&call_lock);
 599
 600         call_data = &data;
 601
 602         smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
 603
 604         /*
 605          * Wait for other cpus to complete function or at
 606          * least snap the call data.
 607          */
 608         timeout = 1000000;
 609         while (atomic_read(&data.finished) != cpus) {
 610                 if (--timeout <= 0)
 611                         goto out_timeout;
 612                 barrier();
 613                 udelay(1);
 614         }
 615
 616         spin_unlock(&call_lock);
 617
 618         return 0;
 619
 620 out_timeout:
 621         spin_unlock(&call_lock);
 622         printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
 623                (long) num_online_cpus() - 1L,
 624                (long) atomic_read(&data.finished));
 625         return 0;
 626 }
 627
 628 int smp_call_function(void (*func)(void *info), void *info,
 629                       int nonatomic, int wait)
 630 {
 631         return smp_call_function_mask(func, info, nonatomic, wait,
 632                                       cpu_online_map);
 633 }
 634
 635 void smp_call_function_client(int irq, struct pt_regs *regs)
 636 {
 637         void (*func) (void *info) = call_data->func;
 638         void *info = call_data->info;
 639
 640         clear_softint(1 << irq);
 641         if (call_data->wait) {
 642                 /* let initiator proceed only after completion */
 643                 func(info);
 644                 atomic_inc(&call_data->finished);
 645         } else {
 646                 /* let initiator proceed after getting data */
 647                 atomic_inc(&call_data->finished);
 648                 func(info);
 649         }
 650 }
 651
 652 static void tsb_sync(void *info)
 653 {
 654         struct mm_struct *mm = info;
 655
 656         if (current->active_mm == mm)
 657                 tsb_context_switch(mm);
 658 }
 659
 660 void smp_tsb_sync(struct mm_struct *mm)
 661 {
 662         smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
 663 }
 664
 665 extern unsigned long xcall_flush_tlb_mm;
 666 extern unsigned long xcall_flush_tlb_pending;
 667 extern unsigned long xcall_flush_tlb_kernel_range;
 668 extern unsigned long xcall_report_regs;
 669 extern unsigned long xcall_receive_signal;
 670
 671 #ifdef DCACHE_ALIASING_POSSIBLE
 672 extern unsigned long xcall_flush_dcache_page_cheetah;
 673 #endif
 674 extern unsigned long xcall_flush_dcache_page_spitfire;
 675
 676 #ifdef CONFIG_DEBUG_DCFLUSH
 677 extern atomic_t dcpage_flushes;
 678 extern atomic_t dcpage_flushes_xcall;
 679 #endif
 680
 681 static __inline__ void __local_flush_dcache_page(struct page *page)
 682 {
 683 #ifdef DCACHE_ALIASING_POSSIBLE
 684         __flush_dcache_page(page_address(page),
 685                             ((tlb_type == spitfire) &&
 686                              page_mapping(page) != NULL));
 687 #else
 688         if (page_mapping(page) != NULL &&
 689             tlb_type == spitfire)
 690                 __flush_icache_page(__pa(page_address(page)));
 691 #endif
 692 }
 693
 694 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 695 {
 696         cpumask_t mask = cpumask_of_cpu(cpu);
 697         int this_cpu = get_cpu();
 698
 699 #ifdef CONFIG_DEBUG_DCFLUSH
 700         atomic_inc(&dcpage_flushes);
 701 #endif
 702         if (cpu == this_cpu) {
 703                 __local_flush_dcache_page(page);
 704         } else if (cpu_online(cpu)) {
 705                 void *pg_addr = page_address(page);
 706                 u64 data0;
 707
 708                 if (tlb_type == spitfire) {
 709                         data0 =
 710                                 ((u64)&xcall_flush_dcache_page_spitfire);
 711                         if (page_mapping(page) != NULL)
 712                                 data0 |= ((u64)1 << 32);
 713                         spitfire_xcall_deliver(data0,
 714                                                __pa(pg_addr),
 715                                                (u64) pg_addr,
 716                                                mask);
 717                 } else {
 718 #ifdef DCACHE_ALIASING_POSSIBLE
 719                         data0 =
 720                                 ((u64)&xcall_flush_dcache_page_cheetah);
 721                         cheetah_xcall_deliver(data0,
 722                                               __pa(pg_addr),
 723                                               0, mask);
 724 #endif
 725                 }
 726 #ifdef CONFIG_DEBUG_DCFLUSH
 727                 atomic_inc(&dcpage_flushes_xcall);
 728 #endif
 729         }
 730
 731         put_cpu();
 732 }
 733
 734 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 735 {
 736         void *pg_addr = page_address(page);
 737         cpumask_t mask = cpu_online_map;
 738         u64 data0;
 739         int this_cpu = get_cpu();
 740
 741         cpu_clear(this_cpu, mask);
 742
 743 #ifdef CONFIG_DEBUG_DCFLUSH
 744         atomic_inc(&dcpage_flushes);
 745 #endif
 746         if (cpus_empty(mask))
 747                 goto flush_self;
 748         if (tlb_type == spitfire) {
 749                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 750                 if (page_mapping(page) != NULL)
 751                         data0 |= ((u64)1 << 32);
 752                 spitfire_xcall_deliver(data0,
 753                                        __pa(pg_addr),
 754                                        (u64) pg_addr,
 755                                        mask);
 756         } else {
 757 #ifdef DCACHE_ALIASING_POSSIBLE
 758                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 759                 cheetah_xcall_deliver(data0,
 760                                       __pa(pg_addr),
 761                                       0, mask);
 762 #endif
 763         }
 764 #ifdef CONFIG_DEBUG_DCFLUSH
 765         atomic_inc(&dcpage_flushes_xcall);
 766 #endif
 767  flush_self:
 768         __local_flush_dcache_page(page);
 769
 770         put_cpu();
 771 }
 772
 773 void smp_receive_signal(int cpu)
 774 {
 775         cpumask_t mask = cpumask_of_cpu(cpu);
 776
 777         if (cpu_online(cpu)) {
 778                 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
 779
 780                 if (tlb_type == spitfire)
 781                         spitfire_xcall_deliver(data0, 0, 0, mask);
 782                 else
 783                         cheetah_xcall_deliver(data0, 0, 0, mask);
 784         }
 785 }
 786
 787 void smp_receive_signal_client(int irq, struct pt_regs *regs)
 788 {
 789         /* Just return, rtrap takes care of the rest. */
 790         clear_softint(1 << irq);
 791 }
 792
 793 void smp_report_regs(void)
 794 {
 795         smp_cross_call(&xcall_report_regs, 0, 0, 0);
 796 }
 797
 798 /* We know that the window frames of the user have been flushed
 799  * to the stack before we get here because all callers of us
 800  * are flush_tlb_*() routines, and these run after flush_cache_*()
 801  * which performs the flushw.
 802  *
 803  * The SMP TLB coherency scheme we use works as follows:
 804  *
 805  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
 806  *    space has (potentially) executed on, this is the heuristic
 807  *    we use to avoid doing cross calls.
 808  *
 809  *    Also, for flushing from kswapd and also for clones, we
 810  *    use cpu_vm_mask as the list of cpus to make run the TLB.
 811  *
 812  * 2) TLB context numbers are shared globally across all processors
 813  *    in the system, this allows us to play several games to avoid
 814  *    cross calls.
 815  *
 816  *    One invariant is that when a cpu switches to a process, and
 817  *    that processes tsk->active_mm->cpu_vm_mask does not have the
 818  *    current cpu's bit set, that tlb context is flushed locally.
 819  *
 820  *    If the address space is non-shared (ie. mm->count == 1) we avoid
 821  *    cross calls when we want to flush the currently running process's
 822  *    tlb state.  This is done by clearing all cpu bits except the current
 823  *    processor's in current->active_mm->cpu_vm_mask and performing the
 824  *    flush locally only.  This will force any subsequent cpus which run
 825  *    this task to flush the context from the local tlb if the process
 826  *    migrates to another cpu (again).
 827  *
 828  * 3) For shared address spaces (threads) and swapping we bite the
 829  *    bullet for most cases and perform the cross call (but only to
 830  *    the cpus listed in cpu_vm_mask).
 831  *
 832  *    The performance gain from "optimizing" away the cross call for threads is
 833  *    questionable (in theory the big win for threads is the massive sharing of
 834  *    address space state across processors).
 835  */
 836
 837 /* This currently is only used by the hugetlb arch pre-fault
 838  * hook on UltraSPARC-III+ and later when changing the pagesize
 839  * bits of the context register for an address space.
 840  */
 841 void smp_flush_tlb_mm(struct mm_struct *mm)
 842 {
 843         u32 ctx = CTX_HWBITS(mm->context);
 844         int cpu = get_cpu();
 845
 846         if (atomic_read(&mm->mm_users) == 1) {
 847                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
 848                 goto local_flush_and_out;
 849         }
 850
 851         smp_cross_call_masked(&xcall_flush_tlb_mm,
 852                               ctx, 0, 0,
 853                               mm->cpu_vm_mask);
 854
 855 local_flush_and_out:
 856         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
 857
 858         put_cpu();
 859 }
 860
 861 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
 862 {
 863         u32 ctx = CTX_HWBITS(mm->context);
 864         int cpu = get_cpu();
 865
 866         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
 867                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
 868         else
 869                 smp_cross_call_masked(&xcall_flush_tlb_pending,
 870                                       ctx, nr, (unsigned long) vaddrs,
 871                                       mm->cpu_vm_mask);
 872
 873         __flush_tlb_pending(ctx, nr, vaddrs);
 874
 875         put_cpu();
 876 }
 877
 878 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
 879 {
 880         start &= PAGE_MASK;
 881         end    = PAGE_ALIGN(end);
 882         if (start != end) {
 883                 smp_cross_call(&xcall_flush_tlb_kernel_range,
 884                                0, start, end);
 885
 886                 __flush_tlb_kernel_range(start, end);
 887         }
 888 }
 889
 890 /* CPU capture. */
 891 /* #define CAPTURE_DEBUG */
 892 extern unsigned long xcall_capture;
 893
 894 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
 895 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
 896 static unsigned long penguins_are_doing_time;
 897
 898 void smp_capture(void)
 899 {
 900         int result = atomic_add_ret(1, &smp_capture_depth);
 901
 902         if (result == 1) {
 903                 int ncpus = num_online_cpus();
 904
 905 #ifdef CAPTURE_DEBUG
 906                 printk("CPU[%d]: Sending penguins to jail...",
 907                        smp_processor_id());
 908 #endif
 909                 penguins_are_doing_time = 1;
 910                 membar_storestore_loadstore();
 911                 atomic_inc(&smp_capture_registry);
 912                 smp_cross_call(&xcall_capture, 0, 0, 0);
 913                 while (atomic_read(&smp_capture_registry) != ncpus)
 914                         rmb();
 915 #ifdef CAPTURE_DEBUG
 916                 printk("done\n");
 917 #endif
 918         }
 919 }
 920
 921 void smp_release(void)
 922 {
 923         if (atomic_dec_and_test(&smp_capture_depth)) {
 924 #ifdef CAPTURE_DEBUG
 925                 printk("CPU[%d]: Giving pardon to "
 926                        "imprisoned penguins\n",
 927                        smp_processor_id());
 928 #endif
 929                 penguins_are_doing_time = 0;
 930                 membar_storeload_storestore();
 931                 atomic_dec(&smp_capture_registry);
 932         }
 933 }
 934
 935 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
 936  * can service tlb flush xcalls...
 937  */
 938 extern void prom_world(int);
 939
 940 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
 941 {
 942         clear_softint(1 << irq);
 943
 944         preempt_disable();
 945
 946         __asm__ __volatile__("flushw");
 947         prom_world(1);
 948         atomic_inc(&smp_capture_registry);
 949         membar_storeload_storestore();
 950         while (penguins_are_doing_time)
 951                 rmb();
 952         atomic_dec(&smp_capture_registry);
 953         prom_world(0);
 954
 955         preempt_enable();
 956 }
 957
 958 #define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
 959 #define prof_counter(__cpu)             cpu_data(__cpu).counter
 960
 961 void smp_percpu_timer_interrupt(struct pt_regs *regs)
 962 {
 963         unsigned long compare, tick, pstate;
 964         int cpu = smp_processor_id();
 965         int user = user_mode(regs);
 966
 967         /*
 968          * Check for level 14 softint.
 969          */
 970         {
 971                 unsigned long tick_mask = tick_ops->softint_mask;
 972
 973                 if (!(get_softint() & tick_mask)) {
 974                         extern void handler_irq(int, struct pt_regs *);
 975
 976                         handler_irq(14, regs);
 977                         return;
 978                 }
 979                 clear_softint(tick_mask);
 980         }
 981
 982         do {
 983                 profile_tick(CPU_PROFILING, regs);
 984                 if (!--prof_counter(cpu)) {
 985                         irq_enter();
 986
 987                         if (cpu == boot_cpu_id) {
 988                                 kstat_this_cpu.irqs[0]++;
 989                                 timer_tick_interrupt(regs);
 990                         }
 991
 992                         update_process_times(user);
 993
 994                         irq_exit();
 995
 996                         prof_counter(cpu) = prof_multiplier(cpu);
 997                 }
 998
 999                 /* Guarantee that the following sequences execute
1000                  * uninterrupted.
1001                  */
1002                 __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1003                                      "wrpr      %0, %1, %%pstate"
1004                                      : "=r" (pstate)
1005                                      : "i" (PSTATE_IE));
1006
1007                 compare = tick_ops->add_compare(current_tick_offset);
1008                 tick = tick_ops->get_tick();
1009
1010                 /* Restore PSTATE_IE. */
1011                 __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1012                                      : /* no outputs */
1013                                      : "r" (pstate));
1014         } while (time_after_eq(tick, compare));
1015 }
1016
1017 static void __init smp_setup_percpu_timer(void)
1018 {
1019         int cpu = smp_processor_id();
1020         unsigned long pstate;
1021
1022         prof_counter(cpu) = prof_multiplier(cpu) = 1;
1023
1024         /* Guarantee that the following sequences execute
1025          * uninterrupted.
1026          */
1027         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1028                              "wrpr      %0, %1, %%pstate"
1029                              : "=r" (pstate)
1030                              : "i" (PSTATE_IE));
1031
1032         tick_ops->init_tick(current_tick_offset);
1033
1034         /* Restore PSTATE_IE. */
1035         __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1036                              : /* no outputs */
1037                              : "r" (pstate));
1038 }
1039
1040 void __init smp_tick_init(void)
1041 {
1042         boot_cpu_id = hard_smp_processor_id();
1043         current_tick_offset = timer_tick_offset;
1044
1045         cpu_set(boot_cpu_id, cpu_online_map);
1046         prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1047 }
1048
1049 /* /proc/profile writes can call this, don't __init it please. */
1050 static DEFINE_SPINLOCK(prof_setup_lock);
1051
1052 int setup_profiling_timer(unsigned int multiplier)
1053 {
1054         unsigned long flags;
1055         int i;
1056
1057         if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1058                 return -EINVAL;
1059
1060         spin_lock_irqsave(&prof_setup_lock, flags);
1061         for (i = 0; i < NR_CPUS; i++)
1062                 prof_multiplier(i) = multiplier;
1063         current_tick_offset = (timer_tick_offset / multiplier);
1064         spin_unlock_irqrestore(&prof_setup_lock, flags);
1065
1066         return 0;
1067 }
1068
1069 /* Constrain the number of cpus to max_cpus.  */
1070 void __init smp_prepare_cpus(unsigned int max_cpus)
1071 {
1072         if (num_possible_cpus() > max_cpus) {
1073                 int instance, mid;
1074
1075                 instance = 0;
1076                 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1077                         if (mid != boot_cpu_id) {
1078                                 cpu_clear(mid, phys_cpu_present_map);
1079                                 if (num_possible_cpus() <= max_cpus)
1080                                         break;
1081                         }
1082                         instance++;
1083                 }
1084         }
1085
1086         smp_store_cpu_info(boot_cpu_id);
1087 }
1088
1089 /* Set this up early so that things like the scheduler can init
1090  * properly.  We use the same cpu mask for both the present and
1091  * possible cpu map.
1092  */
1093 void __init smp_setup_cpu_possible_map(void)
1094 {
1095         int instance, mid;
1096
1097         instance = 0;
1098         while (!cpu_find_by_instance(instance, NULL, &mid)) {
1099                 if (mid < NR_CPUS)
1100                         cpu_set(mid, phys_cpu_present_map);
1101                 instance++;
1102         }
1103 }
1104
1105 void __devinit smp_prepare_boot_cpu(void)
1106 {
1107         int cpu = hard_smp_processor_id();
1108
1109         if (cpu >= NR_CPUS) {
1110                 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1111                 prom_halt();
1112         }
1113
1114         current_thread_info()->cpu = cpu;
1115         __local_per_cpu_offset = __per_cpu_offset(cpu);
1116
1117         cpu_set(smp_processor_id(), cpu_online_map);
1118         cpu_set(smp_processor_id(), phys_cpu_present_map);
1119 }
1120
1121 int __devinit __cpu_up(unsigned int cpu)
1122 {
1123         int ret = smp_boot_one_cpu(cpu);
1124
1125         if (!ret) {
1126                 cpu_set(cpu, smp_commenced_mask);
1127                 while (!cpu_isset(cpu, cpu_online_map))
1128                         mb();
1129                 if (!cpu_isset(cpu, cpu_online_map)) {
1130                         ret = -ENODEV;
1131                 } else {
1132                         smp_synchronize_one_tick(cpu);
1133                 }
1134         }
1135         return ret;
1136 }
1137
1138 void __init smp_cpus_done(unsigned int max_cpus)
1139 {
1140         unsigned long bogosum = 0;
1141         int i;
1142
1143         for (i = 0; i < NR_CPUS; i++) {
1144                 if (cpu_online(i))
1145                         bogosum += cpu_data(i).udelay_val;
1146         }
1147         printk("Total of %ld processors activated "
1148                "(%lu.%02lu BogoMIPS).\n",
1149                (long) num_online_cpus(),
1150                bogosum/(500000/HZ),
1151                (bogosum/(5000/HZ))%100);
1152 }
1153
1154 void smp_send_reschedule(int cpu)
1155 {
1156         smp_receive_signal(cpu);
1157 }
1158
1159 /* This is a nop because we capture all other cpus
1160  * anyways when making the PROM active.
1161  */
1162 void smp_send_stop(void)
1163 {
1164 }
1165
1166 unsigned long __per_cpu_base __read_mostly;
1167 unsigned long __per_cpu_shift __read_mostly;
1168
1169 EXPORT_SYMBOL(__per_cpu_base);
1170 EXPORT_SYMBOL(__per_cpu_shift);
1171
1172 void __init setup_per_cpu_areas(void)
1173 {
1174         unsigned long goal, size, i;
1175         char *ptr;
1176
1177         /* Copy section for each CPU (we discard the original) */
1178         goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
1179 #ifdef CONFIG_MODULES
1180         if (goal < PERCPU_ENOUGH_ROOM)
1181                 goal = PERCPU_ENOUGH_ROOM;
1182 #endif
1183         __per_cpu_shift = 0;
1184         for (size = 1UL; size < goal; size <<= 1UL)
1185                 __per_cpu_shift++;
1186
1187         ptr = alloc_bootmem(size * NR_CPUS);
1188
1189         __per_cpu_base = ptr - __per_cpu_start;
1190
1191         for (i = 0; i < NR_CPUS; i++, ptr += size)
1192                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1193 }