1 # drivers/mtd/chips/Kconfig
3 menu "RAM/ROM/Flash chip drivers"
7 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
10 The Common Flash Interface specification was developed by Intel,
11 AMD and other flash manufactures that provides a universal method
12 for probing the capabilities of flash devices. If you wish to
13 support any device that is CFI-compliant, you need to enable this
14 option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
15 for more information on CFI.
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
21 This option enables JEDEC-style probing of flash chips which are not
22 compatible with the Common Flash Interface, but will use the common
23 CFI-targetted flash drivers for any chips which are identified which
24 are in fact compatible in all but the probe method. This actually
25 covers most AMD/Fujitsu-compatible chips and also non-CFI
31 config MTD_CFI_ADV_OPTIONS
32 bool "Flash chip driver advanced configuration options"
33 depends on MTD_GEN_PROBE
35 If you need to specify a specific endianness for access to flash
36 chips, or if you wish to reduce the size of the kernel by including
37 support for only specific arrangements of flash chips, say 'Y'. This
38 option does not directly affect the code, but will enable other
39 configuration options which allow you to do so.
44 prompt "Flash cmd/query data swapping"
45 depends on MTD_CFI_ADV_OPTIONS
46 default MTD_CFI_NOSWAP
51 This option defines the way in which the CPU attempts to arrange
52 data bits when writing the 'magic' commands to the chips. Saying
53 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
54 enabled, means that the CPU will not do any swapping; the chips
55 are expected to be wired to the CPU in 'host-endian' form.
56 Specific arrangements are possible with the BIG_ENDIAN_BYTE and
57 LITTLE_ENDIAN_BYTE, if the bytes are reversed.
59 If you have a LART, on which the data (and address) lines were
60 connected in a fashion which ensured that the nets were as short
61 as possible, resulting in a bit-shuffling which seems utterly
62 random to the untrained eye, you need the LART_ENDIAN_BYTE option.
64 Yes, there really exists something sicker than PDP-endian :)
66 config MTD_CFI_BE_BYTE_SWAP
67 bool "BIG_ENDIAN_BYTE"
69 config MTD_CFI_LE_BYTE_SWAP
70 bool "LITTLE_ENDIAN_BYTE"
74 config MTD_CFI_GEOMETRY
75 bool "Specific CFI Flash geometry selection"
76 depends on MTD_CFI_ADV_OPTIONS
78 This option does not affect the code directly, but will enable
79 some other configuration options which would allow you to reduce
80 the size of the kernel by including support for only certain
81 arrangements of CFI chips. If unsure, say 'N' and all options
82 which are supported by the current code will be enabled.
84 config MTD_MAP_BANK_WIDTH_1
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
88 If you wish to support CFI devices on a physical bus which is
91 config MTD_MAP_BANK_WIDTH_2
92 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
95 If you wish to support CFI devices on a physical bus which is
96 16 bits wide, say 'Y'.
98 config MTD_MAP_BANK_WIDTH_4
99 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
102 If you wish to support CFI devices on a physical bus which is
103 32 bits wide, say 'Y'.
105 config MTD_MAP_BANK_WIDTH_8
106 bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
109 If you wish to support CFI devices on a physical bus which is
110 64 bits wide, say 'Y'.
112 config MTD_MAP_BANK_WIDTH_16
113 bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
116 If you wish to support CFI devices on a physical bus which is
117 128 bits wide, say 'Y'.
119 config MTD_MAP_BANK_WIDTH_32
120 bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
123 If you wish to support CFI devices on a physical bus which is
124 256 bits wide, say 'Y'.
127 bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
130 If your flash chips are not interleaved - i.e. you only have one
131 flash chip addressed by each bus cycle, then say 'Y'.
134 bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
137 If your flash chips are interleaved in pairs - i.e. you have two
138 flash chips addressed by each bus cycle, then say 'Y'.
141 bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
144 If your flash chips are interleaved in fours - i.e. you have four
145 flash chips addressed by each bus cycle, then say 'Y'.
148 bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
151 If your flash chips are interleaved in eights - i.e. you have eight
152 flash chips addressed by each bus cycle, then say 'Y'.
155 bool "Protection Registers aka one-time programmable (OTP) bits"
156 depends on MTD_CFI_ADV_OPTIONS
160 This enables support for reading, writing and locking so called
161 "Protection Registers" present on some flash chips.
162 A subset of them are pre-programmed at the factory with a
163 unique set of values. The rest is user-programmable.
165 The user-programmable Protection Registers contain one-time
166 programmable (OTP) bits; when programmed, register bits cannot be
167 erased. Each Protection Register can be accessed multiple times to
168 program individual bits, as long as the register remains unlocked.
170 Each Protection Register has an associated Lock Register bit. When a
171 Lock Register bit is programmed, the associated Protection Register
172 can only be read; it can no longer be programmed. Additionally,
173 because the Lock Register bits themselves are OTP, when programmed,
174 Lock Register bits cannot be erased. Therefore, when a Protection
175 Register is locked, it cannot be unlocked.
177 This feature should therefore be used with extreme care. Any mistake
178 in the programming of OTP bits will waste them.
180 config MTD_CFI_INTELEXT
181 tristate "Support for Intel/Sharp flash chips"
182 depends on MTD_GEN_PROBE
185 The Common Flash Interface defines a number of different command
186 sets which a CFI-compliant chip may claim to implement. This code
187 provides support for one of those command sets, used on Intel
188 StrataFlash and other parts.
190 config MTD_CFI_AMDSTD
191 tristate "Support for AMD/Fujitsu flash chips"
192 depends on MTD_GEN_PROBE
195 The Common Flash Interface defines a number of different command
196 sets which a CFI-compliant chip may claim to implement. This code
197 provides support for one of those command sets, used on chips
198 including the AMD Am29LV320.
201 tristate "Support for ST (Advanced Architecture) flash chips"
202 depends on MTD_GEN_PROBE
205 The Common Flash Interface defines a number of different command
206 sets which a CFI-compliant chip may claim to implement. This code
207 provides support for one of those command sets.
213 tristate "Support for RAM chips in bus mapping"
215 This option enables basic support for RAM chips accessed through
216 a bus mapping driver.
219 tristate "Support for ROM chips in bus mapping"
221 This option enables basic support for ROM chips accessed through
222 a bus mapping driver.
225 tristate "Support for absent chips in bus mapping"
227 This option enables support for a dummy probing driver used to
228 allocated placeholder MTD devices on systems that have socketed
229 or removable media. Use of this driver as a fallback chip probe
230 preserves the expected registration order of MTD device nodes on
231 the system regardless of media presence. Device nodes created
232 with this driver will return -ENODEV upon access.
235 bool "XIP aware MTD support"
236 depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
237 default y if XIP_KERNEL
239 This allows MTD support to work with flash memory which is also
240 used for XIP purposes. If you're not sure what this is all about