git.oblomov.eu Git - linux-2.6/blob - drivers/net/cpmac.c

   1 /*
   2  * Copyright (C) 2006, 2007 Eugene Konev
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/moduleparam.h>
  22
  23 #include <linux/sched.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/errno.h>
  27 #include <linux/types.h>
  28 #include <linux/delay.h>
  29 #include <linux/version.h>
  30
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/phy_fixed.h>
  38 #include <linux/platform_device.h>
  39 #include <linux/dma-mapping.h>
  40 #include <asm/gpio.h>
  41
  42 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
  43 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
  44 MODULE_LICENSE("GPL");
  45 MODULE_ALIAS("platform:cpmac");
  46
  47 static int debug_level = 8;
  48 static int dumb_switch;
  49
  50 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
  51 module_param(debug_level, int, 0444);
  52 module_param(dumb_switch, int, 0444);
  53
  54 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
  55 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
  56
  57 #define CPMAC_VERSION "0.5.0"
  58 /* frame size + 802.1q tag */
  59 #define CPMAC_SKB_SIZE          (ETH_FRAME_LEN + 4)
  60 #define CPMAC_QUEUES    8
  61
  62 /* Ethernet registers */
  63 #define CPMAC_TX_CONTROL                0x0004
  64 #define CPMAC_TX_TEARDOWN               0x0008
  65 #define CPMAC_RX_CONTROL                0x0014
  66 #define CPMAC_RX_TEARDOWN               0x0018
  67 #define CPMAC_MBP                       0x0100
  68 # define MBP_RXPASSCRC                  0x40000000
  69 # define MBP_RXQOS                      0x20000000
  70 # define MBP_RXNOCHAIN                  0x10000000
  71 # define MBP_RXCMF                      0x01000000
  72 # define MBP_RXSHORT                    0x00800000
  73 # define MBP_RXCEF                      0x00400000
  74 # define MBP_RXPROMISC                  0x00200000
  75 # define MBP_PROMISCCHAN(channel)       (((channel) & 0x7) << 16)
  76 # define MBP_RXBCAST                    0x00002000
  77 # define MBP_BCASTCHAN(channel)         (((channel) & 0x7) << 8)
  78 # define MBP_RXMCAST                    0x00000020
  79 # define MBP_MCASTCHAN(channel)         ((channel) & 0x7)
  80 #define CPMAC_UNICAST_ENABLE            0x0104
  81 #define CPMAC_UNICAST_CLEAR             0x0108
  82 #define CPMAC_MAX_LENGTH                0x010c
  83 #define CPMAC_BUFFER_OFFSET             0x0110
  84 #define CPMAC_MAC_CONTROL               0x0160
  85 # define MAC_TXPTYPE                    0x00000200
  86 # define MAC_TXPACE                     0x00000040
  87 # define MAC_MII                        0x00000020
  88 # define MAC_TXFLOW                     0x00000010
  89 # define MAC_RXFLOW                     0x00000008
  90 # define MAC_MTEST                      0x00000004
  91 # define MAC_LOOPBACK                   0x00000002
  92 # define MAC_FDX                        0x00000001
  93 #define CPMAC_MAC_STATUS                0x0164
  94 # define MAC_STATUS_QOS                 0x00000004
  95 # define MAC_STATUS_RXFLOW              0x00000002
  96 # define MAC_STATUS_TXFLOW              0x00000001
  97 #define CPMAC_TX_INT_ENABLE             0x0178
  98 #define CPMAC_TX_INT_CLEAR              0x017c
  99 #define CPMAC_MAC_INT_VECTOR            0x0180
 100 # define MAC_INT_STATUS                 0x00080000
 101 # define MAC_INT_HOST                   0x00040000
 102 # define MAC_INT_RX                     0x00020000
 103 # define MAC_INT_TX                     0x00010000
 104 #define CPMAC_MAC_EOI_VECTOR            0x0184
 105 #define CPMAC_RX_INT_ENABLE             0x0198
 106 #define CPMAC_RX_INT_CLEAR              0x019c
 107 #define CPMAC_MAC_INT_ENABLE            0x01a8
 108 #define CPMAC_MAC_INT_CLEAR             0x01ac
 109 #define CPMAC_MAC_ADDR_LO(channel)      (0x01b0 + (channel) * 4)
 110 #define CPMAC_MAC_ADDR_MID              0x01d0
 111 #define CPMAC_MAC_ADDR_HI               0x01d4
 112 #define CPMAC_MAC_HASH_LO               0x01d8
 113 #define CPMAC_MAC_HASH_HI               0x01dc
 114 #define CPMAC_TX_PTR(channel)           (0x0600 + (channel) * 4)
 115 #define CPMAC_RX_PTR(channel)           (0x0620 + (channel) * 4)
 116 #define CPMAC_TX_ACK(channel)           (0x0640 + (channel) * 4)
 117 #define CPMAC_RX_ACK(channel)           (0x0660 + (channel) * 4)
 118 #define CPMAC_REG_END                   0x0680
 119 /*
 120  * Rx/Tx statistics
 121  * TODO: use some of them to fill stats in cpmac_stats()
 122  */
 123 #define CPMAC_STATS_RX_GOOD             0x0200
 124 #define CPMAC_STATS_RX_BCAST            0x0204
 125 #define CPMAC_STATS_RX_MCAST            0x0208
 126 #define CPMAC_STATS_RX_PAUSE            0x020c
 127 #define CPMAC_STATS_RX_CRC              0x0210
 128 #define CPMAC_STATS_RX_ALIGN            0x0214
 129 #define CPMAC_STATS_RX_OVER             0x0218
 130 #define CPMAC_STATS_RX_JABBER           0x021c
 131 #define CPMAC_STATS_RX_UNDER            0x0220
 132 #define CPMAC_STATS_RX_FRAG             0x0224
 133 #define CPMAC_STATS_RX_FILTER           0x0228
 134 #define CPMAC_STATS_RX_QOSFILTER        0x022c
 135 #define CPMAC_STATS_RX_OCTETS           0x0230
 136
 137 #define CPMAC_STATS_TX_GOOD             0x0234
 138 #define CPMAC_STATS_TX_BCAST            0x0238
 139 #define CPMAC_STATS_TX_MCAST            0x023c
 140 #define CPMAC_STATS_TX_PAUSE            0x0240
 141 #define CPMAC_STATS_TX_DEFER            0x0244
 142 #define CPMAC_STATS_TX_COLLISION        0x0248
 143 #define CPMAC_STATS_TX_SINGLECOLL       0x024c
 144 #define CPMAC_STATS_TX_MULTICOLL        0x0250
 145 #define CPMAC_STATS_TX_EXCESSCOLL       0x0254
 146 #define CPMAC_STATS_TX_LATECOLL         0x0258
 147 #define CPMAC_STATS_TX_UNDERRUN         0x025c
 148 #define CPMAC_STATS_TX_CARRIERSENSE     0x0260
 149 #define CPMAC_STATS_TX_OCTETS           0x0264
 150
 151 #define cpmac_read(base, reg)           (readl((void __iomem *)(base) + (reg)))
 152 #define cpmac_write(base, reg, val)     (writel(val, (void __iomem *)(base) + \
 153                                                 (reg)))
 154
 155 /* MDIO bus */
 156 #define CPMAC_MDIO_VERSION              0x0000
 157 #define CPMAC_MDIO_CONTROL              0x0004
 158 # define MDIOC_IDLE                     0x80000000
 159 # define MDIOC_ENABLE                   0x40000000
 160 # define MDIOC_PREAMBLE                 0x00100000
 161 # define MDIOC_FAULT                    0x00080000
 162 # define MDIOC_FAULTDETECT              0x00040000
 163 # define MDIOC_INTTEST                  0x00020000
 164 # define MDIOC_CLKDIV(div)              ((div) & 0xff)
 165 #define CPMAC_MDIO_ALIVE                0x0008
 166 #define CPMAC_MDIO_LINK                 0x000c
 167 #define CPMAC_MDIO_ACCESS(channel)      (0x0080 + (channel) * 8)
 168 # define MDIO_BUSY                      0x80000000
 169 # define MDIO_WRITE                     0x40000000
 170 # define MDIO_REG(reg)                  (((reg) & 0x1f) << 21)
 171 # define MDIO_PHY(phy)                  (((phy) & 0x1f) << 16)
 172 # define MDIO_DATA(data)                ((data) & 0xffff)
 173 #define CPMAC_MDIO_PHYSEL(channel)      (0x0084 + (channel) * 8)
 174 # define PHYSEL_LINKSEL                 0x00000040
 175 # define PHYSEL_LINKINT                 0x00000020
 176
 177 struct cpmac_desc {
 178         u32 hw_next;
 179         u32 hw_data;
 180         u16 buflen;
 181         u16 bufflags;
 182         u16 datalen;
 183         u16 dataflags;
 184 #define CPMAC_SOP                       0x8000
 185 #define CPMAC_EOP                       0x4000
 186 #define CPMAC_OWN                       0x2000
 187 #define CPMAC_EOQ                       0x1000
 188         struct sk_buff *skb;
 189         struct cpmac_desc *next;
 190         dma_addr_t mapping;
 191         dma_addr_t data_mapping;
 192 };
 193
 194 struct cpmac_priv {
 195         spinlock_t lock;
 196         spinlock_t rx_lock;
 197         struct cpmac_desc *rx_head;
 198         int ring_size;
 199         struct cpmac_desc *desc_ring;
 200         dma_addr_t dma_ring;
 201         void __iomem *regs;
 202         struct mii_bus *mii_bus;
 203         struct phy_device *phy;
 204         char phy_name[BUS_ID_SIZE];
 205         int oldlink, oldspeed, oldduplex;
 206         u32 msg_enable;
 207         struct net_device *dev;
 208         struct work_struct reset_work;
 209         struct platform_device *pdev;
 210         struct napi_struct napi;
 211 };
 212
 213 static irqreturn_t cpmac_irq(int, void *);
 214 static void cpmac_hw_start(struct net_device *dev);
 215 static void cpmac_hw_stop(struct net_device *dev);
 216 static int cpmac_stop(struct net_device *dev);
 217 static int cpmac_open(struct net_device *dev);
 218
 219 static void cpmac_dump_regs(struct net_device *dev)
 220 {
 221         int i;
 222         struct cpmac_priv *priv = netdev_priv(dev);
 223         for (i = 0; i < CPMAC_REG_END; i += 4) {
 224                 if (i % 16 == 0) {
 225                         if (i)
 226                                 printk("\n");
 227                         printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
 228                                priv->regs + i);
 229                 }
 230                 printk(" %08x", cpmac_read(priv->regs, i));
 231         }
 232         printk("\n");
 233 }
 234
 235 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
 236 {
 237         int i;
 238         printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
 239         for (i = 0; i < sizeof(*desc) / 4; i++)
 240                 printk(" %08x", ((u32 *)desc)[i]);
 241         printk("\n");
 242 }
 243
 244 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
 245 {
 246         int i;
 247         printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
 248         for (i = 0; i < skb->len; i++) {
 249                 if (i % 16 == 0) {
 250                         if (i)
 251                                 printk("\n");
 252                         printk(KERN_DEBUG "%s: data[%p]:", dev->name,
 253                                skb->data + i);
 254                 }
 255                 printk(" %02x", ((u8 *)skb->data)[i]);
 256         }
 257         printk("\n");
 258 }
 259
 260 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
 261 {
 262         u32 val;
 263
 264         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 265                 cpu_relax();
 266         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
 267                     MDIO_PHY(phy_id));
 268         while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
 269                 cpu_relax();
 270         return MDIO_DATA(val);
 271 }
 272
 273 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
 274                             int reg, u16 val)
 275 {
 276         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 277                 cpu_relax();
 278         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
 279                     MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
 280         return 0;
 281 }
 282
 283 static int cpmac_mdio_reset(struct mii_bus *bus)
 284 {
 285         ar7_device_reset(AR7_RESET_BIT_MDIO);
 286         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
 287                     MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
 288         return 0;
 289 }
 290
 291 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
 292
 293 static struct mii_bus cpmac_mii = {
 294         .name = "cpmac-mii",
 295         .read = cpmac_mdio_read,
 296         .write = cpmac_mdio_write,
 297         .reset = cpmac_mdio_reset,
 298         .irq = mii_irqs,
 299 };
 300
 301 static int cpmac_config(struct net_device *dev, struct ifmap *map)
 302 {
 303         if (dev->flags & IFF_UP)
 304                 return -EBUSY;
 305
 306         /* Don't allow changing the I/O address */
 307         if (map->base_addr != dev->base_addr)
 308                 return -EOPNOTSUPP;
 309
 310         /* ignore other fields */
 311         return 0;
 312 }
 313
 314 static void cpmac_set_multicast_list(struct net_device *dev)
 315 {
 316         struct dev_mc_list *iter;
 317         int i;
 318         u8 tmp;
 319         u32 mbp, bit, hash[2] = { 0, };
 320         struct cpmac_priv *priv = netdev_priv(dev);
 321
 322         mbp = cpmac_read(priv->regs, CPMAC_MBP);
 323         if (dev->flags & IFF_PROMISC) {
 324                 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
 325                             MBP_RXPROMISC);
 326         } else {
 327                 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
 328                 if (dev->flags & IFF_ALLMULTI) {
 329                         /* enable all multicast mode */
 330                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
 331                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
 332                 } else {
 333                         /*
 334                          * cpmac uses some strange mac address hashing
 335                          * (not crc32)
 336                          */
 337                         for (i = 0, iter = dev->mc_list; i < dev->mc_count;
 338                              i++, iter = iter->next) {
 339                                 bit = 0;
 340                                 tmp = iter->dmi_addr[0];
 341                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 342                                 tmp = iter->dmi_addr[1];
 343                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 344                                 tmp = iter->dmi_addr[2];
 345                                 bit  ^= (tmp >> 6) ^ tmp;
 346                                 tmp = iter->dmi_addr[3];
 347                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 348                                 tmp = iter->dmi_addr[4];
 349                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 350                                 tmp = iter->dmi_addr[5];
 351                                 bit  ^= (tmp >> 6) ^ tmp;
 352                                 bit &= 0x3f;
 353                                 hash[bit / 32] |= 1 << (bit % 32);
 354                         }
 355
 356                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
 357                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
 358                 }
 359         }
 360 }
 361
 362 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
 363                                     struct cpmac_desc *desc)
 364 {
 365         struct sk_buff *skb, *result = NULL;
 366
 367         if (unlikely(netif_msg_hw(priv)))
 368                 cpmac_dump_desc(priv->dev, desc);
 369         cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
 370         if (unlikely(!desc->datalen)) {
 371                 if (netif_msg_rx_err(priv) && net_ratelimit())
 372                         printk(KERN_WARNING "%s: rx: spurious interrupt\n",
 373                                priv->dev->name);
 374                 return NULL;
 375         }
 376
 377         skb = netdev_alloc_skb(priv->dev, CPMAC_SKB_SIZE);
 378         if (likely(skb)) {
 379                 skb_reserve(skb, 2);
 380                 skb_put(desc->skb, desc->datalen);
 381                 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
 382                 desc->skb->ip_summed = CHECKSUM_NONE;
 383                 priv->dev->stats.rx_packets++;
 384                 priv->dev->stats.rx_bytes += desc->datalen;
 385                 result = desc->skb;
 386                 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
 387                                  CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
 388                 desc->skb = skb;
 389                 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
 390                                                     CPMAC_SKB_SIZE,
 391                                                     DMA_FROM_DEVICE);
 392                 desc->hw_data = (u32)desc->data_mapping;
 393                 if (unlikely(netif_msg_pktdata(priv))) {
 394                         printk(KERN_DEBUG "%s: received packet:\n",
 395                                priv->dev->name);
 396                         cpmac_dump_skb(priv->dev, result);
 397                 }
 398         } else {
 399                 if (netif_msg_rx_err(priv) && net_ratelimit())
 400                         printk(KERN_WARNING
 401                                "%s: low on skbs, dropping packet\n",
 402                                priv->dev->name);
 403                 priv->dev->stats.rx_dropped++;
 404         }
 405
 406         desc->buflen = CPMAC_SKB_SIZE;
 407         desc->dataflags = CPMAC_OWN;
 408
 409         return result;
 410 }
 411
 412 static int cpmac_poll(struct napi_struct *napi, int budget)
 413 {
 414         struct sk_buff *skb;
 415         struct cpmac_desc *desc;
 416         int received = 0;
 417         struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
 418
 419         spin_lock(&priv->rx_lock);
 420         if (unlikely(!priv->rx_head)) {
 421                 if (netif_msg_rx_err(priv) && net_ratelimit())
 422                         printk(KERN_WARNING "%s: rx: polling, but no queue\n",
 423                                priv->dev->name);
 424                 netif_rx_complete(priv->dev, napi);
 425                 return 0;
 426         }
 427
 428         desc = priv->rx_head;
 429         while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
 430                 skb = cpmac_rx_one(priv, desc);
 431                 if (likely(skb)) {
 432                         netif_receive_skb(skb);
 433                         received++;
 434                 }
 435                 desc = desc->next;
 436         }
 437
 438         priv->rx_head = desc;
 439         spin_unlock(&priv->rx_lock);
 440         if (unlikely(netif_msg_rx_status(priv)))
 441                 printk(KERN_DEBUG "%s: poll processed %d packets\n",
 442                        priv->dev->name, received);
 443         if (desc->dataflags & CPMAC_OWN) {
 444                 netif_rx_complete(priv->dev, napi);
 445                 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
 446                 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 447                 return 0;
 448         }
 449
 450         return 1;
 451 }
 452
 453 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 454 {
 455         int queue, len;
 456         struct cpmac_desc *desc;
 457         struct cpmac_priv *priv = netdev_priv(dev);
 458
 459         if (unlikely(skb_padto(skb, ETH_ZLEN)))
 460                 return NETDEV_TX_OK;
 461
 462         len = max(skb->len, ETH_ZLEN);
 463         queue = skb_get_queue_mapping(skb);
 464 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 465         netif_stop_subqueue(dev, queue);
 466 #else
 467         netif_stop_queue(dev);
 468 #endif
 469
 470         desc = &priv->desc_ring[queue];
 471         if (unlikely(desc->dataflags & CPMAC_OWN)) {
 472                 if (netif_msg_tx_err(priv) && net_ratelimit())
 473                         printk(KERN_WARNING "%s: tx dma ring full\n",
 474                                dev->name);
 475                 return NETDEV_TX_BUSY;
 476         }
 477
 478         spin_lock(&priv->lock);
 479         dev->trans_start = jiffies;
 480         spin_unlock(&priv->lock);
 481         desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
 482         desc->skb = skb;
 483         desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
 484                                             DMA_TO_DEVICE);
 485         desc->hw_data = (u32)desc->data_mapping;
 486         desc->datalen = len;
 487         desc->buflen = len;
 488         if (unlikely(netif_msg_tx_queued(priv)))
 489                 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
 490                        skb->len);
 491         if (unlikely(netif_msg_hw(priv)))
 492                 cpmac_dump_desc(dev, desc);
 493         if (unlikely(netif_msg_pktdata(priv)))
 494                 cpmac_dump_skb(dev, skb);
 495         cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
 496
 497         return NETDEV_TX_OK;
 498 }
 499
 500 static void cpmac_end_xmit(struct net_device *dev, int queue)
 501 {
 502         struct cpmac_desc *desc;
 503         struct cpmac_priv *priv = netdev_priv(dev);
 504
 505         desc = &priv->desc_ring[queue];
 506         cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
 507         if (likely(desc->skb)) {
 508                 spin_lock(&priv->lock);
 509                 dev->stats.tx_packets++;
 510                 dev->stats.tx_bytes += desc->skb->len;
 511                 spin_unlock(&priv->lock);
 512                 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
 513                                  DMA_TO_DEVICE);
 514
 515                 if (unlikely(netif_msg_tx_done(priv)))
 516                         printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
 517                                desc->skb, desc->skb->len);
 518
 519                 dev_kfree_skb_irq(desc->skb);
 520                 desc->skb = NULL;
 521 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 522                 if (netif_subqueue_stopped(dev, queue))
 523                         netif_wake_subqueue(dev, queue);
 524 #else
 525                 if (netif_queue_stopped(dev))
 526                         netif_wake_queue(dev);
 527 #endif
 528         } else {
 529                 if (netif_msg_tx_err(priv) && net_ratelimit())
 530                         printk(KERN_WARNING
 531                                "%s: end_xmit: spurious interrupt\n", dev->name);
 532 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 533                 if (netif_subqueue_stopped(dev, queue))
 534                         netif_wake_subqueue(dev, queue);
 535 #else
 536                 if (netif_queue_stopped(dev))
 537                         netif_wake_queue(dev);
 538 #endif
 539         }
 540 }
 541
 542 static void cpmac_hw_stop(struct net_device *dev)
 543 {
 544         int i;
 545         struct cpmac_priv *priv = netdev_priv(dev);
 546         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
 547
 548         ar7_device_reset(pdata->reset_bit);
 549         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 550                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
 551         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 552                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
 553         for (i = 0; i < 8; i++) {
 554                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 555                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 556         }
 557         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 558         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 559         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 560         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 561         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 562                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
 563 }
 564
 565 static void cpmac_hw_start(struct net_device *dev)
 566 {
 567         int i;
 568         struct cpmac_priv *priv = netdev_priv(dev);
 569         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
 570
 571         ar7_device_reset(pdata->reset_bit);
 572         for (i = 0; i < 8; i++) {
 573                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 574                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 575         }
 576         cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
 577
 578         cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
 579                     MBP_RXMCAST);
 580         cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
 581         for (i = 0; i < 8; i++)
 582                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
 583         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
 584         cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
 585                     (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
 586                     (dev->dev_addr[3] << 24));
 587         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
 588         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 589         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 590         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 591         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 592         cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
 593         cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 594         cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
 595         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
 596
 597         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 598                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
 599         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 600                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
 601         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 602                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
 603                     MAC_FDX);
 604 }
 605
 606 static void cpmac_clear_rx(struct net_device *dev)
 607 {
 608         struct cpmac_priv *priv = netdev_priv(dev);
 609         struct cpmac_desc *desc;
 610         int i;
 611         if (unlikely(!priv->rx_head))
 612                 return;
 613         desc = priv->rx_head;
 614         for (i = 0; i < priv->ring_size; i++) {
 615                 if ((desc->dataflags & CPMAC_OWN) == 0) {
 616                         if (netif_msg_rx_err(priv) && net_ratelimit())
 617                                 printk(KERN_WARNING "%s: packet dropped\n",
 618                                        dev->name);
 619                         if (unlikely(netif_msg_hw(priv)))
 620                                 cpmac_dump_desc(dev, desc);
 621                         desc->dataflags = CPMAC_OWN;
 622                         dev->stats.rx_dropped++;
 623                 }
 624                 desc = desc->next;
 625         }
 626 }
 627
 628 static void cpmac_clear_tx(struct net_device *dev)
 629 {
 630         struct cpmac_priv *priv = netdev_priv(dev);
 631         int i;
 632         if (unlikely(!priv->desc_ring))
 633                 return;
 634         for (i = 0; i < CPMAC_QUEUES; i++) {
 635                 priv->desc_ring[i].dataflags = 0;
 636                 if (priv->desc_ring[i].skb) {
 637                         dev_kfree_skb_any(priv->desc_ring[i].skb);
 638                         if (netif_subqueue_stopped(dev, i))
 639                             netif_wake_subqueue(dev, i);
 640                 }
 641         }
 642 }
 643
 644 static void cpmac_hw_error(struct work_struct *work)
 645 {
 646         struct cpmac_priv *priv =
 647                 container_of(work, struct cpmac_priv, reset_work);
 648
 649         spin_lock(&priv->rx_lock);
 650         cpmac_clear_rx(priv->dev);
 651         spin_unlock(&priv->rx_lock);
 652         cpmac_clear_tx(priv->dev);
 653         cpmac_hw_start(priv->dev);
 654         napi_enable(&priv->napi);
 655         netif_start_queue(priv->dev);
 656 }
 657
 658 static irqreturn_t cpmac_irq(int irq, void *dev_id)
 659 {
 660         struct net_device *dev = dev_id;
 661         struct cpmac_priv *priv;
 662         int queue;
 663         u32 status;
 664
 665         priv = netdev_priv(dev);
 666
 667         status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
 668
 669         if (unlikely(netif_msg_intr(priv)))
 670                 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
 671                        status);
 672
 673         if (status & MAC_INT_TX)
 674                 cpmac_end_xmit(dev, (status & 7));
 675
 676         if (status & MAC_INT_RX) {
 677                 queue = (status >> 8) & 7;
 678                 if (netif_rx_schedule_prep(dev, &priv->napi)) {
 679                         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
 680                         __netif_rx_schedule(dev, &priv->napi);
 681                 }
 682         }
 683
 684         cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
 685
 686         if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) {
 687                 if (netif_msg_drv(priv) && net_ratelimit())
 688                         printk(KERN_ERR "%s: hw error, resetting...\n",
 689                                dev->name);
 690                 netif_stop_queue(dev);
 691                 napi_disable(&priv->napi);
 692                 cpmac_hw_stop(dev);
 693                 schedule_work(&priv->reset_work);
 694                 if (unlikely(netif_msg_hw(priv)))
 695                         cpmac_dump_regs(dev);
 696         }
 697
 698         return IRQ_HANDLED;
 699 }
 700
 701 static void cpmac_tx_timeout(struct net_device *dev)
 702 {
 703         struct cpmac_priv *priv = netdev_priv(dev);
 704         int i;
 705
 706         spin_lock(&priv->lock);
 707         dev->stats.tx_errors++;
 708         spin_unlock(&priv->lock);
 709         if (netif_msg_tx_err(priv) && net_ratelimit())
 710                 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
 711         /*
 712          * FIXME: waking up random queue is not the best thing to
 713          * do... on the other hand why we got here at all?
 714          */
 715 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 716         for (i = 0; i < CPMAC_QUEUES; i++)
 717                 if (priv->desc_ring[i].skb) {
 718                         priv->desc_ring[i].dataflags = 0;
 719                         dev_kfree_skb_any(priv->desc_ring[i].skb);
 720                         netif_wake_subqueue(dev, i);
 721                         break;
 722                 }
 723 #else
 724         priv->desc_ring[0].dataflags = 0;
 725         if (priv->desc_ring[0].skb)
 726                 dev_kfree_skb_any(priv->desc_ring[0].skb);
 727         netif_wake_queue(dev);
 728 #endif
 729 }
 730
 731 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 732 {
 733         struct cpmac_priv *priv = netdev_priv(dev);
 734         if (!(netif_running(dev)))
 735                 return -EINVAL;
 736         if (!priv->phy)
 737                 return -EINVAL;
 738         if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
 739             (cmd == SIOCSMIIREG))
 740                 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
 741
 742         return -EOPNOTSUPP;
 743 }
 744
 745 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 746 {
 747         struct cpmac_priv *priv = netdev_priv(dev);
 748
 749         if (priv->phy)
 750                 return phy_ethtool_gset(priv->phy, cmd);
 751
 752         return -EINVAL;
 753 }
 754
 755 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 756 {
 757         struct cpmac_priv *priv = netdev_priv(dev);
 758
 759         if (!capable(CAP_NET_ADMIN))
 760                 return -EPERM;
 761
 762         if (priv->phy)
 763                 return phy_ethtool_sset(priv->phy, cmd);
 764
 765         return -EINVAL;
 766 }
 767
 768 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
 769 {
 770         struct cpmac_priv *priv = netdev_priv(dev);
 771
 772         ring->rx_max_pending = 1024;
 773         ring->rx_mini_max_pending = 1;
 774         ring->rx_jumbo_max_pending = 1;
 775         ring->tx_max_pending = 1;
 776
 777         ring->rx_pending = priv->ring_size;
 778         ring->rx_mini_pending = 1;
 779         ring->rx_jumbo_pending = 1;
 780         ring->tx_pending = 1;
 781 }
 782
 783 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
 784 {
 785         struct cpmac_priv *priv = netdev_priv(dev);
 786
 787         if (netif_running(dev))
 788                 return -EBUSY;
 789         priv->ring_size = ring->rx_pending;
 790         return 0;
 791 }
 792
 793 static void cpmac_get_drvinfo(struct net_device *dev,
 794                               struct ethtool_drvinfo *info)
 795 {
 796         strcpy(info->driver, "cpmac");
 797         strcpy(info->version, CPMAC_VERSION);
 798         info->fw_version[0] = '\0';
 799         sprintf(info->bus_info, "%s", "cpmac");
 800         info->regdump_len = 0;
 801 }
 802
 803 static const struct ethtool_ops cpmac_ethtool_ops = {
 804         .get_settings = cpmac_get_settings,
 805         .set_settings = cpmac_set_settings,
 806         .get_drvinfo = cpmac_get_drvinfo,
 807         .get_link = ethtool_op_get_link,
 808         .get_ringparam = cpmac_get_ringparam,
 809         .set_ringparam = cpmac_set_ringparam,
 810 };
 811
 812 static void cpmac_adjust_link(struct net_device *dev)
 813 {
 814         struct cpmac_priv *priv = netdev_priv(dev);
 815         int new_state = 0;
 816
 817         spin_lock(&priv->lock);
 818         if (priv->phy->link) {
 819                 netif_start_queue(dev);
 820                 if (priv->phy->duplex != priv->oldduplex) {
 821                         new_state = 1;
 822                         priv->oldduplex = priv->phy->duplex;
 823                 }
 824
 825                 if (priv->phy->speed != priv->oldspeed) {
 826                         new_state = 1;
 827                         priv->oldspeed = priv->phy->speed;
 828                 }
 829
 830                 if (!priv->oldlink) {
 831                         new_state = 1;
 832                         priv->oldlink = 1;
 833                         netif_schedule(dev);
 834                 }
 835         } else if (priv->oldlink) {
 836                 netif_stop_queue(dev);
 837                 new_state = 1;
 838                 priv->oldlink = 0;
 839                 priv->oldspeed = 0;
 840                 priv->oldduplex = -1;
 841         }
 842
 843         if (new_state && netif_msg_link(priv) && net_ratelimit())
 844                 phy_print_status(priv->phy);
 845
 846         spin_unlock(&priv->lock);
 847 }
 848
 849 static int cpmac_open(struct net_device *dev)
 850 {
 851         int i, size, res;
 852         struct cpmac_priv *priv = netdev_priv(dev);
 853         struct resource *mem;
 854         struct cpmac_desc *desc;
 855         struct sk_buff *skb;
 856
 857         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
 858         if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
 859                 if (netif_msg_drv(priv))
 860                         printk(KERN_ERR "%s: failed to request registers\n",
 861                                dev->name);
 862                 res = -ENXIO;
 863                 goto fail_reserve;
 864         }
 865
 866         priv->regs = ioremap(mem->start, mem->end - mem->start);
 867         if (!priv->regs) {
 868                 if (netif_msg_drv(priv))
 869                         printk(KERN_ERR "%s: failed to remap registers\n",
 870                                dev->name);
 871                 res = -ENXIO;
 872                 goto fail_remap;
 873         }
 874
 875         size = priv->ring_size + CPMAC_QUEUES;
 876         priv->desc_ring = dma_alloc_coherent(&dev->dev,
 877                                              sizeof(struct cpmac_desc) * size,
 878                                              &priv->dma_ring,
 879                                              GFP_KERNEL);
 880         if (!priv->desc_ring) {
 881                 res = -ENOMEM;
 882                 goto fail_alloc;
 883         }
 884
 885         for (i = 0; i < size; i++)
 886                 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
 887
 888         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
 889         for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
 890                 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
 891                 if (unlikely(!skb)) {
 892                         res = -ENOMEM;
 893                         goto fail_desc;
 894                 }
 895                 skb_reserve(skb, 2);
 896                 desc->skb = skb;
 897                 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
 898                                                     CPMAC_SKB_SIZE,
 899                                                     DMA_FROM_DEVICE);
 900                 desc->hw_data = (u32)desc->data_mapping;
 901                 desc->buflen = CPMAC_SKB_SIZE;
 902                 desc->dataflags = CPMAC_OWN;
 903                 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
 904                 desc->hw_next = (u32)desc->next->mapping;
 905         }
 906
 907         if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
 908                                dev->name, dev))) {
 909                 if (netif_msg_drv(priv))
 910                         printk(KERN_ERR "%s: failed to obtain irq\n",
 911                                dev->name);
 912                 goto fail_irq;
 913         }
 914
 915         INIT_WORK(&priv->reset_work, cpmac_hw_error);
 916         cpmac_hw_start(dev);
 917
 918         napi_enable(&priv->napi);
 919         priv->phy->state = PHY_CHANGELINK;
 920         phy_start(priv->phy);
 921
 922         return 0;
 923
 924 fail_irq:
 925 fail_desc:
 926         for (i = 0; i < priv->ring_size; i++) {
 927                 if (priv->rx_head[i].skb) {
 928                         dma_unmap_single(&dev->dev,
 929                                          priv->rx_head[i].data_mapping,
 930                                          CPMAC_SKB_SIZE,
 931                                          DMA_FROM_DEVICE);
 932                         kfree_skb(priv->rx_head[i].skb);
 933                 }
 934         }
 935 fail_alloc:
 936         kfree(priv->desc_ring);
 937         iounmap(priv->regs);
 938
 939 fail_remap:
 940         release_mem_region(mem->start, mem->end - mem->start);
 941
 942 fail_reserve:
 943         return res;
 944 }
 945
 946 static int cpmac_stop(struct net_device *dev)
 947 {
 948         int i;
 949         struct cpmac_priv *priv = netdev_priv(dev);
 950         struct resource *mem;
 951
 952         netif_stop_queue(dev);
 953
 954         cancel_work_sync(&priv->reset_work);
 955         napi_disable(&priv->napi);
 956         phy_stop(priv->phy);
 957
 958         cpmac_hw_stop(dev);
 959
 960         for (i = 0; i < 8; i++)
 961                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 962         cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
 963         cpmac_write(priv->regs, CPMAC_MBP, 0);
 964
 965         free_irq(dev->irq, dev);
 966         iounmap(priv->regs);
 967         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
 968         release_mem_region(mem->start, mem->end - mem->start);
 969         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
 970         for (i = 0; i < priv->ring_size; i++) {
 971                 if (priv->rx_head[i].skb) {
 972                         dma_unmap_single(&dev->dev,
 973                                          priv->rx_head[i].data_mapping,
 974                                          CPMAC_SKB_SIZE,
 975                                          DMA_FROM_DEVICE);
 976                         kfree_skb(priv->rx_head[i].skb);
 977                 }
 978         }
 979
 980         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
 981                           (CPMAC_QUEUES + priv->ring_size),
 982                           priv->desc_ring, priv->dma_ring);
 983         return 0;
 984 }
 985
 986 static int external_switch;
 987
 988 static int __devinit cpmac_probe(struct platform_device *pdev)
 989 {
 990         int rc, phy_id, i;
 991         char *mdio_bus_id = "0";
 992         struct resource *mem;
 993         struct cpmac_priv *priv;
 994         struct net_device *dev;
 995         struct plat_cpmac_data *pdata;
 996         DECLARE_MAC_BUF(mac);
 997
 998         pdata = pdev->dev.platform_data;
 999
1000         for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1001                 if (!(pdata->phy_mask & (1 << phy_id)))
1002                         continue;
1003                 if (!cpmac_mii.phy_map[phy_id])
1004                         continue;
1005                 break;
1006         }
1007
1008         if (phy_id == PHY_MAX_ADDR) {
1009                 if (external_switch || dumb_switch) {
1010                         struct fixed_phy_status status = {};
1011
1012                         /*
1013                          * FIXME: this should be in the platform code!
1014                          * Since there is not platform code at all (that is,
1015                          * no mainline users of that driver), place it here
1016                          * for now.
1017                          */
1018                         phy_id = 0;
1019                         status.link = 1;
1020                         status.duplex = 1;
1021                         status.speed = 100;
1022                         fixed_phy_add(PHY_POLL, phy_id, &status);
1023                 } else {
1024                         printk(KERN_ERR "cpmac: no PHY present\n");
1025                         return -ENODEV;
1026                 }
1027         }
1028
1029         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1030
1031         if (!dev) {
1032                 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1033                 return -ENOMEM;
1034         }
1035
1036         platform_set_drvdata(pdev, dev);
1037         priv = netdev_priv(dev);
1038
1039         priv->pdev = pdev;
1040         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1041         if (!mem) {
1042                 rc = -ENODEV;
1043                 goto fail;
1044         }
1045
1046         dev->irq = platform_get_irq_byname(pdev, "irq");
1047
1048         dev->open               = cpmac_open;
1049         dev->stop               = cpmac_stop;
1050         dev->set_config         = cpmac_config;
1051         dev->hard_start_xmit    = cpmac_start_xmit;
1052         dev->do_ioctl           = cpmac_ioctl;
1053         dev->set_multicast_list = cpmac_set_multicast_list;
1054         dev->tx_timeout         = cpmac_tx_timeout;
1055         dev->ethtool_ops        = &cpmac_ethtool_ops;
1056         dev->features |= NETIF_F_MULTI_QUEUE;
1057
1058         netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1059
1060         spin_lock_init(&priv->lock);
1061         spin_lock_init(&priv->rx_lock);
1062         priv->dev = dev;
1063         priv->ring_size = 64;
1064         priv->msg_enable = netif_msg_init(debug_level, 0xff);
1065         memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1066
1067         snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
1068
1069         priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0,
1070                                 PHY_INTERFACE_MODE_MII);
1071         if (IS_ERR(priv->phy)) {
1072                 if (netif_msg_drv(priv))
1073                         printk(KERN_ERR "%s: Could not attach to PHY\n",
1074                                dev->name);
1075                 return PTR_ERR(priv->phy);
1076         }
1077
1078         if ((rc = register_netdev(dev))) {
1079                 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1080                        dev->name);
1081                 goto fail;
1082         }
1083
1084         if (netif_msg_probe(priv)) {
1085                 printk(KERN_INFO
1086                        "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1087                        "mac: %s)\n", dev->name, (void *)mem->start, dev->irq,
1088                        priv->phy_name, print_mac(mac, dev->dev_addr));
1089         }
1090         return 0;
1091
1092 fail:
1093         free_netdev(dev);
1094         return rc;
1095 }
1096
1097 static int __devexit cpmac_remove(struct platform_device *pdev)
1098 {
1099         struct net_device *dev = platform_get_drvdata(pdev);
1100         unregister_netdev(dev);
1101         free_netdev(dev);
1102         return 0;
1103 }
1104
1105 static struct platform_driver cpmac_driver = {
1106         .driver.name = "cpmac",
1107         .driver.owner = THIS_MODULE,
1108         .probe = cpmac_probe,
1109         .remove = __devexit_p(cpmac_remove),
1110 };
1111
1112 int __devinit cpmac_init(void)
1113 {
1114         u32 mask;
1115         int i, res;
1116
1117         cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1118
1119         if (!cpmac_mii.priv) {
1120                 printk(KERN_ERR "Can't ioremap mdio registers\n");
1121                 return -ENXIO;
1122         }
1123
1124 #warning FIXME: unhardcode gpio&reset bits
1125         ar7_gpio_disable(26);
1126         ar7_gpio_disable(27);
1127         ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1128         ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1129         ar7_device_reset(AR7_RESET_BIT_EPHY);
1130
1131         cpmac_mii.reset(&cpmac_mii);
1132
1133         for (i = 0; i < 300000; i++)
1134                 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1135                         break;
1136                 else
1137                         cpu_relax();
1138
1139         mask &= 0x7fffffff;
1140         if (mask & (mask - 1)) {
1141                 external_switch = 1;
1142                 mask = 0;
1143         }
1144
1145         cpmac_mii.phy_mask = ~(mask | 0x80000000);
1146         snprintf(cpmac_mii.id, MII_BUS_ID_SIZE, "0");
1147
1148         res = mdiobus_register(&cpmac_mii);
1149         if (res)
1150                 goto fail_mii;
1151
1152         res = platform_driver_register(&cpmac_driver);
1153         if (res)
1154                 goto fail_cpmac;
1155
1156         return 0;
1157
1158 fail_cpmac:
1159         mdiobus_unregister(&cpmac_mii);
1160
1161 fail_mii:
1162         iounmap(cpmac_mii.priv);
1163
1164         return res;
1165 }
1166
1167 void __devexit cpmac_exit(void)
1168 {
1169         platform_driver_unregister(&cpmac_driver);
1170         mdiobus_unregister(&cpmac_mii);
1171         iounmap(cpmac_mii.priv);
1172 }
1173
1174 module_init(cpmac_init);
1175 module_exit(cpmac_exit);