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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #ifdef CONFIG_R8169_NAPI
  32 #define NAPI_SUFFIX     "-NAPI"
  33 #else
  34 #define NAPI_SUFFIX     ""
  35 #endif
  36
  37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  38 #define MODULENAME "r8169"
  39 #define PFX MODULENAME ": "
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  46         }
  47 #define dprintk(fmt, args...) \
  48         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  49 #else
  50 #define assert(expr) do {} while (0)
  51 #define dprintk(fmt, args...)   do {} while (0)
  52 #endif /* RTL8169_DEBUG */
  53
  54 #define R8169_MSG_DEFAULT \
  55         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  56
  57 #define TX_BUFFS_AVAIL(tp) \
  58         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  59
  60 #ifdef CONFIG_R8169_NAPI
  61 #define rtl8169_rx_skb                  netif_receive_skb
  62 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_receive_skb
  63 #define rtl8169_rx_quota(count, quota)  min(count, quota)
  64 #else
  65 #define rtl8169_rx_skb                  netif_rx
  66 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_rx
  67 #define rtl8169_rx_quota(count, quota)  count
  68 #endif
  69
  70 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  71 static const int max_interrupt_work = 20;
  72
  73 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  74    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  75 static const int multicast_filter_limit = 32;
  76
  77 /* MAC address length */
  78 #define MAC_ADDR_LEN    6
  79
  80 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  81 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  82 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  83 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  84 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  85 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  86 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  87
  88 #define R8169_REGS_SIZE         256
  89 #define R8169_NAPI_WEIGHT       64
  90 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  91 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  92 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  93 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  94 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  95
  96 #define RTL8169_TX_TIMEOUT      (6*HZ)
  97 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  98
  99 /* write/read MMIO register */
 100 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 101 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 102 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 103 #define RTL_R8(reg)             readb (ioaddr + (reg))
 104 #define RTL_R16(reg)            readw (ioaddr + (reg))
 105 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 106
 107 enum mac_version {
 108         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 109         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 110         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 111         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 112         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 113         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 114         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 115         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 116         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 117         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 118         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 119         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 120         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 121         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 122         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 123         RTL_GIGA_MAC_VER_20 = 0x14  // 8168C
 124 };
 125
 126 #define _R(NAME,MAC,MASK) \
 127         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 128
 129 static const struct {
 130         const char *name;
 131         u8 mac_version;
 132         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 133 } rtl_chip_info[] = {
 134         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 135         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 136         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 137         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 138         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 139         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 140         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 141         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 142         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 143         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 144         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 145         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 146         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 147         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 148         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 149         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880)  // PCI-E
 150 };
 151 #undef _R
 152
 153 enum cfg_version {
 154         RTL_CFG_0 = 0x00,
 155         RTL_CFG_1,
 156         RTL_CFG_2
 157 };
 158
 159 static void rtl_hw_start_8169(struct net_device *);
 160 static void rtl_hw_start_8168(struct net_device *);
 161 static void rtl_hw_start_8101(struct net_device *);
 162
 163 static struct pci_device_id rtl8169_pci_tbl[] = {
 164         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 165         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 166         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 167         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 168         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 169         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 170         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 171         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 172         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 173                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 174         { 0x0001,                               0x8168,
 175                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 176         {0,},
 177 };
 178
 179 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 180
 181 static int rx_copybreak = 200;
 182 static int use_dac;
 183 static struct {
 184         u32 msg_enable;
 185 } debug = { -1 };
 186
 187 enum rtl_registers {
 188         MAC0            = 0,    /* Ethernet hardware address. */
 189         MAC4            = 4,
 190         MAR0            = 8,    /* Multicast filter. */
 191         CounterAddrLow          = 0x10,
 192         CounterAddrHigh         = 0x14,
 193         TxDescStartAddrLow      = 0x20,
 194         TxDescStartAddrHigh     = 0x24,
 195         TxHDescStartAddrLow     = 0x28,
 196         TxHDescStartAddrHigh    = 0x2c,
 197         FLASH           = 0x30,
 198         ERSR            = 0x36,
 199         ChipCmd         = 0x37,
 200         TxPoll          = 0x38,
 201         IntrMask        = 0x3c,
 202         IntrStatus      = 0x3e,
 203         TxConfig        = 0x40,
 204         RxConfig        = 0x44,
 205         RxMissed        = 0x4c,
 206         Cfg9346         = 0x50,
 207         Config0         = 0x51,
 208         Config1         = 0x52,
 209         Config2         = 0x53,
 210         Config3         = 0x54,
 211         Config4         = 0x55,
 212         Config5         = 0x56,
 213         MultiIntr       = 0x5c,
 214         PHYAR           = 0x60,
 215         TBICSR          = 0x64,
 216         TBI_ANAR        = 0x68,
 217         TBI_LPAR        = 0x6a,
 218         PHYstatus       = 0x6c,
 219         RxMaxSize       = 0xda,
 220         CPlusCmd        = 0xe0,
 221         IntrMitigate    = 0xe2,
 222         RxDescAddrLow   = 0xe4,
 223         RxDescAddrHigh  = 0xe8,
 224         EarlyTxThres    = 0xec,
 225         FuncEvent       = 0xf0,
 226         FuncEventMask   = 0xf4,
 227         FuncPresetState = 0xf8,
 228         FuncForceEvent  = 0xfc,
 229 };
 230
 231 enum rtl_register_content {
 232         /* InterruptStatusBits */
 233         SYSErr          = 0x8000,
 234         PCSTimeout      = 0x4000,
 235         SWInt           = 0x0100,
 236         TxDescUnavail   = 0x0080,
 237         RxFIFOOver      = 0x0040,
 238         LinkChg         = 0x0020,
 239         RxOverflow      = 0x0010,
 240         TxErr           = 0x0008,
 241         TxOK            = 0x0004,
 242         RxErr           = 0x0002,
 243         RxOK            = 0x0001,
 244
 245         /* RxStatusDesc */
 246         RxFOVF  = (1 << 23),
 247         RxRWT   = (1 << 22),
 248         RxRES   = (1 << 21),
 249         RxRUNT  = (1 << 20),
 250         RxCRC   = (1 << 19),
 251
 252         /* ChipCmdBits */
 253         CmdReset        = 0x10,
 254         CmdRxEnb        = 0x08,
 255         CmdTxEnb        = 0x04,
 256         RxBufEmpty      = 0x01,
 257
 258         /* TXPoll register p.5 */
 259         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 260         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 261         FSWInt          = 0x01,         /* Forced software interrupt */
 262
 263         /* Cfg9346Bits */
 264         Cfg9346_Lock    = 0x00,
 265         Cfg9346_Unlock  = 0xc0,
 266
 267         /* rx_mode_bits */
 268         AcceptErr       = 0x20,
 269         AcceptRunt      = 0x10,
 270         AcceptBroadcast = 0x08,
 271         AcceptMulticast = 0x04,
 272         AcceptMyPhys    = 0x02,
 273         AcceptAllPhys   = 0x01,
 274
 275         /* RxConfigBits */
 276         RxCfgFIFOShift  = 13,
 277         RxCfgDMAShift   =  8,
 278
 279         /* TxConfigBits */
 280         TxInterFrameGapShift = 24,
 281         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 282
 283         /* Config1 register p.24 */
 284         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 285         PMEnable        = (1 << 0),     /* Power Management Enable */
 286
 287         /* Config2 register p. 25 */
 288         PCI_Clock_66MHz = 0x01,
 289         PCI_Clock_33MHz = 0x00,
 290
 291         /* Config3 register p.25 */
 292         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 293         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 294
 295         /* Config5 register p.27 */
 296         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 297         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 298         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 299         LanWake         = (1 << 1),     /* LanWake enable/disable */
 300         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 301
 302         /* TBICSR p.28 */
 303         TBIReset        = 0x80000000,
 304         TBILoopback     = 0x40000000,
 305         TBINwEnable     = 0x20000000,
 306         TBINwRestart    = 0x10000000,
 307         TBILinkOk       = 0x02000000,
 308         TBINwComplete   = 0x01000000,
 309
 310         /* CPlusCmd p.31 */
 311         PktCntrDisable  = (1 << 7),     // 8168
 312         RxVlan          = (1 << 6),
 313         RxChkSum        = (1 << 5),
 314         PCIDAC          = (1 << 4),
 315         PCIMulRW        = (1 << 3),
 316         INTT_0          = 0x0000,       // 8168
 317         INTT_1          = 0x0001,       // 8168
 318         INTT_2          = 0x0002,       // 8168
 319         INTT_3          = 0x0003,       // 8168
 320
 321         /* rtl8169_PHYstatus */
 322         TBI_Enable      = 0x80,
 323         TxFlowCtrl      = 0x40,
 324         RxFlowCtrl      = 0x20,
 325         _1000bpsF       = 0x10,
 326         _100bps         = 0x08,
 327         _10bps          = 0x04,
 328         LinkStatus      = 0x02,
 329         FullDup         = 0x01,
 330
 331         /* _TBICSRBit */
 332         TBILinkOK       = 0x02000000,
 333
 334         /* DumpCounterCommand */
 335         CounterDump     = 0x8,
 336 };
 337
 338 enum desc_status_bit {
 339         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 340         RingEnd         = (1 << 30), /* End of descriptor ring */
 341         FirstFrag       = (1 << 29), /* First segment of a packet */
 342         LastFrag        = (1 << 28), /* Final segment of a packet */
 343
 344         /* Tx private */
 345         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 346         MSSShift        = 16,        /* MSS value position */
 347         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 348         IPCS            = (1 << 18), /* Calculate IP checksum */
 349         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 350         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 351         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 352
 353         /* Rx private */
 354         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 355         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 356
 357 #define RxProtoUDP      (PID1)
 358 #define RxProtoTCP      (PID0)
 359 #define RxProtoIP       (PID1 | PID0)
 360 #define RxProtoMask     RxProtoIP
 361
 362         IPFail          = (1 << 16), /* IP checksum failed */
 363         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 364         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 365         RxVlanTag       = (1 << 16), /* VLAN tag available */
 366 };
 367
 368 #define RsvdMask        0x3fffc000
 369
 370 struct TxDesc {
 371         __le32 opts1;
 372         __le32 opts2;
 373         __le64 addr;
 374 };
 375
 376 struct RxDesc {
 377         __le32 opts1;
 378         __le32 opts2;
 379         __le64 addr;
 380 };
 381
 382 struct ring_info {
 383         struct sk_buff  *skb;
 384         u32             len;
 385         u8              __pad[sizeof(void *) - sizeof(u32)];
 386 };
 387
 388 enum features {
 389         RTL_FEATURE_WOL = (1 << 0),
 390         RTL_FEATURE_MSI = (1 << 1),
 391 };
 392
 393 struct rtl8169_private {
 394         void __iomem *mmio_addr;        /* memory map physical address */
 395         struct pci_dev *pci_dev;        /* Index of PCI device */
 396         struct net_device *dev;
 397 #ifdef CONFIG_R8169_NAPI
 398         struct napi_struct napi;
 399 #endif
 400         spinlock_t lock;                /* spin lock flag */
 401         u32 msg_enable;
 402         int chipset;
 403         int mac_version;
 404         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 405         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 406         u32 dirty_rx;
 407         u32 dirty_tx;
 408         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 409         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 410         dma_addr_t TxPhyAddr;
 411         dma_addr_t RxPhyAddr;
 412         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 413         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 414         unsigned align;
 415         unsigned rx_buf_sz;
 416         struct timer_list timer;
 417         u16 cp_cmd;
 418         u16 intr_event;
 419         u16 napi_event;
 420         u16 intr_mask;
 421         int phy_auto_nego_reg;
 422         int phy_1000_ctrl_reg;
 423 #ifdef CONFIG_R8169_VLAN
 424         struct vlan_group *vlgrp;
 425 #endif
 426         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 427         void (*get_settings)(struct net_device *, struct ethtool_cmd *);
 428         void (*phy_reset_enable)(void __iomem *);
 429         void (*hw_start)(struct net_device *);
 430         unsigned int (*phy_reset_pending)(void __iomem *);
 431         unsigned int (*link_ok)(void __iomem *);
 432         struct delayed_work task;
 433         unsigned features;
 434 };
 435
 436 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 437 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 438 module_param(rx_copybreak, int, 0);
 439 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 440 module_param(use_dac, int, 0);
 441 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 442 module_param_named(debug, debug.msg_enable, int, 0);
 443 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 444 MODULE_LICENSE("GPL");
 445 MODULE_VERSION(RTL8169_VERSION);
 446
 447 static int rtl8169_open(struct net_device *dev);
 448 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 449 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 450 static int rtl8169_init_ring(struct net_device *dev);
 451 static void rtl_hw_start(struct net_device *dev);
 452 static int rtl8169_close(struct net_device *dev);
 453 static void rtl_set_rx_mode(struct net_device *dev);
 454 static void rtl8169_tx_timeout(struct net_device *dev);
 455 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 456 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 457                                 void __iomem *, u32 budget);
 458 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 459 static void rtl8169_down(struct net_device *dev);
 460 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 461
 462 #ifdef CONFIG_R8169_NAPI
 463 static int rtl8169_poll(struct napi_struct *napi, int budget);
 464 #endif
 465
 466 static const unsigned int rtl8169_rx_config =
 467         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 468
 469 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 470 {
 471         int i;
 472
 473         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 474
 475         for (i = 20; i > 0; i--) {
 476                 /*
 477                  * Check if the RTL8169 has completed writing to the specified
 478                  * MII register.
 479                  */
 480                 if (!(RTL_R32(PHYAR) & 0x80000000))
 481                         break;
 482                 udelay(25);
 483         }
 484 }
 485
 486 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 487 {
 488         int i, value = -1;
 489
 490         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 491
 492         for (i = 20; i > 0; i--) {
 493                 /*
 494                  * Check if the RTL8169 has completed retrieving data from
 495                  * the specified MII register.
 496                  */
 497                 if (RTL_R32(PHYAR) & 0x80000000) {
 498                         value = RTL_R32(PHYAR) & 0xffff;
 499                         break;
 500                 }
 501                 udelay(25);
 502         }
 503         return value;
 504 }
 505
 506 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 507 {
 508         RTL_W16(IntrMask, 0x0000);
 509
 510         RTL_W16(IntrStatus, 0xffff);
 511 }
 512
 513 static void rtl8169_asic_down(void __iomem *ioaddr)
 514 {
 515         RTL_W8(ChipCmd, 0x00);
 516         rtl8169_irq_mask_and_ack(ioaddr);
 517         RTL_R16(CPlusCmd);
 518 }
 519
 520 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 521 {
 522         return RTL_R32(TBICSR) & TBIReset;
 523 }
 524
 525 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 526 {
 527         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 528 }
 529
 530 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 531 {
 532         return RTL_R32(TBICSR) & TBILinkOk;
 533 }
 534
 535 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 536 {
 537         return RTL_R8(PHYstatus) & LinkStatus;
 538 }
 539
 540 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 541 {
 542         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 543 }
 544
 545 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 546 {
 547         unsigned int val;
 548
 549         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 550         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 551 }
 552
 553 static void rtl8169_check_link_status(struct net_device *dev,
 554                                       struct rtl8169_private *tp,
 555                                       void __iomem *ioaddr)
 556 {
 557         unsigned long flags;
 558
 559         spin_lock_irqsave(&tp->lock, flags);
 560         if (tp->link_ok(ioaddr)) {
 561                 netif_carrier_on(dev);
 562                 if (netif_msg_ifup(tp))
 563                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 564         } else {
 565                 if (netif_msg_ifdown(tp))
 566                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 567                 netif_carrier_off(dev);
 568         }
 569         spin_unlock_irqrestore(&tp->lock, flags);
 570 }
 571
 572 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 573 {
 574         struct rtl8169_private *tp = netdev_priv(dev);
 575         void __iomem *ioaddr = tp->mmio_addr;
 576         u8 options;
 577
 578         wol->wolopts = 0;
 579
 580 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 581         wol->supported = WAKE_ANY;
 582
 583         spin_lock_irq(&tp->lock);
 584
 585         options = RTL_R8(Config1);
 586         if (!(options & PMEnable))
 587                 goto out_unlock;
 588
 589         options = RTL_R8(Config3);
 590         if (options & LinkUp)
 591                 wol->wolopts |= WAKE_PHY;
 592         if (options & MagicPacket)
 593                 wol->wolopts |= WAKE_MAGIC;
 594
 595         options = RTL_R8(Config5);
 596         if (options & UWF)
 597                 wol->wolopts |= WAKE_UCAST;
 598         if (options & BWF)
 599                 wol->wolopts |= WAKE_BCAST;
 600         if (options & MWF)
 601                 wol->wolopts |= WAKE_MCAST;
 602
 603 out_unlock:
 604         spin_unlock_irq(&tp->lock);
 605 }
 606
 607 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 608 {
 609         struct rtl8169_private *tp = netdev_priv(dev);
 610         void __iomem *ioaddr = tp->mmio_addr;
 611         unsigned int i;
 612         static struct {
 613                 u32 opt;
 614                 u16 reg;
 615                 u8  mask;
 616         } cfg[] = {
 617                 { WAKE_ANY,   Config1, PMEnable },
 618                 { WAKE_PHY,   Config3, LinkUp },
 619                 { WAKE_MAGIC, Config3, MagicPacket },
 620                 { WAKE_UCAST, Config5, UWF },
 621                 { WAKE_BCAST, Config5, BWF },
 622                 { WAKE_MCAST, Config5, MWF },
 623                 { WAKE_ANY,   Config5, LanWake }
 624         };
 625
 626         spin_lock_irq(&tp->lock);
 627
 628         RTL_W8(Cfg9346, Cfg9346_Unlock);
 629
 630         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 631                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 632                 if (wol->wolopts & cfg[i].opt)
 633                         options |= cfg[i].mask;
 634                 RTL_W8(cfg[i].reg, options);
 635         }
 636
 637         RTL_W8(Cfg9346, Cfg9346_Lock);
 638
 639         if (wol->wolopts)
 640                 tp->features |= RTL_FEATURE_WOL;
 641         else
 642                 tp->features &= ~RTL_FEATURE_WOL;
 643
 644         spin_unlock_irq(&tp->lock);
 645
 646         return 0;
 647 }
 648
 649 static void rtl8169_get_drvinfo(struct net_device *dev,
 650                                 struct ethtool_drvinfo *info)
 651 {
 652         struct rtl8169_private *tp = netdev_priv(dev);
 653
 654         strcpy(info->driver, MODULENAME);
 655         strcpy(info->version, RTL8169_VERSION);
 656         strcpy(info->bus_info, pci_name(tp->pci_dev));
 657 }
 658
 659 static int rtl8169_get_regs_len(struct net_device *dev)
 660 {
 661         return R8169_REGS_SIZE;
 662 }
 663
 664 static int rtl8169_set_speed_tbi(struct net_device *dev,
 665                                  u8 autoneg, u16 speed, u8 duplex)
 666 {
 667         struct rtl8169_private *tp = netdev_priv(dev);
 668         void __iomem *ioaddr = tp->mmio_addr;
 669         int ret = 0;
 670         u32 reg;
 671
 672         reg = RTL_R32(TBICSR);
 673         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 674             (duplex == DUPLEX_FULL)) {
 675                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 676         } else if (autoneg == AUTONEG_ENABLE)
 677                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 678         else {
 679                 if (netif_msg_link(tp)) {
 680                         printk(KERN_WARNING "%s: "
 681                                "incorrect speed setting refused in TBI mode\n",
 682                                dev->name);
 683                 }
 684                 ret = -EOPNOTSUPP;
 685         }
 686
 687         return ret;
 688 }
 689
 690 static int rtl8169_set_speed_xmii(struct net_device *dev,
 691                                   u8 autoneg, u16 speed, u8 duplex)
 692 {
 693         struct rtl8169_private *tp = netdev_priv(dev);
 694         void __iomem *ioaddr = tp->mmio_addr;
 695         int auto_nego, giga_ctrl;
 696
 697         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 698         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 699                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 700         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 701         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 702
 703         if (autoneg == AUTONEG_ENABLE) {
 704                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 705                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 706                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 707         } else {
 708                 if (speed == SPEED_10)
 709                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 710                 else if (speed == SPEED_100)
 711                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 712                 else if (speed == SPEED_1000)
 713                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 714
 715                 if (duplex == DUPLEX_HALF)
 716                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 717
 718                 if (duplex == DUPLEX_FULL)
 719                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 720
 721                 /* This tweak comes straight from Realtek's driver. */
 722                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 723                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 724                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
 725                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 726                 }
 727         }
 728
 729         /* The 8100e/8101e do Fast Ethernet only. */
 730         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 731             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 732             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
 733             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
 734                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 735                     netif_msg_link(tp)) {
 736                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 737                                dev->name);
 738                 }
 739                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 740         }
 741
 742         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 743
 744         if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 745             (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
 746                 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
 747                 mdio_write(ioaddr, 0x1f, 0x0000);
 748                 mdio_write(ioaddr, 0x0e, 0x0000);
 749         }
 750
 751         tp->phy_auto_nego_reg = auto_nego;
 752         tp->phy_1000_ctrl_reg = giga_ctrl;
 753
 754         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 755         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 756         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 757         return 0;
 758 }
 759
 760 static int rtl8169_set_speed(struct net_device *dev,
 761                              u8 autoneg, u16 speed, u8 duplex)
 762 {
 763         struct rtl8169_private *tp = netdev_priv(dev);
 764         int ret;
 765
 766         ret = tp->set_speed(dev, autoneg, speed, duplex);
 767
 768         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 769                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 770
 771         return ret;
 772 }
 773
 774 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 775 {
 776         struct rtl8169_private *tp = netdev_priv(dev);
 777         unsigned long flags;
 778         int ret;
 779
 780         spin_lock_irqsave(&tp->lock, flags);
 781         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 782         spin_unlock_irqrestore(&tp->lock, flags);
 783
 784         return ret;
 785 }
 786
 787 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 788 {
 789         struct rtl8169_private *tp = netdev_priv(dev);
 790
 791         return tp->cp_cmd & RxChkSum;
 792 }
 793
 794 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 795 {
 796         struct rtl8169_private *tp = netdev_priv(dev);
 797         void __iomem *ioaddr = tp->mmio_addr;
 798         unsigned long flags;
 799
 800         spin_lock_irqsave(&tp->lock, flags);
 801
 802         if (data)
 803                 tp->cp_cmd |= RxChkSum;
 804         else
 805                 tp->cp_cmd &= ~RxChkSum;
 806
 807         RTL_W16(CPlusCmd, tp->cp_cmd);
 808         RTL_R16(CPlusCmd);
 809
 810         spin_unlock_irqrestore(&tp->lock, flags);
 811
 812         return 0;
 813 }
 814
 815 #ifdef CONFIG_R8169_VLAN
 816
 817 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 818                                       struct sk_buff *skb)
 819 {
 820         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 821                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 822 }
 823
 824 static void rtl8169_vlan_rx_register(struct net_device *dev,
 825                                      struct vlan_group *grp)
 826 {
 827         struct rtl8169_private *tp = netdev_priv(dev);
 828         void __iomem *ioaddr = tp->mmio_addr;
 829         unsigned long flags;
 830
 831         spin_lock_irqsave(&tp->lock, flags);
 832         tp->vlgrp = grp;
 833         if (tp->vlgrp)
 834                 tp->cp_cmd |= RxVlan;
 835         else
 836                 tp->cp_cmd &= ~RxVlan;
 837         RTL_W16(CPlusCmd, tp->cp_cmd);
 838         RTL_R16(CPlusCmd);
 839         spin_unlock_irqrestore(&tp->lock, flags);
 840 }
 841
 842 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 843                                struct sk_buff *skb)
 844 {
 845         u32 opts2 = le32_to_cpu(desc->opts2);
 846         int ret;
 847
 848         if (tp->vlgrp && (opts2 & RxVlanTag)) {
 849                 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
 850                 ret = 0;
 851         } else
 852                 ret = -1;
 853         desc->opts2 = 0;
 854         return ret;
 855 }
 856
 857 #else /* !CONFIG_R8169_VLAN */
 858
 859 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 860                                       struct sk_buff *skb)
 861 {
 862         return 0;
 863 }
 864
 865 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 866                                struct sk_buff *skb)
 867 {
 868         return -1;
 869 }
 870
 871 #endif
 872
 873 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 874 {
 875         struct rtl8169_private *tp = netdev_priv(dev);
 876         void __iomem *ioaddr = tp->mmio_addr;
 877         u32 status;
 878
 879         cmd->supported =
 880                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 881         cmd->port = PORT_FIBRE;
 882         cmd->transceiver = XCVR_INTERNAL;
 883
 884         status = RTL_R32(TBICSR);
 885         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 886         cmd->autoneg = !!(status & TBINwEnable);
 887
 888         cmd->speed = SPEED_1000;
 889         cmd->duplex = DUPLEX_FULL; /* Always set */
 890 }
 891
 892 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 893 {
 894         struct rtl8169_private *tp = netdev_priv(dev);
 895         void __iomem *ioaddr = tp->mmio_addr;
 896         u8 status;
 897
 898         cmd->supported = SUPPORTED_10baseT_Half |
 899                          SUPPORTED_10baseT_Full |
 900                          SUPPORTED_100baseT_Half |
 901                          SUPPORTED_100baseT_Full |
 902                          SUPPORTED_1000baseT_Full |
 903                          SUPPORTED_Autoneg |
 904                          SUPPORTED_TP;
 905
 906         cmd->autoneg = 1;
 907         cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
 908
 909         if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
 910                 cmd->advertising |= ADVERTISED_10baseT_Half;
 911         if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
 912                 cmd->advertising |= ADVERTISED_10baseT_Full;
 913         if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
 914                 cmd->advertising |= ADVERTISED_100baseT_Half;
 915         if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
 916                 cmd->advertising |= ADVERTISED_100baseT_Full;
 917         if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
 918                 cmd->advertising |= ADVERTISED_1000baseT_Full;
 919
 920         status = RTL_R8(PHYstatus);
 921
 922         if (status & _1000bpsF)
 923                 cmd->speed = SPEED_1000;
 924         else if (status & _100bps)
 925                 cmd->speed = SPEED_100;
 926         else if (status & _10bps)
 927                 cmd->speed = SPEED_10;
 928
 929         if (status & TxFlowCtrl)
 930                 cmd->advertising |= ADVERTISED_Asym_Pause;
 931         if (status & RxFlowCtrl)
 932                 cmd->advertising |= ADVERTISED_Pause;
 933
 934         cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
 935                       DUPLEX_FULL : DUPLEX_HALF;
 936 }
 937
 938 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 939 {
 940         struct rtl8169_private *tp = netdev_priv(dev);
 941         unsigned long flags;
 942
 943         spin_lock_irqsave(&tp->lock, flags);
 944
 945         tp->get_settings(dev, cmd);
 946
 947         spin_unlock_irqrestore(&tp->lock, flags);
 948         return 0;
 949 }
 950
 951 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 952                              void *p)
 953 {
 954         struct rtl8169_private *tp = netdev_priv(dev);
 955         unsigned long flags;
 956
 957         if (regs->len > R8169_REGS_SIZE)
 958                 regs->len = R8169_REGS_SIZE;
 959
 960         spin_lock_irqsave(&tp->lock, flags);
 961         memcpy_fromio(p, tp->mmio_addr, regs->len);
 962         spin_unlock_irqrestore(&tp->lock, flags);
 963 }
 964
 965 static u32 rtl8169_get_msglevel(struct net_device *dev)
 966 {
 967         struct rtl8169_private *tp = netdev_priv(dev);
 968
 969         return tp->msg_enable;
 970 }
 971
 972 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 973 {
 974         struct rtl8169_private *tp = netdev_priv(dev);
 975
 976         tp->msg_enable = value;
 977 }
 978
 979 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 980         "tx_packets",
 981         "rx_packets",
 982         "tx_errors",
 983         "rx_errors",
 984         "rx_missed",
 985         "align_errors",
 986         "tx_single_collisions",
 987         "tx_multi_collisions",
 988         "unicast",
 989         "broadcast",
 990         "multicast",
 991         "tx_aborted",
 992         "tx_underrun",
 993 };
 994
 995 struct rtl8169_counters {
 996         __le64  tx_packets;
 997         __le64  rx_packets;
 998         __le64  tx_errors;
 999         __le32  rx_errors;
1000         __le16  rx_missed;
1001         __le16  align_errors;
1002         __le32  tx_one_collision;
1003         __le32  tx_multi_collision;
1004         __le64  rx_unicast;
1005         __le64  rx_broadcast;
1006         __le32  rx_multicast;
1007         __le16  tx_aborted;
1008         __le16  tx_underun;
1009 };
1010
1011 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1012 {
1013         switch (sset) {
1014         case ETH_SS_STATS:
1015                 return ARRAY_SIZE(rtl8169_gstrings);
1016         default:
1017                 return -EOPNOTSUPP;
1018         }
1019 }
1020
1021 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1022                                       struct ethtool_stats *stats, u64 *data)
1023 {
1024         struct rtl8169_private *tp = netdev_priv(dev);
1025         void __iomem *ioaddr = tp->mmio_addr;
1026         struct rtl8169_counters *counters;
1027         dma_addr_t paddr;
1028         u32 cmd;
1029
1030         ASSERT_RTNL();
1031
1032         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1033         if (!counters)
1034                 return;
1035
1036         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1037         cmd = (u64)paddr & DMA_32BIT_MASK;
1038         RTL_W32(CounterAddrLow, cmd);
1039         RTL_W32(CounterAddrLow, cmd | CounterDump);
1040
1041         while (RTL_R32(CounterAddrLow) & CounterDump) {
1042                 if (msleep_interruptible(1))
1043                         break;
1044         }
1045
1046         RTL_W32(CounterAddrLow, 0);
1047         RTL_W32(CounterAddrHigh, 0);
1048
1049         data[0] = le64_to_cpu(counters->tx_packets);
1050         data[1] = le64_to_cpu(counters->rx_packets);
1051         data[2] = le64_to_cpu(counters->tx_errors);
1052         data[3] = le32_to_cpu(counters->rx_errors);
1053         data[4] = le16_to_cpu(counters->rx_missed);
1054         data[5] = le16_to_cpu(counters->align_errors);
1055         data[6] = le32_to_cpu(counters->tx_one_collision);
1056         data[7] = le32_to_cpu(counters->tx_multi_collision);
1057         data[8] = le64_to_cpu(counters->rx_unicast);
1058         data[9] = le64_to_cpu(counters->rx_broadcast);
1059         data[10] = le32_to_cpu(counters->rx_multicast);
1060         data[11] = le16_to_cpu(counters->tx_aborted);
1061         data[12] = le16_to_cpu(counters->tx_underun);
1062
1063         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1064 }
1065
1066 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1067 {
1068         switch(stringset) {
1069         case ETH_SS_STATS:
1070                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1071                 break;
1072         }
1073 }
1074
1075 static const struct ethtool_ops rtl8169_ethtool_ops = {
1076         .get_drvinfo            = rtl8169_get_drvinfo,
1077         .get_regs_len           = rtl8169_get_regs_len,
1078         .get_link               = ethtool_op_get_link,
1079         .get_settings           = rtl8169_get_settings,
1080         .set_settings           = rtl8169_set_settings,
1081         .get_msglevel           = rtl8169_get_msglevel,
1082         .set_msglevel           = rtl8169_set_msglevel,
1083         .get_rx_csum            = rtl8169_get_rx_csum,
1084         .set_rx_csum            = rtl8169_set_rx_csum,
1085         .set_tx_csum            = ethtool_op_set_tx_csum,
1086         .set_sg                 = ethtool_op_set_sg,
1087         .set_tso                = ethtool_op_set_tso,
1088         .get_regs               = rtl8169_get_regs,
1089         .get_wol                = rtl8169_get_wol,
1090         .set_wol                = rtl8169_set_wol,
1091         .get_strings            = rtl8169_get_strings,
1092         .get_sset_count         = rtl8169_get_sset_count,
1093         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1094 };
1095
1096 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1097                                        int bitnum, int bitval)
1098 {
1099         int val;
1100
1101         val = mdio_read(ioaddr, reg);
1102         val = (bitval == 1) ?
1103                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1104         mdio_write(ioaddr, reg, val & 0xffff);
1105 }
1106
1107 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1108                                     void __iomem *ioaddr)
1109 {
1110         /*
1111          * The driver currently handles the 8168Bf and the 8168Be identically
1112          * but they can be identified more specifically through the test below
1113          * if needed:
1114          *
1115          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1116          *
1117          * Same thing for the 8101Eb and the 8101Ec:
1118          *
1119          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1120          */
1121         const struct {
1122                 u32 mask;
1123                 u32 val;
1124                 int mac_version;
1125         } mac_info[] = {
1126                 /* 8168B family. */
1127                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1128                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1129                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1130                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_20 },
1131
1132                 /* 8168B family. */
1133                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1134                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1135                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1136                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1137
1138                 /* 8101 family. */
1139                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1140                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1141                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1142                 /* FIXME: where did these entries come from ? -- FR */
1143                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1144                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1145
1146                 /* 8110 family. */
1147                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1148                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1149                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1150                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1151                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1152                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1153
1154                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1155         }, *p = mac_info;
1156         u32 reg;
1157
1158         reg = RTL_R32(TxConfig);
1159         while ((reg & p->mask) != p->val)
1160                 p++;
1161         tp->mac_version = p->mac_version;
1162
1163         if (p->mask == 0x00000000) {
1164                 struct pci_dev *pdev = tp->pci_dev;
1165
1166                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1167         }
1168 }
1169
1170 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1171 {
1172         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1173 }
1174
1175 struct phy_reg {
1176         u16 reg;
1177         u16 val;
1178 };
1179
1180 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1181 {
1182         while (len-- > 0) {
1183                 mdio_write(ioaddr, regs->reg, regs->val);
1184                 regs++;
1185         }
1186 }
1187
1188 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1189 {
1190         struct {
1191                 u16 regs[5]; /* Beware of bit-sign propagation */
1192         } phy_magic[5] = { {
1193                 { 0x0000,       //w 4 15 12 0
1194                   0x00a1,       //w 3 15 0 00a1
1195                   0x0008,       //w 2 15 0 0008
1196                   0x1020,       //w 1 15 0 1020
1197                   0x1000 } },{  //w 0 15 0 1000
1198                 { 0x7000,       //w 4 15 12 7
1199                   0xff41,       //w 3 15 0 ff41
1200                   0xde60,       //w 2 15 0 de60
1201                   0x0140,       //w 1 15 0 0140
1202                   0x0077 } },{  //w 0 15 0 0077
1203                 { 0xa000,       //w 4 15 12 a
1204                   0xdf01,       //w 3 15 0 df01
1205                   0xdf20,       //w 2 15 0 df20
1206                   0xff95,       //w 1 15 0 ff95
1207                   0xfa00 } },{  //w 0 15 0 fa00
1208                 { 0xb000,       //w 4 15 12 b
1209                   0xff41,       //w 3 15 0 ff41
1210                   0xde20,       //w 2 15 0 de20
1211                   0x0140,       //w 1 15 0 0140
1212                   0x00bb } },{  //w 0 15 0 00bb
1213                 { 0xf000,       //w 4 15 12 f
1214                   0xdf01,       //w 3 15 0 df01
1215                   0xdf20,       //w 2 15 0 df20
1216                   0xff95,       //w 1 15 0 ff95
1217                   0xbf00 }      //w 0 15 0 bf00
1218                 }
1219         }, *p = phy_magic;
1220         unsigned int i;
1221
1222         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1223         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1224         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1225         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1226
1227         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1228                 int val, pos = 4;
1229
1230                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1231                 mdio_write(ioaddr, pos, val);
1232                 while (--pos >= 0)
1233                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1234                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1235                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1236         }
1237         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1238 }
1239
1240 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1241 {
1242         struct phy_reg phy_reg_init[] = {
1243                 { 0x1f, 0x0002 },
1244                 { 0x01, 0x90d0 },
1245                 { 0x1f, 0x0000 }
1246         };
1247
1248         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1249 }
1250
1251 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1252 {
1253         struct phy_reg phy_reg_init[] = {
1254                 { 0x1f, 0x0000 },
1255                 { 0x1d, 0x0f00 },
1256                 { 0x1f, 0x0002 },
1257                 { 0x0c, 0x1ec8 },
1258                 { 0x1f, 0x0000 }
1259         };
1260
1261         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1262 }
1263
1264 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1265 {
1266         struct phy_reg phy_reg_init[] = {
1267                 { 0x1f, 0x0001 },
1268                 { 0x12, 0x2300 },
1269                 { 0x1f, 0x0002 },
1270                 { 0x00, 0x88d4 },
1271                 { 0x01, 0x82b1 },
1272                 { 0x03, 0x7002 },
1273                 { 0x08, 0x9e30 },
1274                 { 0x09, 0x01f0 },
1275                 { 0x0a, 0x5500 },
1276                 { 0x0c, 0x00c8 },
1277                 { 0x1f, 0x0003 },
1278                 { 0x12, 0xc096 },
1279                 { 0x16, 0x000a },
1280                 { 0x1f, 0x0000 }
1281         };
1282
1283         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1284 }
1285
1286 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1287 {
1288         struct phy_reg phy_reg_init[] = {
1289                 { 0x1f, 0x0000 },
1290                 { 0x12, 0x2300 },
1291                 { 0x1f, 0x0003 },
1292                 { 0x16, 0x0f0a },
1293                 { 0x1f, 0x0000 },
1294                 { 0x1f, 0x0002 },
1295                 { 0x0c, 0x7eb8 },
1296                 { 0x1f, 0x0000 }
1297         };
1298
1299         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1300 }
1301
1302 static void rtl_hw_phy_config(struct net_device *dev)
1303 {
1304         struct rtl8169_private *tp = netdev_priv(dev);
1305         void __iomem *ioaddr = tp->mmio_addr;
1306
1307         rtl8169_print_mac_version(tp);
1308
1309         switch (tp->mac_version) {
1310         case RTL_GIGA_MAC_VER_01:
1311                 break;
1312         case RTL_GIGA_MAC_VER_02:
1313         case RTL_GIGA_MAC_VER_03:
1314                 rtl8169s_hw_phy_config(ioaddr);
1315                 break;
1316         case RTL_GIGA_MAC_VER_04:
1317                 rtl8169sb_hw_phy_config(ioaddr);
1318                 break;
1319         case RTL_GIGA_MAC_VER_18:
1320                 rtl8168cp_hw_phy_config(ioaddr);
1321                 break;
1322         case RTL_GIGA_MAC_VER_19:
1323                 rtl8168c_hw_phy_config(ioaddr);
1324                 break;
1325         case RTL_GIGA_MAC_VER_20:
1326                 rtl8168cx_hw_phy_config(ioaddr);
1327                 break;
1328         default:
1329                 break;
1330         }
1331 }
1332
1333 static void rtl8169_phy_timer(unsigned long __opaque)
1334 {
1335         struct net_device *dev = (struct net_device *)__opaque;
1336         struct rtl8169_private *tp = netdev_priv(dev);
1337         struct timer_list *timer = &tp->timer;
1338         void __iomem *ioaddr = tp->mmio_addr;
1339         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1340
1341         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1342
1343         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1344                 return;
1345
1346         spin_lock_irq(&tp->lock);
1347
1348         if (tp->phy_reset_pending(ioaddr)) {
1349                 /*
1350                  * A busy loop could burn quite a few cycles on nowadays CPU.
1351                  * Let's delay the execution of the timer for a few ticks.
1352                  */
1353                 timeout = HZ/10;
1354                 goto out_mod_timer;
1355         }
1356
1357         if (tp->link_ok(ioaddr))
1358                 goto out_unlock;
1359
1360         if (netif_msg_link(tp))
1361                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1362
1363         tp->phy_reset_enable(ioaddr);
1364
1365 out_mod_timer:
1366         mod_timer(timer, jiffies + timeout);
1367 out_unlock:
1368         spin_unlock_irq(&tp->lock);
1369 }
1370
1371 static inline void rtl8169_delete_timer(struct net_device *dev)
1372 {
1373         struct rtl8169_private *tp = netdev_priv(dev);
1374         struct timer_list *timer = &tp->timer;
1375
1376         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1377                 return;
1378
1379         del_timer_sync(timer);
1380 }
1381
1382 static inline void rtl8169_request_timer(struct net_device *dev)
1383 {
1384         struct rtl8169_private *tp = netdev_priv(dev);
1385         struct timer_list *timer = &tp->timer;
1386
1387         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1388                 return;
1389
1390         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1391 }
1392
1393 #ifdef CONFIG_NET_POLL_CONTROLLER
1394 /*
1395  * Polling 'interrupt' - used by things like netconsole to send skbs
1396  * without having to re-enable interrupts. It's not called while
1397  * the interrupt routine is executing.
1398  */
1399 static void rtl8169_netpoll(struct net_device *dev)
1400 {
1401         struct rtl8169_private *tp = netdev_priv(dev);
1402         struct pci_dev *pdev = tp->pci_dev;
1403
1404         disable_irq(pdev->irq);
1405         rtl8169_interrupt(pdev->irq, dev);
1406         enable_irq(pdev->irq);
1407 }
1408 #endif
1409
1410 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1411                                   void __iomem *ioaddr)
1412 {
1413         iounmap(ioaddr);
1414         pci_release_regions(pdev);
1415         pci_disable_device(pdev);
1416         free_netdev(dev);
1417 }
1418
1419 static void rtl8169_phy_reset(struct net_device *dev,
1420                               struct rtl8169_private *tp)
1421 {
1422         void __iomem *ioaddr = tp->mmio_addr;
1423         unsigned int i;
1424
1425         tp->phy_reset_enable(ioaddr);
1426         for (i = 0; i < 100; i++) {
1427                 if (!tp->phy_reset_pending(ioaddr))
1428                         return;
1429                 msleep(1);
1430         }
1431         if (netif_msg_link(tp))
1432                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1433 }
1434
1435 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1436 {
1437         void __iomem *ioaddr = tp->mmio_addr;
1438
1439         rtl_hw_phy_config(dev);
1440
1441         dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1442         RTL_W8(0x82, 0x01);
1443
1444         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1445
1446         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1447                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1448
1449         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1450                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1451                 RTL_W8(0x82, 0x01);
1452                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1453                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1454         }
1455
1456         rtl8169_phy_reset(dev, tp);
1457
1458         /*
1459          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1460          * only 8101. Don't panic.
1461          */
1462         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1463
1464         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1465                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1466 }
1467
1468 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1469 {
1470         void __iomem *ioaddr = tp->mmio_addr;
1471         u32 high;
1472         u32 low;
1473
1474         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1475         high = addr[4] | (addr[5] << 8);
1476
1477         spin_lock_irq(&tp->lock);
1478
1479         RTL_W8(Cfg9346, Cfg9346_Unlock);
1480         RTL_W32(MAC0, low);
1481         RTL_W32(MAC4, high);
1482         RTL_W8(Cfg9346, Cfg9346_Lock);
1483
1484         spin_unlock_irq(&tp->lock);
1485 }
1486
1487 static int rtl_set_mac_address(struct net_device *dev, void *p)
1488 {
1489         struct rtl8169_private *tp = netdev_priv(dev);
1490         struct sockaddr *addr = p;
1491
1492         if (!is_valid_ether_addr(addr->sa_data))
1493                 return -EADDRNOTAVAIL;
1494
1495         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1496
1497         rtl_rar_set(tp, dev->dev_addr);
1498
1499         return 0;
1500 }
1501
1502 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1503 {
1504         struct rtl8169_private *tp = netdev_priv(dev);
1505         struct mii_ioctl_data *data = if_mii(ifr);
1506
1507         if (!netif_running(dev))
1508                 return -ENODEV;
1509
1510         switch (cmd) {
1511         case SIOCGMIIPHY:
1512                 data->phy_id = 32; /* Internal PHY */
1513                 return 0;
1514
1515         case SIOCGMIIREG:
1516                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1517                 return 0;
1518
1519         case SIOCSMIIREG:
1520                 if (!capable(CAP_NET_ADMIN))
1521                         return -EPERM;
1522                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1523                 return 0;
1524         }
1525         return -EOPNOTSUPP;
1526 }
1527
1528 static const struct rtl_cfg_info {
1529         void (*hw_start)(struct net_device *);
1530         unsigned int region;
1531         unsigned int align;
1532         u16 intr_event;
1533         u16 napi_event;
1534         unsigned msi;
1535 } rtl_cfg_infos [] = {
1536         [RTL_CFG_0] = {
1537                 .hw_start       = rtl_hw_start_8169,
1538                 .region         = 1,
1539                 .align          = 0,
1540                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1541                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1542                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1543                 .msi            = 0
1544         },
1545         [RTL_CFG_1] = {
1546                 .hw_start       = rtl_hw_start_8168,
1547                 .region         = 2,
1548                 .align          = 8,
1549                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1550                                   TxErr | TxOK | RxOK | RxErr,
1551                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1552                 .msi            = RTL_FEATURE_MSI
1553         },
1554         [RTL_CFG_2] = {
1555                 .hw_start       = rtl_hw_start_8101,
1556                 .region         = 2,
1557                 .align          = 8,
1558                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1559                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1560                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1561                 .msi            = RTL_FEATURE_MSI
1562         }
1563 };
1564
1565 /* Cfg9346_Unlock assumed. */
1566 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1567                             const struct rtl_cfg_info *cfg)
1568 {
1569         unsigned msi = 0;
1570         u8 cfg2;
1571
1572         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1573         if (cfg->msi) {
1574                 if (pci_enable_msi(pdev)) {
1575                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1576                 } else {
1577                         cfg2 |= MSIEnable;
1578                         msi = RTL_FEATURE_MSI;
1579                 }
1580         }
1581         RTL_W8(Config2, cfg2);
1582         return msi;
1583 }
1584
1585 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1586 {
1587         if (tp->features & RTL_FEATURE_MSI) {
1588                 pci_disable_msi(pdev);
1589                 tp->features &= ~RTL_FEATURE_MSI;
1590         }
1591 }
1592
1593 static int __devinit
1594 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1595 {
1596         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1597         const unsigned int region = cfg->region;
1598         struct rtl8169_private *tp;
1599         struct net_device *dev;
1600         void __iomem *ioaddr;
1601         unsigned int i;
1602         int rc;
1603
1604         if (netif_msg_drv(&debug)) {
1605                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1606                        MODULENAME, RTL8169_VERSION);
1607         }
1608
1609         dev = alloc_etherdev(sizeof (*tp));
1610         if (!dev) {
1611                 if (netif_msg_drv(&debug))
1612                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1613                 rc = -ENOMEM;
1614                 goto out;
1615         }
1616
1617         SET_NETDEV_DEV(dev, &pdev->dev);
1618         tp = netdev_priv(dev);
1619         tp->dev = dev;
1620         tp->pci_dev = pdev;
1621         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1622
1623         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1624         rc = pci_enable_device(pdev);
1625         if (rc < 0) {
1626                 if (netif_msg_probe(tp))
1627                         dev_err(&pdev->dev, "enable failure\n");
1628                 goto err_out_free_dev_1;
1629         }
1630
1631         rc = pci_set_mwi(pdev);
1632         if (rc < 0)
1633                 goto err_out_disable_2;
1634
1635         /* make sure PCI base addr 1 is MMIO */
1636         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1637                 if (netif_msg_probe(tp)) {
1638                         dev_err(&pdev->dev,
1639                                 "region #%d not an MMIO resource, aborting\n",
1640                                 region);
1641                 }
1642                 rc = -ENODEV;
1643                 goto err_out_mwi_3;
1644         }
1645
1646         /* check for weird/broken PCI region reporting */
1647         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1648                 if (netif_msg_probe(tp)) {
1649                         dev_err(&pdev->dev,
1650                                 "Invalid PCI region size(s), aborting\n");
1651                 }
1652                 rc = -ENODEV;
1653                 goto err_out_mwi_3;
1654         }
1655
1656         rc = pci_request_regions(pdev, MODULENAME);
1657         if (rc < 0) {
1658                 if (netif_msg_probe(tp))
1659                         dev_err(&pdev->dev, "could not request regions.\n");
1660                 goto err_out_mwi_3;
1661         }
1662
1663         tp->cp_cmd = PCIMulRW | RxChkSum;
1664
1665         if ((sizeof(dma_addr_t) > 4) &&
1666             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1667                 tp->cp_cmd |= PCIDAC;
1668                 dev->features |= NETIF_F_HIGHDMA;
1669         } else {
1670                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1671                 if (rc < 0) {
1672                         if (netif_msg_probe(tp)) {
1673                                 dev_err(&pdev->dev,
1674                                         "DMA configuration failed.\n");
1675                         }
1676                         goto err_out_free_res_4;
1677                 }
1678         }
1679
1680         pci_set_master(pdev);
1681
1682         /* ioremap MMIO region */
1683         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1684         if (!ioaddr) {
1685                 if (netif_msg_probe(tp))
1686                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1687                 rc = -EIO;
1688                 goto err_out_free_res_4;
1689         }
1690
1691         /* Unneeded ? Don't mess with Mrs. Murphy. */
1692         rtl8169_irq_mask_and_ack(ioaddr);
1693
1694         /* Soft reset the chip. */
1695         RTL_W8(ChipCmd, CmdReset);
1696
1697         /* Check that the chip has finished the reset. */
1698         for (i = 0; i < 100; i++) {
1699                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1700                         break;
1701                 msleep_interruptible(1);
1702         }
1703
1704         /* Identify chip attached to board */
1705         rtl8169_get_mac_version(tp, ioaddr);
1706
1707         rtl8169_print_mac_version(tp);
1708
1709         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1710                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1711                         break;
1712         }
1713         if (i == ARRAY_SIZE(rtl_chip_info)) {
1714                 /* Unknown chip: assume array element #0, original RTL-8169 */
1715                 if (netif_msg_probe(tp)) {
1716                         dev_printk(KERN_DEBUG, &pdev->dev,
1717                                 "unknown chip version, assuming %s\n",
1718                                 rtl_chip_info[0].name);
1719                 }
1720                 i = 0;
1721         }
1722         tp->chipset = i;
1723
1724         RTL_W8(Cfg9346, Cfg9346_Unlock);
1725         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1726         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1727         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1728         RTL_W8(Cfg9346, Cfg9346_Lock);
1729
1730         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1731             (RTL_R8(PHYstatus) & TBI_Enable)) {
1732                 tp->set_speed = rtl8169_set_speed_tbi;
1733                 tp->get_settings = rtl8169_gset_tbi;
1734                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1735                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1736                 tp->link_ok = rtl8169_tbi_link_ok;
1737
1738                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1739         } else {
1740                 tp->set_speed = rtl8169_set_speed_xmii;
1741                 tp->get_settings = rtl8169_gset_xmii;
1742                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1743                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1744                 tp->link_ok = rtl8169_xmii_link_ok;
1745
1746                 dev->do_ioctl = rtl8169_ioctl;
1747         }
1748
1749         /* Get MAC address.  FIXME: read EEPROM */
1750         for (i = 0; i < MAC_ADDR_LEN; i++)
1751                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1752         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1753
1754         dev->open = rtl8169_open;
1755         dev->hard_start_xmit = rtl8169_start_xmit;
1756         dev->get_stats = rtl8169_get_stats;
1757         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1758         dev->stop = rtl8169_close;
1759         dev->tx_timeout = rtl8169_tx_timeout;
1760         dev->set_multicast_list = rtl_set_rx_mode;
1761         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1762         dev->irq = pdev->irq;
1763         dev->base_addr = (unsigned long) ioaddr;
1764         dev->change_mtu = rtl8169_change_mtu;
1765         dev->set_mac_address = rtl_set_mac_address;
1766
1767 #ifdef CONFIG_R8169_NAPI
1768         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1769 #endif
1770
1771 #ifdef CONFIG_R8169_VLAN
1772         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1773         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1774 #endif
1775
1776 #ifdef CONFIG_NET_POLL_CONTROLLER
1777         dev->poll_controller = rtl8169_netpoll;
1778 #endif
1779
1780         tp->intr_mask = 0xffff;
1781         tp->mmio_addr = ioaddr;
1782         tp->align = cfg->align;
1783         tp->hw_start = cfg->hw_start;
1784         tp->intr_event = cfg->intr_event;
1785         tp->napi_event = cfg->napi_event;
1786
1787         init_timer(&tp->timer);
1788         tp->timer.data = (unsigned long) dev;
1789         tp->timer.function = rtl8169_phy_timer;
1790
1791         spin_lock_init(&tp->lock);
1792
1793         rc = register_netdev(dev);
1794         if (rc < 0)
1795                 goto err_out_msi_5;
1796
1797         pci_set_drvdata(pdev, dev);
1798
1799         if (netif_msg_probe(tp)) {
1800                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1801
1802                 printk(KERN_INFO "%s: %s at 0x%lx, "
1803                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1804                        "XID %08x IRQ %d\n",
1805                        dev->name,
1806                        rtl_chip_info[tp->chipset].name,
1807                        dev->base_addr,
1808                        dev->dev_addr[0], dev->dev_addr[1],
1809                        dev->dev_addr[2], dev->dev_addr[3],
1810                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1811         }
1812
1813         rtl8169_init_phy(dev, tp);
1814
1815 out:
1816         return rc;
1817
1818 err_out_msi_5:
1819         rtl_disable_msi(pdev, tp);
1820         iounmap(ioaddr);
1821 err_out_free_res_4:
1822         pci_release_regions(pdev);
1823 err_out_mwi_3:
1824         pci_clear_mwi(pdev);
1825 err_out_disable_2:
1826         pci_disable_device(pdev);
1827 err_out_free_dev_1:
1828         free_netdev(dev);
1829         goto out;
1830 }
1831
1832 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1833 {
1834         struct net_device *dev = pci_get_drvdata(pdev);
1835         struct rtl8169_private *tp = netdev_priv(dev);
1836
1837         flush_scheduled_work();
1838
1839         unregister_netdev(dev);
1840         rtl_disable_msi(pdev, tp);
1841         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1842         pci_set_drvdata(pdev, NULL);
1843 }
1844
1845 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1846                                   struct net_device *dev)
1847 {
1848         unsigned int mtu = dev->mtu;
1849
1850         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1851 }
1852
1853 static int rtl8169_open(struct net_device *dev)
1854 {
1855         struct rtl8169_private *tp = netdev_priv(dev);
1856         struct pci_dev *pdev = tp->pci_dev;
1857         int retval = -ENOMEM;
1858
1859
1860         rtl8169_set_rxbufsize(tp, dev);
1861
1862         /*
1863          * Rx and Tx desscriptors needs 256 bytes alignment.
1864          * pci_alloc_consistent provides more.
1865          */
1866         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1867                                                &tp->TxPhyAddr);
1868         if (!tp->TxDescArray)
1869                 goto out;
1870
1871         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1872                                                &tp->RxPhyAddr);
1873         if (!tp->RxDescArray)
1874                 goto err_free_tx_0;
1875
1876         retval = rtl8169_init_ring(dev);
1877         if (retval < 0)
1878                 goto err_free_rx_1;
1879
1880         INIT_DELAYED_WORK(&tp->task, NULL);
1881
1882         smp_mb();
1883
1884         retval = request_irq(dev->irq, rtl8169_interrupt,
1885                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
1886                              dev->name, dev);
1887         if (retval < 0)
1888                 goto err_release_ring_2;
1889
1890 #ifdef CONFIG_R8169_NAPI
1891         napi_enable(&tp->napi);
1892 #endif
1893
1894         rtl_hw_start(dev);
1895
1896         rtl8169_request_timer(dev);
1897
1898         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1899 out:
1900         return retval;
1901
1902 err_release_ring_2:
1903         rtl8169_rx_clear(tp);
1904 err_free_rx_1:
1905         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1906                             tp->RxPhyAddr);
1907 err_free_tx_0:
1908         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1909                             tp->TxPhyAddr);
1910         goto out;
1911 }
1912
1913 static void rtl8169_hw_reset(void __iomem *ioaddr)
1914 {
1915         /* Disable interrupts */
1916         rtl8169_irq_mask_and_ack(ioaddr);
1917
1918         /* Reset the chipset */
1919         RTL_W8(ChipCmd, CmdReset);
1920
1921         /* PCI commit */
1922         RTL_R8(ChipCmd);
1923 }
1924
1925 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1926 {
1927         void __iomem *ioaddr = tp->mmio_addr;
1928         u32 cfg = rtl8169_rx_config;
1929
1930         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1931         RTL_W32(RxConfig, cfg);
1932
1933         /* Set DMA burst size and Interframe Gap Time */
1934         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1935                 (InterFrameGap << TxInterFrameGapShift));
1936 }
1937
1938 static void rtl_hw_start(struct net_device *dev)
1939 {
1940         struct rtl8169_private *tp = netdev_priv(dev);
1941         void __iomem *ioaddr = tp->mmio_addr;
1942         unsigned int i;
1943
1944         /* Soft reset the chip. */
1945         RTL_W8(ChipCmd, CmdReset);
1946
1947         /* Check that the chip has finished the reset. */
1948         for (i = 0; i < 100; i++) {
1949                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1950                         break;
1951                 msleep_interruptible(1);
1952         }
1953
1954         tp->hw_start(dev);
1955
1956         netif_start_queue(dev);
1957 }
1958
1959
1960 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1961                                          void __iomem *ioaddr)
1962 {
1963         /*
1964          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1965          * register to be written before TxDescAddrLow to work.
1966          * Switching from MMIO to I/O access fixes the issue as well.
1967          */
1968         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1969         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1970         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1971         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1972 }
1973
1974 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1975 {
1976         u16 cmd;
1977
1978         cmd = RTL_R16(CPlusCmd);
1979         RTL_W16(CPlusCmd, cmd);
1980         return cmd;
1981 }
1982
1983 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1984 {
1985         /* Low hurts. Let's disable the filtering. */
1986         RTL_W16(RxMaxSize, 16383);
1987 }
1988
1989 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1990 {
1991         struct {
1992                 u32 mac_version;
1993                 u32 clk;
1994                 u32 val;
1995         } cfg2_info [] = {
1996                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1997                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1998                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1999                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2000         }, *p = cfg2_info;
2001         unsigned int i;
2002         u32 clk;
2003
2004         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2005         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2006                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2007                         RTL_W32(0x7c, p->val);
2008                         break;
2009                 }
2010         }
2011 }
2012
2013 static void rtl_hw_start_8169(struct net_device *dev)
2014 {
2015         struct rtl8169_private *tp = netdev_priv(dev);
2016         void __iomem *ioaddr = tp->mmio_addr;
2017         struct pci_dev *pdev = tp->pci_dev;
2018
2019         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2020                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2021                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2022         }
2023
2024         RTL_W8(Cfg9346, Cfg9346_Unlock);
2025         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2026             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2027             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2028             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2029                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2030
2031         RTL_W8(EarlyTxThres, EarlyTxThld);
2032
2033         rtl_set_rx_max_size(ioaddr);
2034
2035         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2036             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2037             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2038             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2039                 rtl_set_rx_tx_config_registers(tp);
2040
2041         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2042
2043         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2044             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2045                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2046                         "Bit-3 and bit-14 MUST be 1\n");
2047                 tp->cp_cmd |= (1 << 14);
2048         }
2049
2050         RTL_W16(CPlusCmd, tp->cp_cmd);
2051
2052         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2053
2054         /*
2055          * Undocumented corner. Supposedly:
2056          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2057          */
2058         RTL_W16(IntrMitigate, 0x0000);
2059
2060         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2061
2062         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2063             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2064             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2065             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2066                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2067                 rtl_set_rx_tx_config_registers(tp);
2068         }
2069
2070         RTL_W8(Cfg9346, Cfg9346_Lock);
2071
2072         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2073         RTL_R8(IntrMask);
2074
2075         RTL_W32(RxMissed, 0);
2076
2077         rtl_set_rx_mode(dev);
2078
2079         /* no early-rx interrupts */
2080         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2081
2082         /* Enable all known interrupts by setting the interrupt mask. */
2083         RTL_W16(IntrMask, tp->intr_event);
2084 }
2085
2086 static void rtl_hw_start_8168(struct net_device *dev)
2087 {
2088         struct rtl8169_private *tp = netdev_priv(dev);
2089         void __iomem *ioaddr = tp->mmio_addr;
2090         struct pci_dev *pdev = tp->pci_dev;
2091         u8 ctl;
2092
2093         RTL_W8(Cfg9346, Cfg9346_Unlock);
2094
2095         RTL_W8(EarlyTxThres, EarlyTxThld);
2096
2097         rtl_set_rx_max_size(ioaddr);
2098
2099         rtl_set_rx_tx_config_registers(tp);
2100
2101         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2102
2103         RTL_W16(CPlusCmd, tp->cp_cmd);
2104
2105         /* Tx performance tweak. */
2106         pci_read_config_byte(pdev, 0x69, &ctl);
2107         ctl = (ctl & ~0x70) | 0x50;
2108         pci_write_config_byte(pdev, 0x69, ctl);
2109
2110         RTL_W16(IntrMitigate, 0x5151);
2111
2112         /* Work around for RxFIFO overflow. */
2113         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2114                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2115                 tp->intr_event &= ~RxOverflow;
2116         }
2117
2118         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2119
2120         RTL_W8(Cfg9346, Cfg9346_Lock);
2121
2122         RTL_R8(IntrMask);
2123
2124         RTL_W32(RxMissed, 0);
2125
2126         rtl_set_rx_mode(dev);
2127
2128         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2129
2130         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2131
2132         RTL_W16(IntrMask, tp->intr_event);
2133 }
2134
2135 static void rtl_hw_start_8101(struct net_device *dev)
2136 {
2137         struct rtl8169_private *tp = netdev_priv(dev);
2138         void __iomem *ioaddr = tp->mmio_addr;
2139         struct pci_dev *pdev = tp->pci_dev;
2140
2141         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2142             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2143                 pci_write_config_word(pdev, 0x68, 0x00);
2144                 pci_write_config_word(pdev, 0x69, 0x08);
2145         }
2146
2147         RTL_W8(Cfg9346, Cfg9346_Unlock);
2148
2149         RTL_W8(EarlyTxThres, EarlyTxThld);
2150
2151         rtl_set_rx_max_size(ioaddr);
2152
2153         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2154
2155         RTL_W16(CPlusCmd, tp->cp_cmd);
2156
2157         RTL_W16(IntrMitigate, 0x0000);
2158
2159         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2160
2161         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2162         rtl_set_rx_tx_config_registers(tp);
2163
2164         RTL_W8(Cfg9346, Cfg9346_Lock);
2165
2166         RTL_R8(IntrMask);
2167
2168         RTL_W32(RxMissed, 0);
2169
2170         rtl_set_rx_mode(dev);
2171
2172         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2173
2174         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2175
2176         RTL_W16(IntrMask, tp->intr_event);
2177 }
2178
2179 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2180 {
2181         struct rtl8169_private *tp = netdev_priv(dev);
2182         int ret = 0;
2183
2184         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2185                 return -EINVAL;
2186
2187         dev->mtu = new_mtu;
2188
2189         if (!netif_running(dev))
2190                 goto out;
2191
2192         rtl8169_down(dev);
2193
2194         rtl8169_set_rxbufsize(tp, dev);
2195
2196         ret = rtl8169_init_ring(dev);
2197         if (ret < 0)
2198                 goto out;
2199
2200 #ifdef CONFIG_R8169_NAPI
2201         napi_enable(&tp->napi);
2202 #endif
2203
2204         rtl_hw_start(dev);
2205
2206         rtl8169_request_timer(dev);
2207
2208 out:
2209         return ret;
2210 }
2211
2212 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2213 {
2214         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2215         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2216 }
2217
2218 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2219                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2220 {
2221         struct pci_dev *pdev = tp->pci_dev;
2222
2223         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2224                          PCI_DMA_FROMDEVICE);
2225         dev_kfree_skb(*sk_buff);
2226         *sk_buff = NULL;
2227         rtl8169_make_unusable_by_asic(desc);
2228 }
2229
2230 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2231 {
2232         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2233
2234         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2235 }
2236
2237 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2238                                        u32 rx_buf_sz)
2239 {
2240         desc->addr = cpu_to_le64(mapping);
2241         wmb();
2242         rtl8169_mark_to_asic(desc, rx_buf_sz);
2243 }
2244
2245 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2246                                             struct net_device *dev,
2247                                             struct RxDesc *desc, int rx_buf_sz,
2248                                             unsigned int align)
2249 {
2250         struct sk_buff *skb;
2251         dma_addr_t mapping;
2252         unsigned int pad;
2253
2254         pad = align ? align : NET_IP_ALIGN;
2255
2256         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2257         if (!skb)
2258                 goto err_out;
2259
2260         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2261
2262         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2263                                  PCI_DMA_FROMDEVICE);
2264
2265         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2266 out:
2267         return skb;
2268
2269 err_out:
2270         rtl8169_make_unusable_by_asic(desc);
2271         goto out;
2272 }
2273
2274 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2275 {
2276         unsigned int i;
2277
2278         for (i = 0; i < NUM_RX_DESC; i++) {
2279                 if (tp->Rx_skbuff[i]) {
2280                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2281                                             tp->RxDescArray + i);
2282                 }
2283         }
2284 }
2285
2286 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2287                            u32 start, u32 end)
2288 {
2289         u32 cur;
2290
2291         for (cur = start; end - cur != 0; cur++) {
2292                 struct sk_buff *skb;
2293                 unsigned int i = cur % NUM_RX_DESC;
2294
2295                 WARN_ON((s32)(end - cur) < 0);
2296
2297                 if (tp->Rx_skbuff[i])
2298                         continue;
2299
2300                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2301                                            tp->RxDescArray + i,
2302                                            tp->rx_buf_sz, tp->align);
2303                 if (!skb)
2304                         break;
2305
2306                 tp->Rx_skbuff[i] = skb;
2307         }
2308         return cur - start;
2309 }
2310
2311 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2312 {
2313         desc->opts1 |= cpu_to_le32(RingEnd);
2314 }
2315
2316 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2317 {
2318         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2319 }
2320
2321 static int rtl8169_init_ring(struct net_device *dev)
2322 {
2323         struct rtl8169_private *tp = netdev_priv(dev);
2324
2325         rtl8169_init_ring_indexes(tp);
2326
2327         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2328         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2329
2330         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2331                 goto err_out;
2332
2333         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2334
2335         return 0;
2336
2337 err_out:
2338         rtl8169_rx_clear(tp);
2339         return -ENOMEM;
2340 }
2341
2342 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2343                                  struct TxDesc *desc)
2344 {
2345         unsigned int len = tx_skb->len;
2346
2347         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2348         desc->opts1 = 0x00;
2349         desc->opts2 = 0x00;
2350         desc->addr = 0x00;
2351         tx_skb->len = 0;
2352 }
2353
2354 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2355 {
2356         unsigned int i;
2357
2358         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2359                 unsigned int entry = i % NUM_TX_DESC;
2360                 struct ring_info *tx_skb = tp->tx_skb + entry;
2361                 unsigned int len = tx_skb->len;
2362
2363                 if (len) {
2364                         struct sk_buff *skb = tx_skb->skb;
2365
2366                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2367                                              tp->TxDescArray + entry);
2368                         if (skb) {
2369                                 dev_kfree_skb(skb);
2370                                 tx_skb->skb = NULL;
2371                         }
2372                         tp->dev->stats.tx_dropped++;
2373                 }
2374         }
2375         tp->cur_tx = tp->dirty_tx = 0;
2376 }
2377
2378 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2379 {
2380         struct rtl8169_private *tp = netdev_priv(dev);
2381
2382         PREPARE_DELAYED_WORK(&tp->task, task);
2383         schedule_delayed_work(&tp->task, 4);
2384 }
2385
2386 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2387 {
2388         struct rtl8169_private *tp = netdev_priv(dev);
2389         void __iomem *ioaddr = tp->mmio_addr;
2390
2391         synchronize_irq(dev->irq);
2392
2393         /* Wait for any pending NAPI task to complete */
2394 #ifdef CONFIG_R8169_NAPI
2395         napi_disable(&tp->napi);
2396 #endif
2397
2398         rtl8169_irq_mask_and_ack(ioaddr);
2399
2400 #ifdef CONFIG_R8169_NAPI
2401         tp->intr_mask = 0xffff;
2402         RTL_W16(IntrMask, tp->intr_event);
2403         napi_enable(&tp->napi);
2404 #endif
2405 }
2406
2407 static void rtl8169_reinit_task(struct work_struct *work)
2408 {
2409         struct rtl8169_private *tp =
2410                 container_of(work, struct rtl8169_private, task.work);
2411         struct net_device *dev = tp->dev;
2412         int ret;
2413
2414         rtnl_lock();
2415
2416         if (!netif_running(dev))
2417                 goto out_unlock;
2418
2419         rtl8169_wait_for_quiescence(dev);
2420         rtl8169_close(dev);
2421
2422         ret = rtl8169_open(dev);
2423         if (unlikely(ret < 0)) {
2424                 if (net_ratelimit() && netif_msg_drv(tp)) {
2425                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2426                                " Rescheduling.\n", dev->name, ret);
2427                 }
2428                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2429         }
2430
2431 out_unlock:
2432         rtnl_unlock();
2433 }
2434
2435 static void rtl8169_reset_task(struct work_struct *work)
2436 {
2437         struct rtl8169_private *tp =
2438                 container_of(work, struct rtl8169_private, task.work);
2439         struct net_device *dev = tp->dev;
2440
2441         rtnl_lock();
2442
2443         if (!netif_running(dev))
2444                 goto out_unlock;
2445
2446         rtl8169_wait_for_quiescence(dev);
2447
2448         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2449         rtl8169_tx_clear(tp);
2450
2451         if (tp->dirty_rx == tp->cur_rx) {
2452                 rtl8169_init_ring_indexes(tp);
2453                 rtl_hw_start(dev);
2454                 netif_wake_queue(dev);
2455                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2456         } else {
2457                 if (net_ratelimit() && netif_msg_intr(tp)) {
2458                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2459                                dev->name);
2460                 }
2461                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2462         }
2463
2464 out_unlock:
2465         rtnl_unlock();
2466 }
2467
2468 static void rtl8169_tx_timeout(struct net_device *dev)
2469 {
2470         struct rtl8169_private *tp = netdev_priv(dev);
2471
2472         rtl8169_hw_reset(tp->mmio_addr);
2473
2474         /* Let's wait a bit while any (async) irq lands on */
2475         rtl8169_schedule_work(dev, rtl8169_reset_task);
2476 }
2477
2478 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2479                               u32 opts1)
2480 {
2481         struct skb_shared_info *info = skb_shinfo(skb);
2482         unsigned int cur_frag, entry;
2483         struct TxDesc * uninitialized_var(txd);
2484
2485         entry = tp->cur_tx;
2486         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2487                 skb_frag_t *frag = info->frags + cur_frag;
2488                 dma_addr_t mapping;
2489                 u32 status, len;
2490                 void *addr;
2491
2492                 entry = (entry + 1) % NUM_TX_DESC;
2493
2494                 txd = tp->TxDescArray + entry;
2495                 len = frag->size;
2496                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2497                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2498
2499                 /* anti gcc 2.95.3 bugware (sic) */
2500                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2501
2502                 txd->opts1 = cpu_to_le32(status);
2503                 txd->addr = cpu_to_le64(mapping);
2504
2505                 tp->tx_skb[entry].len = len;
2506         }
2507
2508         if (cur_frag) {
2509                 tp->tx_skb[entry].skb = skb;
2510                 txd->opts1 |= cpu_to_le32(LastFrag);
2511         }
2512
2513         return cur_frag;
2514 }
2515
2516 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2517 {
2518         if (dev->features & NETIF_F_TSO) {
2519                 u32 mss = skb_shinfo(skb)->gso_size;
2520
2521                 if (mss)
2522                         return LargeSend | ((mss & MSSMask) << MSSShift);
2523         }
2524         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2525                 const struct iphdr *ip = ip_hdr(skb);
2526
2527                 if (ip->protocol == IPPROTO_TCP)
2528                         return IPCS | TCPCS;
2529                 else if (ip->protocol == IPPROTO_UDP)
2530                         return IPCS | UDPCS;
2531                 WARN_ON(1);     /* we need a WARN() */
2532         }
2533         return 0;
2534 }
2535
2536 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2537 {
2538         struct rtl8169_private *tp = netdev_priv(dev);
2539         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2540         struct TxDesc *txd = tp->TxDescArray + entry;
2541         void __iomem *ioaddr = tp->mmio_addr;
2542         dma_addr_t mapping;
2543         u32 status, len;
2544         u32 opts1;
2545         int ret = NETDEV_TX_OK;
2546
2547         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2548                 if (netif_msg_drv(tp)) {
2549                         printk(KERN_ERR
2550                                "%s: BUG! Tx Ring full when queue awake!\n",
2551                                dev->name);
2552                 }
2553                 goto err_stop;
2554         }
2555
2556         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2557                 goto err_stop;
2558
2559         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2560
2561         frags = rtl8169_xmit_frags(tp, skb, opts1);
2562         if (frags) {
2563                 len = skb_headlen(skb);
2564                 opts1 |= FirstFrag;
2565         } else {
2566                 len = skb->len;
2567
2568                 if (unlikely(len < ETH_ZLEN)) {
2569                         if (skb_padto(skb, ETH_ZLEN))
2570                                 goto err_update_stats;
2571                         len = ETH_ZLEN;
2572                 }
2573
2574                 opts1 |= FirstFrag | LastFrag;
2575                 tp->tx_skb[entry].skb = skb;
2576         }
2577
2578         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2579
2580         tp->tx_skb[entry].len = len;
2581         txd->addr = cpu_to_le64(mapping);
2582         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2583
2584         wmb();
2585
2586         /* anti gcc 2.95.3 bugware (sic) */
2587         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2588         txd->opts1 = cpu_to_le32(status);
2589
2590         dev->trans_start = jiffies;
2591
2592         tp->cur_tx += frags + 1;
2593
2594         smp_wmb();
2595
2596         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2597
2598         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2599                 netif_stop_queue(dev);
2600                 smp_rmb();
2601                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2602                         netif_wake_queue(dev);
2603         }
2604
2605 out:
2606         return ret;
2607
2608 err_stop:
2609         netif_stop_queue(dev);
2610         ret = NETDEV_TX_BUSY;
2611 err_update_stats:
2612         dev->stats.tx_dropped++;
2613         goto out;
2614 }
2615
2616 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2617 {
2618         struct rtl8169_private *tp = netdev_priv(dev);
2619         struct pci_dev *pdev = tp->pci_dev;
2620         void __iomem *ioaddr = tp->mmio_addr;
2621         u16 pci_status, pci_cmd;
2622
2623         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2624         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2625
2626         if (netif_msg_intr(tp)) {
2627                 printk(KERN_ERR
2628                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2629                        dev->name, pci_cmd, pci_status);
2630         }
2631
2632         /*
2633          * The recovery sequence below admits a very elaborated explanation:
2634          * - it seems to work;
2635          * - I did not see what else could be done;
2636          * - it makes iop3xx happy.
2637          *
2638          * Feel free to adjust to your needs.
2639          */
2640         if (pdev->broken_parity_status)
2641                 pci_cmd &= ~PCI_COMMAND_PARITY;
2642         else
2643                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2644
2645         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2646
2647         pci_write_config_word(pdev, PCI_STATUS,
2648                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2649                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2650                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2651
2652         /* The infamous DAC f*ckup only happens at boot time */
2653         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2654                 if (netif_msg_intr(tp))
2655                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2656                 tp->cp_cmd &= ~PCIDAC;
2657                 RTL_W16(CPlusCmd, tp->cp_cmd);
2658                 dev->features &= ~NETIF_F_HIGHDMA;
2659         }
2660
2661         rtl8169_hw_reset(ioaddr);
2662
2663         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2664 }
2665
2666 static void rtl8169_tx_interrupt(struct net_device *dev,
2667                                  struct rtl8169_private *tp,
2668                                  void __iomem *ioaddr)
2669 {
2670         unsigned int dirty_tx, tx_left;
2671
2672         dirty_tx = tp->dirty_tx;
2673         smp_rmb();
2674         tx_left = tp->cur_tx - dirty_tx;
2675
2676         while (tx_left > 0) {
2677                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2678                 struct ring_info *tx_skb = tp->tx_skb + entry;
2679                 u32 len = tx_skb->len;
2680                 u32 status;
2681
2682                 rmb();
2683                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2684                 if (status & DescOwn)
2685                         break;
2686
2687                 dev->stats.tx_bytes += len;
2688                 dev->stats.tx_packets++;
2689
2690                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2691
2692                 if (status & LastFrag) {
2693                         dev_kfree_skb_irq(tx_skb->skb);
2694                         tx_skb->skb = NULL;
2695                 }
2696                 dirty_tx++;
2697                 tx_left--;
2698         }
2699
2700         if (tp->dirty_tx != dirty_tx) {
2701                 tp->dirty_tx = dirty_tx;
2702                 smp_wmb();
2703                 if (netif_queue_stopped(dev) &&
2704                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2705                         netif_wake_queue(dev);
2706                 }
2707                 /*
2708                  * 8168 hack: TxPoll requests are lost when the Tx packets are
2709                  * too close. Let's kick an extra TxPoll request when a burst
2710                  * of start_xmit activity is detected (if it is not detected,
2711                  * it is slow enough). -- FR
2712                  */
2713                 smp_rmb();
2714                 if (tp->cur_tx != dirty_tx)
2715                         RTL_W8(TxPoll, NPQ);
2716         }
2717 }
2718
2719 static inline int rtl8169_fragmented_frame(u32 status)
2720 {
2721         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2722 }
2723
2724 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2725 {
2726         u32 opts1 = le32_to_cpu(desc->opts1);
2727         u32 status = opts1 & RxProtoMask;
2728
2729         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2730             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2731             ((status == RxProtoIP) && !(opts1 & IPFail)))
2732                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2733         else
2734                 skb->ip_summed = CHECKSUM_NONE;
2735 }
2736
2737 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2738                                        struct rtl8169_private *tp, int pkt_size,
2739                                        dma_addr_t addr)
2740 {
2741         struct sk_buff *skb;
2742         bool done = false;
2743
2744         if (pkt_size >= rx_copybreak)
2745                 goto out;
2746
2747         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2748         if (!skb)
2749                 goto out;
2750
2751         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2752                                     PCI_DMA_FROMDEVICE);
2753         skb_reserve(skb, NET_IP_ALIGN);
2754         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2755         *sk_buff = skb;
2756         done = true;
2757 out:
2758         return done;
2759 }
2760
2761 static int rtl8169_rx_interrupt(struct net_device *dev,
2762                                 struct rtl8169_private *tp,
2763                                 void __iomem *ioaddr, u32 budget)
2764 {
2765         unsigned int cur_rx, rx_left;
2766         unsigned int delta, count;
2767
2768         cur_rx = tp->cur_rx;
2769         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2770         rx_left = rtl8169_rx_quota(rx_left, budget);
2771
2772         for (; rx_left > 0; rx_left--, cur_rx++) {
2773                 unsigned int entry = cur_rx % NUM_RX_DESC;
2774                 struct RxDesc *desc = tp->RxDescArray + entry;
2775                 u32 status;
2776
2777                 rmb();
2778                 status = le32_to_cpu(desc->opts1);
2779
2780                 if (status & DescOwn)
2781                         break;
2782                 if (unlikely(status & RxRES)) {
2783                         if (netif_msg_rx_err(tp)) {
2784                                 printk(KERN_INFO
2785                                        "%s: Rx ERROR. status = %08x\n",
2786                                        dev->name, status);
2787                         }
2788                         dev->stats.rx_errors++;
2789                         if (status & (RxRWT | RxRUNT))
2790                                 dev->stats.rx_length_errors++;
2791                         if (status & RxCRC)
2792                                 dev->stats.rx_crc_errors++;
2793                         if (status & RxFOVF) {
2794                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2795                                 dev->stats.rx_fifo_errors++;
2796                         }
2797                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2798                 } else {
2799                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2800                         dma_addr_t addr = le64_to_cpu(desc->addr);
2801                         int pkt_size = (status & 0x00001FFF) - 4;
2802                         struct pci_dev *pdev = tp->pci_dev;
2803
2804                         /*
2805                          * The driver does not support incoming fragmented
2806                          * frames. They are seen as a symptom of over-mtu
2807                          * sized frames.
2808                          */
2809                         if (unlikely(rtl8169_fragmented_frame(status))) {
2810                                 dev->stats.rx_dropped++;
2811                                 dev->stats.rx_length_errors++;
2812                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2813                                 continue;
2814                         }
2815
2816                         rtl8169_rx_csum(skb, desc);
2817
2818                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2819                                 pci_dma_sync_single_for_device(pdev, addr,
2820                                         pkt_size, PCI_DMA_FROMDEVICE);
2821                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2822                         } else {
2823                                 pci_unmap_single(pdev, addr, pkt_size,
2824                                                  PCI_DMA_FROMDEVICE);
2825                                 tp->Rx_skbuff[entry] = NULL;
2826                         }
2827
2828                         skb_put(skb, pkt_size);
2829                         skb->protocol = eth_type_trans(skb, dev);
2830
2831                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2832                                 rtl8169_rx_skb(skb);
2833
2834                         dev->last_rx = jiffies;
2835                         dev->stats.rx_bytes += pkt_size;
2836                         dev->stats.rx_packets++;
2837                 }
2838
2839                 /* Work around for AMD plateform. */
2840                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
2841                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2842                         desc->opts2 = 0;
2843                         cur_rx++;
2844                 }
2845         }
2846
2847         count = cur_rx - tp->cur_rx;
2848         tp->cur_rx = cur_rx;
2849
2850         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2851         if (!delta && count && netif_msg_intr(tp))
2852                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2853         tp->dirty_rx += delta;
2854
2855         /*
2856          * FIXME: until there is periodic timer to try and refill the ring,
2857          * a temporary shortage may definitely kill the Rx process.
2858          * - disable the asic to try and avoid an overflow and kick it again
2859          *   after refill ?
2860          * - how do others driver handle this condition (Uh oh...).
2861          */
2862         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2863                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2864
2865         return count;
2866 }
2867
2868 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2869 {
2870         struct net_device *dev = dev_instance;
2871         struct rtl8169_private *tp = netdev_priv(dev);
2872         int boguscnt = max_interrupt_work;
2873         void __iomem *ioaddr = tp->mmio_addr;
2874         int status;
2875         int handled = 0;
2876
2877         do {
2878                 status = RTL_R16(IntrStatus);
2879
2880                 /* hotplug/major error/no more work/shared irq */
2881                 if ((status == 0xFFFF) || !status)
2882                         break;
2883
2884                 handled = 1;
2885
2886                 if (unlikely(!netif_running(dev))) {
2887                         rtl8169_asic_down(ioaddr);
2888                         goto out;
2889                 }
2890
2891                 status &= tp->intr_mask;
2892                 RTL_W16(IntrStatus,
2893                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
2894
2895                 if (!(status & tp->intr_event))
2896                         break;
2897
2898                 /* Work around for rx fifo overflow */
2899                 if (unlikely(status & RxFIFOOver) &&
2900                     (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2901                         netif_stop_queue(dev);
2902                         rtl8169_tx_timeout(dev);
2903                         break;
2904                 }
2905
2906                 if (unlikely(status & SYSErr)) {
2907                         rtl8169_pcierr_interrupt(dev);
2908                         break;
2909                 }
2910
2911                 if (status & LinkChg)
2912                         rtl8169_check_link_status(dev, tp, ioaddr);
2913
2914 #ifdef CONFIG_R8169_NAPI
2915                 if (status & tp->napi_event) {
2916                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2917                         tp->intr_mask = ~tp->napi_event;
2918
2919                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2920                         __netif_rx_schedule(dev, &tp->napi);
2921                         else if (netif_msg_intr(tp)) {
2922                                 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2923                                        dev->name, status);
2924                         }
2925                 }
2926                 break;
2927 #else
2928                 /* Rx interrupt */
2929                 if (status & (RxOK | RxOverflow | RxFIFOOver))
2930                         rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2931
2932                 /* Tx interrupt */
2933                 if (status & (TxOK | TxErr))
2934                         rtl8169_tx_interrupt(dev, tp, ioaddr);
2935 #endif
2936
2937                 boguscnt--;
2938         } while (boguscnt > 0);
2939
2940         if (boguscnt <= 0) {
2941                 if (netif_msg_intr(tp) && net_ratelimit() ) {
2942                         printk(KERN_WARNING
2943                                "%s: Too much work at interrupt!\n", dev->name);
2944                 }
2945                 /* Clear all interrupt sources. */
2946                 RTL_W16(IntrStatus, 0xffff);
2947         }
2948 out:
2949         return IRQ_RETVAL(handled);
2950 }
2951
2952 #ifdef CONFIG_R8169_NAPI
2953 static int rtl8169_poll(struct napi_struct *napi, int budget)
2954 {
2955         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2956         struct net_device *dev = tp->dev;
2957         void __iomem *ioaddr = tp->mmio_addr;
2958         int work_done;
2959
2960         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2961         rtl8169_tx_interrupt(dev, tp, ioaddr);
2962
2963         if (work_done < budget) {
2964                 netif_rx_complete(dev, napi);
2965                 tp->intr_mask = 0xffff;
2966                 /*
2967                  * 20040426: the barrier is not strictly required but the
2968                  * behavior of the irq handler could be less predictable
2969                  * without it. Btw, the lack of flush for the posted pci
2970                  * write is safe - FR
2971                  */
2972                 smp_wmb();
2973                 RTL_W16(IntrMask, tp->intr_event);
2974         }
2975
2976         return work_done;
2977 }
2978 #endif
2979
2980 static void rtl8169_down(struct net_device *dev)
2981 {
2982         struct rtl8169_private *tp = netdev_priv(dev);
2983         void __iomem *ioaddr = tp->mmio_addr;
2984         unsigned int intrmask;
2985
2986         rtl8169_delete_timer(dev);
2987
2988         netif_stop_queue(dev);
2989
2990 #ifdef CONFIG_R8169_NAPI
2991         napi_disable(&tp->napi);
2992 #endif
2993
2994 core_down:
2995         spin_lock_irq(&tp->lock);
2996
2997         rtl8169_asic_down(ioaddr);
2998
2999         /* Update the error counts. */
3000         dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3001         RTL_W32(RxMissed, 0);
3002
3003         spin_unlock_irq(&tp->lock);
3004
3005         synchronize_irq(dev->irq);
3006
3007         /* Give a racing hard_start_xmit a few cycles to complete. */
3008         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3009
3010         /*
3011          * And now for the 50k$ question: are IRQ disabled or not ?
3012          *
3013          * Two paths lead here:
3014          * 1) dev->close
3015          *    -> netif_running() is available to sync the current code and the
3016          *       IRQ handler. See rtl8169_interrupt for details.
3017          * 2) dev->change_mtu
3018          *    -> rtl8169_poll can not be issued again and re-enable the
3019          *       interruptions. Let's simply issue the IRQ down sequence again.
3020          *
3021          * No loop if hotpluged or major error (0xffff).
3022          */
3023         intrmask = RTL_R16(IntrMask);
3024         if (intrmask && (intrmask != 0xffff))
3025                 goto core_down;
3026
3027         rtl8169_tx_clear(tp);
3028
3029         rtl8169_rx_clear(tp);
3030 }
3031
3032 static int rtl8169_close(struct net_device *dev)
3033 {
3034         struct rtl8169_private *tp = netdev_priv(dev);
3035         struct pci_dev *pdev = tp->pci_dev;
3036
3037         rtl8169_down(dev);
3038
3039         free_irq(dev->irq, dev);
3040
3041         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3042                             tp->RxPhyAddr);
3043         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3044                             tp->TxPhyAddr);
3045         tp->TxDescArray = NULL;
3046         tp->RxDescArray = NULL;
3047
3048         return 0;
3049 }
3050
3051 static void rtl_set_rx_mode(struct net_device *dev)
3052 {
3053         struct rtl8169_private *tp = netdev_priv(dev);
3054         void __iomem *ioaddr = tp->mmio_addr;
3055         unsigned long flags;
3056         u32 mc_filter[2];       /* Multicast hash filter */
3057         int rx_mode;
3058         u32 tmp = 0;
3059
3060         if (dev->flags & IFF_PROMISC) {
3061                 /* Unconditionally log net taps. */
3062                 if (netif_msg_link(tp)) {
3063                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3064                                dev->name);
3065                 }
3066                 rx_mode =
3067                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3068                     AcceptAllPhys;
3069                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3070         } else if ((dev->mc_count > multicast_filter_limit)
3071                    || (dev->flags & IFF_ALLMULTI)) {
3072                 /* Too many to filter perfectly -- accept all multicasts. */
3073                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3074                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3075         } else {
3076                 struct dev_mc_list *mclist;
3077                 unsigned int i;
3078
3079                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3080                 mc_filter[1] = mc_filter[0] = 0;
3081                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3082                      i++, mclist = mclist->next) {
3083                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3084                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3085                         rx_mode |= AcceptMulticast;
3086                 }
3087         }
3088
3089         spin_lock_irqsave(&tp->lock, flags);
3090
3091         tmp = rtl8169_rx_config | rx_mode |
3092               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3093
3094         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3095             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3096             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3097             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
3098             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3099             (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3100             (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
3101                 mc_filter[0] = 0xffffffff;
3102                 mc_filter[1] = 0xffffffff;
3103         }
3104
3105         RTL_W32(MAR0 + 0, mc_filter[0]);
3106         RTL_W32(MAR0 + 4, mc_filter[1]);
3107
3108         RTL_W32(RxConfig, tmp);
3109
3110         spin_unlock_irqrestore(&tp->lock, flags);
3111 }
3112
3113 /**
3114  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3115  *  @dev: The Ethernet Device to get statistics for
3116  *
3117  *  Get TX/RX statistics for rtl8169
3118  */
3119 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3120 {
3121         struct rtl8169_private *tp = netdev_priv(dev);
3122         void __iomem *ioaddr = tp->mmio_addr;
3123         unsigned long flags;
3124
3125         if (netif_running(dev)) {
3126                 spin_lock_irqsave(&tp->lock, flags);
3127                 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3128                 RTL_W32(RxMissed, 0);
3129                 spin_unlock_irqrestore(&tp->lock, flags);
3130         }
3131
3132         return &dev->stats;
3133 }
3134
3135 #ifdef CONFIG_PM
3136
3137 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3138 {
3139         struct net_device *dev = pci_get_drvdata(pdev);
3140         struct rtl8169_private *tp = netdev_priv(dev);
3141         void __iomem *ioaddr = tp->mmio_addr;
3142
3143         if (!netif_running(dev))
3144                 goto out_pci_suspend;
3145
3146         netif_device_detach(dev);
3147         netif_stop_queue(dev);
3148
3149         spin_lock_irq(&tp->lock);
3150
3151         rtl8169_asic_down(ioaddr);
3152
3153         dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3154         RTL_W32(RxMissed, 0);
3155
3156         spin_unlock_irq(&tp->lock);
3157
3158 out_pci_suspend:
3159         pci_save_state(pdev);
3160         pci_enable_wake(pdev, pci_choose_state(pdev, state),
3161                 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3162         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3163
3164         return 0;
3165 }
3166
3167 static int rtl8169_resume(struct pci_dev *pdev)
3168 {
3169         struct net_device *dev = pci_get_drvdata(pdev);
3170
3171         pci_set_power_state(pdev, PCI_D0);
3172         pci_restore_state(pdev);
3173         pci_enable_wake(pdev, PCI_D0, 0);
3174
3175         if (!netif_running(dev))
3176                 goto out;
3177
3178         netif_device_attach(dev);
3179
3180         rtl8169_schedule_work(dev, rtl8169_reset_task);
3181 out:
3182         return 0;
3183 }
3184
3185 #endif /* CONFIG_PM */
3186
3187 static struct pci_driver rtl8169_pci_driver = {
3188         .name           = MODULENAME,
3189         .id_table       = rtl8169_pci_tbl,
3190         .probe          = rtl8169_init_one,
3191         .remove         = __devexit_p(rtl8169_remove_one),
3192 #ifdef CONFIG_PM
3193         .suspend        = rtl8169_suspend,
3194         .resume         = rtl8169_resume,
3195 #endif
3196 };
3197
3198 static int __init rtl8169_init_module(void)
3199 {
3200         return pci_register_driver(&rtl8169_pci_driver);
3201 }
3202
3203 static void __exit rtl8169_cleanup_module(void)
3204 {
3205         pci_unregister_driver(&rtl8169_pci_driver);
3206 }
3207
3208 module_init(rtl8169_init_module);
3209 module_exit(rtl8169_cleanup_module);