Pull bugzilla-5452 into release branch
[linux-2.6] / arch / mips / sibyte / bcm1480 / irq.c
1 /*
2  * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17  */
18 #include <linux/config.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/linkage.h>
22 #include <linux/interrupt.h>
23 #include <linux/spinlock.h>
24 #include <linux/mm.h>
25 #include <linux/slab.h>
26 #include <linux/kernel_stat.h>
27
28 #include <asm/errno.h>
29 #include <asm/signal.h>
30 #include <asm/system.h>
31 #include <asm/ptrace.h>
32 #include <asm/io.h>
33
34 #include <asm/sibyte/bcm1480_regs.h>
35 #include <asm/sibyte/bcm1480_int.h>
36 #include <asm/sibyte/bcm1480_scd.h>
37
38 #include <asm/sibyte/sb1250_uart.h>
39 #include <asm/sibyte/sb1250.h>
40
41 /*
42  * These are the routines that handle all the low level interrupt stuff.
43  * Actions handled here are: initialization of the interrupt map, requesting of
44  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
45  * for interrupt lines
46  */
47
48
49 #define shutdown_bcm1480_irq    disable_bcm1480_irq
50 static void end_bcm1480_irq(unsigned int irq);
51 static void enable_bcm1480_irq(unsigned int irq);
52 static void disable_bcm1480_irq(unsigned int irq);
53 static unsigned int startup_bcm1480_irq(unsigned int irq);
54 static void ack_bcm1480_irq(unsigned int irq);
55 #ifdef CONFIG_SMP
56 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
57 #endif
58
59 #ifdef CONFIG_PCI
60 extern unsigned long ht_eoi_space;
61 #endif
62
63 #ifdef CONFIG_KGDB
64 #include <asm/gdb-stub.h>
65 extern void breakpoint(void);
66 static int kgdb_irq;
67 #ifdef CONFIG_GDB_CONSOLE
68 extern void register_gdb_console(void);
69 #endif
70
71 /* kgdb is on when configured.  Pass "nokgdb" kernel arg to turn it off */
72 static int kgdb_flag = 1;
73 static int __init nokgdb(char *str)
74 {
75         kgdb_flag = 0;
76         return 1;
77 }
78 __setup("nokgdb", nokgdb);
79
80 /* Default to UART1 */
81 int kgdb_port = 1;
82 #ifdef CONFIG_SIBYTE_SB1250_DUART
83 extern char sb1250_duart_present[];
84 #endif
85 #endif
86
87 static struct hw_interrupt_type bcm1480_irq_type = {
88         .typename = "BCM1480-IMR",
89         .startup = startup_bcm1480_irq,
90         .shutdown = shutdown_bcm1480_irq,
91         .enable = enable_bcm1480_irq,
92         .disable = disable_bcm1480_irq,
93         .ack = ack_bcm1480_irq,
94         .end = end_bcm1480_irq,
95 #ifdef CONFIG_SMP
96         .set_affinity = bcm1480_set_affinity
97 #endif
98 };
99
100 /* Store the CPU id (not the logical number) */
101 int bcm1480_irq_owner[BCM1480_NR_IRQS];
102
103 DEFINE_SPINLOCK(bcm1480_imr_lock);
104
105 void bcm1480_mask_irq(int cpu, int irq)
106 {
107         unsigned long flags;
108         u64 cur_ints,hl_spacing;
109
110         spin_lock_irqsave(&bcm1480_imr_lock, flags);
111         hl_spacing = 0;
112         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
113                 hl_spacing = BCM1480_IMR_HL_SPACING;
114                 irq -= BCM1480_NR_IRQS_HALF;
115         }
116         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
117         cur_ints |= (((u64) 1) << irq);
118         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
119         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
120 }
121
122 void bcm1480_unmask_irq(int cpu, int irq)
123 {
124         unsigned long flags;
125         u64 cur_ints,hl_spacing;
126
127         spin_lock_irqsave(&bcm1480_imr_lock, flags);
128         hl_spacing = 0;
129         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
130                 hl_spacing = BCM1480_IMR_HL_SPACING;
131                 irq -= BCM1480_NR_IRQS_HALF;
132         }
133         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
134         cur_ints &= ~(((u64) 1) << irq);
135         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
136         spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
137 }
138
139 #ifdef CONFIG_SMP
140 static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
141 {
142         int i = 0, old_cpu, cpu, int_on, k;
143         u64 cur_ints;
144         irq_desc_t *desc = irq_desc + irq;
145         unsigned long flags;
146         unsigned int irq_dirty;
147
148         i = first_cpu(mask);
149         if (next_cpu(i, mask) <= NR_CPUS) {
150                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
151                 return;
152         }
153
154         /* Convert logical CPU to physical CPU */
155         cpu = cpu_logical_map(i);
156
157         /* Protect against other affinity changers and IMR manipulation */
158         spin_lock_irqsave(&desc->lock, flags);
159         spin_lock(&bcm1480_imr_lock);
160
161         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
162         old_cpu = bcm1480_irq_owner[irq];
163         irq_dirty = irq;
164         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
165                 irq_dirty -= BCM1480_NR_IRQS_HALF;
166         }
167
168         for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
169                 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
170                 int_on = !(cur_ints & (((u64) 1) << irq_dirty));
171                 if (int_on) {
172                         /* If it was on, mask it */
173                         cur_ints |= (((u64) 1) << irq_dirty);
174                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
175                 }
176                 bcm1480_irq_owner[irq] = cpu;
177                 if (int_on) {
178                         /* unmask for the new CPU */
179                         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
180                         cur_ints &= ~(((u64) 1) << irq_dirty);
181                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
182                 }
183         }
184         spin_unlock(&bcm1480_imr_lock);
185         spin_unlock_irqrestore(&desc->lock, flags);
186 }
187 #endif
188
189
190 /*****************************************************************************/
191
192 static unsigned int startup_bcm1480_irq(unsigned int irq)
193 {
194         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
195
196         return 0;               /* never anything pending */
197 }
198
199
200 static void disable_bcm1480_irq(unsigned int irq)
201 {
202         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
203 }
204
205 static void enable_bcm1480_irq(unsigned int irq)
206 {
207         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
208 }
209
210
211 static void ack_bcm1480_irq(unsigned int irq)
212 {
213         u64 pending;
214         unsigned int irq_dirty;
215         int k;
216
217         /*
218          * If the interrupt was an HT interrupt, now is the time to
219          * clear it.  NOTE: we assume the HT bridge was set up to
220          * deliver the interrupts to all CPUs (which makes affinity
221          * changing easier for us)
222          */
223         irq_dirty = irq;
224         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
225                 irq_dirty -= BCM1480_NR_IRQS_HALF;
226         }
227         for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
228                 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
229                                                 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
230                 pending &= ((u64)1 << (irq_dirty));
231                 if (pending) {
232 #ifdef CONFIG_SMP
233                         int i;
234                         for (i=0; i<NR_CPUS; i++) {
235                                 /*
236                                  * Clear for all CPUs so an affinity switch
237                                  * doesn't find an old status
238                                  */
239                                 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
240                                                                 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
241                         }
242 #else
243                         __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
244 #endif
245
246                         /*
247                          * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
248                          * Pass 2, the LDT world may be edge-triggered, but
249                          * this EOI shouldn't hurt.  If they are
250                          * level-sensitive, the EOI is required.
251                          */
252 #ifdef CONFIG_PCI
253                         if (ht_eoi_space)
254                                 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
255 #endif
256                 }
257         }
258         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
259 }
260
261
262 static void end_bcm1480_irq(unsigned int irq)
263 {
264         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
265                 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
266         }
267 }
268
269
270 void __init init_bcm1480_irqs(void)
271 {
272         int i;
273
274         for (i = 0; i < NR_IRQS; i++) {
275                 irq_desc[i].status = IRQ_DISABLED;
276                 irq_desc[i].action = 0;
277                 irq_desc[i].depth = 1;
278                 if (i < BCM1480_NR_IRQS) {
279                         irq_desc[i].handler = &bcm1480_irq_type;
280                         bcm1480_irq_owner[i] = 0;
281                 } else {
282                         irq_desc[i].handler = &no_irq_type;
283                 }
284         }
285 }
286
287
288 static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id,
289         struct pt_regs *regs)
290 {
291         return IRQ_NONE;
292 }
293
294 static struct irqaction bcm1480_dummy_action = {
295         .handler = bcm1480_dummy_handler,
296         .flags   = 0,
297         .mask    = CPU_MASK_NONE,
298         .name    = "bcm1480-private",
299         .next    = NULL,
300         .dev_id  = 0
301 };
302
303 int bcm1480_steal_irq(int irq)
304 {
305         irq_desc_t *desc = irq_desc + irq;
306         unsigned long flags;
307         int retval = 0;
308
309         if (irq >= BCM1480_NR_IRQS)
310                 return -EINVAL;
311
312         spin_lock_irqsave(&desc->lock,flags);
313         /* Don't allow sharing at all for these */
314         if (desc->action != NULL)
315                 retval = -EBUSY;
316         else {
317                 desc->action = &bcm1480_dummy_action;
318                 desc->depth = 0;
319         }
320         spin_unlock_irqrestore(&desc->lock,flags);
321         return 0;
322 }
323
324 /*
325  *  init_IRQ is called early in the boot sequence from init/main.c.  It
326  *  is responsible for setting up the interrupt mapper and installing the
327  *  handler that will be responsible for dispatching interrupts to the
328  *  "right" place.
329  */
330 /*
331  * For now, map all interrupts to IP[2].  We could save
332  * some cycles by parceling out system interrupts to different
333  * IP lines, but keep it simple for bringup.  We'll also direct
334  * all interrupts to a single CPU; we should probably route
335  * PCI and LDT to one cpu and everything else to the other
336  * to balance the load a bit.
337  *
338  * On the second cpu, everything is set to IP5, which is
339  * ignored, EXCEPT the mailbox interrupt.  That one is
340  * set to IP[2] so it is handled.  This is needed so we
341  * can do cross-cpu function calls, as requred by SMP
342  */
343
344 #define IMR_IP2_VAL     K_BCM1480_INT_MAP_I0
345 #define IMR_IP3_VAL     K_BCM1480_INT_MAP_I1
346 #define IMR_IP4_VAL     K_BCM1480_INT_MAP_I2
347 #define IMR_IP5_VAL     K_BCM1480_INT_MAP_I3
348 #define IMR_IP6_VAL     K_BCM1480_INT_MAP_I4
349
350 void __init arch_init_irq(void)
351 {
352
353         unsigned int i, cpu;
354         u64 tmp;
355         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
356                 STATUSF_IP1 | STATUSF_IP0;
357
358         /* Default everything to IP2 */
359         /* Start with _high registers which has no bit 0 interrupt source */
360         for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) {    /* was I0 */
361                 for (cpu = 0; cpu < 4; cpu++) {
362                         __raw_writeq(IMR_IP2_VAL,
363                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
364                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
365                 }
366         }
367
368         /* Now do _low registers */
369         for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
370                 for (cpu = 0; cpu < 4; cpu++) {
371                         __raw_writeq(IMR_IP2_VAL,
372                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
373                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
374                 }
375         }
376
377         init_bcm1480_irqs();
378
379         /*
380          * Map the high 16 bits of mailbox_0 registers to IP[3], for
381          * inter-cpu messages
382          */
383         /* Was I1 */
384         for (cpu = 0; cpu < 4; cpu++) {
385                 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
386                                                  (K_BCM1480_INT_MBOX_0_0 << 3)));
387         }
388
389
390         /* Clear the mailboxes.  The firmware may leave them dirty */
391         for (cpu = 0; cpu < 4; cpu++) {
392                 __raw_writeq(0xffffffffffffffffULL,
393                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
394                 __raw_writeq(0xffffffffffffffffULL,
395                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
396         }
397
398
399         /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
400         tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
401         for (cpu = 0; cpu < 4; cpu++) {
402                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
403         }
404         tmp = ~((u64) 0);
405         for (cpu = 0; cpu < 4; cpu++) {
406                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
407         }
408
409         bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0);
410
411         /*
412          * Note that the timer interrupts are also mapped, but this is
413          * done in bcm1480_time_init().  Also, the profiling driver
414          * does its own management of IP7.
415          */
416
417 #ifdef CONFIG_KGDB
418         imask |= STATUSF_IP6;
419 #endif
420         /* Enable necessary IPs, disable the rest */
421         change_c0_status(ST0_IM, imask);
422
423 #ifdef CONFIG_KGDB
424         if (kgdb_flag) {
425                 kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
426
427 #ifdef CONFIG_SIBYTE_SB1250_DUART
428                 sb1250_duart_present[kgdb_port] = 0;
429 #endif
430                 /* Setup uart 1 settings, mapper */
431                 /* QQQ FIXME */
432                 __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
433
434                 bcm1480_steal_irq(kgdb_irq);
435                 __raw_writeq(IMR_IP6_VAL,
436                              IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
437                              (kgdb_irq<<3));
438                 bcm1480_unmask_irq(0, kgdb_irq);
439
440 #ifdef CONFIG_GDB_CONSOLE
441                 register_gdb_console();
442 #endif
443                 prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
444                 set_debug_traps();
445                 breakpoint();
446         }
447 #endif
448 }
449
450 #ifdef CONFIG_KGDB
451
452 #include <linux/delay.h>
453
454 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
455 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
456
457 void bcm1480_kgdb_interrupt(struct pt_regs *regs)
458 {
459         /*
460          * Clear break-change status (allow some time for the remote
461          * host to stop the break, since we would see another
462          * interrupt on the end-of-break too)
463          */
464         kstat.irqs[smp_processor_id()][kgdb_irq]++;
465         mdelay(500);
466         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
467                                 M_DUART_RX_EN | M_DUART_TX_EN);
468         set_async_breakpoint(&regs->cp0_epc);
469 }
470
471 #endif  /* CONFIG_KGDB */
472
473 static inline int dclz(unsigned long long x)
474 {
475         int lz;
476
477         __asm__ (
478         "       .set    push                                            \n"
479         "       .set    mips64                                          \n"
480         "       dclz    %0, %1                                          \n"
481         "       .set    pop                                             \n"
482         : "=r" (lz)
483         : "r" (x));
484
485         return lz;
486 }
487
488 extern void bcm1480_timer_interrupt(struct pt_regs *regs);
489 extern void bcm1480_mailbox_interrupt(struct pt_regs *regs);
490 extern void bcm1480_kgdb_interrupt(struct pt_regs *regs);
491
492 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
493 {
494         unsigned int pending;
495
496 #ifdef CONFIG_SIBYTE_BCM1480_PROF
497         /* Set compare to count to silence count/compare timer interrupts */
498         write_c0_compare(read_c0_count());
499 #endif
500
501         pending = read_c0_cause();
502
503 #ifdef CONFIG_SIBYTE_BCM1480_PROF
504         if (pending & CAUSEF_IP7)       /* Cpu performance counter interrupt */
505                 sbprof_cpu_intr(exception_epc(regs));
506 #endif
507
508         if (pending & CAUSEF_IP4)
509                 bcm1480_timer_interrupt(regs);
510
511 #ifdef CONFIG_SMP
512         if (pending & CAUSEF_IP3)
513                 bcm1480_mailbox_interrupt(regs);
514 #endif
515
516 #ifdef CONFIG_KGDB
517         if (pending & CAUSEF_IP6)
518                 bcm1480_kgdb_interrupt(regs);           /* KGDB (uart 1) */
519 #endif
520
521         if (pending & CAUSEF_IP2) {
522                 unsigned long long mask_h, mask_l;
523                 unsigned long base;
524
525                 /*
526                  * Default...we've hit an IP[2] interrupt, which means we've
527                  * got to check the 1480 interrupt registers to figure out what
528                  * to do.  Need to detect which CPU we're on, now that
529                  * smp_affinity is supported.
530                  */
531                 base = A_BCM1480_IMR_MAPPER(smp_processor_id());
532                 mask_h = __raw_readq(
533                         IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
534                 mask_l = __raw_readq(
535                         IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
536
537                 if (!mask_h) {
538                         if (mask_h ^ 1)
539                                 do_IRQ(63 - dclz(mask_h), regs);
540                         else
541                                 do_IRQ(127 - dclz(mask_l), regs);
542                 }
543         }
544 }