git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/kernel/vdso32/sigtramp.S

   1 /*
   2  * Signal trampolines for 32 bits processes in a ppc64 kernel for
   3  * use in the vDSO
   4  *
   5  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
   6  * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13 #include <linux/config.h>
  14 #include <asm/processor.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/unistd.h>
  17 #include <asm/vdso.h>
  18
  19         .text
  20
  21 /* The nop here is a hack.  The dwarf2 unwind routines subtract 1 from
  22    the return address to get an address in the middle of the presumed
  23    call instruction.  Since we don't have a call here, we artifically
  24    extend the range covered by the unwind info by adding a nop before
  25    the real start.  */
  26         nop
  27 V_FUNCTION_BEGIN(__kernel_sigtramp32)
  28 .Lsig_start = . - 4
  29         li      r0,__NR_sigreturn
  30         sc
  31 .Lsig_end:
  32 V_FUNCTION_END(__kernel_sigtramp32)
  33
  34 .Lsigrt_start:
  35         nop
  36 V_FUNCTION_BEGIN(__kernel_sigtramp_rt32)
  37         li      r0,__NR_rt_sigreturn
  38         sc
  39 .Lsigrt_end:
  40 V_FUNCTION_END(__kernel_sigtramp_rt32)
  41
  42         .section .eh_frame,"a",@progbits
  43
  44 /* Register r1 can be found at offset 4 of a pt_regs structure.
  45    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
  46 #define cfa_save \
  47   .byte 0x0f;                   /* DW_CFA_def_cfa_expression */         \
  48   .uleb128 9f - 1f;             /*   length */                          \
  49 1:                                                                      \
  50   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
  51   .byte 0x06;                   /*     DW_OP_deref */                   \
  52   .byte 0x23; .uleb128 RSIZE;   /*     DW_OP_plus_uconst */             \
  53   .byte 0x06;                   /*     DW_OP_deref */                   \
  54 9:
  55
  56 /* Register REGNO can be found at offset OFS of a pt_regs structure.
  57    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
  58 #define rsave(regno, ofs) \
  59   .byte 0x10;                   /* DW_CFA_expression */                 \
  60   .uleb128 regno;               /*   regno */                           \
  61   .uleb128 9f - 1f;             /*   length */                          \
  62 1:                                                                      \
  63   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
  64   .byte 0x06;                   /*     DW_OP_deref */                   \
  65   .ifne ofs;                                                            \
  66     .byte 0x23; .uleb128 ofs;   /*     DW_OP_plus_uconst */             \
  67   .endif;                                                               \
  68 9:
  69
  70 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
  71    of the VMX reg struct.  The VMX reg struct is at offset VREGS of
  72    the pt_regs struct.  This macro is for REGNO == 0, and contains
  73    'subroutines' that the other macros jump to.  */
  74 #define vsave_msr0(regno) \
  75   .byte 0x10;                   /* DW_CFA_expression */                 \
  76   .uleb128 regno + 77;          /*   regno */                           \
  77   .uleb128 9f - 1f;             /*   length */                          \
  78 1:                                                                      \
  79   .byte 0x30 + regno;           /*     DW_OP_lit0 */                    \
  80 2:                                                                      \
  81   .byte 0x40;                   /*     DW_OP_lit16 */                   \
  82   .byte 0x1e;                   /*     DW_OP_mul */                     \
  83 3:                                                                      \
  84   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
  85   .byte 0x06;                   /*     DW_OP_deref */                   \
  86   .byte 0x12;                   /*     DW_OP_dup */                     \
  87   .byte 0x23;                   /*     DW_OP_plus_uconst */             \
  88     .uleb128 33*RSIZE;          /*       msr offset */                  \
  89   .byte 0x06;                   /*     DW_OP_deref */                   \
  90   .byte 0x0c; .long 1 << 25;    /*     DW_OP_const4u */                 \
  91   .byte 0x1a;                   /*     DW_OP_and */                     \
  92   .byte 0x12;                   /*     DW_OP_dup, ret 0 if bra taken */ \
  93   .byte 0x30;                   /*     DW_OP_lit0 */                    \
  94   .byte 0x29;                   /*     DW_OP_eq */                      \
  95   .byte 0x28; .short 0x7fff;    /*     DW_OP_bra to end */              \
  96   .byte 0x13;                   /*     DW_OP_drop, pop the 0 */         \
  97   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */             \
  98   .byte 0x22;                   /*     DW_OP_plus */                    \
  99   .byte 0x2f; .short 0x7fff;    /*     DW_OP_skip to end */             \
 100 9:
 101
 102 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
 103    of the VMX reg struct.  REGNO is 1 thru 31.  */
 104 #define vsave_msr1(regno) \
 105   .byte 0x10;                   /* DW_CFA_expression */                 \
 106   .uleb128 regno + 77;          /*   regno */                           \
 107   .uleb128 9f - 1f;             /*   length */                          \
 108 1:                                                                      \
 109   .byte 0x30 + regno;           /*     DW_OP_lit n */                   \
 110   .byte 0x2f; .short 2b - 9f;   /*     DW_OP_skip */                    \
 111 9:
 112
 113 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
 114    the VMX save block.  */
 115 #define vsave_msr2(regno, ofs) \
 116   .byte 0x10;                   /* DW_CFA_expression */                 \
 117   .uleb128 regno + 77;          /*   regno */                           \
 118   .uleb128 9f - 1f;             /*   length */                          \
 119 1:                                                                      \
 120   .byte 0x0a; .short ofs;       /*     DW_OP_const2u */                 \
 121   .byte 0x2f; .short 3b - 9f;   /*     DW_OP_skip */                    \
 122 9:
 123
 124 /* VMX register REGNO is at offset OFS of the VMX save area.  */
 125 #define vsave(regno, ofs) \
 126   .byte 0x10;                   /* DW_CFA_expression */                 \
 127   .uleb128 regno + 77;          /*   regno */                           \
 128   .uleb128 9f - 1f;             /*   length */                          \
 129 1:                                                                      \
 130   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
 131   .byte 0x06;                   /*     DW_OP_deref */                   \
 132   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */             \
 133   .byte 0x23; .uleb128 ofs;     /*     DW_OP_plus_uconst */             \
 134 9:
 135
 136 /* This is where the pt_regs pointer can be found on the stack.  */
 137 #define PTREGS 64+28
 138
 139 /* Size of regs.  */
 140 #define RSIZE 4
 141
 142 /* This is the offset of the VMX regs.  */
 143 #define VREGS 48*RSIZE+34*8
 144
 145 /* Describe where general purpose regs are saved.  */
 146 #define EH_FRAME_GEN \
 147   cfa_save;                                                             \
 148   rsave ( 0,  0*RSIZE);                                                 \
 149   rsave ( 2,  2*RSIZE);                                                 \
 150   rsave ( 3,  3*RSIZE);                                                 \
 151   rsave ( 4,  4*RSIZE);                                                 \
 152   rsave ( 5,  5*RSIZE);                                                 \
 153   rsave ( 6,  6*RSIZE);                                                 \
 154   rsave ( 7,  7*RSIZE);                                                 \
 155   rsave ( 8,  8*RSIZE);                                                 \
 156   rsave ( 9,  9*RSIZE);                                                 \
 157   rsave (10, 10*RSIZE);                                                 \
 158   rsave (11, 11*RSIZE);                                                 \
 159   rsave (12, 12*RSIZE);                                                 \
 160   rsave (13, 13*RSIZE);                                                 \
 161   rsave (14, 14*RSIZE);                                                 \
 162   rsave (15, 15*RSIZE);                                                 \
 163   rsave (16, 16*RSIZE);                                                 \
 164   rsave (17, 17*RSIZE);                                                 \
 165   rsave (18, 18*RSIZE);                                                 \
 166   rsave (19, 19*RSIZE);                                                 \
 167   rsave (20, 20*RSIZE);                                                 \
 168   rsave (21, 21*RSIZE);                                                 \
 169   rsave (22, 22*RSIZE);                                                 \
 170   rsave (23, 23*RSIZE);                                                 \
 171   rsave (24, 24*RSIZE);                                                 \
 172   rsave (25, 25*RSIZE);                                                 \
 173   rsave (26, 26*RSIZE);                                                 \
 174   rsave (27, 27*RSIZE);                                                 \
 175   rsave (28, 28*RSIZE);                                                 \
 176   rsave (29, 29*RSIZE);                                                 \
 177   rsave (30, 30*RSIZE);                                                 \
 178   rsave (31, 31*RSIZE);                                                 \
 179   rsave (67, 32*RSIZE);         /* ap, used as temp for nip */          \
 180   rsave (65, 36*RSIZE);         /* lr */                                \
 181   rsave (70, 38*RSIZE)          /* cr */
 182
 183 /* Describe where the FP regs are saved.  */
 184 #define EH_FRAME_FP \
 185   rsave (32, 48*RSIZE +  0*8);                                          \
 186   rsave (33, 48*RSIZE +  1*8);                                          \
 187   rsave (34, 48*RSIZE +  2*8);                                          \
 188   rsave (35, 48*RSIZE +  3*8);                                          \
 189   rsave (36, 48*RSIZE +  4*8);                                          \
 190   rsave (37, 48*RSIZE +  5*8);                                          \
 191   rsave (38, 48*RSIZE +  6*8);                                          \
 192   rsave (39, 48*RSIZE +  7*8);                                          \
 193   rsave (40, 48*RSIZE +  8*8);                                          \
 194   rsave (41, 48*RSIZE +  9*8);                                          \
 195   rsave (42, 48*RSIZE + 10*8);                                          \
 196   rsave (43, 48*RSIZE + 11*8);                                          \
 197   rsave (44, 48*RSIZE + 12*8);                                          \
 198   rsave (45, 48*RSIZE + 13*8);                                          \
 199   rsave (46, 48*RSIZE + 14*8);                                          \
 200   rsave (47, 48*RSIZE + 15*8);                                          \
 201   rsave (48, 48*RSIZE + 16*8);                                          \
 202   rsave (49, 48*RSIZE + 17*8);                                          \
 203   rsave (50, 48*RSIZE + 18*8);                                          \
 204   rsave (51, 48*RSIZE + 19*8);                                          \
 205   rsave (52, 48*RSIZE + 20*8);                                          \
 206   rsave (53, 48*RSIZE + 21*8);                                          \
 207   rsave (54, 48*RSIZE + 22*8);                                          \
 208   rsave (55, 48*RSIZE + 23*8);                                          \
 209   rsave (56, 48*RSIZE + 24*8);                                          \
 210   rsave (57, 48*RSIZE + 25*8);                                          \
 211   rsave (58, 48*RSIZE + 26*8);                                          \
 212   rsave (59, 48*RSIZE + 27*8);                                          \
 213   rsave (60, 48*RSIZE + 28*8);                                          \
 214   rsave (61, 48*RSIZE + 29*8);                                          \
 215   rsave (62, 48*RSIZE + 30*8);                                          \
 216   rsave (63, 48*RSIZE + 31*8)
 217
 218 /* Describe where the VMX regs are saved.  */
 219 #ifdef CONFIG_ALTIVEC
 220 #define EH_FRAME_VMX \
 221   vsave_msr0 ( 0);                                                      \
 222   vsave_msr1 ( 1);                                                      \
 223   vsave_msr1 ( 2);                                                      \
 224   vsave_msr1 ( 3);                                                      \
 225   vsave_msr1 ( 4);                                                      \
 226   vsave_msr1 ( 5);                                                      \
 227   vsave_msr1 ( 6);                                                      \
 228   vsave_msr1 ( 7);                                                      \
 229   vsave_msr1 ( 8);                                                      \
 230   vsave_msr1 ( 9);                                                      \
 231   vsave_msr1 (10);                                                      \
 232   vsave_msr1 (11);                                                      \
 233   vsave_msr1 (12);                                                      \
 234   vsave_msr1 (13);                                                      \
 235   vsave_msr1 (14);                                                      \
 236   vsave_msr1 (15);                                                      \
 237   vsave_msr1 (16);                                                      \
 238   vsave_msr1 (17);                                                      \
 239   vsave_msr1 (18);                                                      \
 240   vsave_msr1 (19);                                                      \
 241   vsave_msr1 (20);                                                      \
 242   vsave_msr1 (21);                                                      \
 243   vsave_msr1 (22);                                                      \
 244   vsave_msr1 (23);                                                      \
 245   vsave_msr1 (24);                                                      \
 246   vsave_msr1 (25);                                                      \
 247   vsave_msr1 (26);                                                      \
 248   vsave_msr1 (27);                                                      \
 249   vsave_msr1 (28);                                                      \
 250   vsave_msr1 (29);                                                      \
 251   vsave_msr1 (30);                                                      \
 252   vsave_msr1 (31);                                                      \
 253   vsave_msr2 (33, 32*16+12);                                            \
 254   vsave      (32, 32*16)
 255 #else
 256 #define EH_FRAME_VMX
 257 #endif
 258
 259 .Lcie:
 260         .long .Lcie_end - .Lcie_start
 261 .Lcie_start:
 262         .long 0                 /* CIE ID */
 263         .byte 1                 /* Version number */
 264         .string "zRS"           /* NUL-terminated augmentation string */
 265         .uleb128 4              /* Code alignment factor */
 266         .sleb128 -4             /* Data alignment factor */
 267         .byte 67                /* Return address register column, ap */
 268         .uleb128 1              /* Augmentation value length */
 269         .byte 0x1b              /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */
 270         .byte 0x0c,1,0          /* DW_CFA_def_cfa: r1 ofs 0 */
 271         .balign 4
 272 .Lcie_end:
 273
 274         .long .Lfde0_end - .Lfde0_start
 275 .Lfde0_start:
 276         .long .Lfde0_start - .Lcie      /* CIE pointer. */
 277         .long .Lsig_start - .           /* PC start, length */
 278         .long .Lsig_end - .Lsig_start
 279         .uleb128 0                      /* Augmentation */
 280         EH_FRAME_GEN
 281         EH_FRAME_FP
 282         EH_FRAME_VMX
 283         .balign 4
 284 .Lfde0_end:
 285
 286 /* We have a different stack layout for rt_sigreturn.  */
 287 #undef PTREGS
 288 #define PTREGS 64+16+128+20+28
 289
 290         .long .Lfde1_end - .Lfde1_start
 291 .Lfde1_start:
 292         .long .Lfde1_start - .Lcie      /* CIE pointer. */
 293         .long .Lsigrt_start - .         /* PC start, length */
 294         .long .Lsigrt_end - .Lsigrt_start
 295         .uleb128 0                      /* Augmentation */
 296         EH_FRAME_GEN
 297         EH_FRAME_FP
 298         EH_FRAME_VMX
 299         .balign 4
 300 .Lfde1_end: