git.oblomov.eu Git - linux-2.6/blob - arch/x86_64/kernel/nmi.c

   1 /*
   2  *  linux/arch/x86_64/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Pavel Machek and
  12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  13  */
  14
  15 #include <linux/nmi.h>
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cpumask.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/proto.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/mce.h>
  30 #include <asm/intel_arch_perfmon.h>
  31
  32 int unknown_nmi_panic;
  33 int nmi_watchdog_enabled;
  34 int panic_on_unrecovered_nmi;
  35
  36 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  37  * evtsel_nmi_owner tracks the ownership of the event selection
  38  * - different performance counters/ event selection may be reserved for
  39  *   different subsystems this reservation system just tries to coordinate
  40  *   things a little
  41  */
  42
  43 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  44  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  45  */
  46 #define NMI_MAX_COUNTER_BITS 66
  47 #define NMI_MAX_COUNTER_LONGS BITS_TO_LONGS(NMI_MAX_COUNTER_BITS)
  48
  49 static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner[NMI_MAX_COUNTER_LONGS]);
  50 static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[NMI_MAX_COUNTER_LONGS]);
  51
  52 static cpumask_t backtrace_mask = CPU_MASK_NONE;
  53
  54 /* nmi_active:
  55  * >0: the lapic NMI watchdog is active, but can be disabled
  56  * <0: the lapic NMI watchdog has not been set up, and cannot
  57  *     be enabled
  58  *  0: the lapic NMI watchdog is disabled, but can be enabled
  59  */
  60 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  61 int panic_on_timeout;
  62
  63 unsigned int nmi_watchdog = NMI_DEFAULT;
  64 static unsigned int nmi_hz = HZ;
  65
  66 struct nmi_watchdog_ctlblk {
  67         int enabled;
  68         u64 check_bit;
  69         unsigned int cccr_msr;
  70         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  71         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  72 };
  73 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  74
  75 /* local prototypes */
  76 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  77
  78 /* converts an msr to an appropriate reservation bit */
  79 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  80 {
  81         /* returns the bit offset of the performance counter register */
  82         switch (boot_cpu_data.x86_vendor) {
  83         case X86_VENDOR_AMD:
  84                 return (msr - MSR_K7_PERFCTR0);
  85         case X86_VENDOR_INTEL:
  86                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  87                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
  88                 else
  89                         return (msr - MSR_P4_BPU_PERFCTR0);
  90         }
  91         return 0;
  92 }
  93
  94 /* converts an msr to an appropriate reservation bit */
  95 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
  96 {
  97         /* returns the bit offset of the event selection register */
  98         switch (boot_cpu_data.x86_vendor) {
  99         case X86_VENDOR_AMD:
 100                 return (msr - MSR_K7_EVNTSEL0);
 101         case X86_VENDOR_INTEL:
 102                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 103                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
 104                 else
 105                         return (msr - MSR_P4_BSU_ESCR0);
 106         }
 107         return 0;
 108 }
 109
 110 /* checks for a bit availability (hack for oprofile) */
 111 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 112 {
 113         int cpu;
 114         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 115         for_each_possible_cpu (cpu) {
 116                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 117                         return 0;
 118         }
 119         return 1;
 120 }
 121
 122 /* checks the an msr for availability */
 123 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 124 {
 125         unsigned int counter;
 126         int cpu;
 127
 128         counter = nmi_perfctr_msr_to_bit(msr);
 129         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 130
 131         for_each_possible_cpu (cpu) {
 132                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 133                         return 0;
 134         }
 135         return 1;
 136 }
 137
 138 static int __reserve_perfctr_nmi(int cpu, unsigned int msr)
 139 {
 140         unsigned int counter;
 141         if (cpu < 0)
 142                 cpu = smp_processor_id();
 143
 144         counter = nmi_perfctr_msr_to_bit(msr);
 145         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 146
 147         if (!test_and_set_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 148                 return 1;
 149         return 0;
 150 }
 151
 152 static void __release_perfctr_nmi(int cpu, unsigned int msr)
 153 {
 154         unsigned int counter;
 155         if (cpu < 0)
 156                 cpu = smp_processor_id();
 157
 158         counter = nmi_perfctr_msr_to_bit(msr);
 159         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 160
 161         clear_bit(counter, &per_cpu(perfctr_nmi_owner, cpu));
 162 }
 163
 164 int reserve_perfctr_nmi(unsigned int msr)
 165 {
 166         int cpu, i;
 167         for_each_possible_cpu (cpu) {
 168                 if (!__reserve_perfctr_nmi(cpu, msr)) {
 169                         for_each_possible_cpu (i) {
 170                                 if (i >= cpu)
 171                                         break;
 172                                 __release_perfctr_nmi(i, msr);
 173                         }
 174                         return 0;
 175                 }
 176         }
 177         return 1;
 178 }
 179
 180 void release_perfctr_nmi(unsigned int msr)
 181 {
 182         int cpu;
 183         for_each_possible_cpu (cpu)
 184                 __release_perfctr_nmi(cpu, msr);
 185 }
 186
 187 int __reserve_evntsel_nmi(int cpu, unsigned int msr)
 188 {
 189         unsigned int counter;
 190         if (cpu < 0)
 191                 cpu = smp_processor_id();
 192
 193         counter = nmi_evntsel_msr_to_bit(msr);
 194         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 195
 196         if (!test_and_set_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]))
 197                 return 1;
 198         return 0;
 199 }
 200
 201 static void __release_evntsel_nmi(int cpu, unsigned int msr)
 202 {
 203         unsigned int counter;
 204         if (cpu < 0)
 205                 cpu = smp_processor_id();
 206
 207         counter = nmi_evntsel_msr_to_bit(msr);
 208         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 209
 210         clear_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]);
 211 }
 212
 213 int reserve_evntsel_nmi(unsigned int msr)
 214 {
 215         int cpu, i;
 216         for_each_possible_cpu (cpu) {
 217                 if (!__reserve_evntsel_nmi(cpu, msr)) {
 218                         for_each_possible_cpu (i) {
 219                                 if (i >= cpu)
 220                                         break;
 221                                 __release_evntsel_nmi(i, msr);
 222                         }
 223                         return 0;
 224                 }
 225         }
 226         return 1;
 227 }
 228
 229 void release_evntsel_nmi(unsigned int msr)
 230 {
 231         int cpu;
 232         for_each_possible_cpu (cpu) {
 233                 __release_evntsel_nmi(cpu, msr);
 234         }
 235 }
 236
 237 static __cpuinit inline int nmi_known_cpu(void)
 238 {
 239         switch (boot_cpu_data.x86_vendor) {
 240         case X86_VENDOR_AMD:
 241                 return boot_cpu_data.x86 == 15 || boot_cpu_data.x86 == 16;
 242         case X86_VENDOR_INTEL:
 243                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 244                         return 1;
 245                 else
 246                         return (boot_cpu_data.x86 == 15);
 247         }
 248         return 0;
 249 }
 250
 251 /* Run after command line and cpu_init init, but before all other checks */
 252 void nmi_watchdog_default(void)
 253 {
 254         if (nmi_watchdog != NMI_DEFAULT)
 255                 return;
 256         nmi_watchdog = NMI_NONE;
 257 }
 258
 259 static int endflag __initdata = 0;
 260
 261 #ifdef CONFIG_SMP
 262 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 263  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 264  * CPUs during the test make them busy.
 265  */
 266 static __init void nmi_cpu_busy(void *data)
 267 {
 268         local_irq_enable_in_hardirq();
 269         /* Intentionally don't use cpu_relax here. This is
 270            to make sure that the performance counter really ticks,
 271            even if there is a simulator or similar that catches the
 272            pause instruction. On a real HT machine this is fine because
 273            all other CPUs are busy with "useless" delay loops and don't
 274            care if they get somewhat less cycles. */
 275         while (endflag == 0)
 276                 mb();
 277 }
 278 #endif
 279
 280 static unsigned int adjust_for_32bit_ctr(unsigned int hz)
 281 {
 282         unsigned int retval = hz;
 283
 284         /*
 285          * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
 286          * are writable, with higher bits sign extending from bit 31.
 287          * So, we can only program the counter with 31 bit values and
 288          * 32nd bit should be 1, for 33.. to be 1.
 289          * Find the appropriate nmi_hz
 290          */
 291         if ((((u64)cpu_khz * 1000) / retval) > 0x7fffffffULL) {
 292                 retval = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
 293         }
 294         return retval;
 295 }
 296
 297 int __init check_nmi_watchdog (void)
 298 {
 299         int *counts;
 300         int cpu;
 301
 302         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 303                 return 0;
 304
 305         if (!atomic_read(&nmi_active))
 306                 return 0;
 307
 308         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 309         if (!counts)
 310                 return -1;
 311
 312         printk(KERN_INFO "testing NMI watchdog ... ");
 313
 314 #ifdef CONFIG_SMP
 315         if (nmi_watchdog == NMI_LOCAL_APIC)
 316                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 317 #endif
 318
 319         for (cpu = 0; cpu < NR_CPUS; cpu++)
 320                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
 321         local_irq_enable();
 322         mdelay((20*1000)/nmi_hz); // wait 20 ticks
 323
 324         for_each_online_cpu(cpu) {
 325                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 326                         continue;
 327                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
 328                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 329                                cpu,
 330                                counts[cpu],
 331                                cpu_pda(cpu)->__nmi_count);
 332                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 333                         atomic_dec(&nmi_active);
 334                 }
 335         }
 336         if (!atomic_read(&nmi_active)) {
 337                 kfree(counts);
 338                 atomic_set(&nmi_active, -1);
 339                 endflag = 1;
 340                 return -1;
 341         }
 342         endflag = 1;
 343         printk("OK.\n");
 344
 345         /* now that we know it works we can reduce NMI frequency to
 346            something more reasonable; makes a difference in some configs */
 347         if (nmi_watchdog == NMI_LOCAL_APIC) {
 348                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 349
 350                 nmi_hz = 1;
 351                 if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1)
 352                         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 353         }
 354
 355         kfree(counts);
 356         return 0;
 357 }
 358
 359 int __init setup_nmi_watchdog(char *str)
 360 {
 361         int nmi;
 362
 363         if (!strncmp(str,"panic",5)) {
 364                 panic_on_timeout = 1;
 365                 str = strchr(str, ',');
 366                 if (!str)
 367                         return 1;
 368                 ++str;
 369         }
 370
 371         get_option(&str, &nmi);
 372
 373         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 374                 return 0;
 375
 376         nmi_watchdog = nmi;
 377         return 1;
 378 }
 379
 380 __setup("nmi_watchdog=", setup_nmi_watchdog);
 381
 382 static void disable_lapic_nmi_watchdog(void)
 383 {
 384         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 385
 386         if (atomic_read(&nmi_active) <= 0)
 387                 return;
 388
 389         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 390
 391         BUG_ON(atomic_read(&nmi_active) != 0);
 392 }
 393
 394 static void enable_lapic_nmi_watchdog(void)
 395 {
 396         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 397
 398         /* are we already enabled */
 399         if (atomic_read(&nmi_active) != 0)
 400                 return;
 401
 402         /* are we lapic aware */
 403         if (nmi_known_cpu() <= 0)
 404                 return;
 405
 406         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 407         touch_nmi_watchdog();
 408 }
 409
 410 void disable_timer_nmi_watchdog(void)
 411 {
 412         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 413
 414         if (atomic_read(&nmi_active) <= 0)
 415                 return;
 416
 417         disable_irq(0);
 418         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 419
 420         BUG_ON(atomic_read(&nmi_active) != 0);
 421 }
 422
 423 void enable_timer_nmi_watchdog(void)
 424 {
 425         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 426
 427         if (atomic_read(&nmi_active) == 0) {
 428                 touch_nmi_watchdog();
 429                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 430                 enable_irq(0);
 431         }
 432 }
 433
 434 static void __acpi_nmi_disable(void *__unused)
 435 {
 436         apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
 437 }
 438
 439 /*
 440  * Disable timer based NMIs on all CPUs:
 441  */
 442 void acpi_nmi_disable(void)
 443 {
 444         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 445                 on_each_cpu(__acpi_nmi_disable, NULL, 0, 1);
 446 }
 447
 448 static void __acpi_nmi_enable(void *__unused)
 449 {
 450         apic_write(APIC_LVT0, APIC_DM_NMI);
 451 }
 452
 453 /*
 454  * Enable timer based NMIs on all CPUs:
 455  */
 456 void acpi_nmi_enable(void)
 457 {
 458         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 459                 on_each_cpu(__acpi_nmi_enable, NULL, 0, 1);
 460 }
 461 #ifdef CONFIG_PM
 462
 463 static int nmi_pm_active; /* nmi_active before suspend */
 464
 465 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 466 {
 467         /* only CPU0 goes here, other CPUs should be offline */
 468         nmi_pm_active = atomic_read(&nmi_active);
 469         stop_apic_nmi_watchdog(NULL);
 470         BUG_ON(atomic_read(&nmi_active) != 0);
 471         return 0;
 472 }
 473
 474 static int lapic_nmi_resume(struct sys_device *dev)
 475 {
 476         /* only CPU0 goes here, other CPUs should be offline */
 477         if (nmi_pm_active > 0) {
 478                 setup_apic_nmi_watchdog(NULL);
 479                 touch_nmi_watchdog();
 480         }
 481         return 0;
 482 }
 483
 484 static struct sysdev_class nmi_sysclass = {
 485         set_kset_name("lapic_nmi"),
 486         .resume         = lapic_nmi_resume,
 487         .suspend        = lapic_nmi_suspend,
 488 };
 489
 490 static struct sys_device device_lapic_nmi = {
 491         .id             = 0,
 492         .cls    = &nmi_sysclass,
 493 };
 494
 495 static int __init init_lapic_nmi_sysfs(void)
 496 {
 497         int error;
 498
 499         /* should really be a BUG_ON but b/c this is an
 500          * init call, it just doesn't work.  -dcz
 501          */
 502         if (nmi_watchdog != NMI_LOCAL_APIC)
 503                 return 0;
 504
 505         if ( atomic_read(&nmi_active) < 0 )
 506                 return 0;
 507
 508         error = sysdev_class_register(&nmi_sysclass);
 509         if (!error)
 510                 error = sysdev_register(&device_lapic_nmi);
 511         return error;
 512 }
 513 /* must come after the local APIC's device_initcall() */
 514 late_initcall(init_lapic_nmi_sysfs);
 515
 516 #endif  /* CONFIG_PM */
 517
 518 /*
 519  * Activate the NMI watchdog via the local APIC.
 520  * Original code written by Keith Owens.
 521  */
 522
 523 /* Note that these events don't tick when the CPU idles. This means
 524    the frequency varies with CPU load. */
 525
 526 #define K7_EVNTSEL_ENABLE       (1 << 22)
 527 #define K7_EVNTSEL_INT          (1 << 20)
 528 #define K7_EVNTSEL_OS           (1 << 17)
 529 #define K7_EVNTSEL_USR          (1 << 16)
 530 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 531 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 532
 533 static int setup_k7_watchdog(void)
 534 {
 535         unsigned int perfctr_msr, evntsel_msr;
 536         unsigned int evntsel;
 537         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 538
 539         perfctr_msr = MSR_K7_PERFCTR0;
 540         evntsel_msr = MSR_K7_EVNTSEL0;
 541         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 542                 goto fail;
 543
 544         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 545                 goto fail1;
 546
 547         /* Simulator may not support it */
 548         if (checking_wrmsrl(evntsel_msr, 0UL))
 549                 goto fail2;
 550         wrmsrl(perfctr_msr, 0UL);
 551
 552         evntsel = K7_EVNTSEL_INT
 553                 | K7_EVNTSEL_OS
 554                 | K7_EVNTSEL_USR
 555                 | K7_NMI_EVENT;
 556
 557         /* setup the timer */
 558         wrmsr(evntsel_msr, evntsel, 0);
 559         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 560         apic_write(APIC_LVTPC, APIC_DM_NMI);
 561         evntsel |= K7_EVNTSEL_ENABLE;
 562         wrmsr(evntsel_msr, evntsel, 0);
 563
 564         wd->perfctr_msr = perfctr_msr;
 565         wd->evntsel_msr = evntsel_msr;
 566         wd->cccr_msr = 0;  //unused
 567         wd->check_bit = 1ULL<<63;
 568         return 1;
 569 fail2:
 570         __release_evntsel_nmi(-1, evntsel_msr);
 571 fail1:
 572         __release_perfctr_nmi(-1, perfctr_msr);
 573 fail:
 574         return 0;
 575 }
 576
 577 static void stop_k7_watchdog(void)
 578 {
 579         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 580
 581         wrmsr(wd->evntsel_msr, 0, 0);
 582
 583         __release_evntsel_nmi(-1, wd->evntsel_msr);
 584         __release_perfctr_nmi(-1, wd->perfctr_msr);
 585 }
 586
 587 /* Note that these events don't tick when the CPU idles. This means
 588    the frequency varies with CPU load. */
 589
 590 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 591 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 592 #define P4_ESCR_OS              (1<<3)
 593 #define P4_ESCR_USR             (1<<2)
 594 #define P4_CCCR_OVF_PMI0        (1<<26)
 595 #define P4_CCCR_OVF_PMI1        (1<<27)
 596 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 597 #define P4_CCCR_COMPLEMENT      (1<<19)
 598 #define P4_CCCR_COMPARE         (1<<18)
 599 #define P4_CCCR_REQUIRED        (3<<16)
 600 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 601 #define P4_CCCR_ENABLE          (1<<12)
 602 #define P4_CCCR_OVF             (1<<31)
 603 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 604    CRU_ESCR0 (with any non-null event selector) through a complemented
 605    max threshold. [IA32-Vol3, Section 14.9.9] */
 606
 607 static int setup_p4_watchdog(void)
 608 {
 609         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 610         unsigned int evntsel, cccr_val;
 611         unsigned int misc_enable, dummy;
 612         unsigned int ht_num;
 613         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 614
 615         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 616         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 617                 return 0;
 618
 619 #ifdef CONFIG_SMP
 620         /* detect which hyperthread we are on */
 621         if (smp_num_siblings == 2) {
 622                 unsigned int ebx, apicid;
 623
 624                 ebx = cpuid_ebx(1);
 625                 apicid = (ebx >> 24) & 0xff;
 626                 ht_num = apicid & 1;
 627         } else
 628 #endif
 629                 ht_num = 0;
 630
 631         /* performance counters are shared resources
 632          * assign each hyperthread its own set
 633          * (re-use the ESCR0 register, seems safe
 634          * and keeps the cccr_val the same)
 635          */
 636         if (!ht_num) {
 637                 /* logical cpu 0 */
 638                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 639                 evntsel_msr = MSR_P4_CRU_ESCR0;
 640                 cccr_msr = MSR_P4_IQ_CCCR0;
 641                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 642         } else {
 643                 /* logical cpu 1 */
 644                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 645                 evntsel_msr = MSR_P4_CRU_ESCR0;
 646                 cccr_msr = MSR_P4_IQ_CCCR1;
 647                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 648         }
 649
 650         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 651                 goto fail;
 652
 653         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 654                 goto fail1;
 655
 656         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 657                 | P4_ESCR_OS
 658                 | P4_ESCR_USR;
 659
 660         cccr_val |= P4_CCCR_THRESHOLD(15)
 661                  | P4_CCCR_COMPLEMENT
 662                  | P4_CCCR_COMPARE
 663                  | P4_CCCR_REQUIRED;
 664
 665         wrmsr(evntsel_msr, evntsel, 0);
 666         wrmsr(cccr_msr, cccr_val, 0);
 667         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 668         apic_write(APIC_LVTPC, APIC_DM_NMI);
 669         cccr_val |= P4_CCCR_ENABLE;
 670         wrmsr(cccr_msr, cccr_val, 0);
 671
 672         wd->perfctr_msr = perfctr_msr;
 673         wd->evntsel_msr = evntsel_msr;
 674         wd->cccr_msr = cccr_msr;
 675         wd->check_bit = 1ULL<<39;
 676         return 1;
 677 fail1:
 678         __release_perfctr_nmi(-1, perfctr_msr);
 679 fail:
 680         return 0;
 681 }
 682
 683 static void stop_p4_watchdog(void)
 684 {
 685         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 686
 687         wrmsr(wd->cccr_msr, 0, 0);
 688         wrmsr(wd->evntsel_msr, 0, 0);
 689
 690         __release_evntsel_nmi(-1, wd->evntsel_msr);
 691         __release_perfctr_nmi(-1, wd->perfctr_msr);
 692 }
 693
 694 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 695 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 696
 697 static int setup_intel_arch_watchdog(void)
 698 {
 699         unsigned int ebx;
 700         union cpuid10_eax eax;
 701         unsigned int unused;
 702         unsigned int perfctr_msr, evntsel_msr;
 703         unsigned int evntsel;
 704         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 705
 706         /*
 707          * Check whether the Architectural PerfMon supports
 708          * Unhalted Core Cycles Event or not.
 709          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 710          */
 711         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 712         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 713             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 714                 goto fail;
 715
 716         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR1;
 717         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL1;
 718
 719         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 720                 goto fail;
 721
 722         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 723                 goto fail1;
 724
 725         wrmsrl(perfctr_msr, 0UL);
 726
 727         evntsel = ARCH_PERFMON_EVENTSEL_INT
 728                 | ARCH_PERFMON_EVENTSEL_OS
 729                 | ARCH_PERFMON_EVENTSEL_USR
 730                 | ARCH_PERFMON_NMI_EVENT_SEL
 731                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 732
 733         /* setup the timer */
 734         wrmsr(evntsel_msr, evntsel, 0);
 735
 736         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 737         wrmsr(perfctr_msr, (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
 738
 739         apic_write(APIC_LVTPC, APIC_DM_NMI);
 740         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 741         wrmsr(evntsel_msr, evntsel, 0);
 742
 743         wd->perfctr_msr = perfctr_msr;
 744         wd->evntsel_msr = evntsel_msr;
 745         wd->cccr_msr = 0;  //unused
 746         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
 747         return 1;
 748 fail1:
 749         __release_perfctr_nmi(-1, perfctr_msr);
 750 fail:
 751         return 0;
 752 }
 753
 754 static void stop_intel_arch_watchdog(void)
 755 {
 756         unsigned int ebx;
 757         union cpuid10_eax eax;
 758         unsigned int unused;
 759         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 760
 761         /*
 762          * Check whether the Architectural PerfMon supports
 763          * Unhalted Core Cycles Event or not.
 764          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 765          */
 766         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 767         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 768             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 769                 return;
 770
 771         wrmsr(wd->evntsel_msr, 0, 0);
 772
 773         __release_evntsel_nmi(-1, wd->evntsel_msr);
 774         __release_perfctr_nmi(-1, wd->perfctr_msr);
 775 }
 776
 777 void setup_apic_nmi_watchdog(void *unused)
 778 {
 779         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 780
 781         /* only support LOCAL and IO APICs for now */
 782         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 783             (nmi_watchdog != NMI_IO_APIC))
 784                 return;
 785
 786         if (wd->enabled == 1)
 787                 return;
 788
 789         /* cheap hack to support suspend/resume */
 790         /* if cpu0 is not active neither should the other cpus */
 791         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
 792                 return;
 793
 794         if (nmi_watchdog == NMI_LOCAL_APIC) {
 795                 switch (boot_cpu_data.x86_vendor) {
 796                 case X86_VENDOR_AMD:
 797                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 798                                 return;
 799                         if (!setup_k7_watchdog())
 800                                 return;
 801                         break;
 802                 case X86_VENDOR_INTEL:
 803                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 804                                 if (!setup_intel_arch_watchdog())
 805                                         return;
 806                                 break;
 807                         }
 808                         if (!setup_p4_watchdog())
 809                                 return;
 810                         break;
 811                 default:
 812                         return;
 813                 }
 814         }
 815         wd->enabled = 1;
 816         atomic_inc(&nmi_active);
 817 }
 818
 819 void stop_apic_nmi_watchdog(void *unused)
 820 {
 821         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 822
 823         /* only support LOCAL and IO APICs for now */
 824         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 825             (nmi_watchdog != NMI_IO_APIC))
 826                 return;
 827
 828         if (wd->enabled == 0)
 829                 return;
 830
 831         if (nmi_watchdog == NMI_LOCAL_APIC) {
 832                 switch (boot_cpu_data.x86_vendor) {
 833                 case X86_VENDOR_AMD:
 834                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 835                                 return;
 836                         stop_k7_watchdog();
 837                         break;
 838                 case X86_VENDOR_INTEL:
 839                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 840                                 stop_intel_arch_watchdog();
 841                                 break;
 842                         }
 843                         stop_p4_watchdog();
 844                         break;
 845                 default:
 846                         return;
 847                 }
 848         }
 849         wd->enabled = 0;
 850         atomic_dec(&nmi_active);
 851 }
 852
 853 /*
 854  * the best way to detect whether a CPU has a 'hard lockup' problem
 855  * is to check it's local APIC timer IRQ counts. If they are not
 856  * changing then that CPU has some problem.
 857  *
 858  * as these watchdog NMI IRQs are generated on every CPU, we only
 859  * have to check the current processor.
 860  */
 861
 862 static DEFINE_PER_CPU(unsigned, last_irq_sum);
 863 static DEFINE_PER_CPU(local_t, alert_counter);
 864 static DEFINE_PER_CPU(int, nmi_touch);
 865
 866 void touch_nmi_watchdog (void)
 867 {
 868         if (nmi_watchdog > 0) {
 869                 unsigned cpu;
 870
 871                 /*
 872                  * Tell other CPUs to reset their alert counters. We cannot
 873                  * do it ourselves because the alert count increase is not
 874                  * atomic.
 875                  */
 876                 for_each_present_cpu (cpu)
 877                         per_cpu(nmi_touch, cpu) = 1;
 878         }
 879
 880         touch_softlockup_watchdog();
 881 }
 882
 883 int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
 884 {
 885         int sum;
 886         int touched = 0;
 887         int cpu = smp_processor_id();
 888         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 889         u64 dummy;
 890         int rc=0;
 891
 892         /* check for other users first */
 893         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
 894                         == NOTIFY_STOP) {
 895                 rc = 1;
 896                 touched = 1;
 897         }
 898
 899         sum = read_pda(apic_timer_irqs);
 900         if (__get_cpu_var(nmi_touch)) {
 901                 __get_cpu_var(nmi_touch) = 0;
 902                 touched = 1;
 903         }
 904
 905         if (cpu_isset(cpu, backtrace_mask)) {
 906                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
 907
 908                 spin_lock(&lock);
 909                 printk("NMI backtrace for cpu %d\n", cpu);
 910                 dump_stack();
 911                 spin_unlock(&lock);
 912                 cpu_clear(cpu, backtrace_mask);
 913         }
 914
 915 #ifdef CONFIG_X86_MCE
 916         /* Could check oops_in_progress here too, but it's safer
 917            not too */
 918         if (atomic_read(&mce_entry) > 0)
 919                 touched = 1;
 920 #endif
 921         /* if the apic timer isn't firing, this cpu isn't doing much */
 922         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
 923                 /*
 924                  * Ayiee, looks like this CPU is stuck ...
 925                  * wait a few IRQs (5 seconds) before doing the oops ...
 926                  */
 927                 local_inc(&__get_cpu_var(alert_counter));
 928                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
 929                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
 930                                 panic_on_timeout);
 931         } else {
 932                 __get_cpu_var(last_irq_sum) = sum;
 933                 local_set(&__get_cpu_var(alert_counter), 0);
 934         }
 935
 936         /* see if the nmi watchdog went off */
 937         if (wd->enabled) {
 938                 if (nmi_watchdog == NMI_LOCAL_APIC) {
 939                         rdmsrl(wd->perfctr_msr, dummy);
 940                         if (dummy & wd->check_bit){
 941                                 /* this wasn't a watchdog timer interrupt */
 942                                 goto done;
 943                         }
 944
 945                         /* only Intel uses the cccr msr */
 946                         if (wd->cccr_msr != 0) {
 947                                 /*
 948                                  * P4 quirks:
 949                                  * - An overflown perfctr will assert its interrupt
 950                                  *   until the OVF flag in its CCCR is cleared.
 951                                  * - LVTPC is masked on interrupt and must be
 952                                  *   unmasked by the LVTPC handler.
 953                                  */
 954                                 rdmsrl(wd->cccr_msr, dummy);
 955                                 dummy &= ~P4_CCCR_OVF;
 956                                 wrmsrl(wd->cccr_msr, dummy);
 957                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 958                                 /* start the cycle over again */
 959                                 wrmsrl(wd->perfctr_msr,
 960                                        -((u64)cpu_khz * 1000 / nmi_hz));
 961                         } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1) {
 962                                 /*
 963                                  * ArchPerfom/Core Duo needs to re-unmask
 964                                  * the apic vector
 965                                  */
 966                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 967                                 /* ARCH_PERFMON has 32 bit counter writes */
 968                                 wrmsr(wd->perfctr_msr,
 969                                      (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
 970                         } else {
 971                                 /* start the cycle over again */
 972                                 wrmsrl(wd->perfctr_msr,
 973                                        -((u64)cpu_khz * 1000 / nmi_hz));
 974                         }
 975                         rc = 1;
 976                 } else  if (nmi_watchdog == NMI_IO_APIC) {
 977                         /* don't know how to accurately check for this.
 978                          * just assume it was a watchdog timer interrupt
 979                          * This matches the old behaviour.
 980                          */
 981                         rc = 1;
 982                 } else
 983                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
 984         }
 985 done:
 986         return rc;
 987 }
 988
 989 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
 990 {
 991         nmi_enter();
 992         add_pda(__nmi_count,1);
 993         default_do_nmi(regs);
 994         nmi_exit();
 995 }
 996
 997 int do_nmi_callback(struct pt_regs * regs, int cpu)
 998 {
 999 #ifdef CONFIG_SYSCTL
1000         if (unknown_nmi_panic)
1001                 return unknown_nmi_panic_callback(regs, cpu);
1002 #endif
1003         return 0;
1004 }
1005
1006 #ifdef CONFIG_SYSCTL
1007
1008 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
1009 {
1010         unsigned char reason = get_nmi_reason();
1011         char buf[64];
1012
1013         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
1014         die_nmi(buf, regs, 1);  /* Always panic here */
1015         return 0;
1016 }
1017
1018 /*
1019  * proc handler for /proc/sys/kernel/nmi
1020  */
1021 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
1022                         void __user *buffer, size_t *length, loff_t *ppos)
1023 {
1024         int old_state;
1025
1026         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
1027         old_state = nmi_watchdog_enabled;
1028         proc_dointvec(table, write, file, buffer, length, ppos);
1029         if (!!old_state == !!nmi_watchdog_enabled)
1030                 return 0;
1031
1032         if (atomic_read(&nmi_active) < 0) {
1033                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
1034                 return -EIO;
1035         }
1036
1037         /* if nmi_watchdog is not set yet, then set it */
1038         nmi_watchdog_default();
1039
1040         if (nmi_watchdog == NMI_LOCAL_APIC) {
1041                 if (nmi_watchdog_enabled)
1042                         enable_lapic_nmi_watchdog();
1043                 else
1044                         disable_lapic_nmi_watchdog();
1045         } else {
1046                 printk( KERN_WARNING
1047                         "NMI watchdog doesn't know what hardware to touch\n");
1048                 return -EIO;
1049         }
1050         return 0;
1051 }
1052
1053 #endif
1054
1055 void __trigger_all_cpu_backtrace(void)
1056 {
1057         int i;
1058
1059         backtrace_mask = cpu_online_map;
1060         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
1061         for (i = 0; i < 10 * 1000; i++) {
1062                 if (cpus_empty(backtrace_mask))
1063                         break;
1064                 mdelay(1);
1065         }
1066 }
1067
1068 EXPORT_SYMBOL(nmi_active);
1069 EXPORT_SYMBOL(nmi_watchdog);
1070 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
1071 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
1072 EXPORT_SYMBOL(reserve_perfctr_nmi);
1073 EXPORT_SYMBOL(release_perfctr_nmi);
1074 EXPORT_SYMBOL(reserve_evntsel_nmi);
1075 EXPORT_SYMBOL(release_evntsel_nmi);
1076 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
1077 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
1078 EXPORT_SYMBOL(touch_nmi_watchdog);