Merge branch 'master' of git://git.kernel.org/pub/scm/fs/xfs/xfs
[linux-2.6] / drivers / isdn / hisax / jade.c
1 /* $Id: jade.c,v 1.9.2.4 2004/01/14 16:04:48 keil Exp $
2  *
3  * JADE stuff (derived from original hscx.c)
4  *
5  * Author       Roland Klabunde
6  * Copyright    by Roland Klabunde   <R.Klabunde@Berkom.de>
7  * 
8  * This software may be used and distributed according to the terms
9  * of the GNU General Public License, incorporated herein by reference.
10  *
11  */
12
13
14 #include <linux/init.h>
15 #include "hisax.h"
16 #include "hscx.h"
17 #include "jade.h"
18 #include "isdnl1.h"
19 #include <linux/interrupt.h>
20
21
22 int
23 JadeVersion(struct IsdnCardState *cs, char *s)
24 {
25     int ver,i;
26     int to = 50;
27     cs->BC_Write_Reg(cs, -1, 0x50, 0x19);
28     i=0;
29     while (to) {
30         udelay(1);
31         ver = cs->BC_Read_Reg(cs, -1, 0x60);
32         to--;
33         if (ver)
34             break;
35         if (!to) {
36             printk(KERN_INFO "%s JADE version not obtainable\n", s);
37             return (0);
38         }
39     }
40     /* Wait for the JADE */
41     udelay(10);
42     /* Read version */
43     ver = cs->BC_Read_Reg(cs, -1, 0x60);
44     printk(KERN_INFO "%s JADE version: %d\n", s, ver);
45     return (1);
46 }
47
48 /* Write to indirect accessible jade register set */
49 static void
50 jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value)
51 {
52     int to = 50;
53     u_char ret;
54
55     /* Write the data */
56     cs->BC_Write_Reg(cs, -1, COMM_JADE+1, value);
57     /* Say JADE we wanna write indirect reg 'reg' */
58     cs->BC_Write_Reg(cs, -1, COMM_JADE, reg);
59     to = 50;
60     /* Wait for RDY goes high */
61     while (to) {
62         udelay(1);
63         ret = cs->BC_Read_Reg(cs, -1, COMM_JADE);
64         to--;
65         if (ret & 1)
66             /* Got acknowledge */
67             break;
68         if (!to) {
69             printk(KERN_INFO "Can not see ready bit from JADE DSP (reg=0x%X, value=0x%X)\n", reg, value);
70             return;
71         }
72     }
73 }
74
75
76
77 static void
78 modejade(struct BCState *bcs, int mode, int bc)
79 {
80     struct IsdnCardState *cs = bcs->cs;
81     int jade = bcs->hw.hscx.hscx;
82
83     if (cs->debug & L1_DEB_HSCX) {
84         char tmp[40];
85         sprintf(tmp, "jade %c mode %d ichan %d",
86                 'A' + jade, mode, bc);
87         debugl1(cs, tmp);
88     }
89     bcs->mode = mode;
90     bcs->channel = bc;
91         
92     cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO:0x00));
93     cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU|jadeCCR0_ITF));
94     cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00);
95
96     jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08);
97     jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08);
98     jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00);
99     jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00);
100
101     cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07);
102     cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07);
103
104     if (bc == 0) {
105         cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00);
106         cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00);
107     } else {
108         cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04);
109         cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04);
110     }
111     switch (mode) {
112         case (L1_MODE_NULL):
113                 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO);
114                 break;
115         case (L1_MODE_TRANS):
116                 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO|jadeMODE_RAC|jadeMODE_XAC));
117                 break;
118         case (L1_MODE_HDLC):
119                 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC|jadeMODE_XAC));
120                 break;
121     }
122     if (mode) {
123         cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES|jadeRCMD_RMC));
124         cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES);
125         /* Unmask ints */
126         cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8);
127     }
128     else
129         /* Mask ints */
130         cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00);
131 }
132
133 static void
134 jade_l2l1(struct PStack *st, int pr, void *arg)
135 {
136     struct BCState *bcs = st->l1.bcs;
137     struct sk_buff *skb = arg;
138     u_long flags;
139
140     switch (pr) {
141         case (PH_DATA | REQUEST):
142                 spin_lock_irqsave(&bcs->cs->lock, flags);
143                 if (bcs->tx_skb) {
144                         skb_queue_tail(&bcs->squeue, skb);
145                 } else {
146                         bcs->tx_skb = skb;
147                         test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
148                         bcs->hw.hscx.count = 0;
149                         bcs->cs->BC_Send_Data(bcs);
150                 }
151                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
152                 break;
153         case (PH_PULL | INDICATION):
154                 spin_lock_irqsave(&bcs->cs->lock, flags);
155                 if (bcs->tx_skb) {
156                         printk(KERN_WARNING "jade_l2l1: this shouldn't happen\n");
157                 } else {
158                         test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
159                         bcs->tx_skb = skb;
160                         bcs->hw.hscx.count = 0;
161                         bcs->cs->BC_Send_Data(bcs);
162                 }
163                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
164                 break;
165         case (PH_PULL | REQUEST):
166                 if (!bcs->tx_skb) {
167                     test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
168                     st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
169                 } else
170                     test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
171                 break;
172         case (PH_ACTIVATE | REQUEST):
173                 spin_lock_irqsave(&bcs->cs->lock, flags);
174                 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
175                 modejade(bcs, st->l1.mode, st->l1.bc);
176                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
177                 l1_msg_b(st, pr, arg);
178                 break;
179         case (PH_DEACTIVATE | REQUEST):
180                 l1_msg_b(st, pr, arg);
181                 break;
182         case (PH_DEACTIVATE | CONFIRM):
183                 spin_lock_irqsave(&bcs->cs->lock, flags);
184                 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
185                 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
186                 modejade(bcs, 0, st->l1.bc);
187                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
188                 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
189                 break;
190     }
191 }
192
193 static void
194 close_jadestate(struct BCState *bcs)
195 {
196     modejade(bcs, 0, bcs->channel);
197     if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
198         kfree(bcs->hw.hscx.rcvbuf);
199         bcs->hw.hscx.rcvbuf = NULL;
200         kfree(bcs->blog);
201         bcs->blog = NULL;
202         skb_queue_purge(&bcs->rqueue);
203         skb_queue_purge(&bcs->squeue);
204         if (bcs->tx_skb) {
205                 dev_kfree_skb_any(bcs->tx_skb);
206                 bcs->tx_skb = NULL;
207                 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
208         }
209     }
210 }
211
212 static int
213 open_jadestate(struct IsdnCardState *cs, struct BCState *bcs)
214 {
215         if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
216                 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
217                         printk(KERN_WARNING
218                                "HiSax: No memory for hscx.rcvbuf\n");
219                         test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
220                         return (1);
221                 }
222                 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
223                         printk(KERN_WARNING
224                                 "HiSax: No memory for bcs->blog\n");
225                         test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
226                         kfree(bcs->hw.hscx.rcvbuf);
227                         bcs->hw.hscx.rcvbuf = NULL;
228                         return (2);
229                 }
230                 skb_queue_head_init(&bcs->rqueue);
231                 skb_queue_head_init(&bcs->squeue);
232         }
233         bcs->tx_skb = NULL;
234         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
235         bcs->event = 0;
236         bcs->hw.hscx.rcvidx = 0;
237         bcs->tx_cnt = 0;
238         return (0);
239 }
240
241
242 static int
243 setstack_jade(struct PStack *st, struct BCState *bcs)
244 {
245         bcs->channel = st->l1.bc;
246         if (open_jadestate(st->l1.hardware, bcs))
247                 return (-1);
248         st->l1.bcs = bcs;
249         st->l2.l2l1 = jade_l2l1;
250         setstack_manager(st);
251         bcs->st = st;
252         setstack_l1_B(st);
253         return (0);
254 }
255
256 void
257 clear_pending_jade_ints(struct IsdnCardState *cs)
258 {
259         int val;
260         char tmp[64];
261
262         cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
263         cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
264
265         val = cs->BC_Read_Reg(cs, 1, jade_HDLC_ISR);
266         sprintf(tmp, "jade B ISTA %x", val);
267         debugl1(cs, tmp);
268         val = cs->BC_Read_Reg(cs, 0, jade_HDLC_ISR);
269         sprintf(tmp, "jade A ISTA %x", val);
270         debugl1(cs, tmp);
271         val = cs->BC_Read_Reg(cs, 1, jade_HDLC_STAR);
272         sprintf(tmp, "jade B STAR %x", val);
273         debugl1(cs, tmp);
274         val = cs->BC_Read_Reg(cs, 0, jade_HDLC_STAR);
275         sprintf(tmp, "jade A STAR %x", val);
276         debugl1(cs, tmp);
277         /* Unmask ints */
278         cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0xF8);
279         cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0xF8);
280 }
281
282 void
283 initjade(struct IsdnCardState *cs)
284 {
285         cs->bcs[0].BC_SetStack = setstack_jade;
286         cs->bcs[1].BC_SetStack = setstack_jade;
287         cs->bcs[0].BC_Close = close_jadestate;
288         cs->bcs[1].BC_Close = close_jadestate;
289         cs->bcs[0].hw.hscx.hscx = 0;
290         cs->bcs[1].hw.hscx.hscx = 1;
291
292         /* Stop DSP audio tx/rx */
293         jade_write_indirect(cs, 0x11, 0x0f);
294         jade_write_indirect(cs, 0x17, 0x2f);
295
296         /* Transparent Mode, RxTx inactive, No Test, No RFS/TFS */
297         cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO);
298         cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO);
299         /* Power down, 1-Idle, RxTx least significant bit first */
300         cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00);
301         cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00);
302         /* Mask all interrupts */
303         cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR,  0x00);
304         cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR,  0x00);
305         /* Setup host access to hdlc controller */
306         jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1|jadeINDIRECT_HAH2));
307         /* Unmask HDLC int (don't forget DSP int later on)*/
308         cs->BC_Write_Reg(cs, -1,jade_INT, (jadeINT_HDLC1|jadeINT_HDLC2));
309
310         /* once again TRANSPARENT */    
311         modejade(cs->bcs, 0, 0);
312         modejade(cs->bcs + 1, 0, 0);
313 }
314