Automatic merge with /usr/src/ntfs-2.6.git
[linux-2.6] / arch / ppc / syslib / ppc4xx_pic.c
1 /*
2  * arch/ppc/syslib/ppc4xx_pic.c
3  *
4  * Interrupt controller driver for PowerPC 4xx-based processors.
5  *
6  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
7  * Copyright (c) 2004, 2005 Zultys Technologies
8  *
9  * Based on original code by
10  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
11  *    Armin Custer <akuster@mvista.com>
12  *
13  * This program is free software; you can redistribute  it and/or modify it
14  * under  the terms of  the GNU General  Public License as published by the
15  * Free Software Foundation;  either version 2 of the  License, or (at your
16  * option) any later version.
17 */
18 #include <linux/config.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/stddef.h>
23
24 #include <asm/processor.h>
25 #include <asm/system.h>
26 #include <asm/irq.h>
27 #include <asm/ppc4xx_pic.h>
28
29 /* See comment in include/arch-ppc/ppc4xx_pic.h
30  * for more info about these two variables
31  */
32 extern struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[NR_UICS]
33     __attribute__ ((weak));
34 extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
35
36 #define IRQ_MASK_UIC0(irq)              (1 << (31 - (irq)))
37 #define IRQ_MASK_UICx(irq)              (1 << (31 - ((irq) & 0x1f)))
38 #define IRQ_MASK_UIC1(irq)              IRQ_MASK_UICx(irq)
39 #define IRQ_MASK_UIC2(irq)              IRQ_MASK_UICx(irq)
40
41 #define UIC_HANDLERS(n)                                                 \
42 static void ppc4xx_uic##n##_enable(unsigned int irq)                    \
43 {                                                                       \
44         u32 mask = IRQ_MASK_UIC##n(irq);                                \
45         if (irq_desc[irq].status & IRQ_LEVEL)                           \
46                 mtdcr(DCRN_UIC_SR(UIC##n), mask);                       \
47         ppc_cached_irq_mask[n] |= mask;                                 \
48         mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]);             \
49 }                                                                       \
50                                                                         \
51 static void ppc4xx_uic##n##_disable(unsigned int irq)                   \
52 {                                                                       \
53         ppc_cached_irq_mask[n] &= ~IRQ_MASK_UIC##n(irq);                \
54         mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]);             \
55         ACK_UIC##n##_PARENT                                             \
56 }                                                                       \
57                                                                         \
58 static void ppc4xx_uic##n##_ack(unsigned int irq)                       \
59 {                                                                       \
60         u32 mask = IRQ_MASK_UIC##n(irq);                                \
61         ppc_cached_irq_mask[n] &= ~mask;                                \
62         mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]);             \
63         mtdcr(DCRN_UIC_SR(UIC##n), mask);                               \
64         ACK_UIC##n##_PARENT                                             \
65 }                                                                       \
66                                                                         \
67 static void ppc4xx_uic##n##_end(unsigned int irq)                       \
68 {                                                                       \
69         unsigned int status = irq_desc[irq].status;                     \
70         u32 mask = IRQ_MASK_UIC##n(irq);                                \
71         if (status & IRQ_LEVEL) {                                       \
72                 mtdcr(DCRN_UIC_SR(UIC##n), mask);                       \
73                 ACK_UIC##n##_PARENT                                     \
74         }                                                               \
75         if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) {              \
76                 ppc_cached_irq_mask[n] |= mask;                         \
77                 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]);     \
78         }                                                               \
79 }
80
81 #define DECLARE_UIC(n)                                                  \
82 {                                                                       \
83         .typename       = "UIC"#n,                                      \
84         .enable         = ppc4xx_uic##n##_enable,                       \
85         .disable        = ppc4xx_uic##n##_disable,                      \
86         .ack            = ppc4xx_uic##n##_ack,                          \
87         .end            = ppc4xx_uic##n##_end,                          \
88 }                                                                       \
89
90 #if NR_UICS == 3
91 #define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
92 #define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
93 #define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
94 UIC_HANDLERS(0);
95 UIC_HANDLERS(1);
96 UIC_HANDLERS(2);
97
98 static int ppc4xx_pic_get_irq(struct pt_regs *regs)
99 {
100         u32 uicb = mfdcr(DCRN_UIC_MSR(UICB));
101         if (uicb & UICB_UIC0NC)
102                 return 32 - ffs(mfdcr(DCRN_UIC_MSR(UIC0)));
103         else if (uicb & UICB_UIC1NC)
104                 return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
105         else if (uicb & UICB_UIC2NC)
106                 return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
107         else
108                 return -1;
109 }
110
111 static void __init ppc4xx_pic_impl_init(void)
112 {
113         /* Configure Base UIC */
114         mtdcr(DCRN_UIC_CR(UICB), 0);
115         mtdcr(DCRN_UIC_TR(UICB), 0);
116         mtdcr(DCRN_UIC_PR(UICB), 0xffffffff);
117         mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
118         mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
119 }
120
121 #elif NR_UICS == 2
122 #define ACK_UIC0_PARENT
123 #define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
124 UIC_HANDLERS(0);
125 UIC_HANDLERS(1);
126
127 static int ppc4xx_pic_get_irq(struct pt_regs *regs)
128 {
129         u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
130         if (uic0 & UIC0_UIC1NC)
131                 return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
132         else
133                 return uic0 ? 32 - ffs(uic0) : -1;
134 }
135
136 static void __init ppc4xx_pic_impl_init(void)
137 {
138         /* Enable cascade interrupt in UIC0 */
139         ppc_cached_irq_mask[0] |= UIC0_UIC1NC;
140         mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
141         mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
142 }
143
144 #elif NR_UICS == 1
145 #define ACK_UIC0_PARENT
146 UIC_HANDLERS(0);
147
148 static int ppc4xx_pic_get_irq(struct pt_regs *regs)
149 {
150         u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
151         return uic0 ? 32 - ffs(uic0) : -1;
152 }
153
154 static inline void ppc4xx_pic_impl_init(void)
155 {
156 }
157 #endif
158
159 static struct ppc4xx_uic_impl {
160         struct hw_interrupt_type decl;
161         int base;                       /* Base DCR number */
162 } __uic[] = {
163         { .decl = DECLARE_UIC(0), .base = UIC0 },
164 #if NR_UICS > 1
165         { .decl = DECLARE_UIC(1), .base = UIC1 },
166 #if NR_UICS > 2
167         { .decl = DECLARE_UIC(2), .base = UIC2 },
168 #endif
169 #endif
170 };
171
172 static inline int is_level_sensitive(int irq)
173 {
174         u32 tr = mfdcr(DCRN_UIC_TR(__uic[irq >> 5].base));
175         return (tr & IRQ_MASK_UICx(irq)) == 0;
176 }
177
178 void __init ppc4xx_pic_init(void)
179 {
180         int i;
181         unsigned char *eirqs = ppc4xx_uic_ext_irq_cfg;
182
183         for (i = 0; i < NR_UICS; ++i) {
184                 int base = __uic[i].base;
185
186                 /* Disable everything by default */
187                 ppc_cached_irq_mask[i] = 0;
188                 mtdcr(DCRN_UIC_ER(base), 0);
189
190                 /* We don't use critical interrupts */
191                 mtdcr(DCRN_UIC_CR(base), 0);
192
193                 /* Configure polarity and triggering */
194                 if (ppc4xx_core_uic_cfg) {
195                         struct ppc4xx_uic_settings *p = ppc4xx_core_uic_cfg + i;
196                         u32 mask = p->ext_irq_mask;
197                         u32 pr = mfdcr(DCRN_UIC_PR(base)) & mask;
198                         u32 tr = mfdcr(DCRN_UIC_TR(base)) & mask;
199
200                         /* "Fixed" interrupts (on-chip devices) */
201                         pr |= p->polarity & ~mask;
202                         tr |= p->triggering & ~mask;
203
204                         /* Merge external IRQs settings if board port
205                          * provided them
206                          */
207                         if (eirqs && mask) {
208                                 pr &= ~mask;
209                                 tr &= ~mask;
210                                 while (mask) {
211                                         /* Extract current external IRQ mask */
212                                         u32 eirq_mask = 1 << __ilog2(mask);
213
214                                         if (!(*eirqs & IRQ_SENSE_LEVEL))
215                                                 tr |= eirq_mask;
216
217                                         if (*eirqs & IRQ_POLARITY_POSITIVE)
218                                                 pr |= eirq_mask;
219
220                                         mask &= ~eirq_mask;
221                                         ++eirqs;
222                                 }
223                         }
224                         mtdcr(DCRN_UIC_PR(base), pr);
225                         mtdcr(DCRN_UIC_TR(base), tr);
226                 }
227
228                 /* ACK any pending interrupts to prevent false
229                  * triggering after first enable
230                  */
231                 mtdcr(DCRN_UIC_SR(base), 0xffffffff);
232         }
233
234         /* Perform optional implementation specific setup
235          * (e.g. enable cascade interrupts for multi-UIC configurations)
236          */
237         ppc4xx_pic_impl_init();
238
239         /* Attach low-level handlers */
240         for (i = 0; i < (NR_UICS << 5); ++i) {
241                 irq_desc[i].handler = &__uic[i >> 5].decl;
242                 if (is_level_sensitive(i))
243                         irq_desc[i].status |= IRQ_LEVEL;
244         }
245
246         ppc_md.get_irq = ppc4xx_pic_get_irq;
247 }