1 /* Wrapper for DMA channel allocator that starts clocks etc */
3 #include <linux/kernel.h>
4 #include <linux/spinlock.h>
6 #include <hwregs/reg_map.h>
7 #include <hwregs/reg_rdwr.h>
8 #include <hwregs/marb_defs.h>
9 #include <hwregs/config_defs.h>
10 #include <hwregs/strmux_defs.h>
11 #include <linux/errno.h>
12 #include <asm/system.h>
13 #include <mach/arbiter.h>
15 static char used_dma_channels[MAX_DMA_CHANNELS];
16 static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
18 static DEFINE_SPINLOCK(dma_lock);
20 int crisv32_request_dma(unsigned int dmanr, const char *device_id,
21 unsigned options, unsigned int bandwidth,
25 reg_config_rw_clk_ctrl clk_ctrl;
26 reg_strmux_rw_cfg strmux_cfg;
28 if (crisv32_arbiter_allocate_bandwidth(dmanr,
29 options & DMA_INT_MEM ?
30 INT_REGION : EXT_REGION,
34 spin_lock_irqsave(&dma_lock, flags);
36 if (used_dma_channels[dmanr]) {
37 spin_unlock_irqrestore(&dma_lock, flags);
38 if (options & DMA_VERBOSE_ON_ERROR) {
39 printk(KERN_ERR "Failed to request DMA %i for %s, "
40 "already allocated by %s\n",
43 used_dma_channels_users[dmanr]);
45 if (options & DMA_PANIC_ON_ERROR)
46 panic("request_dma error!");
47 spin_unlock_irqrestore(&dma_lock, flags);
50 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
51 strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
56 clk_ctrl.dma01_eth0 = 1;
72 clk_ctrl.dma89_strcop = 1;
74 #if MAX_DMA_CHANNELS-1 != 9
78 spin_unlock_irqrestore(&dma_lock, flags);
79 if (options & DMA_VERBOSE_ON_ERROR) {
80 printk(KERN_ERR "Failed to request DMA %i for %s, "
82 dmanr, device_id, MAX_DMA_CHANNELS - 1);
85 if (options & DMA_PANIC_ON_ERROR)
86 panic("request_dma error!");
93 strmux_cfg.dma0 = regk_strmux_eth0;
95 strmux_cfg.dma1 = regk_strmux_eth0;
97 panic("Invalid DMA channel for eth0\n");
101 strmux_cfg.dma6 = regk_strmux_eth1;
103 strmux_cfg.dma7 = regk_strmux_eth1;
105 panic("Invalid DMA channel for eth1\n");
109 strmux_cfg.dma2 = regk_strmux_iop0;
111 strmux_cfg.dma3 = regk_strmux_iop0;
113 panic("Invalid DMA channel for iop0\n");
117 strmux_cfg.dma4 = regk_strmux_iop1;
119 strmux_cfg.dma5 = regk_strmux_iop1;
121 panic("Invalid DMA channel for iop1\n");
125 strmux_cfg.dma6 = regk_strmux_ser0;
127 strmux_cfg.dma7 = regk_strmux_ser0;
129 panic("Invalid DMA channel for ser0\n");
133 strmux_cfg.dma4 = regk_strmux_ser1;
135 strmux_cfg.dma5 = regk_strmux_ser1;
137 panic("Invalid DMA channel for ser1\n");
141 strmux_cfg.dma2 = regk_strmux_ser2;
143 strmux_cfg.dma3 = regk_strmux_ser2;
145 panic("Invalid DMA channel for ser2\n");
149 strmux_cfg.dma8 = regk_strmux_ser3;
151 strmux_cfg.dma9 = regk_strmux_ser3;
153 panic("Invalid DMA channel for ser3\n");
157 strmux_cfg.dma4 = regk_strmux_sser0;
159 strmux_cfg.dma5 = regk_strmux_sser0;
161 panic("Invalid DMA channel for sser0\n");
165 strmux_cfg.dma6 = regk_strmux_sser1;
167 strmux_cfg.dma7 = regk_strmux_sser1;
169 panic("Invalid DMA channel for sser1\n");
173 strmux_cfg.dma2 = regk_strmux_ata;
175 strmux_cfg.dma3 = regk_strmux_ata;
177 panic("Invalid DMA channel for ata\n");
181 strmux_cfg.dma8 = regk_strmux_strcop;
183 strmux_cfg.dma9 = regk_strmux_strcop;
185 panic("Invalid DMA channel for strp\n");
189 strmux_cfg.dma6 = regk_strmux_ext0;
191 panic("Invalid DMA channel for ext0\n");
195 strmux_cfg.dma7 = regk_strmux_ext1;
197 panic("Invalid DMA channel for ext1\n");
201 strmux_cfg.dma2 = regk_strmux_ext2;
203 strmux_cfg.dma8 = regk_strmux_ext2;
205 panic("Invalid DMA channel for ext2\n");
209 strmux_cfg.dma3 = regk_strmux_ext3;
211 strmux_cfg.dma9 = regk_strmux_ext2;
213 panic("Invalid DMA channel for ext2\n");
217 used_dma_channels[dmanr] = 1;
218 used_dma_channels_users[dmanr] = device_id;
219 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
220 REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
221 spin_unlock_irqrestore(&dma_lock, flags);
225 void crisv32_free_dma(unsigned int dmanr)
227 spin_lock(&dma_lock);
228 used_dma_channels[dmanr] = 0;
229 spin_unlock(&dma_lock);